[qemu.git] / target-microblaze / op_helper.c

/*
 *  Microblaze helper routines.
 *
 *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <assert.h>
#include "cpu.h"
#include "dyngen-exec.h"
#include "helper.h"
#include "host-utils.h"

#define D(x)

#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"

#define MMUSUFFIX _mmu
#define SHIFT 0
#include "softmmu_template.h"
#define SHIFT 1
#include "softmmu_template.h"
#define SHIFT 2
#include "softmmu_template.h"
#define SHIFT 3
#include "softmmu_template.h"

/* Try to fill the TLB and return an exception if error. If retaddr is
   NULL, it means that the function was called in C code (i.e. not
   from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
              void *retaddr)
{
    TranslationBlock *tb;
    CPUState *saved_env;
    unsigned long pc;
    int ret;

    saved_env = env;
    env = env1;

    ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx);
    if (unlikely(ret)) {
        if (retaddr) {
            /* now we have a real cpu fault */
            pc = (unsigned long)retaddr;
            tb = tb_find_pc(pc);
            if (tb) {
                /* the PC is inside the translated code. It means that we have
                   a virtual CPU fault */
                cpu_restore_state(tb, env, pc);
            }
        }
        cpu_loop_exit(env);
    }
    env = saved_env;
}
#endif

void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
{
    int test = ctrl & STREAM_TEST;
    int atomic = ctrl & STREAM_ATOMIC;
    int control = ctrl & STREAM_CONTROL;
    int nonblock = ctrl & STREAM_NONBLOCK;
    int exception = ctrl & STREAM_EXCEPTION;

    qemu_log("Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
             id, data,
             test ? "t" : "",
             nonblock ? "n" : "",
             exception ? "e" : "",
             control ? "c" : "",
             atomic ? "a" : "");
}

uint32_t helper_get(uint32_t id, uint32_t ctrl)
{
    int test = ctrl & STREAM_TEST;
    int atomic = ctrl & STREAM_ATOMIC;
    int control = ctrl & STREAM_CONTROL;
    int nonblock = ctrl & STREAM_NONBLOCK;
    int exception = ctrl & STREAM_EXCEPTION;

    qemu_log("Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
             id,
             test ? "t" : "",
             nonblock ? "n" : "",
             exception ? "e" : "",
             control ? "c" : "",
             atomic ? "a" : "");
    return 0xdead0000 | id;
}

void helper_raise_exception(uint32_t index)
{
    env->exception_index = index;
    cpu_loop_exit(env);
}

void helper_debug(void)
{
    int i;

    qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
    qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
             env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
             env->debug, env->imm, env->iflags);
    qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
             env->btaken, env->btarget,
             (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
             (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
             (env->sregs[SR_MSR] & MSR_EIP),
             (env->sregs[SR_MSR] & MSR_IE));
    for (i = 0; i < 32; i++) {
        qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
        if ((i + 1) % 4 == 0)
            qemu_log("\n");
    }
    qemu_log("\n\n");
}

static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
{
    uint32_t cout = 0;

    if ((b == ~0) && cin)
        cout = 1;
    else if ((~0 - a) < (b + cin))
        cout = 1;
    return cout;
}

uint32_t helper_cmp(uint32_t a, uint32_t b)
{
    uint32_t t;

    t = b + ~a + 1;
    if ((b & 0x80000000) ^ (a & 0x80000000))
        t = (t & 0x7fffffff) | (b & 0x80000000);
    return t;
}

uint32_t helper_cmpu(uint32_t a, uint32_t b)
{
    uint32_t t;

    t = b + ~a + 1;
    if ((b & 0x80000000) ^ (a & 0x80000000))
        t = (t & 0x7fffffff) | (a & 0x80000000);
    return t;
}

uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
{
    uint32_t ncf;
    ncf = compute_carry(a, b, cf);
    return ncf;
}

static inline int div_prepare(uint32_t a, uint32_t b)
{
    if (b == 0) {
        env->sregs[SR_MSR] |= MSR_DZ;

        if ((env->sregs[SR_MSR] & MSR_EE)
            && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_DIVZERO;
            helper_raise_exception(EXCP_HW_EXCP);
        }
        return 0;
    }
    env->sregs[SR_MSR] &= ~MSR_DZ;
    return 1;
}

uint32_t helper_divs(uint32_t a, uint32_t b)
{
    if (!div_prepare(a, b))
        return 0;
    return (int32_t)a / (int32_t)b;
}

uint32_t helper_divu(uint32_t a, uint32_t b)
{
    if (!div_prepare(a, b))
        return 0;
    return a / b;
}

/* raise FPU exception.  */
static void raise_fpu_exception(void)
{
    env->sregs[SR_ESR] = ESR_EC_FPU;
    helper_raise_exception(EXCP_HW_EXCP);
}

static void update_fpu_flags(int flags)
{
    int raise = 0;

    if (flags & float_flag_invalid) {
        env->sregs[SR_FSR] |= FSR_IO;
        raise = 1;
    }
    if (flags & float_flag_divbyzero) {
        env->sregs[SR_FSR] |= FSR_DZ;
        raise = 1;
    }
    if (flags & float_flag_overflow) {
        env->sregs[SR_FSR] |= FSR_OF;
        raise = 1;
    }
    if (flags & float_flag_underflow) {
        env->sregs[SR_FSR] |= FSR_UF;
        raise = 1;
    }
    if (raise
        && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
        && (env->sregs[SR_MSR] & MSR_EE)) {
        raise_fpu_exception();
    }
}

uint32_t helper_fadd(uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_add(fa.f, fb.f, &env->fp_status);

    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);
    return fd.l;
}

uint32_t helper_frsub(uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);
    return fd.l;
}

uint32_t helper_fmul(uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);

    return fd.l;
}

uint32_t helper_fdiv(uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_div(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);

    return fd.l;
}

uint32_t helper_fcmp_un(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    uint32_t r = 0;

    fa.l = a;
    fb.l = b;

    if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
        update_fpu_flags(float_flag_invalid);
        r = 1;
    }

    if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
        r = 1;
    }

    return r;
}

uint32_t helper_fcmp_lt(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int r;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    r = float32_lt(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_eq(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags;
    int r;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_le(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags;
    int r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = float32_le(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);


    return r;
}

uint32_t helper_fcmp_gt(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = float32_lt(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);
    return r;
}

uint32_t helper_fcmp_ne(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_ge(uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = !float32_lt(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags & float_flag_invalid);

    return r;
}

uint32_t helper_flt(uint32_t a)
{
    CPU_FloatU fd, fa;

    fa.l = a;
    fd.f = int32_to_float32(fa.l, &env->fp_status);
    return fd.l;
}

uint32_t helper_fint(uint32_t a)
{
    CPU_FloatU fa;
    uint32_t r;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    r = float32_to_int32(fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);

    return r;
}

uint32_t helper_fsqrt(uint32_t a)
{
    CPU_FloatU fd, fa;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fd.l = float32_sqrt(fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(flags);

    return fd.l;
}

uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
{
    unsigned int i;
    uint32_t mask = 0xff000000;

    for (i = 0; i < 4; i++) {
        if ((a & mask) == (b & mask))
            return i + 1;
        mask >>= 8;
    }
    return 0;
}

void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask)
{
    if (addr & mask) {
            qemu_log_mask(CPU_LOG_INT,
                          "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
                          addr, mask, wr, dr);
            env->sregs[SR_EAR] = addr;
            env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
                                 | (dr & 31) << 5;
            if (mask == 3) {
                env->sregs[SR_ESR] |= 1 << 11;
            }
            if (!(env->sregs[SR_MSR] & MSR_EE)) {
                return;
            }
            helper_raise_exception(EXCP_HW_EXCP);
    }
}

#if !defined(CONFIG_USER_ONLY)
/* Writes/reads to the MMU's special regs end up here.  */
uint32_t helper_mmu_read(uint32_t rn)
{
    return mmu_read(env, rn);
}

void helper_mmu_write(uint32_t rn, uint32_t v)
{
    mmu_write(env, rn, v);
}

void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
                           int is_write, int is_exec, int is_asi, int size)
{
    CPUState *saved_env;

    saved_env = env;
    env = env1;

    qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
             addr, is_write, is_exec);
    if (!(env->sregs[SR_MSR] & MSR_EE)) {
        env = saved_env;
        return;
    }

    env->sregs[SR_EAR] = addr;
    if (is_exec) {
        if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
            helper_raise_exception(EXCP_HW_EXCP);
        }
    } else {
        if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
            helper_raise_exception(EXCP_HW_EXCP);
        }
    }
    env = saved_env;
}
#endif
Commit	Line	Data
4acb54ba EI	1	/*
	2	* Microblaze helper routines.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba EI	18	*/
	19
	20	#include <assert.h>
3e457172 BS	21	#include "cpu.h"
3e457172 BS	22	#include "dyngen-exec.h"
4acb54ba EI	23	#include "helper.h"
	24	#include "host-utils.h"
	25
	26	#define D(x)
	27
	28	#if !defined(CONFIG_USER_ONLY)
3e457172 BS	29	#include "softmmu_exec.h"
3e457172 BS	30
4acb54ba EI	31	#define MMUSUFFIX _mmu
	32	#define SHIFT 0
	33	#include "softmmu_template.h"
	34	#define SHIFT 1
	35	#include "softmmu_template.h"
	36	#define SHIFT 2
	37	#include "softmmu_template.h"
	38	#define SHIFT 3
	39	#include "softmmu_template.h"
	40
	41	/* Try to fill the TLB and return an exception if error. If retaddr is
	42	NULL, it means that the function was called in C code (i.e. not
	43	from generated code or from helper.c) */
	44	/* XXX: fix it to restore all registers */
bccd9ec5 BS	45	void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
bccd9ec5 BS	46	void *retaddr)
4acb54ba EI	47	{
	48	TranslationBlock *tb;
	49	CPUState *saved_env;
	50	unsigned long pc;
	51	int ret;
	52
4acb54ba	53	saved_env = env;
bccd9ec5	54	env = env1;
4acb54ba	55
97b348e7	56	ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx);
4acb54ba EI	57	if (unlikely(ret)) {
	58	if (retaddr) {
	59	/* now we have a real cpu fault */
	60	pc = (unsigned long)retaddr;
	61	tb = tb_find_pc(pc);
	62	if (tb) {
	63	/* the PC is inside the translated code. It means that we have
	64	a virtual CPU fault */
618ba8e6	65	cpu_restore_state(tb, env, pc);
4acb54ba EI	66	}
4acb54ba EI	67	}
1162c041	68	cpu_loop_exit(env);
4acb54ba EI	69	}
	70	env = saved_env;
	71	}
	72	#endif
	73
6d76d23e EI	74	void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
	75	{
	76	int test = ctrl & STREAM_TEST;
	77	int atomic = ctrl & STREAM_ATOMIC;
	78	int control = ctrl & STREAM_CONTROL;
	79	int nonblock = ctrl & STREAM_NONBLOCK;
	80	int exception = ctrl & STREAM_EXCEPTION;
	81
	82	qemu_log("Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
	83	id, data,
	84	test ? "t" : "",
	85	nonblock ? "n" : "",
	86	exception ? "e" : "",
	87	control ? "c" : "",
	88	atomic ? "a" : "");
	89	}
	90
	91	uint32_t helper_get(uint32_t id, uint32_t ctrl)
	92	{
	93	int test = ctrl & STREAM_TEST;
	94	int atomic = ctrl & STREAM_ATOMIC;
	95	int control = ctrl & STREAM_CONTROL;
	96	int nonblock = ctrl & STREAM_NONBLOCK;
	97	int exception = ctrl & STREAM_EXCEPTION;
	98
	99	qemu_log("Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
	100	id,
	101	test ? "t" : "",
	102	nonblock ? "n" : "",
	103	exception ? "e" : "",
	104	control ? "c" : "",
	105	atomic ? "a" : "");
	106	return 0xdead0000 \| id;
	107	}
	108
4acb54ba EI	109	void helper_raise_exception(uint32_t index)
	110	{
	111	env->exception_index = index;
1162c041	112	cpu_loop_exit(env);
4acb54ba EI	113	}
	114
	115	void helper_debug(void)
	116	{
	117	int i;
	118
	119	qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
4c24aa0a MS	120	qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
4c24aa0a MS	121	env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
17c52a43 EI	122	env->debug, env->imm, env->iflags);
	123	qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
	124	env->btaken, env->btarget,
	125	(env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
	126	(env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
	127	(env->sregs[SR_MSR] & MSR_EIP),
	128	(env->sregs[SR_MSR] & MSR_IE));
4acb54ba EI	129	for (i = 0; i < 32; i++) {
	130	qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
	131	if ((i + 1) % 4 == 0)
	132	qemu_log("\n");
	133	}
	134	qemu_log("\n\n");
	135	}
	136
	137	static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
	138	{
	139	uint32_t cout = 0;
	140
	141	if ((b == ~0) && cin)
	142	cout = 1;
	143	else if ((~0 - a) < (b + cin))
	144	cout = 1;
	145	return cout;
	146	}
	147
	148	uint32_t helper_cmp(uint32_t a, uint32_t b)
	149	{
	150	uint32_t t;
	151
	152	t = b + ~a + 1;
	153	if ((b & 0x80000000) ^ (a & 0x80000000))
	154	t = (t & 0x7fffffff) \| (b & 0x80000000);
	155	return t;
	156	}
	157
	158	uint32_t helper_cmpu(uint32_t a, uint32_t b)
	159	{
	160	uint32_t t;
	161
	162	t = b + ~a + 1;
	163	if ((b & 0x80000000) ^ (a & 0x80000000))
	164	t = (t & 0x7fffffff) \| (a & 0x80000000);
	165	return t;
	166	}
	167
5d0bb823	168	uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
4acb54ba	169	{
5d0bb823	170	uint32_t ncf;
40cbf5b7 EI	171	ncf = compute_carry(a, b, cf);
40cbf5b7 EI	172	return ncf;
4acb54ba EI	173	}
4acb54ba EI	174
4acb54ba EI	175	static inline int div_prepare(uint32_t a, uint32_t b)
	176	{
	177	if (b == 0) {
	178	env->sregs[SR_MSR] \|= MSR_DZ;
821ebb33 EI	179
	180	if ((env->sregs[SR_MSR] & MSR_EE)
	181	&& !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
	182	env->sregs[SR_ESR] = ESR_EC_DIVZERO;
	183	helper_raise_exception(EXCP_HW_EXCP);
	184	}
4acb54ba EI	185	return 0;
	186	}
	187	env->sregs[SR_MSR] &= ~MSR_DZ;
	188	return 1;
	189	}
	190
	191	uint32_t helper_divs(uint32_t a, uint32_t b)
	192	{
	193	if (!div_prepare(a, b))
	194	return 0;
	195	return (int32_t)a / (int32_t)b;
	196	}
	197
	198	uint32_t helper_divu(uint32_t a, uint32_t b)
	199	{
	200	if (!div_prepare(a, b))
	201	return 0;
	202	return a / b;
	203	}
	204
97694c57 EI	205	/* raise FPU exception. */
	206	static void raise_fpu_exception(void)
	207	{
	208	env->sregs[SR_ESR] = ESR_EC_FPU;
	209	helper_raise_exception(EXCP_HW_EXCP);
	210	}
	211
	212	static void update_fpu_flags(int flags)
	213	{
	214	int raise = 0;
	215
	216	if (flags & float_flag_invalid) {
	217	env->sregs[SR_FSR] \|= FSR_IO;
	218	raise = 1;
	219	}
	220	if (flags & float_flag_divbyzero) {
	221	env->sregs[SR_FSR] \|= FSR_DZ;
	222	raise = 1;
	223	}
	224	if (flags & float_flag_overflow) {
	225	env->sregs[SR_FSR] \|= FSR_OF;
	226	raise = 1;
	227	}
	228	if (flags & float_flag_underflow) {
	229	env->sregs[SR_FSR] \|= FSR_UF;
	230	raise = 1;
	231	}
	232	if (raise
	233	&& (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
	234	&& (env->sregs[SR_MSR] & MSR_EE)) {
	235	raise_fpu_exception();
	236	}
	237	}
	238
	239	uint32_t helper_fadd(uint32_t a, uint32_t b)
	240	{
	241	CPU_FloatU fd, fa, fb;
	242	int flags;
	243
	244	set_float_exception_flags(0, &env->fp_status);
	245	fa.l = a;
	246	fb.l = b;
	247	fd.f = float32_add(fa.f, fb.f, &env->fp_status);
	248
	249	flags = get_float_exception_flags(&env->fp_status);
	250	update_fpu_flags(flags);
	251	return fd.l;
	252	}
	253
	254	uint32_t helper_frsub(uint32_t a, uint32_t b)
	255	{
	256	CPU_FloatU fd, fa, fb;
	257	int flags;
	258
	259	set_float_exception_flags(0, &env->fp_status);
	260	fa.l = a;
	261	fb.l = b;
	262	fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
	263	flags = get_float_exception_flags(&env->fp_status);
	264	update_fpu_flags(flags);
	265	return fd.l;
	266	}
	267
	268	uint32_t helper_fmul(uint32_t a, uint32_t b)
269	{
270	CPU_FloatU fd, fa, fb;
271	int flags;
272
273	set_float_exception_flags(0, &env->fp_status);
274	fa.l = a;
275	fb.l = b;
276	fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
277	flags = get_float_exception_flags(&env->fp_status);
278	update_fpu_flags(flags);
279
280	return fd.l;
281	}
282
283	uint32_t helper_fdiv(uint32_t a, uint32_t b)
284	{
285	CPU_FloatU fd, fa, fb;
286	int flags;
287
288	set_float_exception_flags(0, &env->fp_status);
289	fa.l = a;
290	fb.l = b;
291	fd.f = float32_div(fb.f, fa.f, &env->fp_status);
292	flags = get_float_exception_flags(&env->fp_status);
293	update_fpu_flags(flags);
294
295	return fd.l;
296	}
297
298	uint32_t helper_fcmp_un(uint32_t a, uint32_t b)
299	{
ef9d48da EI	300	CPU_FloatU fa, fb;
	301	uint32_t r = 0;
	302
	303	fa.l = a;
	304	fb.l = b;
	305
	306	if (float32_is_signaling_nan(fa.f) \|\| float32_is_signaling_nan(fb.f)) {
	307	update_fpu_flags(float_flag_invalid);
	308	r = 1;
	309	}
	310
18569871	311	if (float32_is_quiet_nan(fa.f) \|\| float32_is_quiet_nan(fb.f)) {
ef9d48da EI	312	r = 1;
	313	}
	314
	315	return r;
97694c57 EI	316	}
	317
	318	uint32_t helper_fcmp_lt(uint32_t a, uint32_t b)
	319	{
	320	CPU_FloatU fa, fb;
	321	int r;
	322	int flags;
	323
	324	set_float_exception_flags(0, &env->fp_status);
	325	fa.l = a;
	326	fb.l = b;
	327	r = float32_lt(fb.f, fa.f, &env->fp_status);
	328	flags = get_float_exception_flags(&env->fp_status);
	329	update_fpu_flags(flags & float_flag_invalid);
	330
	331	return r;
	332	}
	333
	334	uint32_t helper_fcmp_eq(uint32_t a, uint32_t b)
	335	{
	336	CPU_FloatU fa, fb;
	337	int flags;
	338	int r;
	339
	340	set_float_exception_flags(0, &env->fp_status);
	341	fa.l = a;
	342	fb.l = b;
211315fb	343	r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
97694c57 EI	344	flags = get_float_exception_flags(&env->fp_status);
	345	update_fpu_flags(flags & float_flag_invalid);
	346
	347	return r;
	348	}
	349
	350	uint32_t helper_fcmp_le(uint32_t a, uint32_t b)
	351	{
	352	CPU_FloatU fa, fb;
	353	int flags;
	354	int r;
	355
	356	fa.l = a;
	357	fb.l = b;
	358	set_float_exception_flags(0, &env->fp_status);
	359	r = float32_le(fa.f, fb.f, &env->fp_status);
	360	flags = get_float_exception_flags(&env->fp_status);
	361	update_fpu_flags(flags & float_flag_invalid);
	362
	363
	364	return r;
	365	}
	366
	367	uint32_t helper_fcmp_gt(uint32_t a, uint32_t b)
	368	{
	369	CPU_FloatU fa, fb;
	370	int flags, r;
	371
	372	fa.l = a;
	373	fb.l = b;
	374	set_float_exception_flags(0, &env->fp_status);
	375	r = float32_lt(fa.f, fb.f, &env->fp_status);
	376	flags = get_float_exception_flags(&env->fp_status);
	377	update_fpu_flags(flags & float_flag_invalid);
	378	return r;
	379	}
	380
	381	uint32_t helper_fcmp_ne(uint32_t a, uint32_t b)
	382	{
	383	CPU_FloatU fa, fb;
	384	int flags, r;
	385
	386	fa.l = a;
	387	fb.l = b;
	388	set_float_exception_flags(0, &env->fp_status);
211315fb	389	r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
97694c57 EI	390	flags = get_float_exception_flags(&env->fp_status);
	391	update_fpu_flags(flags & float_flag_invalid);
	392
	393	return r;
	394	}
	395
	396	uint32_t helper_fcmp_ge(uint32_t a, uint32_t b)
	397	{
	398	CPU_FloatU fa, fb;
	399	int flags, r;
	400
	401	fa.l = a;
	402	fb.l = b;
	403	set_float_exception_flags(0, &env->fp_status);
	404	r = !float32_lt(fa.f, fb.f, &env->fp_status);
	405	flags = get_float_exception_flags(&env->fp_status);
	406	update_fpu_flags(flags & float_flag_invalid);
	407
	408	return r;
	409	}
	410
	411	uint32_t helper_flt(uint32_t a)
	412	{
	413	CPU_FloatU fd, fa;
	414
	415	fa.l = a;
	416	fd.f = int32_to_float32(fa.l, &env->fp_status);
	417	return fd.l;
	418	}
	419
	420	uint32_t helper_fint(uint32_t a)
	421	{
	422	CPU_FloatU fa;
	423	uint32_t r;
	424	int flags;
	425
	426	set_float_exception_flags(0, &env->fp_status);
	427	fa.l = a;
	428	r = float32_to_int32(fa.f, &env->fp_status);
	429	flags = get_float_exception_flags(&env->fp_status);
	430	update_fpu_flags(flags);
	431
	432	return r;
	433	}
	434
	435	uint32_t helper_fsqrt(uint32_t a)
	436	{
	437	CPU_FloatU fd, fa;
	438	int flags;
	439
	440	set_float_exception_flags(0, &env->fp_status);
	441	fa.l = a;
	442	fd.l = float32_sqrt(fa.f, &env->fp_status);
	443	flags = get_float_exception_flags(&env->fp_status);
	444	update_fpu_flags(flags);
	445
	446	return fd.l;
	447	}
	448
4acb54ba EI	449	uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
	450	{
	451	unsigned int i;
	452	uint32_t mask = 0xff000000;
	453
	454	for (i = 0; i < 4; i++) {
	455	if ((a & mask) == (b & mask))
	456	return i + 1;
	457	mask >>= 8;
	458	}
	459	return 0;
	460	}
	461
3aa80988	462	void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask)
968a40f6	463	{
968a40f6	464	if (addr & mask) {
97f90cbf EI	465	qemu_log_mask(CPU_LOG_INT,
	466	"unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
	467	addr, mask, wr, dr);
	468	env->sregs[SR_EAR] = addr;
968a40f6 EI	469	env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA \| (wr << 10) \
968a40f6 EI	470	\| (dr & 31) << 5;
3aa80988	471	if (mask == 3) {
968a40f6 EI	472	env->sregs[SR_ESR] \|= 1 << 11;
968a40f6 EI	473	}
97f90cbf EI	474	if (!(env->sregs[SR_MSR] & MSR_EE)) {
	475	return;
	476	}
968a40f6 EI	477	helper_raise_exception(EXCP_HW_EXCP);
	478	}
	479	}
	480
4acb54ba EI	481	#if !defined(CONFIG_USER_ONLY)
	482	/* Writes/reads to the MMU's special regs end up here. */
	483	uint32_t helper_mmu_read(uint32_t rn)
	484	{
	485	return mmu_read(env, rn);
	486	}
	487
	488	void helper_mmu_write(uint32_t rn, uint32_t v)
	489	{
	490	mmu_write(env, rn, v);
	491	}
faed1c2a	492
b14ef7c9 BS	493	void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
b14ef7c9 BS	494	int is_write, int is_exec, int is_asi, int size)
faed1c2a EI	495	{
faed1c2a EI	496	CPUState *saved_env;
e1aa3254	497
faed1c2a	498	saved_env = env;
b14ef7c9 BS	499	env = env1;
b14ef7c9 BS	500
97f90cbf	501	qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
faed1c2a EI	502	addr, is_write, is_exec);
faed1c2a EI	503	if (!(env->sregs[SR_MSR] & MSR_EE)) {
95b279de	504	env = saved_env;
faed1c2a EI	505	return;
	506	}
	507
97f90cbf	508	env->sregs[SR_EAR] = addr;
faed1c2a	509	if (is_exec) {
97f90cbf	510	if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
faed1c2a EI	511	env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
	512	helper_raise_exception(EXCP_HW_EXCP);
	513	}
	514	} else {
97f90cbf	515	if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
faed1c2a EI	516	env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
	517	helper_raise_exception(EXCP_HW_EXCP);
	518	}
	519	}
95b279de	520	env = saved_env;
faed1c2a	521	}
3c7b48b7	522	#endif