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[qemu.git] / target-microblaze / translate.c
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4acb54ba
EI		 1/*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
dadc1064 5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
4acb54ba
EI		 6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba
EI		 19 */
20
4acb54ba 21#include "cpu.h"
76cad711 22#include "disas/disas.h"
4acb54ba
EI		 23#include "tcg-op.h"
24#include "helper.h"
25#include "microblaze-decode.h"
4acb54ba
EI		 26
27#define GEN_HELPER 1
28#include "helper.h"
29
30#define SIM_COMPAT 0
31#define DISAS_GNU 1
32#define DISAS_MB 1
33#if DISAS_MB && !SIM_COMPAT
34# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
35#else
36# define LOG_DIS(...) do { } while (0)
37#endif
38
39#define D(x)
40
41#define EXTRACT_FIELD(src, start, end) \
42 (((src) >> start) & ((1 << (end - start + 1)) - 1))
43
44static TCGv env_debug;
45static TCGv_ptr cpu_env;
46static TCGv cpu_R[32];
47static TCGv cpu_SR[18];
48static TCGv env_imm;
49static TCGv env_btaken;
50static TCGv env_btarget;
51static TCGv env_iflags;
52
022c62cb 53#include "exec/gen-icount.h"
4acb54ba
EI		 54
55/* This is the state at translation time. */
56typedef struct DisasContext {
68cee38a 57 CPUMBState *env;
a5efa644 58 target_ulong pc;
4acb54ba
EI		 59
60 /* Decoder. */
61 int type_b;
62 uint32_t ir;
63 uint8_t opcode;
64 uint8_t rd, ra, rb;
65 uint16_t imm;
66
67 unsigned int cpustate_changed;
68 unsigned int delayed_branch;
69 unsigned int tb_flags, synced_flags; /* tb dependent flags. */
70 unsigned int clear_imm;
71 int is_jmp;
72
844bab60
EI		 73#define JMP_NOJMP 0
74#define JMP_DIRECT 1
75#define JMP_DIRECT_CC 2
76#define JMP_INDIRECT 3
4acb54ba
EI		 77 unsigned int jmp;
78 uint32_t jmp_pc;
79
80 int abort_at_next_insn;
81 int nr_nops;
82 struct TranslationBlock *tb;
83 int singlestep_enabled;
84} DisasContext;
85
38972938 86static const char *regnames[] =
4acb54ba
EI		 87{
88 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
89 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
90 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
91 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
92};
93
38972938 94static const char *special_regnames[] =
4acb54ba
EI		 95{
96 "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
97 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
98 "sr16", "sr17", "sr18"
99};
100
101/* Sign extend at translation time. */
102static inline int sign_extend(unsigned int val, unsigned int width)
103{
104 int sval;
105
106 /* LSL. */
107 val <<= 31 - width;
108 sval = val;
109 /* ASR. */
110 sval >>= 31 - width;
111 return sval;
112}
113
114static inline void t_sync_flags(DisasContext *dc)
115{
4abf79a4 116 /* Synch the tb dependent flags between translator and runtime. */
4acb54ba
EI		 117 if (dc->tb_flags != dc->synced_flags) {
118 tcg_gen_movi_tl(env_iflags, dc->tb_flags);
119 dc->synced_flags = dc->tb_flags;
120 }
121}
122
123static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
124{
125 TCGv_i32 tmp = tcg_const_i32(index);
126
127 t_sync_flags(dc);
128 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
64254eba 129 gen_helper_raise_exception(cpu_env, tmp);
4acb54ba
EI		 130 tcg_temp_free_i32(tmp);
131 dc->is_jmp = DISAS_UPDATE;
132}
133
134static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
135{
136 TranslationBlock *tb;
137 tb = dc->tb;
138 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
139 tcg_gen_goto_tb(n);
140 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
8cfd0495 141 tcg_gen_exit_tb((uintptr_t)tb + n);
4acb54ba
EI		 142 } else {
143 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
144 tcg_gen_exit_tb(0);
145 }
146}
147
ee8b246f
EI		 148static void read_carry(DisasContext *dc, TCGv d)
149{
150 tcg_gen_shri_tl(d, cpu_SR[SR_MSR], 31);
151}
152
04ec7df7
EI		 153/*
154 * write_carry sets the carry bits in MSR based on bit 0 of v.
155 * v[31:1] are ignored.
156 */
ee8b246f
EI		 157static void write_carry(DisasContext *dc, TCGv v)
158{
159 TCGv t0 = tcg_temp_new();
160 tcg_gen_shli_tl(t0, v, 31);
161 tcg_gen_sari_tl(t0, t0, 31);
162 tcg_gen_andi_tl(t0, t0, (MSR_C | MSR_CC));
163 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR],
164 ~(MSR_C | MSR_CC));
165 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0);
166 tcg_temp_free(t0);
167}
168
65ab5eb4 169static void write_carryi(DisasContext *dc, bool carry)
8cc9b43f
PC		 170{
171 TCGv t0 = tcg_temp_new();
65ab5eb4 172 tcg_gen_movi_tl(t0, carry);
8cc9b43f
PC		 173 write_carry(dc, t0);
174 tcg_temp_free(t0);
175}
176
61204ce8
EI		 177/* True if ALU operand b is a small immediate that may deserve
178 faster treatment. */
179static inline int dec_alu_op_b_is_small_imm(DisasContext *dc)
180{
181 /* Immediate insn without the imm prefix ? */
182 return dc->type_b && !(dc->tb_flags & IMM_FLAG);
183}
184
4acb54ba
EI		 185static inline TCGv *dec_alu_op_b(DisasContext *dc)
186{
187 if (dc->type_b) {
188 if (dc->tb_flags & IMM_FLAG)
189 tcg_gen_ori_tl(env_imm, env_imm, dc->imm);
190 else
191 tcg_gen_movi_tl(env_imm, (int32_t)((int16_t)dc->imm));
192 return &env_imm;
193 } else
194 return &cpu_R[dc->rb];
195}
196
197static void dec_add(DisasContext *dc)
198{
199 unsigned int k, c;
40cbf5b7 200 TCGv cf;
4acb54ba
EI		 201
202 k = dc->opcode & 4;
203 c = dc->opcode & 2;
204
205 LOG_DIS("add%s%s%s r%d r%d r%d\n",
206 dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "",
207 dc->rd, dc->ra, dc->rb);
208
40cbf5b7
EI		 209 /* Take care of the easy cases first. */
210 if (k) {
211 /* k - keep carry, no need to update MSR. */
212 /* If rd == r0, it's a nop. */
213 if (dc->rd) {
214 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
215
216 if (c) {
217 /* c - Add carry into the result. */
218 cf = tcg_temp_new();
219
220 read_carry(dc, cf);
221 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
222 tcg_temp_free(cf);
223 }
224 }
225 return;
226 }
227
228 /* From now on, we can assume k is zero. So we need to update MSR. */
229 /* Extract carry. */
230 cf = tcg_temp_new();
231 if (c) {
232 read_carry(dc, cf);
233 } else {
234 tcg_gen_movi_tl(cf, 0);
235 }
236
237 if (dc->rd) {
238 TCGv ncf = tcg_temp_new();
5d0bb823 239 gen_helper_carry(ncf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf);
4acb54ba 240 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
40cbf5b7
EI		 241 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
242 write_carry(dc, ncf);
243 tcg_temp_free(ncf);
244 } else {
5d0bb823 245 gen_helper_carry(cf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf);
40cbf5b7 246 write_carry(dc, cf);
4acb54ba 247 }
40cbf5b7 248 tcg_temp_free(cf);
4acb54ba
EI		 249}
250
251static void dec_sub(DisasContext *dc)
252{
253 unsigned int u, cmp, k, c;
e0a42ebc 254 TCGv cf, na;
4acb54ba
EI		 255
256 u = dc->imm & 2;
257 k = dc->opcode & 4;
258 c = dc->opcode & 2;
259 cmp = (dc->imm & 1) && (!dc->type_b) && k;
260
261 if (cmp) {
262 LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir);
263 if (dc->rd) {
264 if (u)
265 gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
266 else
267 gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
268 }
e0a42ebc
EI		 269 return;
270 }
271
272 LOG_DIS("sub%s%s r%d, r%d r%d\n",
273 k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb);
274
275 /* Take care of the easy cases first. */
276 if (k) {
277 /* k - keep carry, no need to update MSR. */
278 /* If rd == r0, it's a nop. */
279 if (dc->rd) {
4acb54ba 280 tcg_gen_sub_tl(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
e0a42ebc
EI		 281
282 if (c) {
283 /* c - Add carry into the result. */
284 cf = tcg_temp_new();
285
286 read_carry(dc, cf);
287 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
288 tcg_temp_free(cf);
289 }
290 }
291 return;
292 }
293
294 /* From now on, we can assume k is zero. So we need to update MSR. */
295 /* Extract carry. And complement a into na. */
296 cf = tcg_temp_new();
297 na = tcg_temp_new();
298 if (c) {
299 read_carry(dc, cf);
300 } else {
301 tcg_gen_movi_tl(cf, 1);
302 }
303
304 /* d = b + ~a + c. carry defaults to 1. */
305 tcg_gen_not_tl(na, cpu_R[dc->ra]);
306
307 if (dc->rd) {
308 TCGv ncf = tcg_temp_new();
5d0bb823 309 gen_helper_carry(ncf, na, *(dec_alu_op_b(dc)), cf);
e0a42ebc
EI		 310 tcg_gen_add_tl(cpu_R[dc->rd], na, *(dec_alu_op_b(dc)));
311 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
312 write_carry(dc, ncf);
313 tcg_temp_free(ncf);
314 } else {
5d0bb823 315 gen_helper_carry(cf, na, *(dec_alu_op_b(dc)), cf);
e0a42ebc 316 write_carry(dc, cf);
4acb54ba 317 }
e0a42ebc
EI		 318 tcg_temp_free(cf);
319 tcg_temp_free(na);
4acb54ba
EI		 320}
321
322static void dec_pattern(DisasContext *dc)
323{
324 unsigned int mode;
325 int l1;
326
1567a005 327 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 328 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 329 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
330 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
331 t_gen_raise_exception(dc, EXCP_HW_EXCP);
332 }
333
4acb54ba
EI		 334 mode = dc->opcode & 3;
335 switch (mode) {
336 case 0:
337 /* pcmpbf. */
338 LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
339 if (dc->rd)
340 gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
341 break;
342 case 2:
343 LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
344 if (dc->rd) {
345 TCGv t0 = tcg_temp_local_new();
346 l1 = gen_new_label();
347 tcg_gen_movi_tl(t0, 1);
348 tcg_gen_brcond_tl(TCG_COND_EQ,
349 cpu_R[dc->ra], cpu_R[dc->rb], l1);
350 tcg_gen_movi_tl(t0, 0);
351 gen_set_label(l1);
352 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
353 tcg_temp_free(t0);
354 }
355 break;
356 case 3:
357 LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
358 l1 = gen_new_label();
359 if (dc->rd) {
360 TCGv t0 = tcg_temp_local_new();
361 tcg_gen_movi_tl(t0, 1);
362 tcg_gen_brcond_tl(TCG_COND_NE,
363 cpu_R[dc->ra], cpu_R[dc->rb], l1);
364 tcg_gen_movi_tl(t0, 0);
365 gen_set_label(l1);
366 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
367 tcg_temp_free(t0);
368 }
369 break;
370 default:
371 cpu_abort(dc->env,
372 "unsupported pattern insn opcode=%x\n", dc->opcode);
373 break;
374 }
375}
376
377static void dec_and(DisasContext *dc)
378{
379 unsigned int not;
380
381 if (!dc->type_b && (dc->imm & (1 << 10))) {
382 dec_pattern(dc);
383 return;
384 }
385
386 not = dc->opcode & (1 << 1);
387 LOG_DIS("and%s\n", not ? "n" : "");
388
389 if (!dc->rd)
390 return;
391
392 if (not) {
a235900e 393 tcg_gen_andc_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
4acb54ba
EI		 394 } else
395 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
396}
397
398static void dec_or(DisasContext *dc)
399{
400 if (!dc->type_b && (dc->imm & (1 << 10))) {
401 dec_pattern(dc);
402 return;
403 }
404
405 LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm);
406 if (dc->rd)
407 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
408}
409
410static void dec_xor(DisasContext *dc)
411{
412 if (!dc->type_b && (dc->imm & (1 << 10))) {
413 dec_pattern(dc);
414 return;
415 }
416
417 LOG_DIS("xor r%d\n", dc->rd);
418 if (dc->rd)
419 tcg_gen_xor_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
420}
421
4acb54ba
EI		 422static inline void msr_read(DisasContext *dc, TCGv d)
423{
424 tcg_gen_mov_tl(d, cpu_SR[SR_MSR]);
425}
426
427static inline void msr_write(DisasContext *dc, TCGv v)
428{
97b833c5
EI		 429 TCGv t;
430
431 t = tcg_temp_new();
4acb54ba 432 dc->cpustate_changed = 1;
97b833c5 433 /* PVR bit is not writable. */
8a84fc6b
EI		 434 tcg_gen_andi_tl(t, v, ~MSR_PVR);
435 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR);
97b833c5
EI		 436 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], v);
437 tcg_temp_free(t);
4acb54ba
EI		 438}
439
440static void dec_msr(DisasContext *dc)
441{
442 TCGv t0, t1;
443 unsigned int sr, to, rn;
1567a005 444 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 445
446 sr = dc->imm & ((1 << 14) - 1);
447 to = dc->imm & (1 << 14);
448 dc->type_b = 1;
449 if (to)
450 dc->cpustate_changed = 1;
451
452 /* msrclr and msrset. */
453 if (!(dc->imm & (1 << 15))) {
454 unsigned int clr = dc->ir & (1 << 16);
455
456 LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
457 dc->rd, dc->imm);
1567a005
EI		 458
459 if (!(dc->env->pvr.regs[2] & PVR2_USE_MSR_INSTR)) {
460 /* nop??? */
461 return;
462 }
463
464 if ((dc->tb_flags & MSR_EE_FLAG)
465 && mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) {
466 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
467 t_gen_raise_exception(dc, EXCP_HW_EXCP);
468 return;
469 }
470
4acb54ba
EI		 471 if (dc->rd)
472 msr_read(dc, cpu_R[dc->rd]);
473
474 t0 = tcg_temp_new();
475 t1 = tcg_temp_new();
476 msr_read(dc, t0);
477 tcg_gen_mov_tl(t1, *(dec_alu_op_b(dc)));
478
479 if (clr) {
480 tcg_gen_not_tl(t1, t1);
481 tcg_gen_and_tl(t0, t0, t1);
482 } else
483 tcg_gen_or_tl(t0, t0, t1);
484 msr_write(dc, t0);
485 tcg_temp_free(t0);
486 tcg_temp_free(t1);
487 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
488 dc->is_jmp = DISAS_UPDATE;
489 return;
490 }
491
1567a005
EI		 492 if (to) {
493 if ((dc->tb_flags & MSR_EE_FLAG)
494 && mem_index == MMU_USER_IDX) {
495 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
496 t_gen_raise_exception(dc, EXCP_HW_EXCP);
497 return;
498 }
499 }
500
4acb54ba
EI		 501#if !defined(CONFIG_USER_ONLY)
502 /* Catch read/writes to the mmu block. */
503 if ((sr & ~0xff) == 0x1000) {
504 sr &= 7;
505 LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
506 if (to)
64254eba 507 gen_helper_mmu_write(cpu_env, tcg_const_tl(sr), cpu_R[dc->ra]);
4acb54ba 508 else
64254eba 509 gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tcg_const_tl(sr));
4acb54ba
EI		 510 return;
511 }
512#endif
513
514 if (to) {
515 LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
516 switch (sr) {
517 case 0:
518 break;
519 case 1:
520 msr_write(dc, cpu_R[dc->ra]);
521 break;
522 case 0x3:
523 tcg_gen_mov_tl(cpu_SR[SR_EAR], cpu_R[dc->ra]);
524 break;
525 case 0x5:
526 tcg_gen_mov_tl(cpu_SR[SR_ESR], cpu_R[dc->ra]);
527 break;
528 case 0x7:
97694c57 529 tcg_gen_andi_tl(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
4acb54ba 530 break;
5818dee5 531 case 0x800:
68cee38a 532 tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, slr));
5818dee5
EI		 533 break;
534 case 0x802:
68cee38a 535 tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, shr));
5818dee5 536 break;
4acb54ba
EI		 537 default:
538 cpu_abort(dc->env, "unknown mts reg %x\n", sr);
539 break;
540 }
541 } else {
542 LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm);
543
544 switch (sr) {
545 case 0:
546 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
547 break;
548 case 1:
549 msr_read(dc, cpu_R[dc->rd]);
550 break;
551 case 0x3:
552 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_EAR]);
553 break;
554 case 0x5:
555 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_ESR]);
556 break;
557 case 0x7:
97694c57 558 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_FSR]);
4acb54ba
EI		 559 break;
560 case 0xb:
561 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]);
562 break;
5818dee5 563 case 0x800:
68cee38a 564 tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, slr));
5818dee5
EI		 565 break;
566 case 0x802:
68cee38a 567 tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, shr));
5818dee5 568 break;
4acb54ba
EI		 569 case 0x2000:
570 case 0x2001:
571 case 0x2002:
572 case 0x2003:
573 case 0x2004:
574 case 0x2005:
575 case 0x2006:
576 case 0x2007:
577 case 0x2008:
578 case 0x2009:
579 case 0x200a:
580 case 0x200b:
581 case 0x200c:
582 rn = sr & 0xf;
583 tcg_gen_ld_tl(cpu_R[dc->rd],
68cee38a 584 cpu_env, offsetof(CPUMBState, pvr.regs[rn]));
4acb54ba
EI		 585 break;
586 default:
587 cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
588 break;
589 }
590 }
ee7dbcf8
EI		 591
592 if (dc->rd == 0) {
593 tcg_gen_movi_tl(cpu_R[0], 0);
594 }
4acb54ba
EI		 595}
596
597/* 64-bit signed mul, lower result in d and upper in d2. */
598static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
599{
600 TCGv_i64 t0, t1;
601
602 t0 = tcg_temp_new_i64();
603 t1 = tcg_temp_new_i64();
604
605 tcg_gen_ext_i32_i64(t0, a);
606 tcg_gen_ext_i32_i64(t1, b);
607 tcg_gen_mul_i64(t0, t0, t1);
608
609 tcg_gen_trunc_i64_i32(d, t0);
610 tcg_gen_shri_i64(t0, t0, 32);
611 tcg_gen_trunc_i64_i32(d2, t0);
612
613 tcg_temp_free_i64(t0);
614 tcg_temp_free_i64(t1);
615}
616
617/* 64-bit unsigned muls, lower result in d and upper in d2. */
618static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
619{
620 TCGv_i64 t0, t1;
621
622 t0 = tcg_temp_new_i64();
623 t1 = tcg_temp_new_i64();
624
625 tcg_gen_extu_i32_i64(t0, a);
626 tcg_gen_extu_i32_i64(t1, b);
627 tcg_gen_mul_i64(t0, t0, t1);
628
629 tcg_gen_trunc_i64_i32(d, t0);
630 tcg_gen_shri_i64(t0, t0, 32);
631 tcg_gen_trunc_i64_i32(d2, t0);
632
633 tcg_temp_free_i64(t0);
634 tcg_temp_free_i64(t1);
635}
636
637/* Multiplier unit. */
638static void dec_mul(DisasContext *dc)
639{
640 TCGv d[2];
641 unsigned int subcode;
642
1567a005 643 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 644 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 645 && !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
646 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
647 t_gen_raise_exception(dc, EXCP_HW_EXCP);
648 return;
649 }
650
4acb54ba
EI		 651 subcode = dc->imm & 3;
652 d[0] = tcg_temp_new();
653 d[1] = tcg_temp_new();
654
655 if (dc->type_b) {
656 LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm);
657 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
658 goto done;
659 }
660
1567a005
EI		 661 /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
662 if (subcode >= 1 && subcode <= 3
663 && !((dc->env->pvr.regs[2] & PVR2_USE_MUL64_MASK))) {
664 /* nop??? */
665 }
666
4acb54ba
EI		 667 switch (subcode) {
668 case 0:
669 LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
670 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], cpu_R[dc->rb]);
671 break;
672 case 1:
673 LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
674 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
675 break;
676 case 2:
677 LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
678 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
679 break;
680 case 3:
681 LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
682 t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
683 break;
684 default:
685 cpu_abort(dc->env, "unknown MUL insn %x\n", subcode);
686 break;
687 }
688done:
689 tcg_temp_free(d[0]);
690 tcg_temp_free(d[1]);
691}
692
693/* Div unit. */
694static void dec_div(DisasContext *dc)
695{
696 unsigned int u;
697
698 u = dc->imm & 2;
699 LOG_DIS("div\n");
700
97f90cbf 701 if ((dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 702 && !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) {
703 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
704 t_gen_raise_exception(dc, EXCP_HW_EXCP);
705 }
706
4acb54ba 707 if (u)
64254eba
BS		 708 gen_helper_divu(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)),
709 cpu_R[dc->ra]);
4acb54ba 710 else
64254eba
BS		 711 gen_helper_divs(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)),
712 cpu_R[dc->ra]);
4acb54ba
EI		 713 if (!dc->rd)
714 tcg_gen_movi_tl(cpu_R[dc->rd], 0);
715}
716
717static void dec_barrel(DisasContext *dc)
718{
719 TCGv t0;
720 unsigned int s, t;
721
1567a005 722 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 723 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 724 && !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
725 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
726 t_gen_raise_exception(dc, EXCP_HW_EXCP);
727 return;
728 }
729
4acb54ba
EI		 730 s = dc->imm & (1 << 10);
731 t = dc->imm & (1 << 9);
732
733 LOG_DIS("bs%s%s r%d r%d r%d\n",
734 s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
735
736 t0 = tcg_temp_new();
737
738 tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
739 tcg_gen_andi_tl(t0, t0, 31);
740
741 if (s)
742 tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
743 else {
744 if (t)
745 tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
746 else
747 tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
748 }
749}
750
751static void dec_bit(DisasContext *dc)
752{
09b9f113 753 TCGv t0;
4acb54ba 754 unsigned int op;
1567a005 755 int mem_index = cpu_mmu_index(dc->env);
4acb54ba 756
ace2e4da 757 op = dc->ir & ((1 << 9) - 1);
4acb54ba
EI		 758 switch (op) {
759 case 0x21:
760 /* src. */
761 t0 = tcg_temp_new();
762
763 LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
09b9f113
EI		 764 tcg_gen_andi_tl(t0, cpu_SR[SR_MSR], MSR_CC);
765 write_carry(dc, cpu_R[dc->ra]);
4acb54ba 766 if (dc->rd) {
4acb54ba 767 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
09b9f113 768 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t0);
4acb54ba 769 }
4acb54ba
EI		 770 tcg_temp_free(t0);
771 break;
772
773 case 0x1:
774 case 0x41:
775 /* srl. */
4acb54ba
EI		 776 LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
777
bb3cb951
EI		 778 /* Update carry. Note that write carry only looks at the LSB. */
779 write_carry(dc, cpu_R[dc->ra]);
4acb54ba
EI		 780 if (dc->rd) {
781 if (op == 0x41)
782 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
783 else
784 tcg_gen_sari_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
785 }
786 break;
787 case 0x60:
788 LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra);
789 tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
790 break;
791 case 0x61:
792 LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra);
793 tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
794 break;
795 case 0x64:
f062a3c7
EI		 796 case 0x66:
797 case 0x74:
798 case 0x76:
4acb54ba
EI		 799 /* wdc. */
800 LOG_DIS("wdc r%d\n", dc->ra);
1567a005
EI		 801 if ((dc->tb_flags & MSR_EE_FLAG)
802 && mem_index == MMU_USER_IDX) {
803 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
804 t_gen_raise_exception(dc, EXCP_HW_EXCP);
805 return;
806 }
4acb54ba
EI		 807 break;
808 case 0x68:
809 /* wic. */
810 LOG_DIS("wic r%d\n", dc->ra);
1567a005
EI		 811 if ((dc->tb_flags & MSR_EE_FLAG)
812 && mem_index == MMU_USER_IDX) {
813 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
814 t_gen_raise_exception(dc, EXCP_HW_EXCP);
815 return;
816 }
4acb54ba 817 break;
48b5e96f
EI		 818 case 0xe0:
819 if ((dc->tb_flags & MSR_EE_FLAG)
820 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
821 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
822 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
823 t_gen_raise_exception(dc, EXCP_HW_EXCP);
824 }
825 if (dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR) {
826 gen_helper_clz(cpu_R[dc->rd], cpu_R[dc->ra]);
827 }
828 break;
ace2e4da
PC		 829 case 0x1e0:
830 /* swapb */
831 LOG_DIS("swapb r%d r%d\n", dc->rd, dc->ra);
832 tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
833 break;
b8c6a5d9 834 case 0x1e2:
ace2e4da
PC		 835 /*swaph */
836 LOG_DIS("swaph r%d r%d\n", dc->rd, dc->ra);
837 tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16);
838 break;
4acb54ba
EI		 839 default:
840 cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
841 dc->pc, op, dc->rd, dc->ra, dc->rb);
842 break;
843 }
844}
845
846static inline void sync_jmpstate(DisasContext *dc)
847{
844bab60
EI		 848 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
849 if (dc->jmp == JMP_DIRECT) {
850 tcg_gen_movi_tl(env_btaken, 1);
851 }
23979dc5
EI		 852 dc->jmp = JMP_INDIRECT;
853 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
4acb54ba
EI		 854 }
855}
856
857static void dec_imm(DisasContext *dc)
858{
859 LOG_DIS("imm %x\n", dc->imm << 16);
860 tcg_gen_movi_tl(env_imm, (dc->imm << 16));
861 dc->tb_flags |= IMM_FLAG;
862 dc->clear_imm = 0;
863}
864
865static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
866 unsigned int size)
867{
868 int mem_index = cpu_mmu_index(dc->env);
869
870 if (size == 1) {
871 tcg_gen_qemu_ld8u(dst, addr, mem_index);
872 } else if (size == 2) {
873 tcg_gen_qemu_ld16u(dst, addr, mem_index);
874 } else if (size == 4) {
875 tcg_gen_qemu_ld32u(dst, addr, mem_index);
876 } else
877 cpu_abort(dc->env, "Incorrect load size %d\n", size);
878}
879
880static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
881{
882 unsigned int extimm = dc->tb_flags & IMM_FLAG;
5818dee5
EI		 883 /* Should be set to one if r1 is used by loadstores. */
884 int stackprot = 0;
885
886 /* All load/stores use ra. */
887 if (dc->ra == 1) {
888 stackprot = 1;
889 }
4acb54ba 890
9ef55357 891 /* Treat the common cases first. */
4acb54ba 892 if (!dc->type_b) {
4b5ef0b5
EI		 893 /* If any of the regs is r0, return a ptr to the other. */
894 if (dc->ra == 0) {
895 return &cpu_R[dc->rb];
896 } else if (dc->rb == 0) {
897 return &cpu_R[dc->ra];
898 }
899
5818dee5
EI		 900 if (dc->rb == 1) {
901 stackprot = 1;
902 }
903
4acb54ba
EI		 904 *t = tcg_temp_new();
905 tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
5818dee5
EI		 906
907 if (stackprot) {
64254eba 908 gen_helper_stackprot(cpu_env, *t);
5818dee5 909 }
4acb54ba
EI		 910 return t;
911 }
912 /* Immediate. */
913 if (!extimm) {
914 if (dc->imm == 0) {
915 return &cpu_R[dc->ra];
916 }
917 *t = tcg_temp_new();
918 tcg_gen_movi_tl(*t, (int32_t)((int16_t)dc->imm));
919 tcg_gen_add_tl(*t, cpu_R[dc->ra], *t);
920 } else {
921 *t = tcg_temp_new();
922 tcg_gen_add_tl(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
923 }
924
5818dee5 925 if (stackprot) {
64254eba 926 gen_helper_stackprot(cpu_env, *t);
5818dee5 927 }
4acb54ba
EI		 928 return t;
929}
930
9f8beb66
EI		 931static inline void dec_byteswap(DisasContext *dc, TCGv dst, TCGv src, int size)
932{
933 if (size == 4) {
934 tcg_gen_bswap32_tl(dst, src);
935 } else if (size == 2) {
936 TCGv t = tcg_temp_new();
937
938 /* bswap16 assumes the high bits are zero. */
939 tcg_gen_andi_tl(t, src, 0xffff);
940 tcg_gen_bswap16_tl(dst, t);
941 tcg_temp_free(t);
942 } else {
943 /* Ignore.
944 cpu_abort(dc->env, "Invalid ldst byteswap size %d\n", size);
945 */
946 }
947}
948
4acb54ba
EI		 949static void dec_load(DisasContext *dc)
950{
951 TCGv t, *addr;
8cc9b43f 952 unsigned int size, rev = 0, ex = 0;
4acb54ba
EI		 953
954 size = 1 << (dc->opcode & 3);
9f8beb66
EI		 955
956 if (!dc->type_b) {
957 rev = (dc->ir >> 9) & 1;
8cc9b43f 958 ex = (dc->ir >> 10) & 1;
9f8beb66
EI		 959 }
960
0187688f 961 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
97f90cbf 962 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
0187688f
EI		 963 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
964 t_gen_raise_exception(dc, EXCP_HW_EXCP);
965 return;
966 }
4acb54ba 967
8cc9b43f
PC		 968 LOG_DIS("l%d%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "",
969 ex ? "x" : "");
9f8beb66 970
4acb54ba
EI		 971 t_sync_flags(dc);
972 addr = compute_ldst_addr(dc, &t);
973
9f8beb66
EI		 974 /*
975 * When doing reverse accesses we need to do two things.
976 *
4ff9786c 977 * 1. Reverse the address wrt endianness.
9f8beb66
EI		 978 * 2. Byteswap the data lanes on the way back into the CPU core.
979 */
980 if (rev && size != 4) {
981 /* Endian reverse the address. t is addr. */
982 switch (size) {
983 case 1:
984 {
985 /* 00 -> 11
986 01 -> 10
987 10 -> 10
988 11 -> 00 */
989 TCGv low = tcg_temp_new();
990
991 /* Force addr into the temp. */
992 if (addr != &t) {
993 t = tcg_temp_new();
994 tcg_gen_mov_tl(t, *addr);
995 addr = &t;
996 }
997
998 tcg_gen_andi_tl(low, t, 3);
999 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
1000 tcg_gen_andi_tl(t, t, ~3);
1001 tcg_gen_or_tl(t, t, low);
9f8beb66
EI		 1002 tcg_gen_mov_tl(env_imm, t);
1003 tcg_temp_free(low);
1004 break;
1005 }
1006
1007 case 2:
1008 /* 00 -> 10
1009 10 -> 00. */
1010 /* Force addr into the temp. */
1011 if (addr != &t) {
1012 t = tcg_temp_new();
1013 tcg_gen_xori_tl(t, *addr, 2);
1014 addr = &t;
1015 } else {
1016 tcg_gen_xori_tl(t, t, 2);
1017 }
1018 break;
1019 default:
1020 cpu_abort(dc->env, "Invalid reverse size\n");
1021 break;
1022 }
1023 }
1024
8cc9b43f
PC		 1025 /* lwx does not throw unaligned access errors, so force alignment */
1026 if (ex) {
1027 /* Force addr into the temp. */
1028 if (addr != &t) {
1029 t = tcg_temp_new();
1030 tcg_gen_mov_tl(t, *addr);
1031 addr = &t;
1032 }
1033 tcg_gen_andi_tl(t, t, ~3);
1034 }
1035
4acb54ba
EI		 1036 /* If we get a fault on a dslot, the jmpstate better be in sync. */
1037 sync_jmpstate(dc);
968a40f6
EI		 1038
1039 /* Verify alignment if needed. */
1040 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
a12f6507
EI		 1041 TCGv v = tcg_temp_new();
1042
1043 /*
1044 * Microblaze gives MMU faults priority over faults due to
1045 * unaligned addresses. That's why we speculatively do the load
1046 * into v. If the load succeeds, we verify alignment of the
1047 * address and if that succeeds we write into the destination reg.
1048 */
1049 gen_load(dc, v, *addr, size);
1050
1051 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
64254eba 1052 gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd),
3aa80988 1053 tcg_const_tl(0), tcg_const_tl(size - 1));
9f8beb66
EI		 1054 if (dc->rd) {
1055 if (rev) {
1056 dec_byteswap(dc, cpu_R[dc->rd], v, size);
1057 } else {
1058 tcg_gen_mov_tl(cpu_R[dc->rd], v);
1059 }
1060 }
a12f6507 1061 tcg_temp_free(v);
968a40f6 1062 } else {
a12f6507
EI		 1063 if (dc->rd) {
1064 gen_load(dc, cpu_R[dc->rd], *addr, size);
9f8beb66
EI		 1065 if (rev) {
1066 dec_byteswap(dc, cpu_R[dc->rd], cpu_R[dc->rd], size);
1067 }
a12f6507 1068 } else {
9f8beb66 1069 /* We are loading into r0, no need to reverse. */
a12f6507
EI		 1070 gen_load(dc, env_imm, *addr, size);
1071 }
4acb54ba
EI		 1072 }
1073
8cc9b43f
PC		 1074 if (ex) { /* lwx */
1075 /* no support for for AXI exclusive so always clear C */
1076 write_carryi(dc, 0);
1077 tcg_gen_st_tl(*addr, cpu_env, offsetof(CPUMBState, res_addr));
1078 }
1079
4acb54ba
EI		 1080 if (addr == &t)
1081 tcg_temp_free(t);
1082}
1083
1084static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
1085 unsigned int size)
1086{
1087 int mem_index = cpu_mmu_index(dc->env);
1088
1089 if (size == 1)
1090 tcg_gen_qemu_st8(val, addr, mem_index);
1091 else if (size == 2) {
1092 tcg_gen_qemu_st16(val, addr, mem_index);
1093 } else if (size == 4) {
1094 tcg_gen_qemu_st32(val, addr, mem_index);
1095 } else
1096 cpu_abort(dc->env, "Incorrect store size %d\n", size);
1097}
1098
1099static void dec_store(DisasContext *dc)
1100{
083dbf48 1101 TCGv t, *addr, swx_addr, r_check;
8cc9b43f
PC		 1102 int swx_skip = 0;
1103 unsigned int size, rev = 0, ex = 0;
4acb54ba
EI		 1104
1105 size = 1 << (dc->opcode & 3);
9f8beb66
EI		 1106 if (!dc->type_b) {
1107 rev = (dc->ir >> 9) & 1;
8cc9b43f 1108 ex = (dc->ir >> 10) & 1;
9f8beb66 1109 }
4acb54ba 1110
0187688f 1111 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
97f90cbf 1112 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
0187688f
EI		 1113 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1114 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1115 return;
1116 }
1117
8cc9b43f
PC		 1118 LOG_DIS("s%d%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "",
1119 ex ? "x" : "");
4acb54ba
EI		 1120 t_sync_flags(dc);
1121 /* If we get a fault on a dslot, the jmpstate better be in sync. */
1122 sync_jmpstate(dc);
1123 addr = compute_ldst_addr(dc, &t);
968a40f6 1124
083dbf48
PC		 1125 r_check = tcg_temp_new();
1126 swx_addr = tcg_temp_local_new();
8cc9b43f 1127 if (ex) { /* swx */
8cc9b43f
PC		 1128
1129 /* Force addr into the swx_addr. */
1130 tcg_gen_mov_tl(swx_addr, *addr);
1131 addr = &swx_addr;
1132 /* swx does not throw unaligned access errors, so force alignment */
1133 tcg_gen_andi_tl(swx_addr, swx_addr, ~3);
1134
1135 tcg_gen_ld_tl(r_check, cpu_env, offsetof(CPUMBState, res_addr));
1136 write_carryi(dc, 1);
1137 swx_skip = gen_new_label();
1138 tcg_gen_brcond_tl(TCG_COND_NE, r_check, swx_addr, swx_skip);
1139 write_carryi(dc, 0);
1140 }
1141
9f8beb66
EI		 1142 if (rev && size != 4) {
1143 /* Endian reverse the address. t is addr. */
1144 switch (size) {
1145 case 1:
1146 {
1147 /* 00 -> 11
1148 01 -> 10
1149 10 -> 10
1150 11 -> 00 */
1151 TCGv low = tcg_temp_new();
1152
1153 /* Force addr into the temp. */
1154 if (addr != &t) {
1155 t = tcg_temp_new();
1156 tcg_gen_mov_tl(t, *addr);
1157 addr = &t;
1158 }
1159
1160 tcg_gen_andi_tl(low, t, 3);
1161 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
1162 tcg_gen_andi_tl(t, t, ~3);
1163 tcg_gen_or_tl(t, t, low);
9f8beb66
EI		 1164 tcg_gen_mov_tl(env_imm, t);
1165 tcg_temp_free(low);
1166 break;
1167 }
1168
1169 case 2:
1170 /* 00 -> 10
1171 10 -> 00. */
1172 /* Force addr into the temp. */
1173 if (addr != &t) {
1174 t = tcg_temp_new();
1175 tcg_gen_xori_tl(t, *addr, 2);
1176 addr = &t;
1177 } else {
1178 tcg_gen_xori_tl(t, t, 2);
1179 }
1180 break;
1181 default:
1182 cpu_abort(dc->env, "Invalid reverse size\n");
1183 break;
1184 }
1185
1186 if (size != 1) {
1187 TCGv bs_data = tcg_temp_new();
1188 dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1189 gen_store(dc, *addr, bs_data, size);
1190 tcg_temp_free(bs_data);
1191 } else {
1192 gen_store(dc, *addr, cpu_R[dc->rd], size);
1193 }
1194 } else {
1195 if (rev) {
1196 TCGv bs_data = tcg_temp_new();
1197 dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1198 gen_store(dc, *addr, bs_data, size);
1199 tcg_temp_free(bs_data);
1200 } else {
1201 gen_store(dc, *addr, cpu_R[dc->rd], size);
1202 }
1203 }
a12f6507 1204
968a40f6
EI		 1205 /* Verify alignment if needed. */
1206 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
a12f6507
EI		 1207 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1208 /* FIXME: if the alignment is wrong, we should restore the value
4abf79a4 1209 * in memory. One possible way to achieve this is to probe
9f8beb66
EI		 1210 * the MMU prior to the memaccess, thay way we could put
1211 * the alignment checks in between the probe and the mem
1212 * access.
a12f6507 1213 */
64254eba 1214 gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd),
3aa80988 1215 tcg_const_tl(1), tcg_const_tl(size - 1));
968a40f6 1216 }
083dbf48 1217
8cc9b43f
PC		 1218 if (ex) {
1219 gen_set_label(swx_skip);
8cc9b43f 1220 }
083dbf48
PC		 1221 tcg_temp_free(r_check);
1222 tcg_temp_free(swx_addr);
968a40f6 1223
4acb54ba
EI		 1224 if (addr == &t)
1225 tcg_temp_free(t);
1226}
1227
1228static inline void eval_cc(DisasContext *dc, unsigned int cc,
1229 TCGv d, TCGv a, TCGv b)
1230{
4acb54ba
EI		 1231 switch (cc) {
1232 case CC_EQ:
b2565c69 1233 tcg_gen_setcond_tl(TCG_COND_EQ, d, a, b);
4acb54ba
EI		 1234 break;
1235 case CC_NE:
b2565c69 1236 tcg_gen_setcond_tl(TCG_COND_NE, d, a, b);
4acb54ba
EI		 1237 break;
1238 case CC_LT:
b2565c69 1239 tcg_gen_setcond_tl(TCG_COND_LT, d, a, b);
4acb54ba
EI		 1240 break;
1241 case CC_LE:
b2565c69 1242 tcg_gen_setcond_tl(TCG_COND_LE, d, a, b);
4acb54ba
EI		 1243 break;
1244 case CC_GE:
b2565c69 1245 tcg_gen_setcond_tl(TCG_COND_GE, d, a, b);
4acb54ba
EI		 1246 break;
1247 case CC_GT:
b2565c69 1248 tcg_gen_setcond_tl(TCG_COND_GT, d, a, b);
4acb54ba
EI		 1249 break;
1250 default:
1251 cpu_abort(dc->env, "Unknown condition code %x.\n", cc);
1252 break;
1253 }
1254}
1255
1256static void eval_cond_jmp(DisasContext *dc, TCGv pc_true, TCGv pc_false)
1257{
1258 int l1;
1259
1260 l1 = gen_new_label();
1261 /* Conditional jmp. */
1262 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_false);
1263 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
1264 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_true);
1265 gen_set_label(l1);
1266}
1267
1268static void dec_bcc(DisasContext *dc)
1269{
1270 unsigned int cc;
1271 unsigned int dslot;
1272
1273 cc = EXTRACT_FIELD(dc->ir, 21, 23);
1274 dslot = dc->ir & (1 << 25);
1275 LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm);
1276
1277 dc->delayed_branch = 1;
1278 if (dslot) {
1279 dc->delayed_branch = 2;
1280 dc->tb_flags |= D_FLAG;
1281 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
68cee38a 1282 cpu_env, offsetof(CPUMBState, bimm));
4acb54ba
EI		 1283 }
1284
61204ce8
EI		 1285 if (dec_alu_op_b_is_small_imm(dc)) {
1286 int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */
1287
1288 tcg_gen_movi_tl(env_btarget, dc->pc + offset);
844bab60 1289 dc->jmp = JMP_DIRECT_CC;
23979dc5 1290 dc->jmp_pc = dc->pc + offset;
61204ce8 1291 } else {
23979dc5 1292 dc->jmp = JMP_INDIRECT;
61204ce8
EI		 1293 tcg_gen_movi_tl(env_btarget, dc->pc);
1294 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
1295 }
61204ce8 1296 eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_tl(0));
4acb54ba
EI		 1297}
1298
1299static void dec_br(DisasContext *dc)
1300{
9f6113c7 1301 unsigned int dslot, link, abs, mbar;
ff21f70a 1302 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 1303
1304 dslot = dc->ir & (1 << 20);
1305 abs = dc->ir & (1 << 19);
1306 link = dc->ir & (1 << 18);
9f6113c7
EI		 1307
1308 /* Memory barrier. */
1309 mbar = (dc->ir >> 16) & 31;
1310 if (mbar == 2 && dc->imm == 4) {
5d45de97
EI		 1311 /* mbar IMM & 16 decodes to sleep. */
1312 if (dc->rd & 16) {
1313 TCGv_i32 tmp_hlt = tcg_const_i32(EXCP_HLT);
1314 TCGv_i32 tmp_1 = tcg_const_i32(1);
1315
1316 LOG_DIS("sleep\n");
1317
1318 t_sync_flags(dc);
1319 tcg_gen_st_i32(tmp_1, cpu_env,
1320 -offsetof(MicroBlazeCPU, env)
1321 +offsetof(CPUState, halted));
1322 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
1323 gen_helper_raise_exception(cpu_env, tmp_hlt);
1324 tcg_temp_free_i32(tmp_hlt);
1325 tcg_temp_free_i32(tmp_1);
1326 return;
1327 }
9f6113c7
EI		 1328 LOG_DIS("mbar %d\n", dc->rd);
1329 /* Break the TB. */
1330 dc->cpustate_changed = 1;
1331 return;
1332 }
1333
4acb54ba
EI		 1334 LOG_DIS("br%s%s%s%s imm=%x\n",
1335 abs ? "a" : "", link ? "l" : "",
1336 dc->type_b ? "i" : "", dslot ? "d" : "",
1337 dc->imm);
1338
1339 dc->delayed_branch = 1;
1340 if (dslot) {
1341 dc->delayed_branch = 2;
1342 dc->tb_flags |= D_FLAG;
1343 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
68cee38a 1344 cpu_env, offsetof(CPUMBState, bimm));
4acb54ba
EI		 1345 }
1346 if (link && dc->rd)
1347 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
1348
1349 dc->jmp = JMP_INDIRECT;
1350 if (abs) {
1351 tcg_gen_movi_tl(env_btaken, 1);
1352 tcg_gen_mov_tl(env_btarget, *(dec_alu_op_b(dc)));
ff21f70a
EI		 1353 if (link && !dslot) {
1354 if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18))
1355 t_gen_raise_exception(dc, EXCP_BREAK);
1356 if (dc->imm == 0) {
1357 if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) {
1358 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1359 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1360 return;
1361 }
1362
1363 t_gen_raise_exception(dc, EXCP_DEBUG);
1364 }
1365 }
4acb54ba 1366 } else {
61204ce8
EI		 1367 if (dec_alu_op_b_is_small_imm(dc)) {
1368 dc->jmp = JMP_DIRECT;
1369 dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm);
1370 } else {
4acb54ba
EI		 1371 tcg_gen_movi_tl(env_btaken, 1);
1372 tcg_gen_movi_tl(env_btarget, dc->pc);
1373 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
4acb54ba
EI		 1374 }
1375 }
1376}
1377
1378static inline void do_rti(DisasContext *dc)
1379{
1380 TCGv t0, t1;
1381 t0 = tcg_temp_new();
1382 t1 = tcg_temp_new();
1383 tcg_gen_shri_tl(t0, cpu_SR[SR_MSR], 1);
1384 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_IE);
1385 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1386
1387 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1388 tcg_gen_or_tl(t1, t1, t0);
1389 msr_write(dc, t1);
1390 tcg_temp_free(t1);
1391 tcg_temp_free(t0);
1392 dc->tb_flags &= ~DRTI_FLAG;
1393}
1394
1395static inline void do_rtb(DisasContext *dc)
1396{
1397 TCGv t0, t1;
1398 t0 = tcg_temp_new();
1399 t1 = tcg_temp_new();
1400 tcg_gen_andi_tl(t1, cpu_SR[SR_MSR], ~MSR_BIP);
1401 tcg_gen_shri_tl(t0, t1, 1);
1402 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1403
1404 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1405 tcg_gen_or_tl(t1, t1, t0);
1406 msr_write(dc, t1);
1407 tcg_temp_free(t1);
1408 tcg_temp_free(t0);
1409 dc->tb_flags &= ~DRTB_FLAG;
1410}
1411
1412static inline void do_rte(DisasContext *dc)
1413{
1414 TCGv t0, t1;
1415 t0 = tcg_temp_new();
1416 t1 = tcg_temp_new();
1417
1418 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_EE);
1419 tcg_gen_andi_tl(t1, t1, ~MSR_EIP);
1420 tcg_gen_shri_tl(t0, t1, 1);
1421 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1422
1423 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1424 tcg_gen_or_tl(t1, t1, t0);
1425 msr_write(dc, t1);
1426 tcg_temp_free(t1);
1427 tcg_temp_free(t0);
1428 dc->tb_flags &= ~DRTE_FLAG;
1429}
1430
1431static void dec_rts(DisasContext *dc)
1432{
1433 unsigned int b_bit, i_bit, e_bit;
1567a005 1434 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 1435
1436 i_bit = dc->ir & (1 << 21);
1437 b_bit = dc->ir & (1 << 22);
1438 e_bit = dc->ir & (1 << 23);
1439
1440 dc->delayed_branch = 2;
1441 dc->tb_flags |= D_FLAG;
1442 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
68cee38a 1443 cpu_env, offsetof(CPUMBState, bimm));
4acb54ba
EI		 1444
1445 if (i_bit) {
1446 LOG_DIS("rtid ir=%x\n", dc->ir);
1567a005
EI		 1447 if ((dc->tb_flags & MSR_EE_FLAG)
1448 && mem_index == MMU_USER_IDX) {
1449 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1450 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1451 }
4acb54ba
EI		 1452 dc->tb_flags |= DRTI_FLAG;
1453 } else if (b_bit) {
1454 LOG_DIS("rtbd ir=%x\n", dc->ir);
1567a005
EI		 1455 if ((dc->tb_flags & MSR_EE_FLAG)
1456 && mem_index == MMU_USER_IDX) {
1457 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1458 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1459 }
4acb54ba
EI		 1460 dc->tb_flags |= DRTB_FLAG;
1461 } else if (e_bit) {
1462 LOG_DIS("rted ir=%x\n", dc->ir);
1567a005
EI		 1463 if ((dc->tb_flags & MSR_EE_FLAG)
1464 && mem_index == MMU_USER_IDX) {
1465 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1466 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1467 }
4acb54ba
EI		 1468 dc->tb_flags |= DRTE_FLAG;
1469 } else
1470 LOG_DIS("rts ir=%x\n", dc->ir);
1471
23979dc5 1472 dc->jmp = JMP_INDIRECT;
4acb54ba
EI		 1473 tcg_gen_movi_tl(env_btaken, 1);
1474 tcg_gen_add_tl(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
1475}
1476
97694c57
EI		 1477static int dec_check_fpuv2(DisasContext *dc)
1478{
1479 int r;
1480
1481 r = dc->env->pvr.regs[2] & PVR2_USE_FPU2_MASK;
1482
1483 if (!r && (dc->tb_flags & MSR_EE_FLAG)) {
1484 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
1485 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1486 }
1487 return r;
1488}
1489
1567a005
EI		 1490static void dec_fpu(DisasContext *dc)
1491{
97694c57
EI		 1492 unsigned int fpu_insn;
1493
1567a005 1494 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 1495 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005 1496 && !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) {
97694c57 1497 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1567a005
EI		 1498 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1499 return;
1500 }
1501
97694c57
EI		 1502 fpu_insn = (dc->ir >> 7) & 7;
1503
1504 switch (fpu_insn) {
1505 case 0:
64254eba
BS		 1506 gen_helper_fadd(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1507 cpu_R[dc->rb]);
97694c57
EI		 1508 break;
1509
1510 case 1:
64254eba
BS		 1511 gen_helper_frsub(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1512 cpu_R[dc->rb]);
97694c57
EI		 1513 break;
1514
1515 case 2:
64254eba
BS		 1516 gen_helper_fmul(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1517 cpu_R[dc->rb]);
97694c57
EI		 1518 break;
1519
1520 case 3:
64254eba
BS		 1521 gen_helper_fdiv(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1522 cpu_R[dc->rb]);
97694c57
EI		 1523 break;
1524
1525 case 4:
1526 switch ((dc->ir >> 4) & 7) {
1527 case 0:
64254eba 1528 gen_helper_fcmp_un(cpu_R[dc->rd], cpu_env,
97694c57
EI		 1529 cpu_R[dc->ra], cpu_R[dc->rb]);
1530 break;
1531 case 1:
64254eba 1532 gen_helper_fcmp_lt(cpu_R[dc->rd], cpu_env,
97694c57
EI		 1533 cpu_R[dc->ra], cpu_R[dc->rb]);
1534 break;
1535 case 2:
64254eba 1536 gen_helper_fcmp_eq(cpu_R[dc->rd], cpu_env,
97694c57
EI		 1537 cpu_R[dc->ra], cpu_R[dc->rb]);
1538 break;
1539 case 3:
64254eba 1540 gen_helper_fcmp_le(cpu_R[dc->rd], cpu_env,
97694c57
EI		 1541 cpu_R[dc->ra], cpu_R[dc->rb]);
1542 break;
1543 case 4:
64254eba 1544 gen_helper_fcmp_gt(cpu_R[dc->rd], cpu_env,
97694c57
EI		 1545 cpu_R[dc->ra], cpu_R[dc->rb]);
1546 break;
1547 case 5:
64254eba 1548 gen_helper_fcmp_ne(cpu_R[dc->rd], cpu_env,
97694c57
EI		 1549 cpu_R[dc->ra], cpu_R[dc->rb]);
1550 break;
1551 case 6:
64254eba 1552 gen_helper_fcmp_ge(cpu_R[dc->rd], cpu_env,
97694c57
EI		 1553 cpu_R[dc->ra], cpu_R[dc->rb]);
1554 break;
1555 default:
71547a3b
BS		 1556 qemu_log_mask(LOG_UNIMP,
1557 "unimplemented fcmp fpu_insn=%x pc=%x"
1558 " opc=%x\n",
1559 fpu_insn, dc->pc, dc->opcode);
97694c57
EI		 1560 dc->abort_at_next_insn = 1;
1561 break;
1562 }
1563 break;
1564
1565 case 5:
1566 if (!dec_check_fpuv2(dc)) {
1567 return;
1568 }
64254eba 1569 gen_helper_flt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
97694c57
EI		 1570 break;
1571
1572 case 6:
1573 if (!dec_check_fpuv2(dc)) {
1574 return;
1575 }
64254eba 1576 gen_helper_fint(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
97694c57
EI		 1577 break;
1578
1579 case 7:
1580 if (!dec_check_fpuv2(dc)) {
1581 return;
1582 }
64254eba 1583 gen_helper_fsqrt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
97694c57
EI		 1584 break;
1585
1586 default:
71547a3b
BS		 1587 qemu_log_mask(LOG_UNIMP, "unimplemented FPU insn fpu_insn=%x pc=%x"
1588 " opc=%x\n",
1589 fpu_insn, dc->pc, dc->opcode);
97694c57
EI		 1590 dc->abort_at_next_insn = 1;
1591 break;
1592 }
1567a005
EI		 1593}
1594
4acb54ba
EI		 1595static void dec_null(DisasContext *dc)
1596{
02b33596
EI		 1597 if ((dc->tb_flags & MSR_EE_FLAG)
1598 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
1599 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1600 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1601 return;
1602 }
4acb54ba
EI		 1603 qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
1604 dc->abort_at_next_insn = 1;
1605}
1606
6d76d23e
EI		 1607/* Insns connected to FSL or AXI stream attached devices. */
1608static void dec_stream(DisasContext *dc)
1609{
1610 int mem_index = cpu_mmu_index(dc->env);
1611 TCGv_i32 t_id, t_ctrl;
1612 int ctrl;
1613
1614 LOG_DIS("%s%s imm=%x\n", dc->rd ? "get" : "put",
1615 dc->type_b ? "" : "d", dc->imm);
1616
1617 if ((dc->tb_flags & MSR_EE_FLAG) && (mem_index == MMU_USER_IDX)) {
1618 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1619 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1620 return;
1621 }
1622
1623 t_id = tcg_temp_new();
1624 if (dc->type_b) {
1625 tcg_gen_movi_tl(t_id, dc->imm & 0xf);
1626 ctrl = dc->imm >> 10;
1627 } else {
1628 tcg_gen_andi_tl(t_id, cpu_R[dc->rb], 0xf);
1629 ctrl = dc->imm >> 5;
1630 }
1631
1632 t_ctrl = tcg_const_tl(ctrl);
1633
1634 if (dc->rd == 0) {
1635 gen_helper_put(t_id, t_ctrl, cpu_R[dc->ra]);
1636 } else {
1637 gen_helper_get(cpu_R[dc->rd], t_id, t_ctrl);
1638 }
1639 tcg_temp_free(t_id);
1640 tcg_temp_free(t_ctrl);
1641}
1642
4acb54ba
EI		 1643static struct decoder_info {
1644 struct {
1645 uint32_t bits;
1646 uint32_t mask;
1647 };
1648 void (*dec)(DisasContext *dc);
1649} decinfo[] = {
1650 {DEC_ADD, dec_add},
1651 {DEC_SUB, dec_sub},
1652 {DEC_AND, dec_and},
1653 {DEC_XOR, dec_xor},
1654 {DEC_OR, dec_or},
1655 {DEC_BIT, dec_bit},
1656 {DEC_BARREL, dec_barrel},
1657 {DEC_LD, dec_load},
1658 {DEC_ST, dec_store},
1659 {DEC_IMM, dec_imm},
1660 {DEC_BR, dec_br},
1661 {DEC_BCC, dec_bcc},
1662 {DEC_RTS, dec_rts},
1567a005 1663 {DEC_FPU, dec_fpu},
4acb54ba
EI		 1664 {DEC_MUL, dec_mul},
1665 {DEC_DIV, dec_div},
1666 {DEC_MSR, dec_msr},
6d76d23e 1667 {DEC_STREAM, dec_stream},
4acb54ba
EI		 1668 {{0, 0}, dec_null}
1669};
1670
64254eba 1671static inline void decode(DisasContext *dc, uint32_t ir)
4acb54ba 1672{
4acb54ba
EI		 1673 int i;
1674
fdefe51c 1675 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
4acb54ba 1676 tcg_gen_debug_insn_start(dc->pc);
fdefe51c 1677 }
4acb54ba 1678
64254eba 1679 dc->ir = ir;
4acb54ba
EI		 1680 LOG_DIS("%8.8x\t", dc->ir);
1681
1682 if (dc->ir)
1683 dc->nr_nops = 0;
1684 else {
1567a005 1685 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf
EI		 1686 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1687 && (dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
1567a005
EI		 1688 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1689 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1690 return;
1691 }
1692
4acb54ba
EI		 1693 LOG_DIS("nr_nops=%d\t", dc->nr_nops);
1694 dc->nr_nops++;
1695 if (dc->nr_nops > 4)
1696 cpu_abort(dc->env, "fetching nop sequence\n");
1697 }
1698 /* bit 2 seems to indicate insn type. */
1699 dc->type_b = ir & (1 << 29);
1700
1701 dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1702 dc->rd = EXTRACT_FIELD(ir, 21, 25);
1703 dc->ra = EXTRACT_FIELD(ir, 16, 20);
1704 dc->rb = EXTRACT_FIELD(ir, 11, 15);
1705 dc->imm = EXTRACT_FIELD(ir, 0, 15);
1706
1707 /* Large switch for all insns. */
1708 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
1709 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
1710 decinfo[i].dec(dc);
1711 break;
1712 }
1713 }
1714}
1715
68cee38a 1716static void check_breakpoint(CPUMBState *env, DisasContext *dc)
4acb54ba
EI		 1717{
1718 CPUBreakpoint *bp;
1719
72cf2d4f
BS		 1720 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1721 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
4acb54ba
EI		 1722 if (bp->pc == dc->pc) {
1723 t_gen_raise_exception(dc, EXCP_DEBUG);
1724 dc->is_jmp = DISAS_UPDATE;
1725 }
1726 }
1727 }
1728}
1729
1730/* generate intermediate code for basic block 'tb'. */
fd327f48 1731static inline void
4a274212
AF		 1732gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
1733 bool search_pc)
4acb54ba 1734{
ed2803da 1735 CPUState *cs = CPU(cpu);
4a274212 1736 CPUMBState *env = &cpu->env;
4acb54ba
EI		 1737 uint16_t *gen_opc_end;
1738 uint32_t pc_start;
1739 int j, lj;
1740 struct DisasContext ctx;
1741 struct DisasContext *dc = &ctx;
1742 uint32_t next_page_start, org_flags;
1743 target_ulong npc;
1744 int num_insns;
1745 int max_insns;
1746
4acb54ba
EI		 1747 pc_start = tb->pc;
1748 dc->env = env;
1749 dc->tb = tb;
1750 org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
1751
92414b31 1752 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
4acb54ba
EI		 1753
1754 dc->is_jmp = DISAS_NEXT;
1755 dc->jmp = 0;
1756 dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
23979dc5
EI		 1757 if (dc->delayed_branch) {
1758 dc->jmp = JMP_INDIRECT;
1759 }
4acb54ba 1760 dc->pc = pc_start;
ed2803da 1761 dc->singlestep_enabled = cs->singlestep_enabled;
4acb54ba
EI		 1762 dc->cpustate_changed = 0;
1763 dc->abort_at_next_insn = 0;
1764 dc->nr_nops = 0;
1765
1766 if (pc_start & 3)
1767 cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start);
1768
1769 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1770#if !SIM_COMPAT
1771 qemu_log("--------------\n");
a0762859 1772 log_cpu_state(CPU(cpu), 0);
4acb54ba
EI		 1773#endif
1774 }
1775
1776 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1777 lj = -1;
1778 num_insns = 0;
1779 max_insns = tb->cflags & CF_COUNT_MASK;
1780 if (max_insns == 0)
1781 max_insns = CF_COUNT_MASK;
1782
806f352d 1783 gen_tb_start();
4acb54ba
EI		 1784 do
1785 {
1786#if SIM_COMPAT
1787 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1788 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1789 gen_helper_debug();
1790 }
1791#endif
1792 check_breakpoint(env, dc);
1793
1794 if (search_pc) {
92414b31 1795 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4acb54ba
EI		 1796 if (lj < j) {
1797 lj++;
1798 while (lj < j)
ab1103de 1799 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4acb54ba 1800 }
25983cad 1801 tcg_ctx.gen_opc_pc[lj] = dc->pc;
ab1103de 1802 tcg_ctx.gen_opc_instr_start[lj] = 1;
c9c99c22 1803 tcg_ctx.gen_opc_icount[lj] = num_insns;
4acb54ba
EI		 1804 }
1805
1806 /* Pretty disas. */
1807 LOG_DIS("%8.8x:\t", dc->pc);
1808
1809 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1810 gen_io_start();
1811
1812 dc->clear_imm = 1;
64254eba 1813 decode(dc, cpu_ldl_code(env, dc->pc));
4acb54ba
EI		 1814 if (dc->clear_imm)
1815 dc->tb_flags &= ~IMM_FLAG;
4acb54ba
EI		 1816 dc->pc += 4;
1817 num_insns++;
1818
1819 if (dc->delayed_branch) {
1820 dc->delayed_branch--;
1821 if (!dc->delayed_branch) {
1822 if (dc->tb_flags & DRTI_FLAG)
1823 do_rti(dc);
1824 if (dc->tb_flags & DRTB_FLAG)
1825 do_rtb(dc);
1826 if (dc->tb_flags & DRTE_FLAG)
1827 do_rte(dc);
1828 /* Clear the delay slot flag. */
1829 dc->tb_flags &= ~D_FLAG;
1830 /* If it is a direct jump, try direct chaining. */
23979dc5 1831 if (dc->jmp == JMP_INDIRECT) {
4acb54ba
EI		 1832 eval_cond_jmp(dc, env_btarget, tcg_const_tl(dc->pc));
1833 dc->is_jmp = DISAS_JUMP;
23979dc5 1834 } else if (dc->jmp == JMP_DIRECT) {
844bab60
EI		 1835 t_sync_flags(dc);
1836 gen_goto_tb(dc, 0, dc->jmp_pc);
1837 dc->is_jmp = DISAS_TB_JUMP;
1838 } else if (dc->jmp == JMP_DIRECT_CC) {
23979dc5
EI		 1839 int l1;
1840
1841 t_sync_flags(dc);
1842 l1 = gen_new_label();
1843 /* Conditional jmp. */
1844 tcg_gen_brcondi_tl(TCG_COND_NE, env_btaken, 0, l1);
1845 gen_goto_tb(dc, 1, dc->pc);
1846 gen_set_label(l1);
1847 gen_goto_tb(dc, 0, dc->jmp_pc);
1848
1849 dc->is_jmp = DISAS_TB_JUMP;
4acb54ba
EI		 1850 }
1851 break;
1852 }
1853 }
ed2803da 1854 if (cs->singlestep_enabled) {
4acb54ba 1855 break;
ed2803da 1856 }
4acb54ba 1857 } while (!dc->is_jmp && !dc->cpustate_changed
efd7f486 1858 && tcg_ctx.gen_opc_ptr < gen_opc_end
4acb54ba
EI		 1859 && !singlestep
1860 && (dc->pc < next_page_start)
1861 && num_insns < max_insns);
1862
1863 npc = dc->pc;
844bab60 1864 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
4acb54ba
EI		 1865 if (dc->tb_flags & D_FLAG) {
1866 dc->is_jmp = DISAS_UPDATE;
1867 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1868 sync_jmpstate(dc);
1869 } else
1870 npc = dc->jmp_pc;
1871 }
1872
1873 if (tb->cflags & CF_LAST_IO)
1874 gen_io_end();
1875 /* Force an update if the per-tb cpu state has changed. */
1876 if (dc->is_jmp == DISAS_NEXT
1877 && (dc->cpustate_changed || org_flags != dc->tb_flags)) {
1878 dc->is_jmp = DISAS_UPDATE;
1879 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1880 }
1881 t_sync_flags(dc);
1882
ed2803da 1883 if (unlikely(cs->singlestep_enabled)) {
6c5f738d
EI		 1884 TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
1885
1886 if (dc->is_jmp != DISAS_JUMP) {
4acb54ba 1887 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
6c5f738d 1888 }
64254eba 1889 gen_helper_raise_exception(cpu_env, tmp);
6c5f738d 1890 tcg_temp_free_i32(tmp);
4acb54ba
EI		 1891 } else {
1892 switch(dc->is_jmp) {
1893 case DISAS_NEXT:
1894 gen_goto_tb(dc, 1, npc);
1895 break;
1896 default:
1897 case DISAS_JUMP:
1898 case DISAS_UPDATE:
1899 /* indicate that the hash table must be used
1900 to find the next TB */
1901 tcg_gen_exit_tb(0);
1902 break;
1903 case DISAS_TB_JUMP:
1904 /* nothing more to generate */
1905 break;
1906 }
1907 }
806f352d 1908 gen_tb_end(tb, num_insns);
efd7f486 1909 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
4acb54ba 1910 if (search_pc) {
92414b31 1911 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4acb54ba
EI		 1912 lj++;
1913 while (lj <= j)
ab1103de 1914 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4acb54ba
EI		 1915 } else {
1916 tb->size = dc->pc - pc_start;
1917 tb->icount = num_insns;
1918 }
1919
1920#ifdef DEBUG_DISAS
1921#if !SIM_COMPAT
1922 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1923 qemu_log("\n");
1924#if DISAS_GNU
f4359b9f 1925 log_target_disas(env, pc_start, dc->pc - pc_start, 0);
4acb54ba 1926#endif
e6aa0f11 1927 qemu_log("\nisize=%d osize=%td\n",
92414b31
EV		 1928 dc->pc - pc_start, tcg_ctx.gen_opc_ptr -
1929 tcg_ctx.gen_opc_buf);
4acb54ba
EI		 1930 }
1931#endif
1932#endif
1933 assert(!dc->abort_at_next_insn);
1934}
1935
68cee38a 1936void gen_intermediate_code (CPUMBState *env, struct TranslationBlock *tb)
4acb54ba 1937{
4a274212 1938 gen_intermediate_code_internal(mb_env_get_cpu(env), tb, false);
4acb54ba
EI		 1939}
1940
68cee38a 1941void gen_intermediate_code_pc (CPUMBState *env, struct TranslationBlock *tb)
4acb54ba 1942{
4a274212 1943 gen_intermediate_code_internal(mb_env_get_cpu(env), tb, true);
4acb54ba
EI		 1944}
1945
878096ee
AF		 1946void mb_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
1947 int flags)
4acb54ba 1948{
878096ee
AF		 1949 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
1950 CPUMBState *env = &cpu->env;
4acb54ba
EI		 1951 int i;
1952
1953 if (!env || !f)
1954 return;
1955
1956 cpu_fprintf(f, "IN: PC=%x %s\n",
1957 env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC]));
97694c57 1958 cpu_fprintf(f, "rmsr=%x resr=%x rear=%x debug=%x imm=%x iflags=%x fsr=%x\n",
4c24aa0a 1959 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
97694c57 1960 env->debug, env->imm, env->iflags, env->sregs[SR_FSR]);
17c52a43 1961 cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
4acb54ba
EI		 1962 env->btaken, env->btarget,
1963 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
17c52a43
EI		 1964 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
1965 (env->sregs[SR_MSR] & MSR_EIP),
1966 (env->sregs[SR_MSR] & MSR_IE));
1967
4acb54ba
EI		 1968 for (i = 0; i < 32; i++) {
1969 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1970 if ((i + 1) % 4 == 0)
1971 cpu_fprintf(f, "\n");
1972 }
1973 cpu_fprintf(f, "\n\n");
1974}
1975
b33ab1f7 1976MicroBlazeCPU *cpu_mb_init(const char *cpu_model)
4acb54ba 1977{
b77f98ca 1978 MicroBlazeCPU *cpu;
4acb54ba 1979
b77f98ca 1980 cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
4acb54ba 1981
746b03b2 1982 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
4acb54ba 1983
cd0c24f9
AF		 1984 return cpu;
1985}
4acb54ba 1986
cd0c24f9
AF		 1987void mb_tcg_init(void)
1988{
1989 int i;
4acb54ba
EI		 1990
1991 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1992
1993 env_debug = tcg_global_mem_new(TCG_AREG0,
68cee38a 1994 offsetof(CPUMBState, debug),
4acb54ba
EI		 1995 "debug0");
1996 env_iflags = tcg_global_mem_new(TCG_AREG0,
68cee38a 1997 offsetof(CPUMBState, iflags),
4acb54ba
EI		 1998 "iflags");
1999 env_imm = tcg_global_mem_new(TCG_AREG0,
68cee38a 2000 offsetof(CPUMBState, imm),
4acb54ba
EI		 2001 "imm");
2002 env_btarget = tcg_global_mem_new(TCG_AREG0,
68cee38a 2003 offsetof(CPUMBState, btarget),
4acb54ba
EI		 2004 "btarget");
2005 env_btaken = tcg_global_mem_new(TCG_AREG0,
68cee38a 2006 offsetof(CPUMBState, btaken),
4acb54ba
EI		 2007 "btaken");
2008 for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
2009 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
68cee38a 2010 offsetof(CPUMBState, regs[i]),
4acb54ba
EI		 2011 regnames[i]);
2012 }
2013 for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) {
2014 cpu_SR[i] = tcg_global_mem_new(TCG_AREG0,
68cee38a 2015 offsetof(CPUMBState, sregs[i]),
4acb54ba
EI		 2016 special_regnames[i]);
2017 }
4acb54ba
EI		 2018}
2019
68cee38a 2020void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, int pc_pos)
4acb54ba 2021{
25983cad 2022 env->sregs[SR_PC] = tcg_ctx.gen_opc_pc[pc_pos];
4acb54ba 2023}
Qemu copy for testing