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microblaze: Add support for the clz insn
[qemu.git] / target-microblaze / translate.c
CommitLineData
4acb54ba
EI		 1/*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba
EI		 18 */
19
20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25#include <assert.h>
26
27#include "cpu.h"
4acb54ba
EI		 28#include "disas.h"
29#include "tcg-op.h"
30#include "helper.h"
31#include "microblaze-decode.h"
32#include "qemu-common.h"
33
34#define GEN_HELPER 1
35#include "helper.h"
36
37#define SIM_COMPAT 0
38#define DISAS_GNU 1
39#define DISAS_MB 1
40#if DISAS_MB && !SIM_COMPAT
41# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
42#else
43# define LOG_DIS(...) do { } while (0)
44#endif
45
46#define D(x)
47
48#define EXTRACT_FIELD(src, start, end) \
49 (((src) >> start) & ((1 << (end - start + 1)) - 1))
50
51static TCGv env_debug;
52static TCGv_ptr cpu_env;
53static TCGv cpu_R[32];
54static TCGv cpu_SR[18];
55static TCGv env_imm;
56static TCGv env_btaken;
57static TCGv env_btarget;
58static TCGv env_iflags;
59
60#include "gen-icount.h"
61
62/* This is the state at translation time. */
63typedef struct DisasContext {
64 CPUState *env;
a5efa644 65 target_ulong pc;
4acb54ba
EI		 66
67 /* Decoder. */
68 int type_b;
69 uint32_t ir;
70 uint8_t opcode;
71 uint8_t rd, ra, rb;
72 uint16_t imm;
73
74 unsigned int cpustate_changed;
75 unsigned int delayed_branch;
76 unsigned int tb_flags, synced_flags; /* tb dependent flags. */
77 unsigned int clear_imm;
78 int is_jmp;
79
844bab60
EI		 80#define JMP_NOJMP 0
81#define JMP_DIRECT 1
82#define JMP_DIRECT_CC 2
83#define JMP_INDIRECT 3
4acb54ba
EI		 84 unsigned int jmp;
85 uint32_t jmp_pc;
86
87 int abort_at_next_insn;
88 int nr_nops;
89 struct TranslationBlock *tb;
90 int singlestep_enabled;
91} DisasContext;
92
38972938 93static const char *regnames[] =
4acb54ba
EI		 94{
95 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
96 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
97 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
98 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
99};
100
38972938 101static const char *special_regnames[] =
4acb54ba
EI		 102{
103 "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
104 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
105 "sr16", "sr17", "sr18"
106};
107
108/* Sign extend at translation time. */
109static inline int sign_extend(unsigned int val, unsigned int width)
110{
111 int sval;
112
113 /* LSL. */
114 val <<= 31 - width;
115 sval = val;
116 /* ASR. */
117 sval >>= 31 - width;
118 return sval;
119}
120
121static inline void t_sync_flags(DisasContext *dc)
122{
4abf79a4 123 /* Synch the tb dependent flags between translator and runtime. */
4acb54ba
EI		 124 if (dc->tb_flags != dc->synced_flags) {
125 tcg_gen_movi_tl(env_iflags, dc->tb_flags);
126 dc->synced_flags = dc->tb_flags;
127 }
128}
129
130static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
131{
132 TCGv_i32 tmp = tcg_const_i32(index);
133
134 t_sync_flags(dc);
135 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
136 gen_helper_raise_exception(tmp);
137 tcg_temp_free_i32(tmp);
138 dc->is_jmp = DISAS_UPDATE;
139}
140
141static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
142{
143 TranslationBlock *tb;
144 tb = dc->tb;
145 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
146 tcg_gen_goto_tb(n);
147 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
4b4a72e5 148 tcg_gen_exit_tb((tcg_target_long)tb + n);
4acb54ba
EI		 149 } else {
150 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
151 tcg_gen_exit_tb(0);
152 }
153}
154
ee8b246f
EI		 155static void read_carry(DisasContext *dc, TCGv d)
156{
157 tcg_gen_shri_tl(d, cpu_SR[SR_MSR], 31);
158}
159
160static void write_carry(DisasContext *dc, TCGv v)
161{
162 TCGv t0 = tcg_temp_new();
163 tcg_gen_shli_tl(t0, v, 31);
164 tcg_gen_sari_tl(t0, t0, 31);
165 tcg_gen_andi_tl(t0, t0, (MSR_C | MSR_CC));
166 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR],
167 ~(MSR_C | MSR_CC));
168 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0);
169 tcg_temp_free(t0);
170}
171
61204ce8
EI		 172/* True if ALU operand b is a small immediate that may deserve
173 faster treatment. */
174static inline int dec_alu_op_b_is_small_imm(DisasContext *dc)
175{
176 /* Immediate insn without the imm prefix ? */
177 return dc->type_b && !(dc->tb_flags & IMM_FLAG);
178}
179
4acb54ba
EI		 180static inline TCGv *dec_alu_op_b(DisasContext *dc)
181{
182 if (dc->type_b) {
183 if (dc->tb_flags & IMM_FLAG)
184 tcg_gen_ori_tl(env_imm, env_imm, dc->imm);
185 else
186 tcg_gen_movi_tl(env_imm, (int32_t)((int16_t)dc->imm));
187 return &env_imm;
188 } else
189 return &cpu_R[dc->rb];
190}
191
192static void dec_add(DisasContext *dc)
193{
194 unsigned int k, c;
40cbf5b7 195 TCGv cf;
4acb54ba
EI		 196
197 k = dc->opcode & 4;
198 c = dc->opcode & 2;
199
200 LOG_DIS("add%s%s%s r%d r%d r%d\n",
201 dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "",
202 dc->rd, dc->ra, dc->rb);
203
40cbf5b7
EI		 204 /* Take care of the easy cases first. */
205 if (k) {
206 /* k - keep carry, no need to update MSR. */
207 /* If rd == r0, it's a nop. */
208 if (dc->rd) {
209 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
210
211 if (c) {
212 /* c - Add carry into the result. */
213 cf = tcg_temp_new();
214
215 read_carry(dc, cf);
216 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
217 tcg_temp_free(cf);
218 }
219 }
220 return;
221 }
222
223 /* From now on, we can assume k is zero. So we need to update MSR. */
224 /* Extract carry. */
225 cf = tcg_temp_new();
226 if (c) {
227 read_carry(dc, cf);
228 } else {
229 tcg_gen_movi_tl(cf, 0);
230 }
231
232 if (dc->rd) {
233 TCGv ncf = tcg_temp_new();
5d0bb823 234 gen_helper_carry(ncf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf);
4acb54ba 235 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
40cbf5b7
EI		 236 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
237 write_carry(dc, ncf);
238 tcg_temp_free(ncf);
239 } else {
5d0bb823 240 gen_helper_carry(cf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf);
40cbf5b7 241 write_carry(dc, cf);
4acb54ba 242 }
40cbf5b7 243 tcg_temp_free(cf);
4acb54ba
EI		 244}
245
246static void dec_sub(DisasContext *dc)
247{
248 unsigned int u, cmp, k, c;
e0a42ebc 249 TCGv cf, na;
4acb54ba
EI		 250
251 u = dc->imm & 2;
252 k = dc->opcode & 4;
253 c = dc->opcode & 2;
254 cmp = (dc->imm & 1) && (!dc->type_b) && k;
255
256 if (cmp) {
257 LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir);
258 if (dc->rd) {
259 if (u)
260 gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
261 else
262 gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
263 }
e0a42ebc
EI		 264 return;
265 }
266
267 LOG_DIS("sub%s%s r%d, r%d r%d\n",
268 k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb);
269
270 /* Take care of the easy cases first. */
271 if (k) {
272 /* k - keep carry, no need to update MSR. */
273 /* If rd == r0, it's a nop. */
274 if (dc->rd) {
4acb54ba 275 tcg_gen_sub_tl(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
e0a42ebc
EI		 276
277 if (c) {
278 /* c - Add carry into the result. */
279 cf = tcg_temp_new();
280
281 read_carry(dc, cf);
282 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
283 tcg_temp_free(cf);
284 }
285 }
286 return;
287 }
288
289 /* From now on, we can assume k is zero. So we need to update MSR. */
290 /* Extract carry. And complement a into na. */
291 cf = tcg_temp_new();
292 na = tcg_temp_new();
293 if (c) {
294 read_carry(dc, cf);
295 } else {
296 tcg_gen_movi_tl(cf, 1);
297 }
298
299 /* d = b + ~a + c. carry defaults to 1. */
300 tcg_gen_not_tl(na, cpu_R[dc->ra]);
301
302 if (dc->rd) {
303 TCGv ncf = tcg_temp_new();
5d0bb823 304 gen_helper_carry(ncf, na, *(dec_alu_op_b(dc)), cf);
e0a42ebc
EI		 305 tcg_gen_add_tl(cpu_R[dc->rd], na, *(dec_alu_op_b(dc)));
306 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
307 write_carry(dc, ncf);
308 tcg_temp_free(ncf);
309 } else {
5d0bb823 310 gen_helper_carry(cf, na, *(dec_alu_op_b(dc)), cf);
e0a42ebc 311 write_carry(dc, cf);
4acb54ba 312 }
e0a42ebc
EI		 313 tcg_temp_free(cf);
314 tcg_temp_free(na);
4acb54ba
EI		 315}
316
317static void dec_pattern(DisasContext *dc)
318{
319 unsigned int mode;
320 int l1;
321
1567a005 322 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 323 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 324 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
325 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
326 t_gen_raise_exception(dc, EXCP_HW_EXCP);
327 }
328
4acb54ba
EI		 329 mode = dc->opcode & 3;
330 switch (mode) {
331 case 0:
332 /* pcmpbf. */
333 LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
334 if (dc->rd)
335 gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
336 break;
337 case 2:
338 LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
339 if (dc->rd) {
340 TCGv t0 = tcg_temp_local_new();
341 l1 = gen_new_label();
342 tcg_gen_movi_tl(t0, 1);
343 tcg_gen_brcond_tl(TCG_COND_EQ,
344 cpu_R[dc->ra], cpu_R[dc->rb], l1);
345 tcg_gen_movi_tl(t0, 0);
346 gen_set_label(l1);
347 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
348 tcg_temp_free(t0);
349 }
350 break;
351 case 3:
352 LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
353 l1 = gen_new_label();
354 if (dc->rd) {
355 TCGv t0 = tcg_temp_local_new();
356 tcg_gen_movi_tl(t0, 1);
357 tcg_gen_brcond_tl(TCG_COND_NE,
358 cpu_R[dc->ra], cpu_R[dc->rb], l1);
359 tcg_gen_movi_tl(t0, 0);
360 gen_set_label(l1);
361 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
362 tcg_temp_free(t0);
363 }
364 break;
365 default:
366 cpu_abort(dc->env,
367 "unsupported pattern insn opcode=%x\n", dc->opcode);
368 break;
369 }
370}
371
372static void dec_and(DisasContext *dc)
373{
374 unsigned int not;
375
376 if (!dc->type_b && (dc->imm & (1 << 10))) {
377 dec_pattern(dc);
378 return;
379 }
380
381 not = dc->opcode & (1 << 1);
382 LOG_DIS("and%s\n", not ? "n" : "");
383
384 if (!dc->rd)
385 return;
386
387 if (not) {
388 TCGv t = tcg_temp_new();
389 tcg_gen_not_tl(t, *(dec_alu_op_b(dc)));
390 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], t);
391 tcg_temp_free(t);
392 } else
393 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
394}
395
396static void dec_or(DisasContext *dc)
397{
398 if (!dc->type_b && (dc->imm & (1 << 10))) {
399 dec_pattern(dc);
400 return;
401 }
402
403 LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm);
404 if (dc->rd)
405 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
406}
407
408static void dec_xor(DisasContext *dc)
409{
410 if (!dc->type_b && (dc->imm & (1 << 10))) {
411 dec_pattern(dc);
412 return;
413 }
414
415 LOG_DIS("xor r%d\n", dc->rd);
416 if (dc->rd)
417 tcg_gen_xor_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
418}
419
4acb54ba
EI		 420static inline void msr_read(DisasContext *dc, TCGv d)
421{
422 tcg_gen_mov_tl(d, cpu_SR[SR_MSR]);
423}
424
425static inline void msr_write(DisasContext *dc, TCGv v)
426{
97b833c5
EI		 427 TCGv t;
428
429 t = tcg_temp_new();
4acb54ba 430 dc->cpustate_changed = 1;
97b833c5 431 /* PVR bit is not writable. */
8a84fc6b
EI		 432 tcg_gen_andi_tl(t, v, ~MSR_PVR);
433 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR);
97b833c5
EI		 434 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], v);
435 tcg_temp_free(t);
4acb54ba
EI		 436}
437
438static void dec_msr(DisasContext *dc)
439{
440 TCGv t0, t1;
441 unsigned int sr, to, rn;
1567a005 442 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 443
444 sr = dc->imm & ((1 << 14) - 1);
445 to = dc->imm & (1 << 14);
446 dc->type_b = 1;
447 if (to)
448 dc->cpustate_changed = 1;
449
450 /* msrclr and msrset. */
451 if (!(dc->imm & (1 << 15))) {
452 unsigned int clr = dc->ir & (1 << 16);
453
454 LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
455 dc->rd, dc->imm);
1567a005
EI		 456
457 if (!(dc->env->pvr.regs[2] & PVR2_USE_MSR_INSTR)) {
458 /* nop??? */
459 return;
460 }
461
462 if ((dc->tb_flags & MSR_EE_FLAG)
463 && mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) {
464 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
465 t_gen_raise_exception(dc, EXCP_HW_EXCP);
466 return;
467 }
468
4acb54ba
EI		 469 if (dc->rd)
470 msr_read(dc, cpu_R[dc->rd]);
471
472 t0 = tcg_temp_new();
473 t1 = tcg_temp_new();
474 msr_read(dc, t0);
475 tcg_gen_mov_tl(t1, *(dec_alu_op_b(dc)));
476
477 if (clr) {
478 tcg_gen_not_tl(t1, t1);
479 tcg_gen_and_tl(t0, t0, t1);
480 } else
481 tcg_gen_or_tl(t0, t0, t1);
482 msr_write(dc, t0);
483 tcg_temp_free(t0);
484 tcg_temp_free(t1);
485 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
486 dc->is_jmp = DISAS_UPDATE;
487 return;
488 }
489
1567a005
EI		 490 if (to) {
491 if ((dc->tb_flags & MSR_EE_FLAG)
492 && mem_index == MMU_USER_IDX) {
493 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
494 t_gen_raise_exception(dc, EXCP_HW_EXCP);
495 return;
496 }
497 }
498
4acb54ba
EI		 499#if !defined(CONFIG_USER_ONLY)
500 /* Catch read/writes to the mmu block. */
501 if ((sr & ~0xff) == 0x1000) {
502 sr &= 7;
503 LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
504 if (to)
505 gen_helper_mmu_write(tcg_const_tl(sr), cpu_R[dc->ra]);
506 else
507 gen_helper_mmu_read(cpu_R[dc->rd], tcg_const_tl(sr));
508 return;
509 }
510#endif
511
512 if (to) {
513 LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
514 switch (sr) {
515 case 0:
516 break;
517 case 1:
518 msr_write(dc, cpu_R[dc->ra]);
519 break;
520 case 0x3:
521 tcg_gen_mov_tl(cpu_SR[SR_EAR], cpu_R[dc->ra]);
522 break;
523 case 0x5:
524 tcg_gen_mov_tl(cpu_SR[SR_ESR], cpu_R[dc->ra]);
525 break;
526 case 0x7:
97694c57 527 tcg_gen_andi_tl(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
4acb54ba
EI		 528 break;
529 default:
530 cpu_abort(dc->env, "unknown mts reg %x\n", sr);
531 break;
532 }
533 } else {
534 LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm);
535
536 switch (sr) {
537 case 0:
538 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
539 break;
540 case 1:
541 msr_read(dc, cpu_R[dc->rd]);
542 break;
543 case 0x3:
544 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_EAR]);
545 break;
546 case 0x5:
547 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_ESR]);
548 break;
549 case 0x7:
97694c57 550 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_FSR]);
4acb54ba
EI		 551 break;
552 case 0xb:
553 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]);
554 break;
555 case 0x2000:
556 case 0x2001:
557 case 0x2002:
558 case 0x2003:
559 case 0x2004:
560 case 0x2005:
561 case 0x2006:
562 case 0x2007:
563 case 0x2008:
564 case 0x2009:
565 case 0x200a:
566 case 0x200b:
567 case 0x200c:
568 rn = sr & 0xf;
569 tcg_gen_ld_tl(cpu_R[dc->rd],
570 cpu_env, offsetof(CPUState, pvr.regs[rn]));
571 break;
572 default:
573 cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
574 break;
575 }
576 }
ee7dbcf8
EI		 577
578 if (dc->rd == 0) {
579 tcg_gen_movi_tl(cpu_R[0], 0);
580 }
4acb54ba
EI		 581}
582
583/* 64-bit signed mul, lower result in d and upper in d2. */
584static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
585{
586 TCGv_i64 t0, t1;
587
588 t0 = tcg_temp_new_i64();
589 t1 = tcg_temp_new_i64();
590
591 tcg_gen_ext_i32_i64(t0, a);
592 tcg_gen_ext_i32_i64(t1, b);
593 tcg_gen_mul_i64(t0, t0, t1);
594
595 tcg_gen_trunc_i64_i32(d, t0);
596 tcg_gen_shri_i64(t0, t0, 32);
597 tcg_gen_trunc_i64_i32(d2, t0);
598
599 tcg_temp_free_i64(t0);
600 tcg_temp_free_i64(t1);
601}
602
603/* 64-bit unsigned muls, lower result in d and upper in d2. */
604static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
605{
606 TCGv_i64 t0, t1;
607
608 t0 = tcg_temp_new_i64();
609 t1 = tcg_temp_new_i64();
610
611 tcg_gen_extu_i32_i64(t0, a);
612 tcg_gen_extu_i32_i64(t1, b);
613 tcg_gen_mul_i64(t0, t0, t1);
614
615 tcg_gen_trunc_i64_i32(d, t0);
616 tcg_gen_shri_i64(t0, t0, 32);
617 tcg_gen_trunc_i64_i32(d2, t0);
618
619 tcg_temp_free_i64(t0);
620 tcg_temp_free_i64(t1);
621}
622
623/* Multiplier unit. */
624static void dec_mul(DisasContext *dc)
625{
626 TCGv d[2];
627 unsigned int subcode;
628
1567a005 629 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 630 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 631 && !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
632 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
633 t_gen_raise_exception(dc, EXCP_HW_EXCP);
634 return;
635 }
636
4acb54ba
EI		 637 subcode = dc->imm & 3;
638 d[0] = tcg_temp_new();
639 d[1] = tcg_temp_new();
640
641 if (dc->type_b) {
642 LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm);
643 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
644 goto done;
645 }
646
1567a005
EI		 647 /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
648 if (subcode >= 1 && subcode <= 3
649 && !((dc->env->pvr.regs[2] & PVR2_USE_MUL64_MASK))) {
650 /* nop??? */
651 }
652
4acb54ba
EI		 653 switch (subcode) {
654 case 0:
655 LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
656 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], cpu_R[dc->rb]);
657 break;
658 case 1:
659 LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
660 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
661 break;
662 case 2:
663 LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
664 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
665 break;
666 case 3:
667 LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
668 t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
669 break;
670 default:
671 cpu_abort(dc->env, "unknown MUL insn %x\n", subcode);
672 break;
673 }
674done:
675 tcg_temp_free(d[0]);
676 tcg_temp_free(d[1]);
677}
678
679/* Div unit. */
680static void dec_div(DisasContext *dc)
681{
682 unsigned int u;
683
684 u = dc->imm & 2;
685 LOG_DIS("div\n");
686
97f90cbf 687 if ((dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 688 && !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) {
689 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
690 t_gen_raise_exception(dc, EXCP_HW_EXCP);
691 }
692
4acb54ba
EI		 693 if (u)
694 gen_helper_divu(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
695 else
696 gen_helper_divs(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
697 if (!dc->rd)
698 tcg_gen_movi_tl(cpu_R[dc->rd], 0);
699}
700
701static void dec_barrel(DisasContext *dc)
702{
703 TCGv t0;
704 unsigned int s, t;
705
1567a005 706 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 707 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 708 && !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
709 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
710 t_gen_raise_exception(dc, EXCP_HW_EXCP);
711 return;
712 }
713
4acb54ba
EI		 714 s = dc->imm & (1 << 10);
715 t = dc->imm & (1 << 9);
716
717 LOG_DIS("bs%s%s r%d r%d r%d\n",
718 s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
719
720 t0 = tcg_temp_new();
721
722 tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
723 tcg_gen_andi_tl(t0, t0, 31);
724
725 if (s)
726 tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
727 else {
728 if (t)
729 tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
730 else
731 tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
732 }
733}
734
735static void dec_bit(DisasContext *dc)
736{
737 TCGv t0, t1;
738 unsigned int op;
1567a005 739 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 740
741 op = dc->ir & ((1 << 8) - 1);
742 switch (op) {
743 case 0x21:
744 /* src. */
745 t0 = tcg_temp_new();
746
747 LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
748 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
749 if (dc->rd) {
750 t1 = tcg_temp_new();
751 read_carry(dc, t1);
752 tcg_gen_shli_tl(t1, t1, 31);
753
754 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
755 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t1);
756 tcg_temp_free(t1);
757 }
758
759 /* Update carry. */
760 write_carry(dc, t0);
761 tcg_temp_free(t0);
762 break;
763
764 case 0x1:
765 case 0x41:
766 /* srl. */
767 t0 = tcg_temp_new();
768 LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
769
770 /* Update carry. */
771 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
772 write_carry(dc, t0);
773 tcg_temp_free(t0);
774 if (dc->rd) {
775 if (op == 0x41)
776 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
777 else
778 tcg_gen_sari_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
779 }
780 break;
781 case 0x60:
782 LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra);
783 tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
784 break;
785 case 0x61:
786 LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra);
787 tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
788 break;
789 case 0x64:
f062a3c7
EI		 790 case 0x66:
791 case 0x74:
792 case 0x76:
4acb54ba
EI		 793 /* wdc. */
794 LOG_DIS("wdc r%d\n", dc->ra);
1567a005
EI		 795 if ((dc->tb_flags & MSR_EE_FLAG)
796 && mem_index == MMU_USER_IDX) {
797 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
798 t_gen_raise_exception(dc, EXCP_HW_EXCP);
799 return;
800 }
4acb54ba
EI		 801 break;
802 case 0x68:
803 /* wic. */
804 LOG_DIS("wic r%d\n", dc->ra);
1567a005
EI		 805 if ((dc->tb_flags & MSR_EE_FLAG)
806 && mem_index == MMU_USER_IDX) {
807 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
808 t_gen_raise_exception(dc, EXCP_HW_EXCP);
809 return;
810 }
4acb54ba 811 break;
48b5e96f
EI		 812 case 0xe0:
813 if ((dc->tb_flags & MSR_EE_FLAG)
814 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
815 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
816 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
817 t_gen_raise_exception(dc, EXCP_HW_EXCP);
818 }
819 if (dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR) {
820 gen_helper_clz(cpu_R[dc->rd], cpu_R[dc->ra]);
821 }
822 break;
4acb54ba
EI		 823 default:
824 cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
825 dc->pc, op, dc->rd, dc->ra, dc->rb);
826 break;
827 }
828}
829
830static inline void sync_jmpstate(DisasContext *dc)
831{
844bab60
EI		 832 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
833 if (dc->jmp == JMP_DIRECT) {
834 tcg_gen_movi_tl(env_btaken, 1);
835 }
23979dc5
EI		 836 dc->jmp = JMP_INDIRECT;
837 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
4acb54ba
EI		 838 }
839}
840
841static void dec_imm(DisasContext *dc)
842{
843 LOG_DIS("imm %x\n", dc->imm << 16);
844 tcg_gen_movi_tl(env_imm, (dc->imm << 16));
845 dc->tb_flags |= IMM_FLAG;
846 dc->clear_imm = 0;
847}
848
849static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
850 unsigned int size)
851{
852 int mem_index = cpu_mmu_index(dc->env);
853
854 if (size == 1) {
855 tcg_gen_qemu_ld8u(dst, addr, mem_index);
856 } else if (size == 2) {
857 tcg_gen_qemu_ld16u(dst, addr, mem_index);
858 } else if (size == 4) {
859 tcg_gen_qemu_ld32u(dst, addr, mem_index);
860 } else
861 cpu_abort(dc->env, "Incorrect load size %d\n", size);
862}
863
864static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
865{
866 unsigned int extimm = dc->tb_flags & IMM_FLAG;
867
9ef55357 868 /* Treat the common cases first. */
4acb54ba 869 if (!dc->type_b) {
4b5ef0b5
EI		 870 /* If any of the regs is r0, return a ptr to the other. */
871 if (dc->ra == 0) {
872 return &cpu_R[dc->rb];
873 } else if (dc->rb == 0) {
874 return &cpu_R[dc->ra];
875 }
876
4acb54ba
EI		 877 *t = tcg_temp_new();
878 tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
879 return t;
880 }
881 /* Immediate. */
882 if (!extimm) {
883 if (dc->imm == 0) {
884 return &cpu_R[dc->ra];
885 }
886 *t = tcg_temp_new();
887 tcg_gen_movi_tl(*t, (int32_t)((int16_t)dc->imm));
888 tcg_gen_add_tl(*t, cpu_R[dc->ra], *t);
889 } else {
890 *t = tcg_temp_new();
891 tcg_gen_add_tl(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
892 }
893
894 return t;
895}
896
9f8beb66
EI		 897static inline void dec_byteswap(DisasContext *dc, TCGv dst, TCGv src, int size)
898{
899 if (size == 4) {
900 tcg_gen_bswap32_tl(dst, src);
901 } else if (size == 2) {
902 TCGv t = tcg_temp_new();
903
904 /* bswap16 assumes the high bits are zero. */
905 tcg_gen_andi_tl(t, src, 0xffff);
906 tcg_gen_bswap16_tl(dst, t);
907 tcg_temp_free(t);
908 } else {
909 /* Ignore.
910 cpu_abort(dc->env, "Invalid ldst byteswap size %d\n", size);
911 */
912 }
913}
914
4acb54ba
EI		 915static void dec_load(DisasContext *dc)
916{
917 TCGv t, *addr;
9f8beb66 918 unsigned int size, rev = 0;
4acb54ba
EI		 919
920 size = 1 << (dc->opcode & 3);
9f8beb66
EI		 921
922 if (!dc->type_b) {
923 rev = (dc->ir >> 9) & 1;
924 }
925
0187688f 926 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
97f90cbf 927 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
0187688f
EI		 928 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
929 t_gen_raise_exception(dc, EXCP_HW_EXCP);
930 return;
931 }
4acb54ba 932
9f8beb66
EI		 933 LOG_DIS("l%d%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "");
934
4acb54ba
EI		 935 t_sync_flags(dc);
936 addr = compute_ldst_addr(dc, &t);
937
9f8beb66
EI		 938 /*
939 * When doing reverse accesses we need to do two things.
940 *
4ff9786c 941 * 1. Reverse the address wrt endianness.
9f8beb66
EI		 942 * 2. Byteswap the data lanes on the way back into the CPU core.
943 */
944 if (rev && size != 4) {
945 /* Endian reverse the address. t is addr. */
946 switch (size) {
947 case 1:
948 {
949 /* 00 -> 11
950 01 -> 10
951 10 -> 10
952 11 -> 00 */
953 TCGv low = tcg_temp_new();
954
955 /* Force addr into the temp. */
956 if (addr != &t) {
957 t = tcg_temp_new();
958 tcg_gen_mov_tl(t, *addr);
959 addr = &t;
960 }
961
962 tcg_gen_andi_tl(low, t, 3);
963 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
964 tcg_gen_andi_tl(t, t, ~3);
965 tcg_gen_or_tl(t, t, low);
9f8beb66
EI		 966 tcg_gen_mov_tl(env_imm, t);
967 tcg_temp_free(low);
968 break;
969 }
970
971 case 2:
972 /* 00 -> 10
973 10 -> 00. */
974 /* Force addr into the temp. */
975 if (addr != &t) {
976 t = tcg_temp_new();
977 tcg_gen_xori_tl(t, *addr, 2);
978 addr = &t;
979 } else {
980 tcg_gen_xori_tl(t, t, 2);
981 }
982 break;
983 default:
984 cpu_abort(dc->env, "Invalid reverse size\n");
985 break;
986 }
987 }
988
4acb54ba
EI		 989 /* If we get a fault on a dslot, the jmpstate better be in sync. */
990 sync_jmpstate(dc);
968a40f6
EI		 991
992 /* Verify alignment if needed. */
993 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
a12f6507
EI		 994 TCGv v = tcg_temp_new();
995
996 /*
997 * Microblaze gives MMU faults priority over faults due to
998 * unaligned addresses. That's why we speculatively do the load
999 * into v. If the load succeeds, we verify alignment of the
1000 * address and if that succeeds we write into the destination reg.
1001 */
1002 gen_load(dc, v, *addr, size);
1003
1004 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
968a40f6 1005 gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
3aa80988 1006 tcg_const_tl(0), tcg_const_tl(size - 1));
9f8beb66
EI		 1007 if (dc->rd) {
1008 if (rev) {
1009 dec_byteswap(dc, cpu_R[dc->rd], v, size);
1010 } else {
1011 tcg_gen_mov_tl(cpu_R[dc->rd], v);
1012 }
1013 }
a12f6507 1014 tcg_temp_free(v);
968a40f6 1015 } else {
a12f6507
EI		 1016 if (dc->rd) {
1017 gen_load(dc, cpu_R[dc->rd], *addr, size);
9f8beb66
EI		 1018 if (rev) {
1019 dec_byteswap(dc, cpu_R[dc->rd], cpu_R[dc->rd], size);
1020 }
a12f6507 1021 } else {
9f8beb66 1022 /* We are loading into r0, no need to reverse. */
a12f6507
EI		 1023 gen_load(dc, env_imm, *addr, size);
1024 }
4acb54ba
EI		 1025 }
1026
1027 if (addr == &t)
1028 tcg_temp_free(t);
1029}
1030
1031static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
1032 unsigned int size)
1033{
1034 int mem_index = cpu_mmu_index(dc->env);
1035
1036 if (size == 1)
1037 tcg_gen_qemu_st8(val, addr, mem_index);
1038 else if (size == 2) {
1039 tcg_gen_qemu_st16(val, addr, mem_index);
1040 } else if (size == 4) {
1041 tcg_gen_qemu_st32(val, addr, mem_index);
1042 } else
1043 cpu_abort(dc->env, "Incorrect store size %d\n", size);
1044}
1045
1046static void dec_store(DisasContext *dc)
1047{
1048 TCGv t, *addr;
9f8beb66 1049 unsigned int size, rev = 0;
4acb54ba
EI		 1050
1051 size = 1 << (dc->opcode & 3);
9f8beb66
EI		 1052 if (!dc->type_b) {
1053 rev = (dc->ir >> 9) & 1;
1054 }
4acb54ba 1055
0187688f 1056 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
97f90cbf 1057 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
0187688f
EI		 1058 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1059 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1060 return;
1061 }
1062
9f8beb66 1063 LOG_DIS("s%d%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "");
4acb54ba
EI		 1064 t_sync_flags(dc);
1065 /* If we get a fault on a dslot, the jmpstate better be in sync. */
1066 sync_jmpstate(dc);
1067 addr = compute_ldst_addr(dc, &t);
968a40f6 1068
9f8beb66
EI		 1069 if (rev && size != 4) {
1070 /* Endian reverse the address. t is addr. */
1071 switch (size) {
1072 case 1:
1073 {
1074 /* 00 -> 11
1075 01 -> 10
1076 10 -> 10
1077 11 -> 00 */
1078 TCGv low = tcg_temp_new();
1079
1080 /* Force addr into the temp. */
1081 if (addr != &t) {
1082 t = tcg_temp_new();
1083 tcg_gen_mov_tl(t, *addr);
1084 addr = &t;
1085 }
1086
1087 tcg_gen_andi_tl(low, t, 3);
1088 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
1089 tcg_gen_andi_tl(t, t, ~3);
1090 tcg_gen_or_tl(t, t, low);
9f8beb66
EI		 1091 tcg_gen_mov_tl(env_imm, t);
1092 tcg_temp_free(low);
1093 break;
1094 }
1095
1096 case 2:
1097 /* 00 -> 10
1098 10 -> 00. */
1099 /* Force addr into the temp. */
1100 if (addr != &t) {
1101 t = tcg_temp_new();
1102 tcg_gen_xori_tl(t, *addr, 2);
1103 addr = &t;
1104 } else {
1105 tcg_gen_xori_tl(t, t, 2);
1106 }
1107 break;
1108 default:
1109 cpu_abort(dc->env, "Invalid reverse size\n");
1110 break;
1111 }
1112
1113 if (size != 1) {
1114 TCGv bs_data = tcg_temp_new();
1115 dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1116 gen_store(dc, *addr, bs_data, size);
1117 tcg_temp_free(bs_data);
1118 } else {
1119 gen_store(dc, *addr, cpu_R[dc->rd], size);
1120 }
1121 } else {
1122 if (rev) {
1123 TCGv bs_data = tcg_temp_new();
1124 dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1125 gen_store(dc, *addr, bs_data, size);
1126 tcg_temp_free(bs_data);
1127 } else {
1128 gen_store(dc, *addr, cpu_R[dc->rd], size);
1129 }
1130 }
a12f6507 1131
968a40f6
EI		 1132 /* Verify alignment if needed. */
1133 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
a12f6507
EI		 1134 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1135 /* FIXME: if the alignment is wrong, we should restore the value
4abf79a4 1136 * in memory. One possible way to achieve this is to probe
9f8beb66
EI		 1137 * the MMU prior to the memaccess, thay way we could put
1138 * the alignment checks in between the probe and the mem
1139 * access.
a12f6507 1140 */
968a40f6 1141 gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
3aa80988 1142 tcg_const_tl(1), tcg_const_tl(size - 1));
968a40f6
EI		 1143 }
1144
4acb54ba
EI		 1145 if (addr == &t)
1146 tcg_temp_free(t);
1147}
1148
1149static inline void eval_cc(DisasContext *dc, unsigned int cc,
1150 TCGv d, TCGv a, TCGv b)
1151{
4acb54ba
EI		 1152 switch (cc) {
1153 case CC_EQ:
b2565c69 1154 tcg_gen_setcond_tl(TCG_COND_EQ, d, a, b);
4acb54ba
EI		 1155 break;
1156 case CC_NE:
b2565c69 1157 tcg_gen_setcond_tl(TCG_COND_NE, d, a, b);
4acb54ba
EI		 1158 break;
1159 case CC_LT:
b2565c69 1160 tcg_gen_setcond_tl(TCG_COND_LT, d, a, b);
4acb54ba
EI		 1161 break;
1162 case CC_LE:
b2565c69 1163 tcg_gen_setcond_tl(TCG_COND_LE, d, a, b);
4acb54ba
EI		 1164 break;
1165 case CC_GE:
b2565c69 1166 tcg_gen_setcond_tl(TCG_COND_GE, d, a, b);
4acb54ba
EI		 1167 break;
1168 case CC_GT:
b2565c69 1169 tcg_gen_setcond_tl(TCG_COND_GT, d, a, b);
4acb54ba
EI		 1170 break;
1171 default:
1172 cpu_abort(dc->env, "Unknown condition code %x.\n", cc);
1173 break;
1174 }
1175}
1176
1177static void eval_cond_jmp(DisasContext *dc, TCGv pc_true, TCGv pc_false)
1178{
1179 int l1;
1180
1181 l1 = gen_new_label();
1182 /* Conditional jmp. */
1183 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_false);
1184 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
1185 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_true);
1186 gen_set_label(l1);
1187}
1188
1189static void dec_bcc(DisasContext *dc)
1190{
1191 unsigned int cc;
1192 unsigned int dslot;
1193
1194 cc = EXTRACT_FIELD(dc->ir, 21, 23);
1195 dslot = dc->ir & (1 << 25);
1196 LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm);
1197
1198 dc->delayed_branch = 1;
1199 if (dslot) {
1200 dc->delayed_branch = 2;
1201 dc->tb_flags |= D_FLAG;
1202 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1203 cpu_env, offsetof(CPUState, bimm));
1204 }
1205
61204ce8
EI		 1206 if (dec_alu_op_b_is_small_imm(dc)) {
1207 int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */
1208
1209 tcg_gen_movi_tl(env_btarget, dc->pc + offset);
844bab60 1210 dc->jmp = JMP_DIRECT_CC;
23979dc5 1211 dc->jmp_pc = dc->pc + offset;
61204ce8 1212 } else {
23979dc5 1213 dc->jmp = JMP_INDIRECT;
61204ce8
EI		 1214 tcg_gen_movi_tl(env_btarget, dc->pc);
1215 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
1216 }
61204ce8 1217 eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_tl(0));
4acb54ba
EI		 1218}
1219
1220static void dec_br(DisasContext *dc)
1221{
1222 unsigned int dslot, link, abs;
ff21f70a 1223 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 1224
1225 dslot = dc->ir & (1 << 20);
1226 abs = dc->ir & (1 << 19);
1227 link = dc->ir & (1 << 18);
1228 LOG_DIS("br%s%s%s%s imm=%x\n",
1229 abs ? "a" : "", link ? "l" : "",
1230 dc->type_b ? "i" : "", dslot ? "d" : "",
1231 dc->imm);
1232
1233 dc->delayed_branch = 1;
1234 if (dslot) {
1235 dc->delayed_branch = 2;
1236 dc->tb_flags |= D_FLAG;
1237 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1238 cpu_env, offsetof(CPUState, bimm));
1239 }
1240 if (link && dc->rd)
1241 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
1242
1243 dc->jmp = JMP_INDIRECT;
1244 if (abs) {
1245 tcg_gen_movi_tl(env_btaken, 1);
1246 tcg_gen_mov_tl(env_btarget, *(dec_alu_op_b(dc)));
ff21f70a
EI		 1247 if (link && !dslot) {
1248 if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18))
1249 t_gen_raise_exception(dc, EXCP_BREAK);
1250 if (dc->imm == 0) {
1251 if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) {
1252 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1253 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1254 return;
1255 }
1256
1257 t_gen_raise_exception(dc, EXCP_DEBUG);
1258 }
1259 }
4acb54ba 1260 } else {
61204ce8
EI		 1261 if (dec_alu_op_b_is_small_imm(dc)) {
1262 dc->jmp = JMP_DIRECT;
1263 dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm);
1264 } else {
4acb54ba
EI		 1265 tcg_gen_movi_tl(env_btaken, 1);
1266 tcg_gen_movi_tl(env_btarget, dc->pc);
1267 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
4acb54ba
EI		 1268 }
1269 }
1270}
1271
1272static inline void do_rti(DisasContext *dc)
1273{
1274 TCGv t0, t1;
1275 t0 = tcg_temp_new();
1276 t1 = tcg_temp_new();
1277 tcg_gen_shri_tl(t0, cpu_SR[SR_MSR], 1);
1278 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_IE);
1279 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1280
1281 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1282 tcg_gen_or_tl(t1, t1, t0);
1283 msr_write(dc, t1);
1284 tcg_temp_free(t1);
1285 tcg_temp_free(t0);
1286 dc->tb_flags &= ~DRTI_FLAG;
1287}
1288
1289static inline void do_rtb(DisasContext *dc)
1290{
1291 TCGv t0, t1;
1292 t0 = tcg_temp_new();
1293 t1 = tcg_temp_new();
1294 tcg_gen_andi_tl(t1, cpu_SR[SR_MSR], ~MSR_BIP);
1295 tcg_gen_shri_tl(t0, t1, 1);
1296 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1297
1298 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1299 tcg_gen_or_tl(t1, t1, t0);
1300 msr_write(dc, t1);
1301 tcg_temp_free(t1);
1302 tcg_temp_free(t0);
1303 dc->tb_flags &= ~DRTB_FLAG;
1304}
1305
1306static inline void do_rte(DisasContext *dc)
1307{
1308 TCGv t0, t1;
1309 t0 = tcg_temp_new();
1310 t1 = tcg_temp_new();
1311
1312 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_EE);
1313 tcg_gen_andi_tl(t1, t1, ~MSR_EIP);
1314 tcg_gen_shri_tl(t0, t1, 1);
1315 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1316
1317 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1318 tcg_gen_or_tl(t1, t1, t0);
1319 msr_write(dc, t1);
1320 tcg_temp_free(t1);
1321 tcg_temp_free(t0);
1322 dc->tb_flags &= ~DRTE_FLAG;
1323}
1324
1325static void dec_rts(DisasContext *dc)
1326{
1327 unsigned int b_bit, i_bit, e_bit;
1567a005 1328 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 1329
1330 i_bit = dc->ir & (1 << 21);
1331 b_bit = dc->ir & (1 << 22);
1332 e_bit = dc->ir & (1 << 23);
1333
1334 dc->delayed_branch = 2;
1335 dc->tb_flags |= D_FLAG;
1336 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1337 cpu_env, offsetof(CPUState, bimm));
1338
1339 if (i_bit) {
1340 LOG_DIS("rtid ir=%x\n", dc->ir);
1567a005
EI		 1341 if ((dc->tb_flags & MSR_EE_FLAG)
1342 && mem_index == MMU_USER_IDX) {
1343 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1344 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1345 }
4acb54ba
EI		 1346 dc->tb_flags |= DRTI_FLAG;
1347 } else if (b_bit) {
1348 LOG_DIS("rtbd ir=%x\n", dc->ir);
1567a005
EI		 1349 if ((dc->tb_flags & MSR_EE_FLAG)
1350 && mem_index == MMU_USER_IDX) {
1351 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1352 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1353 }
4acb54ba
EI		 1354 dc->tb_flags |= DRTB_FLAG;
1355 } else if (e_bit) {
1356 LOG_DIS("rted ir=%x\n", dc->ir);
1567a005
EI		 1357 if ((dc->tb_flags & MSR_EE_FLAG)
1358 && mem_index == MMU_USER_IDX) {
1359 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1360 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1361 }
4acb54ba
EI		 1362 dc->tb_flags |= DRTE_FLAG;
1363 } else
1364 LOG_DIS("rts ir=%x\n", dc->ir);
1365
23979dc5 1366 dc->jmp = JMP_INDIRECT;
4acb54ba
EI		 1367 tcg_gen_movi_tl(env_btaken, 1);
1368 tcg_gen_add_tl(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
1369}
1370
97694c57
EI		 1371static int dec_check_fpuv2(DisasContext *dc)
1372{
1373 int r;
1374
1375 r = dc->env->pvr.regs[2] & PVR2_USE_FPU2_MASK;
1376
1377 if (!r && (dc->tb_flags & MSR_EE_FLAG)) {
1378 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
1379 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1380 }
1381 return r;
1382}
1383
1567a005
EI		 1384static void dec_fpu(DisasContext *dc)
1385{
97694c57
EI		 1386 unsigned int fpu_insn;
1387
1567a005 1388 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 1389 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005 1390 && !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) {
97694c57 1391 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1567a005
EI		 1392 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1393 return;
1394 }
1395
97694c57
EI		 1396 fpu_insn = (dc->ir >> 7) & 7;
1397
1398 switch (fpu_insn) {
1399 case 0:
1400 gen_helper_fadd(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1401 break;
1402
1403 case 1:
1404 gen_helper_frsub(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1405 break;
1406
1407 case 2:
1408 gen_helper_fmul(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1409 break;
1410
1411 case 3:
1412 gen_helper_fdiv(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1413 break;
1414
1415 case 4:
1416 switch ((dc->ir >> 4) & 7) {
1417 case 0:
1418 gen_helper_fcmp_un(cpu_R[dc->rd],
1419 cpu_R[dc->ra], cpu_R[dc->rb]);
1420 break;
1421 case 1:
1422 gen_helper_fcmp_lt(cpu_R[dc->rd],
1423 cpu_R[dc->ra], cpu_R[dc->rb]);
1424 break;
1425 case 2:
1426 gen_helper_fcmp_eq(cpu_R[dc->rd],
1427 cpu_R[dc->ra], cpu_R[dc->rb]);
1428 break;
1429 case 3:
1430 gen_helper_fcmp_le(cpu_R[dc->rd],
1431 cpu_R[dc->ra], cpu_R[dc->rb]);
1432 break;
1433 case 4:
1434 gen_helper_fcmp_gt(cpu_R[dc->rd],
1435 cpu_R[dc->ra], cpu_R[dc->rb]);
1436 break;
1437 case 5:
1438 gen_helper_fcmp_ne(cpu_R[dc->rd],
1439 cpu_R[dc->ra], cpu_R[dc->rb]);
1440 break;
1441 case 6:
1442 gen_helper_fcmp_ge(cpu_R[dc->rd],
1443 cpu_R[dc->ra], cpu_R[dc->rb]);
1444 break;
1445 default:
1446 qemu_log ("unimplemented fcmp fpu_insn=%x pc=%x opc=%x\n",
1447 fpu_insn, dc->pc, dc->opcode);
1448 dc->abort_at_next_insn = 1;
1449 break;
1450 }
1451 break;
1452
1453 case 5:
1454 if (!dec_check_fpuv2(dc)) {
1455 return;
1456 }
1457 gen_helper_flt(cpu_R[dc->rd], cpu_R[dc->ra]);
1458 break;
1459
1460 case 6:
1461 if (!dec_check_fpuv2(dc)) {
1462 return;
1463 }
1464 gen_helper_fint(cpu_R[dc->rd], cpu_R[dc->ra]);
1465 break;
1466
1467 case 7:
1468 if (!dec_check_fpuv2(dc)) {
1469 return;
1470 }
1471 gen_helper_fsqrt(cpu_R[dc->rd], cpu_R[dc->ra]);
1472 break;
1473
1474 default:
1475 qemu_log ("unimplemented FPU insn fpu_insn=%x pc=%x opc=%x\n",
1476 fpu_insn, dc->pc, dc->opcode);
1477 dc->abort_at_next_insn = 1;
1478 break;
1479 }
1567a005
EI		 1480}
1481
4acb54ba
EI		 1482static void dec_null(DisasContext *dc)
1483{
02b33596
EI		 1484 if ((dc->tb_flags & MSR_EE_FLAG)
1485 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
1486 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1487 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1488 return;
1489 }
4acb54ba
EI		 1490 qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
1491 dc->abort_at_next_insn = 1;
1492}
1493
6d76d23e
EI		 1494/* Insns connected to FSL or AXI stream attached devices. */
1495static void dec_stream(DisasContext *dc)
1496{
1497 int mem_index = cpu_mmu_index(dc->env);
1498 TCGv_i32 t_id, t_ctrl;
1499 int ctrl;
1500
1501 LOG_DIS("%s%s imm=%x\n", dc->rd ? "get" : "put",
1502 dc->type_b ? "" : "d", dc->imm);
1503
1504 if ((dc->tb_flags & MSR_EE_FLAG) && (mem_index == MMU_USER_IDX)) {
1505 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1506 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1507 return;
1508 }
1509
1510 t_id = tcg_temp_new();
1511 if (dc->type_b) {
1512 tcg_gen_movi_tl(t_id, dc->imm & 0xf);
1513 ctrl = dc->imm >> 10;
1514 } else {
1515 tcg_gen_andi_tl(t_id, cpu_R[dc->rb], 0xf);
1516 ctrl = dc->imm >> 5;
1517 }
1518
1519 t_ctrl = tcg_const_tl(ctrl);
1520
1521 if (dc->rd == 0) {
1522 gen_helper_put(t_id, t_ctrl, cpu_R[dc->ra]);
1523 } else {
1524 gen_helper_get(cpu_R[dc->rd], t_id, t_ctrl);
1525 }
1526 tcg_temp_free(t_id);
1527 tcg_temp_free(t_ctrl);
1528}
1529
4acb54ba
EI		 1530static struct decoder_info {
1531 struct {
1532 uint32_t bits;
1533 uint32_t mask;
1534 };
1535 void (*dec)(DisasContext *dc);
1536} decinfo[] = {
1537 {DEC_ADD, dec_add},
1538 {DEC_SUB, dec_sub},
1539 {DEC_AND, dec_and},
1540 {DEC_XOR, dec_xor},
1541 {DEC_OR, dec_or},
1542 {DEC_BIT, dec_bit},
1543 {DEC_BARREL, dec_barrel},
1544 {DEC_LD, dec_load},
1545 {DEC_ST, dec_store},
1546 {DEC_IMM, dec_imm},
1547 {DEC_BR, dec_br},
1548 {DEC_BCC, dec_bcc},
1549 {DEC_RTS, dec_rts},
1567a005 1550 {DEC_FPU, dec_fpu},
4acb54ba
EI		 1551 {DEC_MUL, dec_mul},
1552 {DEC_DIV, dec_div},
1553 {DEC_MSR, dec_msr},
6d76d23e 1554 {DEC_STREAM, dec_stream},
4acb54ba
EI		 1555 {{0, 0}, dec_null}
1556};
1557
1558static inline void decode(DisasContext *dc)
1559{
1560 uint32_t ir;
1561 int i;
1562
1563 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
1564 tcg_gen_debug_insn_start(dc->pc);
1565
1566 dc->ir = ir = ldl_code(dc->pc);
1567 LOG_DIS("%8.8x\t", dc->ir);
1568
1569 if (dc->ir)
1570 dc->nr_nops = 0;
1571 else {
1567a005 1572 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf
EI		 1573 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1574 && (dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
1567a005
EI		 1575 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1576 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1577 return;
1578 }
1579
4acb54ba
EI		 1580 LOG_DIS("nr_nops=%d\t", dc->nr_nops);
1581 dc->nr_nops++;
1582 if (dc->nr_nops > 4)
1583 cpu_abort(dc->env, "fetching nop sequence\n");
1584 }
1585 /* bit 2 seems to indicate insn type. */
1586 dc->type_b = ir & (1 << 29);
1587
1588 dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1589 dc->rd = EXTRACT_FIELD(ir, 21, 25);
1590 dc->ra = EXTRACT_FIELD(ir, 16, 20);
1591 dc->rb = EXTRACT_FIELD(ir, 11, 15);
1592 dc->imm = EXTRACT_FIELD(ir, 0, 15);
1593
1594 /* Large switch for all insns. */
1595 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
1596 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
1597 decinfo[i].dec(dc);
1598 break;
1599 }
1600 }
1601}
1602
4acb54ba
EI		 1603static void check_breakpoint(CPUState *env, DisasContext *dc)
1604{
1605 CPUBreakpoint *bp;
1606
72cf2d4f
BS		 1607 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1608 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
4acb54ba
EI		 1609 if (bp->pc == dc->pc) {
1610 t_gen_raise_exception(dc, EXCP_DEBUG);
1611 dc->is_jmp = DISAS_UPDATE;
1612 }
1613 }
1614 }
1615}
1616
1617/* generate intermediate code for basic block 'tb'. */
1618static void
1619gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
1620 int search_pc)
1621{
1622 uint16_t *gen_opc_end;
1623 uint32_t pc_start;
1624 int j, lj;
1625 struct DisasContext ctx;
1626 struct DisasContext *dc = &ctx;
1627 uint32_t next_page_start, org_flags;
1628 target_ulong npc;
1629 int num_insns;
1630 int max_insns;
1631
1632 qemu_log_try_set_file(stderr);
1633
1634 pc_start = tb->pc;
1635 dc->env = env;
1636 dc->tb = tb;
1637 org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
1638
1639 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1640
1641 dc->is_jmp = DISAS_NEXT;
1642 dc->jmp = 0;
1643 dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
23979dc5
EI		 1644 if (dc->delayed_branch) {
1645 dc->jmp = JMP_INDIRECT;
1646 }
4acb54ba 1647 dc->pc = pc_start;
4acb54ba
EI		 1648 dc->singlestep_enabled = env->singlestep_enabled;
1649 dc->cpustate_changed = 0;
1650 dc->abort_at_next_insn = 0;
1651 dc->nr_nops = 0;
1652
1653 if (pc_start & 3)
1654 cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start);
1655
1656 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1657#if !SIM_COMPAT
1658 qemu_log("--------------\n");
1659 log_cpu_state(env, 0);
1660#endif
1661 }
1662
1663 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1664 lj = -1;
1665 num_insns = 0;
1666 max_insns = tb->cflags & CF_COUNT_MASK;
1667 if (max_insns == 0)
1668 max_insns = CF_COUNT_MASK;
1669
1670 gen_icount_start();
1671 do
1672 {
1673#if SIM_COMPAT
1674 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1675 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1676 gen_helper_debug();
1677 }
1678#endif
1679 check_breakpoint(env, dc);
1680
1681 if (search_pc) {
1682 j = gen_opc_ptr - gen_opc_buf;
1683 if (lj < j) {
1684 lj++;
1685 while (lj < j)
1686 gen_opc_instr_start[lj++] = 0;
1687 }
1688 gen_opc_pc[lj] = dc->pc;
1689 gen_opc_instr_start[lj] = 1;
1690 gen_opc_icount[lj] = num_insns;
1691 }
1692
1693 /* Pretty disas. */
1694 LOG_DIS("%8.8x:\t", dc->pc);
1695
1696 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1697 gen_io_start();
1698
1699 dc->clear_imm = 1;
1700 decode(dc);
1701 if (dc->clear_imm)
1702 dc->tb_flags &= ~IMM_FLAG;
4acb54ba
EI		 1703 dc->pc += 4;
1704 num_insns++;
1705
1706 if (dc->delayed_branch) {
1707 dc->delayed_branch--;
1708 if (!dc->delayed_branch) {
1709 if (dc->tb_flags & DRTI_FLAG)
1710 do_rti(dc);
1711 if (dc->tb_flags & DRTB_FLAG)
1712 do_rtb(dc);
1713 if (dc->tb_flags & DRTE_FLAG)
1714 do_rte(dc);
1715 /* Clear the delay slot flag. */
1716 dc->tb_flags &= ~D_FLAG;
1717 /* If it is a direct jump, try direct chaining. */
23979dc5 1718 if (dc->jmp == JMP_INDIRECT) {
4acb54ba
EI		 1719 eval_cond_jmp(dc, env_btarget, tcg_const_tl(dc->pc));
1720 dc->is_jmp = DISAS_JUMP;
23979dc5 1721 } else if (dc->jmp == JMP_DIRECT) {
844bab60
EI		 1722 t_sync_flags(dc);
1723 gen_goto_tb(dc, 0, dc->jmp_pc);
1724 dc->is_jmp = DISAS_TB_JUMP;
1725 } else if (dc->jmp == JMP_DIRECT_CC) {
23979dc5
EI		 1726 int l1;
1727
1728 t_sync_flags(dc);
1729 l1 = gen_new_label();
1730 /* Conditional jmp. */
1731 tcg_gen_brcondi_tl(TCG_COND_NE, env_btaken, 0, l1);
1732 gen_goto_tb(dc, 1, dc->pc);
1733 gen_set_label(l1);
1734 gen_goto_tb(dc, 0, dc->jmp_pc);
1735
1736 dc->is_jmp = DISAS_TB_JUMP;
4acb54ba
EI		 1737 }
1738 break;
1739 }
1740 }
1741 if (env->singlestep_enabled)
1742 break;
1743 } while (!dc->is_jmp && !dc->cpustate_changed
1744 && gen_opc_ptr < gen_opc_end
1745 && !singlestep
1746 && (dc->pc < next_page_start)
1747 && num_insns < max_insns);
1748
1749 npc = dc->pc;
844bab60 1750 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
4acb54ba
EI		 1751 if (dc->tb_flags & D_FLAG) {
1752 dc->is_jmp = DISAS_UPDATE;
1753 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1754 sync_jmpstate(dc);
1755 } else
1756 npc = dc->jmp_pc;
1757 }
1758
1759 if (tb->cflags & CF_LAST_IO)
1760 gen_io_end();
1761 /* Force an update if the per-tb cpu state has changed. */
1762 if (dc->is_jmp == DISAS_NEXT
1763 && (dc->cpustate_changed || org_flags != dc->tb_flags)) {
1764 dc->is_jmp = DISAS_UPDATE;
1765 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1766 }
1767 t_sync_flags(dc);
1768
1769 if (unlikely(env->singlestep_enabled)) {
6c5f738d
EI		 1770 TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
1771
1772 if (dc->is_jmp != DISAS_JUMP) {
4acb54ba 1773 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
6c5f738d
EI		 1774 }
1775 gen_helper_raise_exception(tmp);
1776 tcg_temp_free_i32(tmp);
4acb54ba
EI		 1777 } else {
1778 switch(dc->is_jmp) {
1779 case DISAS_NEXT:
1780 gen_goto_tb(dc, 1, npc);
1781 break;
1782 default:
1783 case DISAS_JUMP:
1784 case DISAS_UPDATE:
1785 /* indicate that the hash table must be used
1786 to find the next TB */
1787 tcg_gen_exit_tb(0);
1788 break;
1789 case DISAS_TB_JUMP:
1790 /* nothing more to generate */
1791 break;
1792 }
1793 }
1794 gen_icount_end(tb, num_insns);
1795 *gen_opc_ptr = INDEX_op_end;
1796 if (search_pc) {
1797 j = gen_opc_ptr - gen_opc_buf;
1798 lj++;
1799 while (lj <= j)
1800 gen_opc_instr_start[lj++] = 0;
1801 } else {
1802 tb->size = dc->pc - pc_start;
1803 tb->icount = num_insns;
1804 }
1805
1806#ifdef DEBUG_DISAS
1807#if !SIM_COMPAT
1808 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1809 qemu_log("\n");
1810#if DISAS_GNU
1811 log_target_disas(pc_start, dc->pc - pc_start, 0);
1812#endif
e6aa0f11 1813 qemu_log("\nisize=%d osize=%td\n",
4acb54ba
EI		 1814 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
1815 }
1816#endif
1817#endif
1818 assert(!dc->abort_at_next_insn);
1819}
1820
1821void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
1822{
1823 gen_intermediate_code_internal(env, tb, 0);
1824}
1825
1826void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
1827{
1828 gen_intermediate_code_internal(env, tb, 1);
1829}
1830
9a78eead 1831void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
4acb54ba
EI		 1832 int flags)
1833{
1834 int i;
1835
1836 if (!env || !f)
1837 return;
1838
1839 cpu_fprintf(f, "IN: PC=%x %s\n",
1840 env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC]));
97694c57 1841 cpu_fprintf(f, "rmsr=%x resr=%x rear=%x debug=%x imm=%x iflags=%x fsr=%x\n",
4c24aa0a 1842 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
97694c57 1843 env->debug, env->imm, env->iflags, env->sregs[SR_FSR]);
17c52a43 1844 cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
4acb54ba
EI		 1845 env->btaken, env->btarget,
1846 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
17c52a43
EI		 1847 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
1848 (env->sregs[SR_MSR] & MSR_EIP),
1849 (env->sregs[SR_MSR] & MSR_IE));
1850
4acb54ba
EI		 1851 for (i = 0; i < 32; i++) {
1852 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1853 if ((i + 1) % 4 == 0)
1854 cpu_fprintf(f, "\n");
1855 }
1856 cpu_fprintf(f, "\n\n");
1857}
1858
1859CPUState *cpu_mb_init (const char *cpu_model)
1860{
1861 CPUState *env;
1862 static int tcg_initialized = 0;
1863 int i;
1864
7267c094 1865 env = g_malloc0(sizeof(CPUState));
4acb54ba
EI		 1866
1867 cpu_exec_init(env);
1868 cpu_reset(env);
927d7217 1869 qemu_init_vcpu(env);
97694c57 1870 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
4acb54ba
EI		 1871
1872 if (tcg_initialized)
1873 return env;
1874
1875 tcg_initialized = 1;
1876
1877 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1878
1879 env_debug = tcg_global_mem_new(TCG_AREG0,
1880 offsetof(CPUState, debug),
1881 "debug0");
1882 env_iflags = tcg_global_mem_new(TCG_AREG0,
1883 offsetof(CPUState, iflags),
1884 "iflags");
1885 env_imm = tcg_global_mem_new(TCG_AREG0,
1886 offsetof(CPUState, imm),
1887 "imm");
1888 env_btarget = tcg_global_mem_new(TCG_AREG0,
1889 offsetof(CPUState, btarget),
1890 "btarget");
1891 env_btaken = tcg_global_mem_new(TCG_AREG0,
1892 offsetof(CPUState, btaken),
1893 "btaken");
1894 for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
1895 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
1896 offsetof(CPUState, regs[i]),
1897 regnames[i]);
1898 }
1899 for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) {
1900 cpu_SR[i] = tcg_global_mem_new(TCG_AREG0,
1901 offsetof(CPUState, sregs[i]),
1902 special_regnames[i]);
1903 }
1904#define GEN_HELPER 2
1905#include "helper.h"
1906
1907 return env;
1908}
1909
1910void cpu_reset (CPUState *env)
1911{
1912 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1913 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1914 log_cpu_state(env, 0);
1915 }
1916
1917 memset(env, 0, offsetof(CPUMBState, breakpoints));
1918 tlb_flush(env, 1);
1919
4898427e
EI		 1920 env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
1921 | PVR0_USE_BARREL_MASK \
1922 | PVR0_USE_DIV_MASK \
1923 | PVR0_USE_HW_MUL_MASK \
1924 | PVR0_USE_EXC_MASK \
1925 | PVR0_USE_ICACHE_MASK \
1926 | PVR0_USE_DCACHE_MASK \
1927 | PVR0_USE_MMU \
1928 | (0xb << 8);
1929 env->pvr.regs[2] = PVR2_D_OPB_MASK \
1930 | PVR2_D_LMB_MASK \
1931 | PVR2_I_OPB_MASK \
1932 | PVR2_I_LMB_MASK \
1933 | PVR2_USE_MSR_INSTR \
1934 | PVR2_USE_PCMP_INSTR \
1935 | PVR2_USE_BARREL_MASK \
1936 | PVR2_USE_DIV_MASK \
1937 | PVR2_USE_HW_MUL_MASK \
1938 | PVR2_USE_MUL64_MASK \
97694c57
EI		 1939 | PVR2_USE_FPU_MASK \
1940 | PVR2_USE_FPU2_MASK \
1941 | PVR2_FPU_EXC_MASK \
4898427e
EI		 1942 | 0;
1943 env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
1944 env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
1945
4acb54ba
EI		 1946#if defined(CONFIG_USER_ONLY)
1947 /* start in user mode with interrupts enabled. */
97694c57 1948 env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
4acb54ba
EI		 1949 env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */
1950#else
97694c57 1951 env->sregs[SR_MSR] = 0;
4acb54ba 1952 mmu_init(&env->mmu);
4898427e
EI		 1953 env->mmu.c_mmu = 3;
1954 env->mmu.c_mmu_tlb_access = 3;
1955 env->mmu.c_mmu_zones = 16;
4acb54ba
EI		 1956#endif
1957}
1958
e87b7cb0 1959void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
4acb54ba
EI		 1960{
1961 env->sregs[SR_PC] = gen_opc_pc[pc_pos];
1962}
Qemu copy for testing