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microblaze: Speed up base + index addressing mode
[qemu.git] / target-microblaze / translate.c
CommitLineData
4acb54ba
EI		 1/*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba
EI		 18 */
19
20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25#include <assert.h>
26
27#include "cpu.h"
28#include "exec-all.h"
29#include "disas.h"
30#include "tcg-op.h"
31#include "helper.h"
32#include "microblaze-decode.h"
33#include "qemu-common.h"
34
35#define GEN_HELPER 1
36#include "helper.h"
37
38#define SIM_COMPAT 0
39#define DISAS_GNU 1
40#define DISAS_MB 1
41#if DISAS_MB && !SIM_COMPAT
42# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
43#else
44# define LOG_DIS(...) do { } while (0)
45#endif
46
47#define D(x)
48
49#define EXTRACT_FIELD(src, start, end) \
50 (((src) >> start) & ((1 << (end - start + 1)) - 1))
51
52static TCGv env_debug;
53static TCGv_ptr cpu_env;
54static TCGv cpu_R[32];
55static TCGv cpu_SR[18];
56static TCGv env_imm;
57static TCGv env_btaken;
58static TCGv env_btarget;
59static TCGv env_iflags;
60
61#include "gen-icount.h"
62
63/* This is the state at translation time. */
64typedef struct DisasContext {
65 CPUState *env;
66 target_ulong pc, ppc;
67 target_ulong cache_pc;
68
69 /* Decoder. */
70 int type_b;
71 uint32_t ir;
72 uint8_t opcode;
73 uint8_t rd, ra, rb;
74 uint16_t imm;
75
76 unsigned int cpustate_changed;
77 unsigned int delayed_branch;
78 unsigned int tb_flags, synced_flags; /* tb dependent flags. */
79 unsigned int clear_imm;
80 int is_jmp;
81
82#define JMP_NOJMP 0
83#define JMP_DIRECT 1
84#define JMP_INDIRECT 2
85 unsigned int jmp;
86 uint32_t jmp_pc;
87
88 int abort_at_next_insn;
89 int nr_nops;
90 struct TranslationBlock *tb;
91 int singlestep_enabled;
92} DisasContext;
93
38972938 94static const char *regnames[] =
4acb54ba
EI		 95{
96 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
97 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
98 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
99 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
100};
101
38972938 102static const char *special_regnames[] =
4acb54ba
EI		 103{
104 "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
105 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
106 "sr16", "sr17", "sr18"
107};
108
109/* Sign extend at translation time. */
110static inline int sign_extend(unsigned int val, unsigned int width)
111{
112 int sval;
113
114 /* LSL. */
115 val <<= 31 - width;
116 sval = val;
117 /* ASR. */
118 sval >>= 31 - width;
119 return sval;
120}
121
122static inline void t_sync_flags(DisasContext *dc)
123{
124 /* Synch the tb dependant flags between translator and runtime. */
125 if (dc->tb_flags != dc->synced_flags) {
126 tcg_gen_movi_tl(env_iflags, dc->tb_flags);
127 dc->synced_flags = dc->tb_flags;
128 }
129}
130
131static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
132{
133 TCGv_i32 tmp = tcg_const_i32(index);
134
135 t_sync_flags(dc);
136 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
137 gen_helper_raise_exception(tmp);
138 tcg_temp_free_i32(tmp);
139 dc->is_jmp = DISAS_UPDATE;
140}
141
142static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
143{
144 TranslationBlock *tb;
145 tb = dc->tb;
146 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
147 tcg_gen_goto_tb(n);
148 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
149 tcg_gen_exit_tb((long)tb + n);
150 } else {
151 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
152 tcg_gen_exit_tb(0);
153 }
154}
155
61204ce8
EI		 156/* True if ALU operand b is a small immediate that may deserve
157 faster treatment. */
158static inline int dec_alu_op_b_is_small_imm(DisasContext *dc)
159{
160 /* Immediate insn without the imm prefix ? */
161 return dc->type_b && !(dc->tb_flags & IMM_FLAG);
162}
163
4acb54ba
EI		 164static inline TCGv *dec_alu_op_b(DisasContext *dc)
165{
166 if (dc->type_b) {
167 if (dc->tb_flags & IMM_FLAG)
168 tcg_gen_ori_tl(env_imm, env_imm, dc->imm);
169 else
170 tcg_gen_movi_tl(env_imm, (int32_t)((int16_t)dc->imm));
171 return &env_imm;
172 } else
173 return &cpu_R[dc->rb];
174}
175
176static void dec_add(DisasContext *dc)
177{
178 unsigned int k, c;
179
180 k = dc->opcode & 4;
181 c = dc->opcode & 2;
182
183 LOG_DIS("add%s%s%s r%d r%d r%d\n",
184 dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "",
185 dc->rd, dc->ra, dc->rb);
186
187 if (k && !c && dc->rd)
188 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
189 else if (dc->rd)
190 gen_helper_addkc(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)),
191 tcg_const_tl(k), tcg_const_tl(c));
192 else {
193 TCGv d = tcg_temp_new();
194 gen_helper_addkc(d, cpu_R[dc->ra], *(dec_alu_op_b(dc)),
195 tcg_const_tl(k), tcg_const_tl(c));
196 tcg_temp_free(d);
197 }
198}
199
200static void dec_sub(DisasContext *dc)
201{
202 unsigned int u, cmp, k, c;
203
204 u = dc->imm & 2;
205 k = dc->opcode & 4;
206 c = dc->opcode & 2;
207 cmp = (dc->imm & 1) && (!dc->type_b) && k;
208
209 if (cmp) {
210 LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir);
211 if (dc->rd) {
212 if (u)
213 gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
214 else
215 gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
216 }
217 } else {
218 LOG_DIS("sub%s%s r%d, r%d r%d\n",
219 k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb);
220
221 if (!k || c) {
222 TCGv t;
223 t = tcg_temp_new();
224 if (dc->rd)
225 gen_helper_subkc(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)),
226 tcg_const_tl(k), tcg_const_tl(c));
227 else
228 gen_helper_subkc(t, cpu_R[dc->ra], *(dec_alu_op_b(dc)),
229 tcg_const_tl(k), tcg_const_tl(c));
230 tcg_temp_free(t);
231 }
232 else if (dc->rd)
233 tcg_gen_sub_tl(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
234 }
235}
236
237static void dec_pattern(DisasContext *dc)
238{
239 unsigned int mode;
240 int l1;
241
1567a005 242 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 243 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 244 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
245 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
246 t_gen_raise_exception(dc, EXCP_HW_EXCP);
247 }
248
4acb54ba
EI		 249 mode = dc->opcode & 3;
250 switch (mode) {
251 case 0:
252 /* pcmpbf. */
253 LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
254 if (dc->rd)
255 gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
256 break;
257 case 2:
258 LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
259 if (dc->rd) {
260 TCGv t0 = tcg_temp_local_new();
261 l1 = gen_new_label();
262 tcg_gen_movi_tl(t0, 1);
263 tcg_gen_brcond_tl(TCG_COND_EQ,
264 cpu_R[dc->ra], cpu_R[dc->rb], l1);
265 tcg_gen_movi_tl(t0, 0);
266 gen_set_label(l1);
267 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
268 tcg_temp_free(t0);
269 }
270 break;
271 case 3:
272 LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
273 l1 = gen_new_label();
274 if (dc->rd) {
275 TCGv t0 = tcg_temp_local_new();
276 tcg_gen_movi_tl(t0, 1);
277 tcg_gen_brcond_tl(TCG_COND_NE,
278 cpu_R[dc->ra], cpu_R[dc->rb], l1);
279 tcg_gen_movi_tl(t0, 0);
280 gen_set_label(l1);
281 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
282 tcg_temp_free(t0);
283 }
284 break;
285 default:
286 cpu_abort(dc->env,
287 "unsupported pattern insn opcode=%x\n", dc->opcode);
288 break;
289 }
290}
291
292static void dec_and(DisasContext *dc)
293{
294 unsigned int not;
295
296 if (!dc->type_b && (dc->imm & (1 << 10))) {
297 dec_pattern(dc);
298 return;
299 }
300
301 not = dc->opcode & (1 << 1);
302 LOG_DIS("and%s\n", not ? "n" : "");
303
304 if (!dc->rd)
305 return;
306
307 if (not) {
308 TCGv t = tcg_temp_new();
309 tcg_gen_not_tl(t, *(dec_alu_op_b(dc)));
310 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], t);
311 tcg_temp_free(t);
312 } else
313 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
314}
315
316static void dec_or(DisasContext *dc)
317{
318 if (!dc->type_b && (dc->imm & (1 << 10))) {
319 dec_pattern(dc);
320 return;
321 }
322
323 LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm);
324 if (dc->rd)
325 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
326}
327
328static void dec_xor(DisasContext *dc)
329{
330 if (!dc->type_b && (dc->imm & (1 << 10))) {
331 dec_pattern(dc);
332 return;
333 }
334
335 LOG_DIS("xor r%d\n", dc->rd);
336 if (dc->rd)
337 tcg_gen_xor_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
338}
339
340static void read_carry(DisasContext *dc, TCGv d)
341{
342 tcg_gen_shri_tl(d, cpu_SR[SR_MSR], 31);
343}
344
345static void write_carry(DisasContext *dc, TCGv v)
346{
347 TCGv t0 = tcg_temp_new();
348 tcg_gen_shli_tl(t0, v, 31);
349 tcg_gen_sari_tl(t0, t0, 31);
350 tcg_gen_mov_tl(env_debug, t0);
351 tcg_gen_andi_tl(t0, t0, (MSR_C | MSR_CC));
352 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR],
353 ~(MSR_C | MSR_CC));
354 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0);
355 tcg_temp_free(t0);
356}
357
358
359static inline void msr_read(DisasContext *dc, TCGv d)
360{
361 tcg_gen_mov_tl(d, cpu_SR[SR_MSR]);
362}
363
364static inline void msr_write(DisasContext *dc, TCGv v)
365{
366 dc->cpustate_changed = 1;
367 tcg_gen_mov_tl(cpu_SR[SR_MSR], v);
368 /* PVR, we have a processor version register. */
369 tcg_gen_ori_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], (1 << 10));
370}
371
372static void dec_msr(DisasContext *dc)
373{
374 TCGv t0, t1;
375 unsigned int sr, to, rn;
1567a005 376 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 377
378 sr = dc->imm & ((1 << 14) - 1);
379 to = dc->imm & (1 << 14);
380 dc->type_b = 1;
381 if (to)
382 dc->cpustate_changed = 1;
383
384 /* msrclr and msrset. */
385 if (!(dc->imm & (1 << 15))) {
386 unsigned int clr = dc->ir & (1 << 16);
387
388 LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
389 dc->rd, dc->imm);
1567a005
EI		 390
391 if (!(dc->env->pvr.regs[2] & PVR2_USE_MSR_INSTR)) {
392 /* nop??? */
393 return;
394 }
395
396 if ((dc->tb_flags & MSR_EE_FLAG)
397 && mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) {
398 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
399 t_gen_raise_exception(dc, EXCP_HW_EXCP);
400 return;
401 }
402
4acb54ba
EI		 403 if (dc->rd)
404 msr_read(dc, cpu_R[dc->rd]);
405
406 t0 = tcg_temp_new();
407 t1 = tcg_temp_new();
408 msr_read(dc, t0);
409 tcg_gen_mov_tl(t1, *(dec_alu_op_b(dc)));
410
411 if (clr) {
412 tcg_gen_not_tl(t1, t1);
413 tcg_gen_and_tl(t0, t0, t1);
414 } else
415 tcg_gen_or_tl(t0, t0, t1);
416 msr_write(dc, t0);
417 tcg_temp_free(t0);
418 tcg_temp_free(t1);
419 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
420 dc->is_jmp = DISAS_UPDATE;
421 return;
422 }
423
1567a005
EI		 424 if (to) {
425 if ((dc->tb_flags & MSR_EE_FLAG)
426 && mem_index == MMU_USER_IDX) {
427 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
428 t_gen_raise_exception(dc, EXCP_HW_EXCP);
429 return;
430 }
431 }
432
4acb54ba
EI		 433#if !defined(CONFIG_USER_ONLY)
434 /* Catch read/writes to the mmu block. */
435 if ((sr & ~0xff) == 0x1000) {
436 sr &= 7;
437 LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
438 if (to)
439 gen_helper_mmu_write(tcg_const_tl(sr), cpu_R[dc->ra]);
440 else
441 gen_helper_mmu_read(cpu_R[dc->rd], tcg_const_tl(sr));
442 return;
443 }
444#endif
445
446 if (to) {
447 LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
448 switch (sr) {
449 case 0:
450 break;
451 case 1:
452 msr_write(dc, cpu_R[dc->ra]);
453 break;
454 case 0x3:
455 tcg_gen_mov_tl(cpu_SR[SR_EAR], cpu_R[dc->ra]);
456 break;
457 case 0x5:
458 tcg_gen_mov_tl(cpu_SR[SR_ESR], cpu_R[dc->ra]);
459 break;
460 case 0x7:
461 /* Ignored at the moment. */
462 break;
463 default:
464 cpu_abort(dc->env, "unknown mts reg %x\n", sr);
465 break;
466 }
467 } else {
468 LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm);
469
470 switch (sr) {
471 case 0:
472 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
473 break;
474 case 1:
475 msr_read(dc, cpu_R[dc->rd]);
476 break;
477 case 0x3:
478 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_EAR]);
479 break;
480 case 0x5:
481 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_ESR]);
482 break;
483 case 0x7:
484 tcg_gen_movi_tl(cpu_R[dc->rd], 0);
485 break;
486 case 0xb:
487 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]);
488 break;
489 case 0x2000:
490 case 0x2001:
491 case 0x2002:
492 case 0x2003:
493 case 0x2004:
494 case 0x2005:
495 case 0x2006:
496 case 0x2007:
497 case 0x2008:
498 case 0x2009:
499 case 0x200a:
500 case 0x200b:
501 case 0x200c:
502 rn = sr & 0xf;
503 tcg_gen_ld_tl(cpu_R[dc->rd],
504 cpu_env, offsetof(CPUState, pvr.regs[rn]));
505 break;
506 default:
507 cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
508 break;
509 }
510 }
ee7dbcf8
EI		 511
512 if (dc->rd == 0) {
513 tcg_gen_movi_tl(cpu_R[0], 0);
514 }
4acb54ba
EI		 515}
516
517/* 64-bit signed mul, lower result in d and upper in d2. */
518static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
519{
520 TCGv_i64 t0, t1;
521
522 t0 = tcg_temp_new_i64();
523 t1 = tcg_temp_new_i64();
524
525 tcg_gen_ext_i32_i64(t0, a);
526 tcg_gen_ext_i32_i64(t1, b);
527 tcg_gen_mul_i64(t0, t0, t1);
528
529 tcg_gen_trunc_i64_i32(d, t0);
530 tcg_gen_shri_i64(t0, t0, 32);
531 tcg_gen_trunc_i64_i32(d2, t0);
532
533 tcg_temp_free_i64(t0);
534 tcg_temp_free_i64(t1);
535}
536
537/* 64-bit unsigned muls, lower result in d and upper in d2. */
538static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
539{
540 TCGv_i64 t0, t1;
541
542 t0 = tcg_temp_new_i64();
543 t1 = tcg_temp_new_i64();
544
545 tcg_gen_extu_i32_i64(t0, a);
546 tcg_gen_extu_i32_i64(t1, b);
547 tcg_gen_mul_i64(t0, t0, t1);
548
549 tcg_gen_trunc_i64_i32(d, t0);
550 tcg_gen_shri_i64(t0, t0, 32);
551 tcg_gen_trunc_i64_i32(d2, t0);
552
553 tcg_temp_free_i64(t0);
554 tcg_temp_free_i64(t1);
555}
556
557/* Multiplier unit. */
558static void dec_mul(DisasContext *dc)
559{
560 TCGv d[2];
561 unsigned int subcode;
562
1567a005 563 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 564 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 565 && !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
566 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
567 t_gen_raise_exception(dc, EXCP_HW_EXCP);
568 return;
569 }
570
4acb54ba
EI		 571 subcode = dc->imm & 3;
572 d[0] = tcg_temp_new();
573 d[1] = tcg_temp_new();
574
575 if (dc->type_b) {
576 LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm);
577 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
578 goto done;
579 }
580
1567a005
EI		 581 /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
582 if (subcode >= 1 && subcode <= 3
583 && !((dc->env->pvr.regs[2] & PVR2_USE_MUL64_MASK))) {
584 /* nop??? */
585 }
586
4acb54ba
EI		 587 switch (subcode) {
588 case 0:
589 LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
590 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], cpu_R[dc->rb]);
591 break;
592 case 1:
593 LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
594 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
595 break;
596 case 2:
597 LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
598 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
599 break;
600 case 3:
601 LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
602 t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
603 break;
604 default:
605 cpu_abort(dc->env, "unknown MUL insn %x\n", subcode);
606 break;
607 }
608done:
609 tcg_temp_free(d[0]);
610 tcg_temp_free(d[1]);
611}
612
613/* Div unit. */
614static void dec_div(DisasContext *dc)
615{
616 unsigned int u;
617
618 u = dc->imm & 2;
619 LOG_DIS("div\n");
620
97f90cbf 621 if ((dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 622 && !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) {
623 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
624 t_gen_raise_exception(dc, EXCP_HW_EXCP);
625 }
626
4acb54ba
EI		 627 if (u)
628 gen_helper_divu(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
629 else
630 gen_helper_divs(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
631 if (!dc->rd)
632 tcg_gen_movi_tl(cpu_R[dc->rd], 0);
633}
634
635static void dec_barrel(DisasContext *dc)
636{
637 TCGv t0;
638 unsigned int s, t;
639
1567a005 640 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 641 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 642 && !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
643 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
644 t_gen_raise_exception(dc, EXCP_HW_EXCP);
645 return;
646 }
647
4acb54ba
EI		 648 s = dc->imm & (1 << 10);
649 t = dc->imm & (1 << 9);
650
651 LOG_DIS("bs%s%s r%d r%d r%d\n",
652 s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
653
654 t0 = tcg_temp_new();
655
656 tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
657 tcg_gen_andi_tl(t0, t0, 31);
658
659 if (s)
660 tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
661 else {
662 if (t)
663 tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
664 else
665 tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
666 }
667}
668
669static void dec_bit(DisasContext *dc)
670{
671 TCGv t0, t1;
672 unsigned int op;
1567a005 673 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 674
675 op = dc->ir & ((1 << 8) - 1);
676 switch (op) {
677 case 0x21:
678 /* src. */
679 t0 = tcg_temp_new();
680
681 LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
682 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
683 if (dc->rd) {
684 t1 = tcg_temp_new();
685 read_carry(dc, t1);
686 tcg_gen_shli_tl(t1, t1, 31);
687
688 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
689 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t1);
690 tcg_temp_free(t1);
691 }
692
693 /* Update carry. */
694 write_carry(dc, t0);
695 tcg_temp_free(t0);
696 break;
697
698 case 0x1:
699 case 0x41:
700 /* srl. */
701 t0 = tcg_temp_new();
702 LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
703
704 /* Update carry. */
705 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
706 write_carry(dc, t0);
707 tcg_temp_free(t0);
708 if (dc->rd) {
709 if (op == 0x41)
710 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
711 else
712 tcg_gen_sari_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
713 }
714 break;
715 case 0x60:
716 LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra);
717 tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
718 break;
719 case 0x61:
720 LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra);
721 tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
722 break;
723 case 0x64:
f062a3c7
EI		 724 case 0x66:
725 case 0x74:
726 case 0x76:
4acb54ba
EI		 727 /* wdc. */
728 LOG_DIS("wdc r%d\n", dc->ra);
1567a005
EI		 729 if ((dc->tb_flags & MSR_EE_FLAG)
730 && mem_index == MMU_USER_IDX) {
731 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
732 t_gen_raise_exception(dc, EXCP_HW_EXCP);
733 return;
734 }
4acb54ba
EI		 735 break;
736 case 0x68:
737 /* wic. */
738 LOG_DIS("wic r%d\n", dc->ra);
1567a005
EI		 739 if ((dc->tb_flags & MSR_EE_FLAG)
740 && mem_index == MMU_USER_IDX) {
741 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
742 t_gen_raise_exception(dc, EXCP_HW_EXCP);
743 return;
744 }
4acb54ba
EI		 745 break;
746 default:
747 cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
748 dc->pc, op, dc->rd, dc->ra, dc->rb);
749 break;
750 }
751}
752
753static inline void sync_jmpstate(DisasContext *dc)
754{
755 if (dc->jmp == JMP_DIRECT) {
756 dc->jmp = JMP_INDIRECT;
757 tcg_gen_movi_tl(env_btaken, 1);
758 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
759 }
760}
761
762static void dec_imm(DisasContext *dc)
763{
764 LOG_DIS("imm %x\n", dc->imm << 16);
765 tcg_gen_movi_tl(env_imm, (dc->imm << 16));
766 dc->tb_flags |= IMM_FLAG;
767 dc->clear_imm = 0;
768}
769
770static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
771 unsigned int size)
772{
773 int mem_index = cpu_mmu_index(dc->env);
774
775 if (size == 1) {
776 tcg_gen_qemu_ld8u(dst, addr, mem_index);
777 } else if (size == 2) {
778 tcg_gen_qemu_ld16u(dst, addr, mem_index);
779 } else if (size == 4) {
780 tcg_gen_qemu_ld32u(dst, addr, mem_index);
781 } else
782 cpu_abort(dc->env, "Incorrect load size %d\n", size);
783}
784
785static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
786{
787 unsigned int extimm = dc->tb_flags & IMM_FLAG;
788
789 /* Treat the fast cases first. */
790 if (!dc->type_b) {
4b5ef0b5
EI		 791 /* If any of the regs is r0, return a ptr to the other. */
792 if (dc->ra == 0) {
793 return &cpu_R[dc->rb];
794 } else if (dc->rb == 0) {
795 return &cpu_R[dc->ra];
796 }
797
4acb54ba
EI		 798 *t = tcg_temp_new();
799 tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
800 return t;
801 }
802 /* Immediate. */
803 if (!extimm) {
804 if (dc->imm == 0) {
805 return &cpu_R[dc->ra];
806 }
807 *t = tcg_temp_new();
808 tcg_gen_movi_tl(*t, (int32_t)((int16_t)dc->imm));
809 tcg_gen_add_tl(*t, cpu_R[dc->ra], *t);
810 } else {
811 *t = tcg_temp_new();
812 tcg_gen_add_tl(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
813 }
814
815 return t;
816}
817
818static void dec_load(DisasContext *dc)
819{
820 TCGv t, *addr;
821 unsigned int size;
822
823 size = 1 << (dc->opcode & 3);
0187688f 824 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
97f90cbf 825 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
0187688f
EI		 826 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
827 t_gen_raise_exception(dc, EXCP_HW_EXCP);
828 return;
829 }
4acb54ba
EI		 830
831 LOG_DIS("l %x %d\n", dc->opcode, size);
832 t_sync_flags(dc);
833 addr = compute_ldst_addr(dc, &t);
834
835 /* If we get a fault on a dslot, the jmpstate better be in sync. */
836 sync_jmpstate(dc);
968a40f6
EI		 837
838 /* Verify alignment if needed. */
839 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
a12f6507
EI		 840 TCGv v = tcg_temp_new();
841
842 /*
843 * Microblaze gives MMU faults priority over faults due to
844 * unaligned addresses. That's why we speculatively do the load
845 * into v. If the load succeeds, we verify alignment of the
846 * address and if that succeeds we write into the destination reg.
847 */
848 gen_load(dc, v, *addr, size);
849
850 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
968a40f6 851 gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
3aa80988 852 tcg_const_tl(0), tcg_const_tl(size - 1));
a12f6507
EI		 853 if (dc->rd)
854 tcg_gen_mov_tl(cpu_R[dc->rd], v);
855 tcg_temp_free(v);
968a40f6 856 } else {
a12f6507
EI		 857 if (dc->rd) {
858 gen_load(dc, cpu_R[dc->rd], *addr, size);
859 } else {
860 gen_load(dc, env_imm, *addr, size);
861 }
4acb54ba
EI		 862 }
863
864 if (addr == &t)
865 tcg_temp_free(t);
866}
867
868static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
869 unsigned int size)
870{
871 int mem_index = cpu_mmu_index(dc->env);
872
873 if (size == 1)
874 tcg_gen_qemu_st8(val, addr, mem_index);
875 else if (size == 2) {
876 tcg_gen_qemu_st16(val, addr, mem_index);
877 } else if (size == 4) {
878 tcg_gen_qemu_st32(val, addr, mem_index);
879 } else
880 cpu_abort(dc->env, "Incorrect store size %d\n", size);
881}
882
883static void dec_store(DisasContext *dc)
884{
885 TCGv t, *addr;
886 unsigned int size;
887
888 size = 1 << (dc->opcode & 3);
889
0187688f 890 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
97f90cbf 891 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
0187688f
EI		 892 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
893 t_gen_raise_exception(dc, EXCP_HW_EXCP);
894 return;
895 }
896
4acb54ba
EI		 897 LOG_DIS("s%d%s\n", size, dc->type_b ? "i" : "");
898 t_sync_flags(dc);
899 /* If we get a fault on a dslot, the jmpstate better be in sync. */
900 sync_jmpstate(dc);
901 addr = compute_ldst_addr(dc, &t);
968a40f6 902
a12f6507
EI		 903 gen_store(dc, *addr, cpu_R[dc->rd], size);
904
968a40f6
EI		 905 /* Verify alignment if needed. */
906 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
a12f6507
EI		 907 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
908 /* FIXME: if the alignment is wrong, we should restore the value
909 * in memory.
910 */
968a40f6 911 gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
3aa80988 912 tcg_const_tl(1), tcg_const_tl(size - 1));
968a40f6
EI		 913 }
914
4acb54ba
EI		 915 if (addr == &t)
916 tcg_temp_free(t);
917}
918
919static inline void eval_cc(DisasContext *dc, unsigned int cc,
920 TCGv d, TCGv a, TCGv b)
921{
4acb54ba
EI		 922 switch (cc) {
923 case CC_EQ:
b2565c69 924 tcg_gen_setcond_tl(TCG_COND_EQ, d, a, b);
4acb54ba
EI		 925 break;
926 case CC_NE:
b2565c69 927 tcg_gen_setcond_tl(TCG_COND_NE, d, a, b);
4acb54ba
EI		 928 break;
929 case CC_LT:
b2565c69 930 tcg_gen_setcond_tl(TCG_COND_LT, d, a, b);
4acb54ba
EI		 931 break;
932 case CC_LE:
b2565c69 933 tcg_gen_setcond_tl(TCG_COND_LE, d, a, b);
4acb54ba
EI		 934 break;
935 case CC_GE:
b2565c69 936 tcg_gen_setcond_tl(TCG_COND_GE, d, a, b);
4acb54ba
EI		 937 break;
938 case CC_GT:
b2565c69 939 tcg_gen_setcond_tl(TCG_COND_GT, d, a, b);
4acb54ba
EI		 940 break;
941 default:
942 cpu_abort(dc->env, "Unknown condition code %x.\n", cc);
943 break;
944 }
945}
946
947static void eval_cond_jmp(DisasContext *dc, TCGv pc_true, TCGv pc_false)
948{
949 int l1;
950
951 l1 = gen_new_label();
952 /* Conditional jmp. */
953 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_false);
954 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
955 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_true);
956 gen_set_label(l1);
957}
958
959static void dec_bcc(DisasContext *dc)
960{
961 unsigned int cc;
962 unsigned int dslot;
963
964 cc = EXTRACT_FIELD(dc->ir, 21, 23);
965 dslot = dc->ir & (1 << 25);
966 LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm);
967
968 dc->delayed_branch = 1;
969 if (dslot) {
970 dc->delayed_branch = 2;
971 dc->tb_flags |= D_FLAG;
972 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
973 cpu_env, offsetof(CPUState, bimm));
974 }
975
61204ce8
EI		 976 if (dec_alu_op_b_is_small_imm(dc)) {
977 int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */
978
979 tcg_gen_movi_tl(env_btarget, dc->pc + offset);
980 } else {
981 tcg_gen_movi_tl(env_btarget, dc->pc);
982 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
983 }
4acb54ba 984 dc->jmp = JMP_INDIRECT;
61204ce8 985 eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_tl(0));
4acb54ba
EI		 986}
987
988static void dec_br(DisasContext *dc)
989{
990 unsigned int dslot, link, abs;
ff21f70a 991 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 992
993 dslot = dc->ir & (1 << 20);
994 abs = dc->ir & (1 << 19);
995 link = dc->ir & (1 << 18);
996 LOG_DIS("br%s%s%s%s imm=%x\n",
997 abs ? "a" : "", link ? "l" : "",
998 dc->type_b ? "i" : "", dslot ? "d" : "",
999 dc->imm);
1000
1001 dc->delayed_branch = 1;
1002 if (dslot) {
1003 dc->delayed_branch = 2;
1004 dc->tb_flags |= D_FLAG;
1005 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1006 cpu_env, offsetof(CPUState, bimm));
1007 }
1008 if (link && dc->rd)
1009 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
1010
1011 dc->jmp = JMP_INDIRECT;
1012 if (abs) {
1013 tcg_gen_movi_tl(env_btaken, 1);
1014 tcg_gen_mov_tl(env_btarget, *(dec_alu_op_b(dc)));
ff21f70a
EI		 1015 if (link && !dslot) {
1016 if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18))
1017 t_gen_raise_exception(dc, EXCP_BREAK);
1018 if (dc->imm == 0) {
1019 if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) {
1020 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1021 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1022 return;
1023 }
1024
1025 t_gen_raise_exception(dc, EXCP_DEBUG);
1026 }
1027 }
4acb54ba 1028 } else {
61204ce8
EI		 1029 if (dec_alu_op_b_is_small_imm(dc)) {
1030 dc->jmp = JMP_DIRECT;
1031 dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm);
1032 } else {
4acb54ba
EI		 1033 tcg_gen_movi_tl(env_btaken, 1);
1034 tcg_gen_movi_tl(env_btarget, dc->pc);
1035 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
4acb54ba
EI		 1036 }
1037 }
1038}
1039
1040static inline void do_rti(DisasContext *dc)
1041{
1042 TCGv t0, t1;
1043 t0 = tcg_temp_new();
1044 t1 = tcg_temp_new();
1045 tcg_gen_shri_tl(t0, cpu_SR[SR_MSR], 1);
1046 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_IE);
1047 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1048
1049 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1050 tcg_gen_or_tl(t1, t1, t0);
1051 msr_write(dc, t1);
1052 tcg_temp_free(t1);
1053 tcg_temp_free(t0);
1054 dc->tb_flags &= ~DRTI_FLAG;
1055}
1056
1057static inline void do_rtb(DisasContext *dc)
1058{
1059 TCGv t0, t1;
1060 t0 = tcg_temp_new();
1061 t1 = tcg_temp_new();
1062 tcg_gen_andi_tl(t1, cpu_SR[SR_MSR], ~MSR_BIP);
1063 tcg_gen_shri_tl(t0, t1, 1);
1064 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1065
1066 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1067 tcg_gen_or_tl(t1, t1, t0);
1068 msr_write(dc, t1);
1069 tcg_temp_free(t1);
1070 tcg_temp_free(t0);
1071 dc->tb_flags &= ~DRTB_FLAG;
1072}
1073
1074static inline void do_rte(DisasContext *dc)
1075{
1076 TCGv t0, t1;
1077 t0 = tcg_temp_new();
1078 t1 = tcg_temp_new();
1079
1080 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_EE);
1081 tcg_gen_andi_tl(t1, t1, ~MSR_EIP);
1082 tcg_gen_shri_tl(t0, t1, 1);
1083 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1084
1085 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1086 tcg_gen_or_tl(t1, t1, t0);
1087 msr_write(dc, t1);
1088 tcg_temp_free(t1);
1089 tcg_temp_free(t0);
1090 dc->tb_flags &= ~DRTE_FLAG;
1091}
1092
1093static void dec_rts(DisasContext *dc)
1094{
1095 unsigned int b_bit, i_bit, e_bit;
1567a005 1096 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 1097
1098 i_bit = dc->ir & (1 << 21);
1099 b_bit = dc->ir & (1 << 22);
1100 e_bit = dc->ir & (1 << 23);
1101
1102 dc->delayed_branch = 2;
1103 dc->tb_flags |= D_FLAG;
1104 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1105 cpu_env, offsetof(CPUState, bimm));
1106
1107 if (i_bit) {
1108 LOG_DIS("rtid ir=%x\n", dc->ir);
1567a005
EI		 1109 if ((dc->tb_flags & MSR_EE_FLAG)
1110 && mem_index == MMU_USER_IDX) {
1111 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1112 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1113 }
4acb54ba
EI		 1114 dc->tb_flags |= DRTI_FLAG;
1115 } else if (b_bit) {
1116 LOG_DIS("rtbd ir=%x\n", dc->ir);
1567a005
EI		 1117 if ((dc->tb_flags & MSR_EE_FLAG)
1118 && mem_index == MMU_USER_IDX) {
1119 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1120 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1121 }
4acb54ba
EI		 1122 dc->tb_flags |= DRTB_FLAG;
1123 } else if (e_bit) {
1124 LOG_DIS("rted ir=%x\n", dc->ir);
1567a005
EI		 1125 if ((dc->tb_flags & MSR_EE_FLAG)
1126 && mem_index == MMU_USER_IDX) {
1127 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1128 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1129 }
4acb54ba
EI		 1130 dc->tb_flags |= DRTE_FLAG;
1131 } else
1132 LOG_DIS("rts ir=%x\n", dc->ir);
1133
1134 tcg_gen_movi_tl(env_btaken, 1);
1135 tcg_gen_add_tl(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
1136}
1137
1567a005
EI		 1138static void dec_fpu(DisasContext *dc)
1139{
1140 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 1141 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005 1142 && !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) {
97f90cbf 1143 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
1567a005
EI		 1144 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1145 return;
1146 }
1147
1148 qemu_log ("unimplemented FPU insn pc=%x opc=%x\n", dc->pc, dc->opcode);
1149 dc->abort_at_next_insn = 1;
1150}
1151
4acb54ba
EI		 1152static void dec_null(DisasContext *dc)
1153{
02b33596
EI		 1154 if ((dc->tb_flags & MSR_EE_FLAG)
1155 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
1156 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1157 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1158 return;
1159 }
4acb54ba
EI		 1160 qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
1161 dc->abort_at_next_insn = 1;
1162}
1163
1164static struct decoder_info {
1165 struct {
1166 uint32_t bits;
1167 uint32_t mask;
1168 };
1169 void (*dec)(DisasContext *dc);
1170} decinfo[] = {
1171 {DEC_ADD, dec_add},
1172 {DEC_SUB, dec_sub},
1173 {DEC_AND, dec_and},
1174 {DEC_XOR, dec_xor},
1175 {DEC_OR, dec_or},
1176 {DEC_BIT, dec_bit},
1177 {DEC_BARREL, dec_barrel},
1178 {DEC_LD, dec_load},
1179 {DEC_ST, dec_store},
1180 {DEC_IMM, dec_imm},
1181 {DEC_BR, dec_br},
1182 {DEC_BCC, dec_bcc},
1183 {DEC_RTS, dec_rts},
1567a005 1184 {DEC_FPU, dec_fpu},
4acb54ba
EI		 1185 {DEC_MUL, dec_mul},
1186 {DEC_DIV, dec_div},
1187 {DEC_MSR, dec_msr},
1188 {{0, 0}, dec_null}
1189};
1190
1191static inline void decode(DisasContext *dc)
1192{
1193 uint32_t ir;
1194 int i;
1195
1196 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
1197 tcg_gen_debug_insn_start(dc->pc);
1198
1199 dc->ir = ir = ldl_code(dc->pc);
1200 LOG_DIS("%8.8x\t", dc->ir);
1201
1202 if (dc->ir)
1203 dc->nr_nops = 0;
1204 else {
1567a005 1205 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf
EI		 1206 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1207 && (dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
1567a005
EI		 1208 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1209 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1210 return;
1211 }
1212
4acb54ba
EI		 1213 LOG_DIS("nr_nops=%d\t", dc->nr_nops);
1214 dc->nr_nops++;
1215 if (dc->nr_nops > 4)
1216 cpu_abort(dc->env, "fetching nop sequence\n");
1217 }
1218 /* bit 2 seems to indicate insn type. */
1219 dc->type_b = ir & (1 << 29);
1220
1221 dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1222 dc->rd = EXTRACT_FIELD(ir, 21, 25);
1223 dc->ra = EXTRACT_FIELD(ir, 16, 20);
1224 dc->rb = EXTRACT_FIELD(ir, 11, 15);
1225 dc->imm = EXTRACT_FIELD(ir, 0, 15);
1226
1227 /* Large switch for all insns. */
1228 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
1229 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
1230 decinfo[i].dec(dc);
1231 break;
1232 }
1233 }
1234}
1235
4acb54ba
EI		 1236static void check_breakpoint(CPUState *env, DisasContext *dc)
1237{
1238 CPUBreakpoint *bp;
1239
72cf2d4f
BS		 1240 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1241 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
4acb54ba
EI		 1242 if (bp->pc == dc->pc) {
1243 t_gen_raise_exception(dc, EXCP_DEBUG);
1244 dc->is_jmp = DISAS_UPDATE;
1245 }
1246 }
1247 }
1248}
1249
1250/* generate intermediate code for basic block 'tb'. */
1251static void
1252gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
1253 int search_pc)
1254{
1255 uint16_t *gen_opc_end;
1256 uint32_t pc_start;
1257 int j, lj;
1258 struct DisasContext ctx;
1259 struct DisasContext *dc = &ctx;
1260 uint32_t next_page_start, org_flags;
1261 target_ulong npc;
1262 int num_insns;
1263 int max_insns;
1264
1265 qemu_log_try_set_file(stderr);
1266
1267 pc_start = tb->pc;
1268 dc->env = env;
1269 dc->tb = tb;
1270 org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
1271
1272 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1273
1274 dc->is_jmp = DISAS_NEXT;
1275 dc->jmp = 0;
1276 dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
1277 dc->ppc = pc_start;
1278 dc->pc = pc_start;
1279 dc->cache_pc = -1;
1280 dc->singlestep_enabled = env->singlestep_enabled;
1281 dc->cpustate_changed = 0;
1282 dc->abort_at_next_insn = 0;
1283 dc->nr_nops = 0;
1284
1285 if (pc_start & 3)
1286 cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start);
1287
1288 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1289#if !SIM_COMPAT
1290 qemu_log("--------------\n");
1291 log_cpu_state(env, 0);
1292#endif
1293 }
1294
1295 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1296 lj = -1;
1297 num_insns = 0;
1298 max_insns = tb->cflags & CF_COUNT_MASK;
1299 if (max_insns == 0)
1300 max_insns = CF_COUNT_MASK;
1301
1302 gen_icount_start();
1303 do
1304 {
1305#if SIM_COMPAT
1306 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1307 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1308 gen_helper_debug();
1309 }
1310#endif
1311 check_breakpoint(env, dc);
1312
1313 if (search_pc) {
1314 j = gen_opc_ptr - gen_opc_buf;
1315 if (lj < j) {
1316 lj++;
1317 while (lj < j)
1318 gen_opc_instr_start[lj++] = 0;
1319 }
1320 gen_opc_pc[lj] = dc->pc;
1321 gen_opc_instr_start[lj] = 1;
1322 gen_opc_icount[lj] = num_insns;
1323 }
1324
1325 /* Pretty disas. */
1326 LOG_DIS("%8.8x:\t", dc->pc);
1327
1328 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1329 gen_io_start();
1330
1331 dc->clear_imm = 1;
1332 decode(dc);
1333 if (dc->clear_imm)
1334 dc->tb_flags &= ~IMM_FLAG;
1335 dc->ppc = dc->pc;
1336 dc->pc += 4;
1337 num_insns++;
1338
1339 if (dc->delayed_branch) {
1340 dc->delayed_branch--;
1341 if (!dc->delayed_branch) {
1342 if (dc->tb_flags & DRTI_FLAG)
1343 do_rti(dc);
1344 if (dc->tb_flags & DRTB_FLAG)
1345 do_rtb(dc);
1346 if (dc->tb_flags & DRTE_FLAG)
1347 do_rte(dc);
1348 /* Clear the delay slot flag. */
1349 dc->tb_flags &= ~D_FLAG;
1350 /* If it is a direct jump, try direct chaining. */
1351 if (dc->jmp != JMP_DIRECT) {
1352 eval_cond_jmp(dc, env_btarget, tcg_const_tl(dc->pc));
1353 dc->is_jmp = DISAS_JUMP;
1354 }
1355 break;
1356 }
1357 }
1358 if (env->singlestep_enabled)
1359 break;
1360 } while (!dc->is_jmp && !dc->cpustate_changed
1361 && gen_opc_ptr < gen_opc_end
1362 && !singlestep
1363 && (dc->pc < next_page_start)
1364 && num_insns < max_insns);
1365
1366 npc = dc->pc;
1367 if (dc->jmp == JMP_DIRECT) {
1368 if (dc->tb_flags & D_FLAG) {
1369 dc->is_jmp = DISAS_UPDATE;
1370 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1371 sync_jmpstate(dc);
1372 } else
1373 npc = dc->jmp_pc;
1374 }
1375
1376 if (tb->cflags & CF_LAST_IO)
1377 gen_io_end();
1378 /* Force an update if the per-tb cpu state has changed. */
1379 if (dc->is_jmp == DISAS_NEXT
1380 && (dc->cpustate_changed || org_flags != dc->tb_flags)) {
1381 dc->is_jmp = DISAS_UPDATE;
1382 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1383 }
1384 t_sync_flags(dc);
1385
1386 if (unlikely(env->singlestep_enabled)) {
1387 t_gen_raise_exception(dc, EXCP_DEBUG);
1388 if (dc->is_jmp == DISAS_NEXT)
1389 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1390 } else {
1391 switch(dc->is_jmp) {
1392 case DISAS_NEXT:
1393 gen_goto_tb(dc, 1, npc);
1394 break;
1395 default:
1396 case DISAS_JUMP:
1397 case DISAS_UPDATE:
1398 /* indicate that the hash table must be used
1399 to find the next TB */
1400 tcg_gen_exit_tb(0);
1401 break;
1402 case DISAS_TB_JUMP:
1403 /* nothing more to generate */
1404 break;
1405 }
1406 }
1407 gen_icount_end(tb, num_insns);
1408 *gen_opc_ptr = INDEX_op_end;
1409 if (search_pc) {
1410 j = gen_opc_ptr - gen_opc_buf;
1411 lj++;
1412 while (lj <= j)
1413 gen_opc_instr_start[lj++] = 0;
1414 } else {
1415 tb->size = dc->pc - pc_start;
1416 tb->icount = num_insns;
1417 }
1418
1419#ifdef DEBUG_DISAS
1420#if !SIM_COMPAT
1421 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1422 qemu_log("\n");
1423#if DISAS_GNU
1424 log_target_disas(pc_start, dc->pc - pc_start, 0);
1425#endif
1426 qemu_log("\nisize=%d osize=%zd\n",
1427 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
1428 }
1429#endif
1430#endif
1431 assert(!dc->abort_at_next_insn);
1432}
1433
1434void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
1435{
1436 gen_intermediate_code_internal(env, tb, 0);
1437}
1438
1439void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
1440{
1441 gen_intermediate_code_internal(env, tb, 1);
1442}
1443
1444void cpu_dump_state (CPUState *env, FILE *f,
1445 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1446 int flags)
1447{
1448 int i;
1449
1450 if (!env || !f)
1451 return;
1452
1453 cpu_fprintf(f, "IN: PC=%x %s\n",
1454 env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC]));
4c24aa0a
MS		 1455 cpu_fprintf(f, "rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
1456 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
4acb54ba 1457 env->debug, env->imm, env->iflags);
17c52a43 1458 cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
4acb54ba
EI		 1459 env->btaken, env->btarget,
1460 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
17c52a43
EI		 1461 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
1462 (env->sregs[SR_MSR] & MSR_EIP),
1463 (env->sregs[SR_MSR] & MSR_IE));
1464
4acb54ba
EI		 1465 for (i = 0; i < 32; i++) {
1466 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1467 if ((i + 1) % 4 == 0)
1468 cpu_fprintf(f, "\n");
1469 }
1470 cpu_fprintf(f, "\n\n");
1471}
1472
1473CPUState *cpu_mb_init (const char *cpu_model)
1474{
1475 CPUState *env;
1476 static int tcg_initialized = 0;
1477 int i;
1478
1479 env = qemu_mallocz(sizeof(CPUState));
1480
1481 cpu_exec_init(env);
1482 cpu_reset(env);
1483
4acb54ba
EI		 1484
1485 if (tcg_initialized)
1486 return env;
1487
1488 tcg_initialized = 1;
1489
1490 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1491
1492 env_debug = tcg_global_mem_new(TCG_AREG0,
1493 offsetof(CPUState, debug),
1494 "debug0");
1495 env_iflags = tcg_global_mem_new(TCG_AREG0,
1496 offsetof(CPUState, iflags),
1497 "iflags");
1498 env_imm = tcg_global_mem_new(TCG_AREG0,
1499 offsetof(CPUState, imm),
1500 "imm");
1501 env_btarget = tcg_global_mem_new(TCG_AREG0,
1502 offsetof(CPUState, btarget),
1503 "btarget");
1504 env_btaken = tcg_global_mem_new(TCG_AREG0,
1505 offsetof(CPUState, btaken),
1506 "btaken");
1507 for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
1508 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
1509 offsetof(CPUState, regs[i]),
1510 regnames[i]);
1511 }
1512 for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) {
1513 cpu_SR[i] = tcg_global_mem_new(TCG_AREG0,
1514 offsetof(CPUState, sregs[i]),
1515 special_regnames[i]);
1516 }
1517#define GEN_HELPER 2
1518#include "helper.h"
1519
1520 return env;
1521}
1522
1523void cpu_reset (CPUState *env)
1524{
1525 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1526 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1527 log_cpu_state(env, 0);
1528 }
1529
1530 memset(env, 0, offsetof(CPUMBState, breakpoints));
1531 tlb_flush(env, 1);
1532
4898427e
EI		 1533 env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
1534 | PVR0_USE_BARREL_MASK \
1535 | PVR0_USE_DIV_MASK \
1536 | PVR0_USE_HW_MUL_MASK \
1537 | PVR0_USE_EXC_MASK \
1538 | PVR0_USE_ICACHE_MASK \
1539 | PVR0_USE_DCACHE_MASK \
1540 | PVR0_USE_MMU \
1541 | (0xb << 8);
1542 env->pvr.regs[2] = PVR2_D_OPB_MASK \
1543 | PVR2_D_LMB_MASK \
1544 | PVR2_I_OPB_MASK \
1545 | PVR2_I_LMB_MASK \
1546 | PVR2_USE_MSR_INSTR \
1547 | PVR2_USE_PCMP_INSTR \
1548 | PVR2_USE_BARREL_MASK \
1549 | PVR2_USE_DIV_MASK \
1550 | PVR2_USE_HW_MUL_MASK \
1551 | PVR2_USE_MUL64_MASK \
1552 | 0;
1553 env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
1554 env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
1555
4acb54ba
EI		 1556 env->sregs[SR_MSR] = 0;
1557#if defined(CONFIG_USER_ONLY)
1558 /* start in user mode with interrupts enabled. */
1559 env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */
1560#else
1561 mmu_init(&env->mmu);
4898427e
EI		 1562 env->mmu.c_mmu = 3;
1563 env->mmu.c_mmu_tlb_access = 3;
1564 env->mmu.c_mmu_zones = 16;
4acb54ba
EI		 1565#endif
1566}
1567
1568void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
1569 unsigned long searched_pc, int pc_pos, void *puc)
1570{
1571 env->sregs[SR_PC] = gen_opc_pc[pc_pos];
1572}
Qemu copy for testing