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microblaze: Make write_carryi input a boolean
[qemu.git] / target-microblaze / translate.c
CommitLineData
4acb54ba
EI		 1/*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
dadc1064 5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
4acb54ba
EI		 6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba
EI		 19 */
20
4acb54ba 21#include "cpu.h"
76cad711 22#include "disas/disas.h"
4acb54ba
EI		 23#include "tcg-op.h"
24#include "helper.h"
25#include "microblaze-decode.h"
4acb54ba
EI		 26
27#define GEN_HELPER 1
28#include "helper.h"
29
30#define SIM_COMPAT 0
31#define DISAS_GNU 1
32#define DISAS_MB 1
33#if DISAS_MB && !SIM_COMPAT
34# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
35#else
36# define LOG_DIS(...) do { } while (0)
37#endif
38
39#define D(x)
40
41#define EXTRACT_FIELD(src, start, end) \
42 (((src) >> start) & ((1 << (end - start + 1)) - 1))
43
44static TCGv env_debug;
45static TCGv_ptr cpu_env;
46static TCGv cpu_R[32];
47static TCGv cpu_SR[18];
48static TCGv env_imm;
49static TCGv env_btaken;
50static TCGv env_btarget;
51static TCGv env_iflags;
52
022c62cb 53#include "exec/gen-icount.h"
4acb54ba
EI		 54
55/* This is the state at translation time. */
56typedef struct DisasContext {
68cee38a 57 CPUMBState *env;
a5efa644 58 target_ulong pc;
4acb54ba
EI		 59
60 /* Decoder. */
61 int type_b;
62 uint32_t ir;
63 uint8_t opcode;
64 uint8_t rd, ra, rb;
65 uint16_t imm;
66
67 unsigned int cpustate_changed;
68 unsigned int delayed_branch;
69 unsigned int tb_flags, synced_flags; /* tb dependent flags. */
70 unsigned int clear_imm;
71 int is_jmp;
72
844bab60
EI		 73#define JMP_NOJMP 0
74#define JMP_DIRECT 1
75#define JMP_DIRECT_CC 2
76#define JMP_INDIRECT 3
4acb54ba
EI		 77 unsigned int jmp;
78 uint32_t jmp_pc;
79
80 int abort_at_next_insn;
81 int nr_nops;
82 struct TranslationBlock *tb;
83 int singlestep_enabled;
84} DisasContext;
85
38972938 86static const char *regnames[] =
4acb54ba
EI		 87{
88 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
89 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
90 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
91 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
92};
93
38972938 94static const char *special_regnames[] =
4acb54ba
EI		 95{
96 "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
97 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
98 "sr16", "sr17", "sr18"
99};
100
101/* Sign extend at translation time. */
102static inline int sign_extend(unsigned int val, unsigned int width)
103{
104 int sval;
105
106 /* LSL. */
107 val <<= 31 - width;
108 sval = val;
109 /* ASR. */
110 sval >>= 31 - width;
111 return sval;
112}
113
114static inline void t_sync_flags(DisasContext *dc)
115{
4abf79a4 116 /* Synch the tb dependent flags between translator and runtime. */
4acb54ba
EI		 117 if (dc->tb_flags != dc->synced_flags) {
118 tcg_gen_movi_tl(env_iflags, dc->tb_flags);
119 dc->synced_flags = dc->tb_flags;
120 }
121}
122
123static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
124{
125 TCGv_i32 tmp = tcg_const_i32(index);
126
127 t_sync_flags(dc);
128 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
64254eba 129 gen_helper_raise_exception(cpu_env, tmp);
4acb54ba
EI		 130 tcg_temp_free_i32(tmp);
131 dc->is_jmp = DISAS_UPDATE;
132}
133
134static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
135{
136 TranslationBlock *tb;
137 tb = dc->tb;
138 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
139 tcg_gen_goto_tb(n);
140 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
8cfd0495 141 tcg_gen_exit_tb((uintptr_t)tb + n);
4acb54ba
EI		 142 } else {
143 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
144 tcg_gen_exit_tb(0);
145 }
146}
147
ee8b246f
EI		 148static void read_carry(DisasContext *dc, TCGv d)
149{
150 tcg_gen_shri_tl(d, cpu_SR[SR_MSR], 31);
151}
152
04ec7df7
EI		 153/*
154 * write_carry sets the carry bits in MSR based on bit 0 of v.
155 * v[31:1] are ignored.
156 */
ee8b246f
EI		 157static void write_carry(DisasContext *dc, TCGv v)
158{
159 TCGv t0 = tcg_temp_new();
160 tcg_gen_shli_tl(t0, v, 31);
161 tcg_gen_sari_tl(t0, t0, 31);
162 tcg_gen_andi_tl(t0, t0, (MSR_C | MSR_CC));
163 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR],
164 ~(MSR_C | MSR_CC));
165 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0);
166 tcg_temp_free(t0);
167}
168
65ab5eb4 169static void write_carryi(DisasContext *dc, bool carry)
8cc9b43f
PC		 170{
171 TCGv t0 = tcg_temp_new();
65ab5eb4 172 tcg_gen_movi_tl(t0, carry);
8cc9b43f
PC		 173 write_carry(dc, t0);
174 tcg_temp_free(t0);
175}
176
61204ce8
EI		 177/* True if ALU operand b is a small immediate that may deserve
178 faster treatment. */
179static inline int dec_alu_op_b_is_small_imm(DisasContext *dc)
180{
181 /* Immediate insn without the imm prefix ? */
182 return dc->type_b && !(dc->tb_flags & IMM_FLAG);
183}
184
4acb54ba
EI		 185static inline TCGv *dec_alu_op_b(DisasContext *dc)
186{
187 if (dc->type_b) {
188 if (dc->tb_flags & IMM_FLAG)
189 tcg_gen_ori_tl(env_imm, env_imm, dc->imm);
190 else
191 tcg_gen_movi_tl(env_imm, (int32_t)((int16_t)dc->imm));
192 return &env_imm;
193 } else
194 return &cpu_R[dc->rb];
195}
196
197static void dec_add(DisasContext *dc)
198{
199 unsigned int k, c;
40cbf5b7 200 TCGv cf;
4acb54ba
EI		 201
202 k = dc->opcode & 4;
203 c = dc->opcode & 2;
204
205 LOG_DIS("add%s%s%s r%d r%d r%d\n",
206 dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "",
207 dc->rd, dc->ra, dc->rb);
208
40cbf5b7
EI		 209 /* Take care of the easy cases first. */
210 if (k) {
211 /* k - keep carry, no need to update MSR. */
212 /* If rd == r0, it's a nop. */
213 if (dc->rd) {
214 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
215
216 if (c) {
217 /* c - Add carry into the result. */
218 cf = tcg_temp_new();
219
220 read_carry(dc, cf);
221 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
222 tcg_temp_free(cf);
223 }
224 }
225 return;
226 }
227
228 /* From now on, we can assume k is zero. So we need to update MSR. */
229 /* Extract carry. */
230 cf = tcg_temp_new();
231 if (c) {
232 read_carry(dc, cf);
233 } else {
234 tcg_gen_movi_tl(cf, 0);
235 }
236
237 if (dc->rd) {
238 TCGv ncf = tcg_temp_new();
5d0bb823 239 gen_helper_carry(ncf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf);
4acb54ba 240 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
40cbf5b7
EI		 241 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
242 write_carry(dc, ncf);
243 tcg_temp_free(ncf);
244 } else {
5d0bb823 245 gen_helper_carry(cf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf);
40cbf5b7 246 write_carry(dc, cf);
4acb54ba 247 }
40cbf5b7 248 tcg_temp_free(cf);
4acb54ba
EI		 249}
250
251static void dec_sub(DisasContext *dc)
252{
253 unsigned int u, cmp, k, c;
e0a42ebc 254 TCGv cf, na;
4acb54ba
EI		 255
256 u = dc->imm & 2;
257 k = dc->opcode & 4;
258 c = dc->opcode & 2;
259 cmp = (dc->imm & 1) && (!dc->type_b) && k;
260
261 if (cmp) {
262 LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir);
263 if (dc->rd) {
264 if (u)
265 gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
266 else
267 gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
268 }
e0a42ebc
EI		 269 return;
270 }
271
272 LOG_DIS("sub%s%s r%d, r%d r%d\n",
273 k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb);
274
275 /* Take care of the easy cases first. */
276 if (k) {
277 /* k - keep carry, no need to update MSR. */
278 /* If rd == r0, it's a nop. */
279 if (dc->rd) {
4acb54ba 280 tcg_gen_sub_tl(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
e0a42ebc
EI		 281
282 if (c) {
283 /* c - Add carry into the result. */
284 cf = tcg_temp_new();
285
286 read_carry(dc, cf);
287 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
288 tcg_temp_free(cf);
289 }
290 }
291 return;
292 }
293
294 /* From now on, we can assume k is zero. So we need to update MSR. */
295 /* Extract carry. And complement a into na. */
296 cf = tcg_temp_new();
297 na = tcg_temp_new();
298 if (c) {
299 read_carry(dc, cf);
300 } else {
301 tcg_gen_movi_tl(cf, 1);
302 }
303
304 /* d = b + ~a + c. carry defaults to 1. */
305 tcg_gen_not_tl(na, cpu_R[dc->ra]);
306
307 if (dc->rd) {
308 TCGv ncf = tcg_temp_new();
5d0bb823 309 gen_helper_carry(ncf, na, *(dec_alu_op_b(dc)), cf);
e0a42ebc
EI		 310 tcg_gen_add_tl(cpu_R[dc->rd], na, *(dec_alu_op_b(dc)));
311 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
312 write_carry(dc, ncf);
313 tcg_temp_free(ncf);
314 } else {
5d0bb823 315 gen_helper_carry(cf, na, *(dec_alu_op_b(dc)), cf);
e0a42ebc 316 write_carry(dc, cf);
4acb54ba 317 }
e0a42ebc
EI		 318 tcg_temp_free(cf);
319 tcg_temp_free(na);
4acb54ba
EI		 320}
321
322static void dec_pattern(DisasContext *dc)
323{
324 unsigned int mode;
325 int l1;
326
1567a005 327 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 328 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 329 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
330 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
331 t_gen_raise_exception(dc, EXCP_HW_EXCP);
332 }
333
4acb54ba
EI		 334 mode = dc->opcode & 3;
335 switch (mode) {
336 case 0:
337 /* pcmpbf. */
338 LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
339 if (dc->rd)
340 gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
341 break;
342 case 2:
343 LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
344 if (dc->rd) {
345 TCGv t0 = tcg_temp_local_new();
346 l1 = gen_new_label();
347 tcg_gen_movi_tl(t0, 1);
348 tcg_gen_brcond_tl(TCG_COND_EQ,
349 cpu_R[dc->ra], cpu_R[dc->rb], l1);
350 tcg_gen_movi_tl(t0, 0);
351 gen_set_label(l1);
352 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
353 tcg_temp_free(t0);
354 }
355 break;
356 case 3:
357 LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
358 l1 = gen_new_label();
359 if (dc->rd) {
360 TCGv t0 = tcg_temp_local_new();
361 tcg_gen_movi_tl(t0, 1);
362 tcg_gen_brcond_tl(TCG_COND_NE,
363 cpu_R[dc->ra], cpu_R[dc->rb], l1);
364 tcg_gen_movi_tl(t0, 0);
365 gen_set_label(l1);
366 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
367 tcg_temp_free(t0);
368 }
369 break;
370 default:
371 cpu_abort(dc->env,
372 "unsupported pattern insn opcode=%x\n", dc->opcode);
373 break;
374 }
375}
376
377static void dec_and(DisasContext *dc)
378{
379 unsigned int not;
380
381 if (!dc->type_b && (dc->imm & (1 << 10))) {
382 dec_pattern(dc);
383 return;
384 }
385
386 not = dc->opcode & (1 << 1);
387 LOG_DIS("and%s\n", not ? "n" : "");
388
389 if (!dc->rd)
390 return;
391
392 if (not) {
393 TCGv t = tcg_temp_new();
394 tcg_gen_not_tl(t, *(dec_alu_op_b(dc)));
395 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], t);
396 tcg_temp_free(t);
397 } else
398 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
399}
400
401static void dec_or(DisasContext *dc)
402{
403 if (!dc->type_b && (dc->imm & (1 << 10))) {
404 dec_pattern(dc);
405 return;
406 }
407
408 LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm);
409 if (dc->rd)
410 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
411}
412
413static void dec_xor(DisasContext *dc)
414{
415 if (!dc->type_b && (dc->imm & (1 << 10))) {
416 dec_pattern(dc);
417 return;
418 }
419
420 LOG_DIS("xor r%d\n", dc->rd);
421 if (dc->rd)
422 tcg_gen_xor_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
423}
424
4acb54ba
EI		 425static inline void msr_read(DisasContext *dc, TCGv d)
426{
427 tcg_gen_mov_tl(d, cpu_SR[SR_MSR]);
428}
429
430static inline void msr_write(DisasContext *dc, TCGv v)
431{
97b833c5
EI		 432 TCGv t;
433
434 t = tcg_temp_new();
4acb54ba 435 dc->cpustate_changed = 1;
97b833c5 436 /* PVR bit is not writable. */
8a84fc6b
EI		 437 tcg_gen_andi_tl(t, v, ~MSR_PVR);
438 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR);
97b833c5
EI		 439 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], v);
440 tcg_temp_free(t);
4acb54ba
EI		 441}
442
443static void dec_msr(DisasContext *dc)
444{
445 TCGv t0, t1;
446 unsigned int sr, to, rn;
1567a005 447 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 448
449 sr = dc->imm & ((1 << 14) - 1);
450 to = dc->imm & (1 << 14);
451 dc->type_b = 1;
452 if (to)
453 dc->cpustate_changed = 1;
454
455 /* msrclr and msrset. */
456 if (!(dc->imm & (1 << 15))) {
457 unsigned int clr = dc->ir & (1 << 16);
458
459 LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
460 dc->rd, dc->imm);
1567a005
EI		 461
462 if (!(dc->env->pvr.regs[2] & PVR2_USE_MSR_INSTR)) {
463 /* nop??? */
464 return;
465 }
466
467 if ((dc->tb_flags & MSR_EE_FLAG)
468 && mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) {
469 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
470 t_gen_raise_exception(dc, EXCP_HW_EXCP);
471 return;
472 }
473
4acb54ba
EI		 474 if (dc->rd)
475 msr_read(dc, cpu_R[dc->rd]);
476
477 t0 = tcg_temp_new();
478 t1 = tcg_temp_new();
479 msr_read(dc, t0);
480 tcg_gen_mov_tl(t1, *(dec_alu_op_b(dc)));
481
482 if (clr) {
483 tcg_gen_not_tl(t1, t1);
484 tcg_gen_and_tl(t0, t0, t1);
485 } else
486 tcg_gen_or_tl(t0, t0, t1);
487 msr_write(dc, t0);
488 tcg_temp_free(t0);
489 tcg_temp_free(t1);
490 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
491 dc->is_jmp = DISAS_UPDATE;
492 return;
493 }
494
1567a005
EI		 495 if (to) {
496 if ((dc->tb_flags & MSR_EE_FLAG)
497 && mem_index == MMU_USER_IDX) {
498 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
499 t_gen_raise_exception(dc, EXCP_HW_EXCP);
500 return;
501 }
502 }
503
4acb54ba
EI		 504#if !defined(CONFIG_USER_ONLY)
505 /* Catch read/writes to the mmu block. */
506 if ((sr & ~0xff) == 0x1000) {
507 sr &= 7;
508 LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
509 if (to)
64254eba 510 gen_helper_mmu_write(cpu_env, tcg_const_tl(sr), cpu_R[dc->ra]);
4acb54ba 511 else
64254eba 512 gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tcg_const_tl(sr));
4acb54ba
EI		 513 return;
514 }
515#endif
516
517 if (to) {
518 LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
519 switch (sr) {
520 case 0:
521 break;
522 case 1:
523 msr_write(dc, cpu_R[dc->ra]);
524 break;
525 case 0x3:
526 tcg_gen_mov_tl(cpu_SR[SR_EAR], cpu_R[dc->ra]);
527 break;
528 case 0x5:
529 tcg_gen_mov_tl(cpu_SR[SR_ESR], cpu_R[dc->ra]);
530 break;
531 case 0x7:
97694c57 532 tcg_gen_andi_tl(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
4acb54ba 533 break;
5818dee5 534 case 0x800:
68cee38a 535 tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, slr));
5818dee5
EI		 536 break;
537 case 0x802:
68cee38a 538 tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, shr));
5818dee5 539 break;
4acb54ba
EI		 540 default:
541 cpu_abort(dc->env, "unknown mts reg %x\n", sr);
542 break;
543 }
544 } else {
545 LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm);
546
547 switch (sr) {
548 case 0:
549 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
550 break;
551 case 1:
552 msr_read(dc, cpu_R[dc->rd]);
553 break;
554 case 0x3:
555 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_EAR]);
556 break;
557 case 0x5:
558 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_ESR]);
559 break;
560 case 0x7:
97694c57 561 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_FSR]);
4acb54ba
EI		 562 break;
563 case 0xb:
564 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]);
565 break;
5818dee5 566 case 0x800:
68cee38a 567 tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, slr));
5818dee5
EI		 568 break;
569 case 0x802:
68cee38a 570 tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, shr));
5818dee5 571 break;
4acb54ba
EI		 572 case 0x2000:
573 case 0x2001:
574 case 0x2002:
575 case 0x2003:
576 case 0x2004:
577 case 0x2005:
578 case 0x2006:
579 case 0x2007:
580 case 0x2008:
581 case 0x2009:
582 case 0x200a:
583 case 0x200b:
584 case 0x200c:
585 rn = sr & 0xf;
586 tcg_gen_ld_tl(cpu_R[dc->rd],
68cee38a 587 cpu_env, offsetof(CPUMBState, pvr.regs[rn]));
4acb54ba
EI		 588 break;
589 default:
590 cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
591 break;
592 }
593 }
ee7dbcf8
EI		 594
595 if (dc->rd == 0) {
596 tcg_gen_movi_tl(cpu_R[0], 0);
597 }
4acb54ba
EI		 598}
599
600/* 64-bit signed mul, lower result in d and upper in d2. */
601static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
602{
603 TCGv_i64 t0, t1;
604
605 t0 = tcg_temp_new_i64();
606 t1 = tcg_temp_new_i64();
607
608 tcg_gen_ext_i32_i64(t0, a);
609 tcg_gen_ext_i32_i64(t1, b);
610 tcg_gen_mul_i64(t0, t0, t1);
611
612 tcg_gen_trunc_i64_i32(d, t0);
613 tcg_gen_shri_i64(t0, t0, 32);
614 tcg_gen_trunc_i64_i32(d2, t0);
615
616 tcg_temp_free_i64(t0);
617 tcg_temp_free_i64(t1);
618}
619
620/* 64-bit unsigned muls, lower result in d and upper in d2. */
621static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
622{
623 TCGv_i64 t0, t1;
624
625 t0 = tcg_temp_new_i64();
626 t1 = tcg_temp_new_i64();
627
628 tcg_gen_extu_i32_i64(t0, a);
629 tcg_gen_extu_i32_i64(t1, b);
630 tcg_gen_mul_i64(t0, t0, t1);
631
632 tcg_gen_trunc_i64_i32(d, t0);
633 tcg_gen_shri_i64(t0, t0, 32);
634 tcg_gen_trunc_i64_i32(d2, t0);
635
636 tcg_temp_free_i64(t0);
637 tcg_temp_free_i64(t1);
638}
639
640/* Multiplier unit. */
641static void dec_mul(DisasContext *dc)
642{
643 TCGv d[2];
644 unsigned int subcode;
645
1567a005 646 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 647 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 648 && !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
649 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
650 t_gen_raise_exception(dc, EXCP_HW_EXCP);
651 return;
652 }
653
4acb54ba
EI		 654 subcode = dc->imm & 3;
655 d[0] = tcg_temp_new();
656 d[1] = tcg_temp_new();
657
658 if (dc->type_b) {
659 LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm);
660 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
661 goto done;
662 }
663
1567a005
EI		 664 /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
665 if (subcode >= 1 && subcode <= 3
666 && !((dc->env->pvr.regs[2] & PVR2_USE_MUL64_MASK))) {
667 /* nop??? */
668 }
669
4acb54ba
EI		 670 switch (subcode) {
671 case 0:
672 LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
673 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], cpu_R[dc->rb]);
674 break;
675 case 1:
676 LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
677 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
678 break;
679 case 2:
680 LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
681 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
682 break;
683 case 3:
684 LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
685 t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
686 break;
687 default:
688 cpu_abort(dc->env, "unknown MUL insn %x\n", subcode);
689 break;
690 }
691done:
692 tcg_temp_free(d[0]);
693 tcg_temp_free(d[1]);
694}
695
696/* Div unit. */
697static void dec_div(DisasContext *dc)
698{
699 unsigned int u;
700
701 u = dc->imm & 2;
702 LOG_DIS("div\n");
703
97f90cbf 704 if ((dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 705 && !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) {
706 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
707 t_gen_raise_exception(dc, EXCP_HW_EXCP);
708 }
709
4acb54ba 710 if (u)
64254eba
BS		 711 gen_helper_divu(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)),
712 cpu_R[dc->ra]);
4acb54ba 713 else
64254eba
BS		 714 gen_helper_divs(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)),
715 cpu_R[dc->ra]);
4acb54ba
EI		 716 if (!dc->rd)
717 tcg_gen_movi_tl(cpu_R[dc->rd], 0);
718}
719
720static void dec_barrel(DisasContext *dc)
721{
722 TCGv t0;
723 unsigned int s, t;
724
1567a005 725 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 726 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 727 && !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
728 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
729 t_gen_raise_exception(dc, EXCP_HW_EXCP);
730 return;
731 }
732
4acb54ba
EI		 733 s = dc->imm & (1 << 10);
734 t = dc->imm & (1 << 9);
735
736 LOG_DIS("bs%s%s r%d r%d r%d\n",
737 s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
738
739 t0 = tcg_temp_new();
740
741 tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
742 tcg_gen_andi_tl(t0, t0, 31);
743
744 if (s)
745 tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
746 else {
747 if (t)
748 tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
749 else
750 tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
751 }
752}
753
754static void dec_bit(DisasContext *dc)
755{
756 TCGv t0, t1;
757 unsigned int op;
1567a005 758 int mem_index = cpu_mmu_index(dc->env);
4acb54ba 759
ace2e4da 760 op = dc->ir & ((1 << 9) - 1);
4acb54ba
EI		 761 switch (op) {
762 case 0x21:
763 /* src. */
764 t0 = tcg_temp_new();
765
766 LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
767 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
768 if (dc->rd) {
769 t1 = tcg_temp_new();
770 read_carry(dc, t1);
771 tcg_gen_shli_tl(t1, t1, 31);
772
773 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
774 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t1);
775 tcg_temp_free(t1);
776 }
777
778 /* Update carry. */
779 write_carry(dc, t0);
780 tcg_temp_free(t0);
781 break;
782
783 case 0x1:
784 case 0x41:
785 /* srl. */
786 t0 = tcg_temp_new();
787 LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
788
789 /* Update carry. */
790 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
791 write_carry(dc, t0);
792 tcg_temp_free(t0);
793 if (dc->rd) {
794 if (op == 0x41)
795 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
796 else
797 tcg_gen_sari_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
798 }
799 break;
800 case 0x60:
801 LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra);
802 tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
803 break;
804 case 0x61:
805 LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra);
806 tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
807 break;
808 case 0x64:
f062a3c7
EI		 809 case 0x66:
810 case 0x74:
811 case 0x76:
4acb54ba
EI		 812 /* wdc. */
813 LOG_DIS("wdc r%d\n", dc->ra);
1567a005
EI		 814 if ((dc->tb_flags & MSR_EE_FLAG)
815 && mem_index == MMU_USER_IDX) {
816 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
817 t_gen_raise_exception(dc, EXCP_HW_EXCP);
818 return;
819 }
4acb54ba
EI		 820 break;
821 case 0x68:
822 /* wic. */
823 LOG_DIS("wic r%d\n", dc->ra);
1567a005
EI		 824 if ((dc->tb_flags & MSR_EE_FLAG)
825 && mem_index == MMU_USER_IDX) {
826 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
827 t_gen_raise_exception(dc, EXCP_HW_EXCP);
828 return;
829 }
4acb54ba 830 break;
48b5e96f
EI		 831 case 0xe0:
832 if ((dc->tb_flags & MSR_EE_FLAG)
833 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
834 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
835 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
836 t_gen_raise_exception(dc, EXCP_HW_EXCP);
837 }
838 if (dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR) {
839 gen_helper_clz(cpu_R[dc->rd], cpu_R[dc->ra]);
840 }
841 break;
ace2e4da
PC		 842 case 0x1e0:
843 /* swapb */
844 LOG_DIS("swapb r%d r%d\n", dc->rd, dc->ra);
845 tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
846 break;
b8c6a5d9 847 case 0x1e2:
ace2e4da
PC		 848 /*swaph */
849 LOG_DIS("swaph r%d r%d\n", dc->rd, dc->ra);
850 tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16);
851 break;
4acb54ba
EI		 852 default:
853 cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
854 dc->pc, op, dc->rd, dc->ra, dc->rb);
855 break;
856 }
857}
858
859static inline void sync_jmpstate(DisasContext *dc)
860{
844bab60
EI		 861 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
862 if (dc->jmp == JMP_DIRECT) {
863 tcg_gen_movi_tl(env_btaken, 1);
864 }
23979dc5
EI		 865 dc->jmp = JMP_INDIRECT;
866 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
4acb54ba
EI		 867 }
868}
869
870static void dec_imm(DisasContext *dc)
871{
872 LOG_DIS("imm %x\n", dc->imm << 16);
873 tcg_gen_movi_tl(env_imm, (dc->imm << 16));
874 dc->tb_flags |= IMM_FLAG;
875 dc->clear_imm = 0;
876}
877
878static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
879 unsigned int size)
880{
881 int mem_index = cpu_mmu_index(dc->env);
882
883 if (size == 1) {
884 tcg_gen_qemu_ld8u(dst, addr, mem_index);
885 } else if (size == 2) {
886 tcg_gen_qemu_ld16u(dst, addr, mem_index);
887 } else if (size == 4) {
888 tcg_gen_qemu_ld32u(dst, addr, mem_index);
889 } else
890 cpu_abort(dc->env, "Incorrect load size %d\n", size);
891}
892
893static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
894{
895 unsigned int extimm = dc->tb_flags & IMM_FLAG;
5818dee5
EI		 896 /* Should be set to one if r1 is used by loadstores. */
897 int stackprot = 0;
898
899 /* All load/stores use ra. */
900 if (dc->ra == 1) {
901 stackprot = 1;
902 }
4acb54ba 903
9ef55357 904 /* Treat the common cases first. */
4acb54ba 905 if (!dc->type_b) {
4b5ef0b5
EI		 906 /* If any of the regs is r0, return a ptr to the other. */
907 if (dc->ra == 0) {
908 return &cpu_R[dc->rb];
909 } else if (dc->rb == 0) {
910 return &cpu_R[dc->ra];
911 }
912
5818dee5
EI		 913 if (dc->rb == 1) {
914 stackprot = 1;
915 }
916
4acb54ba
EI		 917 *t = tcg_temp_new();
918 tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
5818dee5
EI		 919
920 if (stackprot) {
64254eba 921 gen_helper_stackprot(cpu_env, *t);
5818dee5 922 }
4acb54ba
EI		 923 return t;
924 }
925 /* Immediate. */
926 if (!extimm) {
927 if (dc->imm == 0) {
928 return &cpu_R[dc->ra];
929 }
930 *t = tcg_temp_new();
931 tcg_gen_movi_tl(*t, (int32_t)((int16_t)dc->imm));
932 tcg_gen_add_tl(*t, cpu_R[dc->ra], *t);
933 } else {
934 *t = tcg_temp_new();
935 tcg_gen_add_tl(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
936 }
937
5818dee5 938 if (stackprot) {
64254eba 939 gen_helper_stackprot(cpu_env, *t);
5818dee5 940 }
4acb54ba
EI		 941 return t;
942}
943
9f8beb66
EI		 944static inline void dec_byteswap(DisasContext *dc, TCGv dst, TCGv src, int size)
945{
946 if (size == 4) {
947 tcg_gen_bswap32_tl(dst, src);
948 } else if (size == 2) {
949 TCGv t = tcg_temp_new();
950
951 /* bswap16 assumes the high bits are zero. */
952 tcg_gen_andi_tl(t, src, 0xffff);
953 tcg_gen_bswap16_tl(dst, t);
954 tcg_temp_free(t);
955 } else {
956 /* Ignore.
957 cpu_abort(dc->env, "Invalid ldst byteswap size %d\n", size);
958 */
959 }
960}
961
4acb54ba
EI		 962static void dec_load(DisasContext *dc)
963{
964 TCGv t, *addr;
8cc9b43f 965 unsigned int size, rev = 0, ex = 0;
4acb54ba
EI		 966
967 size = 1 << (dc->opcode & 3);
9f8beb66
EI		 968
969 if (!dc->type_b) {
970 rev = (dc->ir >> 9) & 1;
8cc9b43f 971 ex = (dc->ir >> 10) & 1;
9f8beb66
EI		 972 }
973
0187688f 974 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
97f90cbf 975 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
0187688f
EI		 976 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
977 t_gen_raise_exception(dc, EXCP_HW_EXCP);
978 return;
979 }
4acb54ba 980
8cc9b43f
PC		 981 LOG_DIS("l%d%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "",
982 ex ? "x" : "");
9f8beb66 983
4acb54ba
EI		 984 t_sync_flags(dc);
985 addr = compute_ldst_addr(dc, &t);
986
9f8beb66
EI		 987 /*
988 * When doing reverse accesses we need to do two things.
989 *
4ff9786c 990 * 1. Reverse the address wrt endianness.
9f8beb66
EI		 991 * 2. Byteswap the data lanes on the way back into the CPU core.
992 */
993 if (rev && size != 4) {
994 /* Endian reverse the address. t is addr. */
995 switch (size) {
996 case 1:
997 {
998 /* 00 -> 11
999 01 -> 10
1000 10 -> 10
1001 11 -> 00 */
1002 TCGv low = tcg_temp_new();
1003
1004 /* Force addr into the temp. */
1005 if (addr != &t) {
1006 t = tcg_temp_new();
1007 tcg_gen_mov_tl(t, *addr);
1008 addr = &t;
1009 }
1010
1011 tcg_gen_andi_tl(low, t, 3);
1012 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
1013 tcg_gen_andi_tl(t, t, ~3);
1014 tcg_gen_or_tl(t, t, low);
9f8beb66
EI		 1015 tcg_gen_mov_tl(env_imm, t);
1016 tcg_temp_free(low);
1017 break;
1018 }
1019
1020 case 2:
1021 /* 00 -> 10
1022 10 -> 00. */
1023 /* Force addr into the temp. */
1024 if (addr != &t) {
1025 t = tcg_temp_new();
1026 tcg_gen_xori_tl(t, *addr, 2);
1027 addr = &t;
1028 } else {
1029 tcg_gen_xori_tl(t, t, 2);
1030 }
1031 break;
1032 default:
1033 cpu_abort(dc->env, "Invalid reverse size\n");
1034 break;
1035 }
1036 }
1037
8cc9b43f
PC		 1038 /* lwx does not throw unaligned access errors, so force alignment */
1039 if (ex) {
1040 /* Force addr into the temp. */
1041 if (addr != &t) {
1042 t = tcg_temp_new();
1043 tcg_gen_mov_tl(t, *addr);
1044 addr = &t;
1045 }
1046 tcg_gen_andi_tl(t, t, ~3);
1047 }
1048
4acb54ba
EI		 1049 /* If we get a fault on a dslot, the jmpstate better be in sync. */
1050 sync_jmpstate(dc);
968a40f6
EI		 1051
1052 /* Verify alignment if needed. */
1053 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
a12f6507
EI		 1054 TCGv v = tcg_temp_new();
1055
1056 /*
1057 * Microblaze gives MMU faults priority over faults due to
1058 * unaligned addresses. That's why we speculatively do the load
1059 * into v. If the load succeeds, we verify alignment of the
1060 * address and if that succeeds we write into the destination reg.
1061 */
1062 gen_load(dc, v, *addr, size);
1063
1064 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
64254eba 1065 gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd),
3aa80988 1066 tcg_const_tl(0), tcg_const_tl(size - 1));
9f8beb66
EI		 1067 if (dc->rd) {
1068 if (rev) {
1069 dec_byteswap(dc, cpu_R[dc->rd], v, size);
1070 } else {
1071 tcg_gen_mov_tl(cpu_R[dc->rd], v);
1072 }
1073 }
a12f6507 1074 tcg_temp_free(v);
968a40f6 1075 } else {
a12f6507
EI		 1076 if (dc->rd) {
1077 gen_load(dc, cpu_R[dc->rd], *addr, size);
9f8beb66
EI		 1078 if (rev) {
1079 dec_byteswap(dc, cpu_R[dc->rd], cpu_R[dc->rd], size);
1080 }
a12f6507 1081 } else {
9f8beb66 1082 /* We are loading into r0, no need to reverse. */
a12f6507
EI		 1083 gen_load(dc, env_imm, *addr, size);
1084 }
4acb54ba
EI		 1085 }
1086
8cc9b43f
PC		 1087 if (ex) { /* lwx */
1088 /* no support for for AXI exclusive so always clear C */
1089 write_carryi(dc, 0);
1090 tcg_gen_st_tl(*addr, cpu_env, offsetof(CPUMBState, res_addr));
1091 }
1092
4acb54ba
EI		 1093 if (addr == &t)
1094 tcg_temp_free(t);
1095}
1096
1097static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
1098 unsigned int size)
1099{
1100 int mem_index = cpu_mmu_index(dc->env);
1101
1102 if (size == 1)
1103 tcg_gen_qemu_st8(val, addr, mem_index);
1104 else if (size == 2) {
1105 tcg_gen_qemu_st16(val, addr, mem_index);
1106 } else if (size == 4) {
1107 tcg_gen_qemu_st32(val, addr, mem_index);
1108 } else
1109 cpu_abort(dc->env, "Incorrect store size %d\n", size);
1110}
1111
1112static void dec_store(DisasContext *dc)
1113{
083dbf48 1114 TCGv t, *addr, swx_addr, r_check;
8cc9b43f
PC		 1115 int swx_skip = 0;
1116 unsigned int size, rev = 0, ex = 0;
4acb54ba
EI		 1117
1118 size = 1 << (dc->opcode & 3);
9f8beb66
EI		 1119 if (!dc->type_b) {
1120 rev = (dc->ir >> 9) & 1;
8cc9b43f 1121 ex = (dc->ir >> 10) & 1;
9f8beb66 1122 }
4acb54ba 1123
0187688f 1124 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
97f90cbf 1125 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
0187688f
EI		 1126 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1127 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1128 return;
1129 }
1130
8cc9b43f
PC		 1131 LOG_DIS("s%d%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "",
1132 ex ? "x" : "");
4acb54ba
EI		 1133 t_sync_flags(dc);
1134 /* If we get a fault on a dslot, the jmpstate better be in sync. */
1135 sync_jmpstate(dc);
1136 addr = compute_ldst_addr(dc, &t);
968a40f6 1137
083dbf48
PC		 1138 r_check = tcg_temp_new();
1139 swx_addr = tcg_temp_local_new();
8cc9b43f 1140 if (ex) { /* swx */
8cc9b43f
PC		 1141
1142 /* Force addr into the swx_addr. */
1143 tcg_gen_mov_tl(swx_addr, *addr);
1144 addr = &swx_addr;
1145 /* swx does not throw unaligned access errors, so force alignment */
1146 tcg_gen_andi_tl(swx_addr, swx_addr, ~3);
1147
1148 tcg_gen_ld_tl(r_check, cpu_env, offsetof(CPUMBState, res_addr));
1149 write_carryi(dc, 1);
1150 swx_skip = gen_new_label();
1151 tcg_gen_brcond_tl(TCG_COND_NE, r_check, swx_addr, swx_skip);
1152 write_carryi(dc, 0);
1153 }
1154
9f8beb66
EI		 1155 if (rev && size != 4) {
1156 /* Endian reverse the address. t is addr. */
1157 switch (size) {
1158 case 1:
1159 {
1160 /* 00 -> 11
1161 01 -> 10
1162 10 -> 10
1163 11 -> 00 */
1164 TCGv low = tcg_temp_new();
1165
1166 /* Force addr into the temp. */
1167 if (addr != &t) {
1168 t = tcg_temp_new();
1169 tcg_gen_mov_tl(t, *addr);
1170 addr = &t;
1171 }
1172
1173 tcg_gen_andi_tl(low, t, 3);
1174 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
1175 tcg_gen_andi_tl(t, t, ~3);
1176 tcg_gen_or_tl(t, t, low);
9f8beb66
EI		 1177 tcg_gen_mov_tl(env_imm, t);
1178 tcg_temp_free(low);
1179 break;
1180 }
1181
1182 case 2:
1183 /* 00 -> 10
1184 10 -> 00. */
1185 /* Force addr into the temp. */
1186 if (addr != &t) {
1187 t = tcg_temp_new();
1188 tcg_gen_xori_tl(t, *addr, 2);
1189 addr = &t;
1190 } else {
1191 tcg_gen_xori_tl(t, t, 2);
1192 }
1193 break;
1194 default:
1195 cpu_abort(dc->env, "Invalid reverse size\n");
1196 break;
1197 }
1198
1199 if (size != 1) {
1200 TCGv bs_data = tcg_temp_new();
1201 dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1202 gen_store(dc, *addr, bs_data, size);
1203 tcg_temp_free(bs_data);
1204 } else {
1205 gen_store(dc, *addr, cpu_R[dc->rd], size);
1206 }
1207 } else {
1208 if (rev) {
1209 TCGv bs_data = tcg_temp_new();
1210 dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1211 gen_store(dc, *addr, bs_data, size);
1212 tcg_temp_free(bs_data);
1213 } else {
1214 gen_store(dc, *addr, cpu_R[dc->rd], size);
1215 }
1216 }
a12f6507 1217
968a40f6
EI		 1218 /* Verify alignment if needed. */
1219 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
a12f6507
EI		 1220 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1221 /* FIXME: if the alignment is wrong, we should restore the value
4abf79a4 1222 * in memory. One possible way to achieve this is to probe
9f8beb66
EI		 1223 * the MMU prior to the memaccess, thay way we could put
1224 * the alignment checks in between the probe and the mem
1225 * access.
a12f6507 1226 */
64254eba 1227 gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd),
3aa80988 1228 tcg_const_tl(1), tcg_const_tl(size - 1));
968a40f6 1229 }
083dbf48 1230
8cc9b43f
PC		 1231 if (ex) {
1232 gen_set_label(swx_skip);
8cc9b43f 1233 }
083dbf48
PC		 1234 tcg_temp_free(r_check);
1235 tcg_temp_free(swx_addr);
968a40f6 1236
4acb54ba
EI		 1237 if (addr == &t)
1238 tcg_temp_free(t);
1239}
1240
1241static inline void eval_cc(DisasContext *dc, unsigned int cc,
1242 TCGv d, TCGv a, TCGv b)
1243{
4acb54ba
EI		 1244 switch (cc) {
1245 case CC_EQ:
b2565c69 1246 tcg_gen_setcond_tl(TCG_COND_EQ, d, a, b);
4acb54ba
EI		 1247 break;
1248 case CC_NE:
b2565c69 1249 tcg_gen_setcond_tl(TCG_COND_NE, d, a, b);
4acb54ba
EI		 1250 break;
1251 case CC_LT:
b2565c69 1252 tcg_gen_setcond_tl(TCG_COND_LT, d, a, b);
4acb54ba
EI		 1253 break;
1254 case CC_LE:
b2565c69 1255 tcg_gen_setcond_tl(TCG_COND_LE, d, a, b);
4acb54ba
EI		 1256 break;
1257 case CC_GE:
b2565c69 1258 tcg_gen_setcond_tl(TCG_COND_GE, d, a, b);
4acb54ba
EI		 1259 break;
1260 case CC_GT:
b2565c69 1261 tcg_gen_setcond_tl(TCG_COND_GT, d, a, b);
4acb54ba
EI		 1262 break;
1263 default:
1264 cpu_abort(dc->env, "Unknown condition code %x.\n", cc);
1265 break;
1266 }
1267}
1268
1269static void eval_cond_jmp(DisasContext *dc, TCGv pc_true, TCGv pc_false)
1270{
1271 int l1;
1272
1273 l1 = gen_new_label();
1274 /* Conditional jmp. */
1275 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_false);
1276 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
1277 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_true);
1278 gen_set_label(l1);
1279}
1280
1281static void dec_bcc(DisasContext *dc)
1282{
1283 unsigned int cc;
1284 unsigned int dslot;
1285
1286 cc = EXTRACT_FIELD(dc->ir, 21, 23);
1287 dslot = dc->ir & (1 << 25);
1288 LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm);
1289
1290 dc->delayed_branch = 1;
1291 if (dslot) {
1292 dc->delayed_branch = 2;
1293 dc->tb_flags |= D_FLAG;
1294 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
68cee38a 1295 cpu_env, offsetof(CPUMBState, bimm));
4acb54ba
EI		 1296 }
1297
61204ce8
EI		 1298 if (dec_alu_op_b_is_small_imm(dc)) {
1299 int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */
1300
1301 tcg_gen_movi_tl(env_btarget, dc->pc + offset);
844bab60 1302 dc->jmp = JMP_DIRECT_CC;
23979dc5 1303 dc->jmp_pc = dc->pc + offset;
61204ce8 1304 } else {
23979dc5 1305 dc->jmp = JMP_INDIRECT;
61204ce8
EI		 1306 tcg_gen_movi_tl(env_btarget, dc->pc);
1307 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
1308 }
61204ce8 1309 eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_tl(0));
4acb54ba
EI		 1310}
1311
1312static void dec_br(DisasContext *dc)
1313{
9f6113c7 1314 unsigned int dslot, link, abs, mbar;
ff21f70a 1315 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 1316
1317 dslot = dc->ir & (1 << 20);
1318 abs = dc->ir & (1 << 19);
1319 link = dc->ir & (1 << 18);
9f6113c7
EI		 1320
1321 /* Memory barrier. */
1322 mbar = (dc->ir >> 16) & 31;
1323 if (mbar == 2 && dc->imm == 4) {
5d45de97
EI		 1324 /* mbar IMM & 16 decodes to sleep. */
1325 if (dc->rd & 16) {
1326 TCGv_i32 tmp_hlt = tcg_const_i32(EXCP_HLT);
1327 TCGv_i32 tmp_1 = tcg_const_i32(1);
1328
1329 LOG_DIS("sleep\n");
1330
1331 t_sync_flags(dc);
1332 tcg_gen_st_i32(tmp_1, cpu_env,
1333 -offsetof(MicroBlazeCPU, env)
1334 +offsetof(CPUState, halted));
1335 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
1336 gen_helper_raise_exception(cpu_env, tmp_hlt);
1337 tcg_temp_free_i32(tmp_hlt);
1338 tcg_temp_free_i32(tmp_1);
1339 return;
1340 }
9f6113c7
EI		 1341 LOG_DIS("mbar %d\n", dc->rd);
1342 /* Break the TB. */
1343 dc->cpustate_changed = 1;
1344 return;
1345 }
1346
4acb54ba
EI		 1347 LOG_DIS("br%s%s%s%s imm=%x\n",
1348 abs ? "a" : "", link ? "l" : "",
1349 dc->type_b ? "i" : "", dslot ? "d" : "",
1350 dc->imm);
1351
1352 dc->delayed_branch = 1;
1353 if (dslot) {
1354 dc->delayed_branch = 2;
1355 dc->tb_flags |= D_FLAG;
1356 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
68cee38a 1357 cpu_env, offsetof(CPUMBState, bimm));
4acb54ba
EI		 1358 }
1359 if (link && dc->rd)
1360 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
1361
1362 dc->jmp = JMP_INDIRECT;
1363 if (abs) {
1364 tcg_gen_movi_tl(env_btaken, 1);
1365 tcg_gen_mov_tl(env_btarget, *(dec_alu_op_b(dc)));
ff21f70a
EI		 1366 if (link && !dslot) {
1367 if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18))
1368 t_gen_raise_exception(dc, EXCP_BREAK);
1369 if (dc->imm == 0) {
1370 if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) {
1371 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1372 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1373 return;
1374 }
1375
1376 t_gen_raise_exception(dc, EXCP_DEBUG);
1377 }
1378 }
4acb54ba 1379 } else {
61204ce8
EI		 1380 if (dec_alu_op_b_is_small_imm(dc)) {
1381 dc->jmp = JMP_DIRECT;
1382 dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm);
1383 } else {
4acb54ba
EI		 1384 tcg_gen_movi_tl(env_btaken, 1);
1385 tcg_gen_movi_tl(env_btarget, dc->pc);
1386 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
4acb54ba
EI		 1387 }
1388 }
1389}
1390
1391static inline void do_rti(DisasContext *dc)
1392{
1393 TCGv t0, t1;
1394 t0 = tcg_temp_new();
1395 t1 = tcg_temp_new();
1396 tcg_gen_shri_tl(t0, cpu_SR[SR_MSR], 1);
1397 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_IE);
1398 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1399
1400 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1401 tcg_gen_or_tl(t1, t1, t0);
1402 msr_write(dc, t1);
1403 tcg_temp_free(t1);
1404 tcg_temp_free(t0);
1405 dc->tb_flags &= ~DRTI_FLAG;
1406}
1407
1408static inline void do_rtb(DisasContext *dc)
1409{
1410 TCGv t0, t1;
1411 t0 = tcg_temp_new();
1412 t1 = tcg_temp_new();
1413 tcg_gen_andi_tl(t1, cpu_SR[SR_MSR], ~MSR_BIP);
1414 tcg_gen_shri_tl(t0, t1, 1);
1415 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1416
1417 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1418 tcg_gen_or_tl(t1, t1, t0);
1419 msr_write(dc, t1);
1420 tcg_temp_free(t1);
1421 tcg_temp_free(t0);
1422 dc->tb_flags &= ~DRTB_FLAG;
1423}
1424
1425static inline void do_rte(DisasContext *dc)
1426{
1427 TCGv t0, t1;
1428 t0 = tcg_temp_new();
1429 t1 = tcg_temp_new();
1430
1431 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_EE);
1432 tcg_gen_andi_tl(t1, t1, ~MSR_EIP);
1433 tcg_gen_shri_tl(t0, t1, 1);
1434 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1435
1436 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1437 tcg_gen_or_tl(t1, t1, t0);
1438 msr_write(dc, t1);
1439 tcg_temp_free(t1);
1440 tcg_temp_free(t0);
1441 dc->tb_flags &= ~DRTE_FLAG;
1442}
1443
1444static void dec_rts(DisasContext *dc)
1445{
1446 unsigned int b_bit, i_bit, e_bit;
1567a005 1447 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 1448
1449 i_bit = dc->ir & (1 << 21);
1450 b_bit = dc->ir & (1 << 22);
1451 e_bit = dc->ir & (1 << 23);
1452
1453 dc->delayed_branch = 2;
1454 dc->tb_flags |= D_FLAG;
1455 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
68cee38a 1456 cpu_env, offsetof(CPUMBState, bimm));
4acb54ba
EI		 1457
1458 if (i_bit) {
1459 LOG_DIS("rtid ir=%x\n", dc->ir);
1567a005
EI		 1460 if ((dc->tb_flags & MSR_EE_FLAG)
1461 && mem_index == MMU_USER_IDX) {
1462 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1463 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1464 }
4acb54ba
EI		 1465 dc->tb_flags |= DRTI_FLAG;
1466 } else if (b_bit) {
1467 LOG_DIS("rtbd ir=%x\n", dc->ir);
1567a005
EI		 1468 if ((dc->tb_flags & MSR_EE_FLAG)
1469 && mem_index == MMU_USER_IDX) {
1470 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1471 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1472 }
4acb54ba
EI		 1473 dc->tb_flags |= DRTB_FLAG;
1474 } else if (e_bit) {
1475 LOG_DIS("rted ir=%x\n", dc->ir);
1567a005
EI		 1476 if ((dc->tb_flags & MSR_EE_FLAG)
1477 && mem_index == MMU_USER_IDX) {
1478 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1479 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1480 }
4acb54ba
EI		 1481 dc->tb_flags |= DRTE_FLAG;
1482 } else
1483 LOG_DIS("rts ir=%x\n", dc->ir);
1484
23979dc5 1485 dc->jmp = JMP_INDIRECT;
4acb54ba
EI		 1486 tcg_gen_movi_tl(env_btaken, 1);
1487 tcg_gen_add_tl(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
1488}
1489
97694c57
EI		 1490static int dec_check_fpuv2(DisasContext *dc)
1491{
1492 int r;
1493
1494 r = dc->env->pvr.regs[2] & PVR2_USE_FPU2_MASK;
1495
1496 if (!r && (dc->tb_flags & MSR_EE_FLAG)) {
1497 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
1498 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1499 }
1500 return r;
1501}
1502
1567a005
EI		 1503static void dec_fpu(DisasContext *dc)
1504{
97694c57
EI		 1505 unsigned int fpu_insn;
1506
1567a005 1507 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 1508 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005 1509 && !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) {
97694c57 1510 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1567a005
EI		 1511 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1512 return;
1513 }
1514
97694c57
EI		 1515 fpu_insn = (dc->ir >> 7) & 7;
1516
1517 switch (fpu_insn) {
1518 case 0:
64254eba
BS		 1519 gen_helper_fadd(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1520 cpu_R[dc->rb]);
97694c57
EI		 1521 break;
1522
1523 case 1:
64254eba
BS		 1524 gen_helper_frsub(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1525 cpu_R[dc->rb]);
97694c57
EI		 1526 break;
1527
1528 case 2:
64254eba
BS		 1529 gen_helper_fmul(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1530 cpu_R[dc->rb]);
97694c57
EI		 1531 break;
1532
1533 case 3:
64254eba
BS		 1534 gen_helper_fdiv(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1535 cpu_R[dc->rb]);
97694c57
EI		 1536 break;
1537
1538 case 4:
1539 switch ((dc->ir >> 4) & 7) {
1540 case 0:
64254eba 1541 gen_helper_fcmp_un(cpu_R[dc->rd], cpu_env,
97694c57
EI		 1542 cpu_R[dc->ra], cpu_R[dc->rb]);
1543 break;
1544 case 1:
64254eba 1545 gen_helper_fcmp_lt(cpu_R[dc->rd], cpu_env,
97694c57
EI		 1546 cpu_R[dc->ra], cpu_R[dc->rb]);
1547 break;
1548 case 2:
64254eba 1549 gen_helper_fcmp_eq(cpu_R[dc->rd], cpu_env,
97694c57
EI		 1550 cpu_R[dc->ra], cpu_R[dc->rb]);
1551 break;
1552 case 3:
64254eba 1553 gen_helper_fcmp_le(cpu_R[dc->rd], cpu_env,
97694c57
EI		 1554 cpu_R[dc->ra], cpu_R[dc->rb]);
1555 break;
1556 case 4:
64254eba 1557 gen_helper_fcmp_gt(cpu_R[dc->rd], cpu_env,
97694c57
EI		 1558 cpu_R[dc->ra], cpu_R[dc->rb]);
1559 break;
1560 case 5:
64254eba 1561 gen_helper_fcmp_ne(cpu_R[dc->rd], cpu_env,
97694c57
EI		 1562 cpu_R[dc->ra], cpu_R[dc->rb]);
1563 break;
1564 case 6:
64254eba 1565 gen_helper_fcmp_ge(cpu_R[dc->rd], cpu_env,
97694c57
EI		 1566 cpu_R[dc->ra], cpu_R[dc->rb]);
1567 break;
1568 default:
71547a3b
BS		 1569 qemu_log_mask(LOG_UNIMP,
1570 "unimplemented fcmp fpu_insn=%x pc=%x"
1571 " opc=%x\n",
1572 fpu_insn, dc->pc, dc->opcode);
97694c57
EI		 1573 dc->abort_at_next_insn = 1;
1574 break;
1575 }
1576 break;
1577
1578 case 5:
1579 if (!dec_check_fpuv2(dc)) {
1580 return;
1581 }
64254eba 1582 gen_helper_flt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
97694c57
EI		 1583 break;
1584
1585 case 6:
1586 if (!dec_check_fpuv2(dc)) {
1587 return;
1588 }
64254eba 1589 gen_helper_fint(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
97694c57
EI		 1590 break;
1591
1592 case 7:
1593 if (!dec_check_fpuv2(dc)) {
1594 return;
1595 }
64254eba 1596 gen_helper_fsqrt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
97694c57
EI		 1597 break;
1598
1599 default:
71547a3b
BS		 1600 qemu_log_mask(LOG_UNIMP, "unimplemented FPU insn fpu_insn=%x pc=%x"
1601 " opc=%x\n",
1602 fpu_insn, dc->pc, dc->opcode);
97694c57
EI		 1603 dc->abort_at_next_insn = 1;
1604 break;
1605 }
1567a005
EI		 1606}
1607
4acb54ba
EI		 1608static void dec_null(DisasContext *dc)
1609{
02b33596
EI		 1610 if ((dc->tb_flags & MSR_EE_FLAG)
1611 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
1612 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1613 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1614 return;
1615 }
4acb54ba
EI		 1616 qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
1617 dc->abort_at_next_insn = 1;
1618}
1619
6d76d23e
EI		 1620/* Insns connected to FSL or AXI stream attached devices. */
1621static void dec_stream(DisasContext *dc)
1622{
1623 int mem_index = cpu_mmu_index(dc->env);
1624 TCGv_i32 t_id, t_ctrl;
1625 int ctrl;
1626
1627 LOG_DIS("%s%s imm=%x\n", dc->rd ? "get" : "put",
1628 dc->type_b ? "" : "d", dc->imm);
1629
1630 if ((dc->tb_flags & MSR_EE_FLAG) && (mem_index == MMU_USER_IDX)) {
1631 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1632 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1633 return;
1634 }
1635
1636 t_id = tcg_temp_new();
1637 if (dc->type_b) {
1638 tcg_gen_movi_tl(t_id, dc->imm & 0xf);
1639 ctrl = dc->imm >> 10;
1640 } else {
1641 tcg_gen_andi_tl(t_id, cpu_R[dc->rb], 0xf);
1642 ctrl = dc->imm >> 5;
1643 }
1644
1645 t_ctrl = tcg_const_tl(ctrl);
1646
1647 if (dc->rd == 0) {
1648 gen_helper_put(t_id, t_ctrl, cpu_R[dc->ra]);
1649 } else {
1650 gen_helper_get(cpu_R[dc->rd], t_id, t_ctrl);
1651 }
1652 tcg_temp_free(t_id);
1653 tcg_temp_free(t_ctrl);
1654}
1655
4acb54ba
EI		 1656static struct decoder_info {
1657 struct {
1658 uint32_t bits;
1659 uint32_t mask;
1660 };
1661 void (*dec)(DisasContext *dc);
1662} decinfo[] = {
1663 {DEC_ADD, dec_add},
1664 {DEC_SUB, dec_sub},
1665 {DEC_AND, dec_and},
1666 {DEC_XOR, dec_xor},
1667 {DEC_OR, dec_or},
1668 {DEC_BIT, dec_bit},
1669 {DEC_BARREL, dec_barrel},
1670 {DEC_LD, dec_load},
1671 {DEC_ST, dec_store},
1672 {DEC_IMM, dec_imm},
1673 {DEC_BR, dec_br},
1674 {DEC_BCC, dec_bcc},
1675 {DEC_RTS, dec_rts},
1567a005 1676 {DEC_FPU, dec_fpu},
4acb54ba
EI		 1677 {DEC_MUL, dec_mul},
1678 {DEC_DIV, dec_div},
1679 {DEC_MSR, dec_msr},
6d76d23e 1680 {DEC_STREAM, dec_stream},
4acb54ba
EI		 1681 {{0, 0}, dec_null}
1682};
1683
64254eba 1684static inline void decode(DisasContext *dc, uint32_t ir)
4acb54ba 1685{
4acb54ba
EI		 1686 int i;
1687
fdefe51c 1688 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
4acb54ba 1689 tcg_gen_debug_insn_start(dc->pc);
fdefe51c 1690 }
4acb54ba 1691
64254eba 1692 dc->ir = ir;
4acb54ba
EI		 1693 LOG_DIS("%8.8x\t", dc->ir);
1694
1695 if (dc->ir)
1696 dc->nr_nops = 0;
1697 else {
1567a005 1698 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf
EI		 1699 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1700 && (dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
1567a005
EI		 1701 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1702 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1703 return;
1704 }
1705
4acb54ba
EI		 1706 LOG_DIS("nr_nops=%d\t", dc->nr_nops);
1707 dc->nr_nops++;
1708 if (dc->nr_nops > 4)
1709 cpu_abort(dc->env, "fetching nop sequence\n");
1710 }
1711 /* bit 2 seems to indicate insn type. */
1712 dc->type_b = ir & (1 << 29);
1713
1714 dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1715 dc->rd = EXTRACT_FIELD(ir, 21, 25);
1716 dc->ra = EXTRACT_FIELD(ir, 16, 20);
1717 dc->rb = EXTRACT_FIELD(ir, 11, 15);
1718 dc->imm = EXTRACT_FIELD(ir, 0, 15);
1719
1720 /* Large switch for all insns. */
1721 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
1722 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
1723 decinfo[i].dec(dc);
1724 break;
1725 }
1726 }
1727}
1728
68cee38a 1729static void check_breakpoint(CPUMBState *env, DisasContext *dc)
4acb54ba
EI		 1730{
1731 CPUBreakpoint *bp;
1732
72cf2d4f
BS		 1733 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1734 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
4acb54ba
EI		 1735 if (bp->pc == dc->pc) {
1736 t_gen_raise_exception(dc, EXCP_DEBUG);
1737 dc->is_jmp = DISAS_UPDATE;
1738 }
1739 }
1740 }
1741}
1742
1743/* generate intermediate code for basic block 'tb'. */
fd327f48 1744static inline void
4a274212
AF		 1745gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
1746 bool search_pc)
4acb54ba 1747{
ed2803da 1748 CPUState *cs = CPU(cpu);
4a274212 1749 CPUMBState *env = &cpu->env;
4acb54ba
EI		 1750 uint16_t *gen_opc_end;
1751 uint32_t pc_start;
1752 int j, lj;
1753 struct DisasContext ctx;
1754 struct DisasContext *dc = &ctx;
1755 uint32_t next_page_start, org_flags;
1756 target_ulong npc;
1757 int num_insns;
1758 int max_insns;
1759
4acb54ba
EI		 1760 pc_start = tb->pc;
1761 dc->env = env;
1762 dc->tb = tb;
1763 org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
1764
92414b31 1765 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
4acb54ba
EI		 1766
1767 dc->is_jmp = DISAS_NEXT;
1768 dc->jmp = 0;
1769 dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
23979dc5
EI		 1770 if (dc->delayed_branch) {
1771 dc->jmp = JMP_INDIRECT;
1772 }
4acb54ba 1773 dc->pc = pc_start;
ed2803da 1774 dc->singlestep_enabled = cs->singlestep_enabled;
4acb54ba
EI		 1775 dc->cpustate_changed = 0;
1776 dc->abort_at_next_insn = 0;
1777 dc->nr_nops = 0;
1778
1779 if (pc_start & 3)
1780 cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start);
1781
1782 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1783#if !SIM_COMPAT
1784 qemu_log("--------------\n");
a0762859 1785 log_cpu_state(CPU(cpu), 0);
4acb54ba
EI		 1786#endif
1787 }
1788
1789 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1790 lj = -1;
1791 num_insns = 0;
1792 max_insns = tb->cflags & CF_COUNT_MASK;
1793 if (max_insns == 0)
1794 max_insns = CF_COUNT_MASK;
1795
806f352d 1796 gen_tb_start();
4acb54ba
EI		 1797 do
1798 {
1799#if SIM_COMPAT
1800 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1801 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1802 gen_helper_debug();
1803 }
1804#endif
1805 check_breakpoint(env, dc);
1806
1807 if (search_pc) {
92414b31 1808 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4acb54ba
EI		 1809 if (lj < j) {
1810 lj++;
1811 while (lj < j)
ab1103de 1812 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4acb54ba 1813 }
25983cad 1814 tcg_ctx.gen_opc_pc[lj] = dc->pc;
ab1103de 1815 tcg_ctx.gen_opc_instr_start[lj] = 1;
c9c99c22 1816 tcg_ctx.gen_opc_icount[lj] = num_insns;
4acb54ba
EI		 1817 }
1818
1819 /* Pretty disas. */
1820 LOG_DIS("%8.8x:\t", dc->pc);
1821
1822 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1823 gen_io_start();
1824
1825 dc->clear_imm = 1;
64254eba 1826 decode(dc, cpu_ldl_code(env, dc->pc));
4acb54ba
EI		 1827 if (dc->clear_imm)
1828 dc->tb_flags &= ~IMM_FLAG;
4acb54ba
EI		 1829 dc->pc += 4;
1830 num_insns++;
1831
1832 if (dc->delayed_branch) {
1833 dc->delayed_branch--;
1834 if (!dc->delayed_branch) {
1835 if (dc->tb_flags & DRTI_FLAG)
1836 do_rti(dc);
1837 if (dc->tb_flags & DRTB_FLAG)
1838 do_rtb(dc);
1839 if (dc->tb_flags & DRTE_FLAG)
1840 do_rte(dc);
1841 /* Clear the delay slot flag. */
1842 dc->tb_flags &= ~D_FLAG;
1843 /* If it is a direct jump, try direct chaining. */
23979dc5 1844 if (dc->jmp == JMP_INDIRECT) {
4acb54ba
EI		 1845 eval_cond_jmp(dc, env_btarget, tcg_const_tl(dc->pc));
1846 dc->is_jmp = DISAS_JUMP;
23979dc5 1847 } else if (dc->jmp == JMP_DIRECT) {
844bab60
EI		 1848 t_sync_flags(dc);
1849 gen_goto_tb(dc, 0, dc->jmp_pc);
1850 dc->is_jmp = DISAS_TB_JUMP;
1851 } else if (dc->jmp == JMP_DIRECT_CC) {
23979dc5
EI		 1852 int l1;
1853
1854 t_sync_flags(dc);
1855 l1 = gen_new_label();
1856 /* Conditional jmp. */
1857 tcg_gen_brcondi_tl(TCG_COND_NE, env_btaken, 0, l1);
1858 gen_goto_tb(dc, 1, dc->pc);
1859 gen_set_label(l1);
1860 gen_goto_tb(dc, 0, dc->jmp_pc);
1861
1862 dc->is_jmp = DISAS_TB_JUMP;
4acb54ba
EI		 1863 }
1864 break;
1865 }
1866 }
ed2803da 1867 if (cs->singlestep_enabled) {
4acb54ba 1868 break;
ed2803da 1869 }
4acb54ba 1870 } while (!dc->is_jmp && !dc->cpustate_changed
efd7f486 1871 && tcg_ctx.gen_opc_ptr < gen_opc_end
4acb54ba
EI		 1872 && !singlestep
1873 && (dc->pc < next_page_start)
1874 && num_insns < max_insns);
1875
1876 npc = dc->pc;
844bab60 1877 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
4acb54ba
EI		 1878 if (dc->tb_flags & D_FLAG) {
1879 dc->is_jmp = DISAS_UPDATE;
1880 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1881 sync_jmpstate(dc);
1882 } else
1883 npc = dc->jmp_pc;
1884 }
1885
1886 if (tb->cflags & CF_LAST_IO)
1887 gen_io_end();
1888 /* Force an update if the per-tb cpu state has changed. */
1889 if (dc->is_jmp == DISAS_NEXT
1890 && (dc->cpustate_changed || org_flags != dc->tb_flags)) {
1891 dc->is_jmp = DISAS_UPDATE;
1892 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1893 }
1894 t_sync_flags(dc);
1895
ed2803da 1896 if (unlikely(cs->singlestep_enabled)) {
6c5f738d
EI		 1897 TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
1898
1899 if (dc->is_jmp != DISAS_JUMP) {
4acb54ba 1900 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
6c5f738d 1901 }
64254eba 1902 gen_helper_raise_exception(cpu_env, tmp);
6c5f738d 1903 tcg_temp_free_i32(tmp);
4acb54ba
EI		 1904 } else {
1905 switch(dc->is_jmp) {
1906 case DISAS_NEXT:
1907 gen_goto_tb(dc, 1, npc);
1908 break;
1909 default:
1910 case DISAS_JUMP:
1911 case DISAS_UPDATE:
1912 /* indicate that the hash table must be used
1913 to find the next TB */
1914 tcg_gen_exit_tb(0);
1915 break;
1916 case DISAS_TB_JUMP:
1917 /* nothing more to generate */
1918 break;
1919 }
1920 }
806f352d 1921 gen_tb_end(tb, num_insns);
efd7f486 1922 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
4acb54ba 1923 if (search_pc) {
92414b31 1924 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
4acb54ba
EI		 1925 lj++;
1926 while (lj <= j)
ab1103de 1927 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4acb54ba
EI		 1928 } else {
1929 tb->size = dc->pc - pc_start;
1930 tb->icount = num_insns;
1931 }
1932
1933#ifdef DEBUG_DISAS
1934#if !SIM_COMPAT
1935 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1936 qemu_log("\n");
1937#if DISAS_GNU
f4359b9f 1938 log_target_disas(env, pc_start, dc->pc - pc_start, 0);
4acb54ba 1939#endif
e6aa0f11 1940 qemu_log("\nisize=%d osize=%td\n",
92414b31
EV		 1941 dc->pc - pc_start, tcg_ctx.gen_opc_ptr -
1942 tcg_ctx.gen_opc_buf);
4acb54ba
EI		 1943 }
1944#endif
1945#endif
1946 assert(!dc->abort_at_next_insn);
1947}
1948
68cee38a 1949void gen_intermediate_code (CPUMBState *env, struct TranslationBlock *tb)
4acb54ba 1950{
4a274212 1951 gen_intermediate_code_internal(mb_env_get_cpu(env), tb, false);
4acb54ba
EI		 1952}
1953
68cee38a 1954void gen_intermediate_code_pc (CPUMBState *env, struct TranslationBlock *tb)
4acb54ba 1955{
4a274212 1956 gen_intermediate_code_internal(mb_env_get_cpu(env), tb, true);
4acb54ba
EI		 1957}
1958
878096ee
AF		 1959void mb_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
1960 int flags)
4acb54ba 1961{
878096ee
AF		 1962 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
1963 CPUMBState *env = &cpu->env;
4acb54ba
EI		 1964 int i;
1965
1966 if (!env || !f)
1967 return;
1968
1969 cpu_fprintf(f, "IN: PC=%x %s\n",
1970 env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC]));
97694c57 1971 cpu_fprintf(f, "rmsr=%x resr=%x rear=%x debug=%x imm=%x iflags=%x fsr=%x\n",
4c24aa0a 1972 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
97694c57 1973 env->debug, env->imm, env->iflags, env->sregs[SR_FSR]);
17c52a43 1974 cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
4acb54ba
EI		 1975 env->btaken, env->btarget,
1976 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
17c52a43
EI		 1977 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
1978 (env->sregs[SR_MSR] & MSR_EIP),
1979 (env->sregs[SR_MSR] & MSR_IE));
1980
4acb54ba
EI		 1981 for (i = 0; i < 32; i++) {
1982 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1983 if ((i + 1) % 4 == 0)
1984 cpu_fprintf(f, "\n");
1985 }
1986 cpu_fprintf(f, "\n\n");
1987}
1988
b33ab1f7 1989MicroBlazeCPU *cpu_mb_init(const char *cpu_model)
4acb54ba 1990{
b77f98ca 1991 MicroBlazeCPU *cpu;
4acb54ba 1992
b77f98ca 1993 cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
4acb54ba 1994
746b03b2 1995 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
4acb54ba 1996
cd0c24f9
AF		 1997 return cpu;
1998}
4acb54ba 1999
cd0c24f9
AF		 2000void mb_tcg_init(void)
2001{
2002 int i;
4acb54ba
EI		 2003
2004 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
2005
2006 env_debug = tcg_global_mem_new(TCG_AREG0,
68cee38a 2007 offsetof(CPUMBState, debug),
4acb54ba
EI		 2008 "debug0");
2009 env_iflags = tcg_global_mem_new(TCG_AREG0,
68cee38a 2010 offsetof(CPUMBState, iflags),
4acb54ba
EI		 2011 "iflags");
2012 env_imm = tcg_global_mem_new(TCG_AREG0,
68cee38a 2013 offsetof(CPUMBState, imm),
4acb54ba
EI		 2014 "imm");
2015 env_btarget = tcg_global_mem_new(TCG_AREG0,
68cee38a 2016 offsetof(CPUMBState, btarget),
4acb54ba
EI		 2017 "btarget");
2018 env_btaken = tcg_global_mem_new(TCG_AREG0,
68cee38a 2019 offsetof(CPUMBState, btaken),
4acb54ba
EI		 2020 "btaken");
2021 for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
2022 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
68cee38a 2023 offsetof(CPUMBState, regs[i]),
4acb54ba
EI		 2024 regnames[i]);
2025 }
2026 for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) {
2027 cpu_SR[i] = tcg_global_mem_new(TCG_AREG0,
68cee38a 2028 offsetof(CPUMBState, sregs[i]),
4acb54ba
EI		 2029 special_regnames[i]);
2030 }
4acb54ba
EI		 2031}
2032
68cee38a 2033void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, int pc_pos)
4acb54ba 2034{
25983cad 2035 env->sregs[SR_PC] = tcg_ctx.gen_opc_pc[pc_pos];
4acb54ba 2036}
Qemu copy for testing