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microblaze: Fix 3rd addkc arg when rd is r0
[qemu.git] / target-microblaze / translate.c
CommitLineData
4acb54ba
EI		 1/*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba
EI		 18 */
19
20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25#include <assert.h>
26
27#include "cpu.h"
28#include "exec-all.h"
29#include "disas.h"
30#include "tcg-op.h"
31#include "helper.h"
32#include "microblaze-decode.h"
33#include "qemu-common.h"
34
35#define GEN_HELPER 1
36#include "helper.h"
37
38#define SIM_COMPAT 0
39#define DISAS_GNU 1
40#define DISAS_MB 1
41#if DISAS_MB && !SIM_COMPAT
42# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
43#else
44# define LOG_DIS(...) do { } while (0)
45#endif
46
47#define D(x)
48
49#define EXTRACT_FIELD(src, start, end) \
50 (((src) >> start) & ((1 << (end - start + 1)) - 1))
51
52static TCGv env_debug;
53static TCGv_ptr cpu_env;
54static TCGv cpu_R[32];
55static TCGv cpu_SR[18];
56static TCGv env_imm;
57static TCGv env_btaken;
58static TCGv env_btarget;
59static TCGv env_iflags;
60
61#include "gen-icount.h"
62
63/* This is the state at translation time. */
64typedef struct DisasContext {
65 CPUState *env;
a5efa644 66 target_ulong pc;
4acb54ba
EI		 67
68 /* Decoder. */
69 int type_b;
70 uint32_t ir;
71 uint8_t opcode;
72 uint8_t rd, ra, rb;
73 uint16_t imm;
74
75 unsigned int cpustate_changed;
76 unsigned int delayed_branch;
77 unsigned int tb_flags, synced_flags; /* tb dependent flags. */
78 unsigned int clear_imm;
79 int is_jmp;
80
844bab60
EI		 81#define JMP_NOJMP 0
82#define JMP_DIRECT 1
83#define JMP_DIRECT_CC 2
84#define JMP_INDIRECT 3
4acb54ba
EI		 85 unsigned int jmp;
86 uint32_t jmp_pc;
87
88 int abort_at_next_insn;
89 int nr_nops;
90 struct TranslationBlock *tb;
91 int singlestep_enabled;
92} DisasContext;
93
38972938 94static const char *regnames[] =
4acb54ba
EI		 95{
96 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
97 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
98 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
99 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
100};
101
38972938 102static const char *special_regnames[] =
4acb54ba
EI		 103{
104 "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
105 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
106 "sr16", "sr17", "sr18"
107};
108
109/* Sign extend at translation time. */
110static inline int sign_extend(unsigned int val, unsigned int width)
111{
112 int sval;
113
114 /* LSL. */
115 val <<= 31 - width;
116 sval = val;
117 /* ASR. */
118 sval >>= 31 - width;
119 return sval;
120}
121
122static inline void t_sync_flags(DisasContext *dc)
123{
124 /* Synch the tb dependant flags between translator and runtime. */
125 if (dc->tb_flags != dc->synced_flags) {
126 tcg_gen_movi_tl(env_iflags, dc->tb_flags);
127 dc->synced_flags = dc->tb_flags;
128 }
129}
130
131static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
132{
133 TCGv_i32 tmp = tcg_const_i32(index);
134
135 t_sync_flags(dc);
136 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
137 gen_helper_raise_exception(tmp);
138 tcg_temp_free_i32(tmp);
139 dc->is_jmp = DISAS_UPDATE;
140}
141
142static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
143{
144 TranslationBlock *tb;
145 tb = dc->tb;
146 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
147 tcg_gen_goto_tb(n);
148 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
149 tcg_gen_exit_tb((long)tb + n);
150 } else {
151 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
152 tcg_gen_exit_tb(0);
153 }
154}
155
ee8b246f
EI		 156static void read_carry(DisasContext *dc, TCGv d)
157{
158 tcg_gen_shri_tl(d, cpu_SR[SR_MSR], 31);
159}
160
161static void write_carry(DisasContext *dc, TCGv v)
162{
163 TCGv t0 = tcg_temp_new();
164 tcg_gen_shli_tl(t0, v, 31);
165 tcg_gen_sari_tl(t0, t0, 31);
166 tcg_gen_andi_tl(t0, t0, (MSR_C | MSR_CC));
167 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR],
168 ~(MSR_C | MSR_CC));
169 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0);
170 tcg_temp_free(t0);
171}
172
61204ce8
EI		 173/* True if ALU operand b is a small immediate that may deserve
174 faster treatment. */
175static inline int dec_alu_op_b_is_small_imm(DisasContext *dc)
176{
177 /* Immediate insn without the imm prefix ? */
178 return dc->type_b && !(dc->tb_flags & IMM_FLAG);
179}
180
4acb54ba
EI		 181static inline TCGv *dec_alu_op_b(DisasContext *dc)
182{
183 if (dc->type_b) {
184 if (dc->tb_flags & IMM_FLAG)
185 tcg_gen_ori_tl(env_imm, env_imm, dc->imm);
186 else
187 tcg_gen_movi_tl(env_imm, (int32_t)((int16_t)dc->imm));
188 return &env_imm;
189 } else
190 return &cpu_R[dc->rb];
191}
192
193static void dec_add(DisasContext *dc)
194{
195 unsigned int k, c;
40cbf5b7 196 TCGv cf;
4acb54ba
EI		 197
198 k = dc->opcode & 4;
199 c = dc->opcode & 2;
200
201 LOG_DIS("add%s%s%s r%d r%d r%d\n",
202 dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "",
203 dc->rd, dc->ra, dc->rb);
204
40cbf5b7
EI		 205 /* Take care of the easy cases first. */
206 if (k) {
207 /* k - keep carry, no need to update MSR. */
208 /* If rd == r0, it's a nop. */
209 if (dc->rd) {
210 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
211
212 if (c) {
213 /* c - Add carry into the result. */
214 cf = tcg_temp_new();
215
216 read_carry(dc, cf);
217 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
218 tcg_temp_free(cf);
219 }
220 }
221 return;
222 }
223
224 /* From now on, we can assume k is zero. So we need to update MSR. */
225 /* Extract carry. */
226 cf = tcg_temp_new();
227 if (c) {
228 read_carry(dc, cf);
229 } else {
230 tcg_gen_movi_tl(cf, 0);
231 }
232
233 if (dc->rd) {
234 TCGv ncf = tcg_temp_new();
235 gen_helper_addkc(ncf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf);
4acb54ba 236 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
40cbf5b7
EI		 237 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
238 write_carry(dc, ncf);
239 tcg_temp_free(ncf);
240 } else {
7e9e4330 241 gen_helper_addkc(cf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf);
40cbf5b7 242 write_carry(dc, cf);
4acb54ba 243 }
40cbf5b7 244 tcg_temp_free(cf);
4acb54ba
EI		 245}
246
247static void dec_sub(DisasContext *dc)
248{
249 unsigned int u, cmp, k, c;
250
251 u = dc->imm & 2;
252 k = dc->opcode & 4;
253 c = dc->opcode & 2;
254 cmp = (dc->imm & 1) && (!dc->type_b) && k;
255
256 if (cmp) {
257 LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir);
258 if (dc->rd) {
259 if (u)
260 gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
261 else
262 gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
263 }
264 } else {
265 LOG_DIS("sub%s%s r%d, r%d r%d\n",
266 k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb);
267
268 if (!k || c) {
269 TCGv t;
270 t = tcg_temp_new();
271 if (dc->rd)
272 gen_helper_subkc(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)),
273 tcg_const_tl(k), tcg_const_tl(c));
274 else
275 gen_helper_subkc(t, cpu_R[dc->ra], *(dec_alu_op_b(dc)),
276 tcg_const_tl(k), tcg_const_tl(c));
277 tcg_temp_free(t);
278 }
279 else if (dc->rd)
280 tcg_gen_sub_tl(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
281 }
282}
283
284static void dec_pattern(DisasContext *dc)
285{
286 unsigned int mode;
287 int l1;
288
1567a005 289 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 290 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 291 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
292 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
293 t_gen_raise_exception(dc, EXCP_HW_EXCP);
294 }
295
4acb54ba
EI		 296 mode = dc->opcode & 3;
297 switch (mode) {
298 case 0:
299 /* pcmpbf. */
300 LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
301 if (dc->rd)
302 gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
303 break;
304 case 2:
305 LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
306 if (dc->rd) {
307 TCGv t0 = tcg_temp_local_new();
308 l1 = gen_new_label();
309 tcg_gen_movi_tl(t0, 1);
310 tcg_gen_brcond_tl(TCG_COND_EQ,
311 cpu_R[dc->ra], cpu_R[dc->rb], l1);
312 tcg_gen_movi_tl(t0, 0);
313 gen_set_label(l1);
314 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
315 tcg_temp_free(t0);
316 }
317 break;
318 case 3:
319 LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
320 l1 = gen_new_label();
321 if (dc->rd) {
322 TCGv t0 = tcg_temp_local_new();
323 tcg_gen_movi_tl(t0, 1);
324 tcg_gen_brcond_tl(TCG_COND_NE,
325 cpu_R[dc->ra], cpu_R[dc->rb], l1);
326 tcg_gen_movi_tl(t0, 0);
327 gen_set_label(l1);
328 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
329 tcg_temp_free(t0);
330 }
331 break;
332 default:
333 cpu_abort(dc->env,
334 "unsupported pattern insn opcode=%x\n", dc->opcode);
335 break;
336 }
337}
338
339static void dec_and(DisasContext *dc)
340{
341 unsigned int not;
342
343 if (!dc->type_b && (dc->imm & (1 << 10))) {
344 dec_pattern(dc);
345 return;
346 }
347
348 not = dc->opcode & (1 << 1);
349 LOG_DIS("and%s\n", not ? "n" : "");
350
351 if (!dc->rd)
352 return;
353
354 if (not) {
355 TCGv t = tcg_temp_new();
356 tcg_gen_not_tl(t, *(dec_alu_op_b(dc)));
357 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], t);
358 tcg_temp_free(t);
359 } else
360 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
361}
362
363static void dec_or(DisasContext *dc)
364{
365 if (!dc->type_b && (dc->imm & (1 << 10))) {
366 dec_pattern(dc);
367 return;
368 }
369
370 LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm);
371 if (dc->rd)
372 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
373}
374
375static void dec_xor(DisasContext *dc)
376{
377 if (!dc->type_b && (dc->imm & (1 << 10))) {
378 dec_pattern(dc);
379 return;
380 }
381
382 LOG_DIS("xor r%d\n", dc->rd);
383 if (dc->rd)
384 tcg_gen_xor_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
385}
386
4acb54ba
EI		 387static inline void msr_read(DisasContext *dc, TCGv d)
388{
389 tcg_gen_mov_tl(d, cpu_SR[SR_MSR]);
390}
391
392static inline void msr_write(DisasContext *dc, TCGv v)
393{
394 dc->cpustate_changed = 1;
395 tcg_gen_mov_tl(cpu_SR[SR_MSR], v);
396 /* PVR, we have a processor version register. */
397 tcg_gen_ori_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], (1 << 10));
398}
399
400static void dec_msr(DisasContext *dc)
401{
402 TCGv t0, t1;
403 unsigned int sr, to, rn;
1567a005 404 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 405
406 sr = dc->imm & ((1 << 14) - 1);
407 to = dc->imm & (1 << 14);
408 dc->type_b = 1;
409 if (to)
410 dc->cpustate_changed = 1;
411
412 /* msrclr and msrset. */
413 if (!(dc->imm & (1 << 15))) {
414 unsigned int clr = dc->ir & (1 << 16);
415
416 LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
417 dc->rd, dc->imm);
1567a005
EI		 418
419 if (!(dc->env->pvr.regs[2] & PVR2_USE_MSR_INSTR)) {
420 /* nop??? */
421 return;
422 }
423
424 if ((dc->tb_flags & MSR_EE_FLAG)
425 && mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) {
426 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
427 t_gen_raise_exception(dc, EXCP_HW_EXCP);
428 return;
429 }
430
4acb54ba
EI		 431 if (dc->rd)
432 msr_read(dc, cpu_R[dc->rd]);
433
434 t0 = tcg_temp_new();
435 t1 = tcg_temp_new();
436 msr_read(dc, t0);
437 tcg_gen_mov_tl(t1, *(dec_alu_op_b(dc)));
438
439 if (clr) {
440 tcg_gen_not_tl(t1, t1);
441 tcg_gen_and_tl(t0, t0, t1);
442 } else
443 tcg_gen_or_tl(t0, t0, t1);
444 msr_write(dc, t0);
445 tcg_temp_free(t0);
446 tcg_temp_free(t1);
447 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
448 dc->is_jmp = DISAS_UPDATE;
449 return;
450 }
451
1567a005
EI		 452 if (to) {
453 if ((dc->tb_flags & MSR_EE_FLAG)
454 && mem_index == MMU_USER_IDX) {
455 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
456 t_gen_raise_exception(dc, EXCP_HW_EXCP);
457 return;
458 }
459 }
460
4acb54ba
EI		 461#if !defined(CONFIG_USER_ONLY)
462 /* Catch read/writes to the mmu block. */
463 if ((sr & ~0xff) == 0x1000) {
464 sr &= 7;
465 LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
466 if (to)
467 gen_helper_mmu_write(tcg_const_tl(sr), cpu_R[dc->ra]);
468 else
469 gen_helper_mmu_read(cpu_R[dc->rd], tcg_const_tl(sr));
470 return;
471 }
472#endif
473
474 if (to) {
475 LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
476 switch (sr) {
477 case 0:
478 break;
479 case 1:
480 msr_write(dc, cpu_R[dc->ra]);
481 break;
482 case 0x3:
483 tcg_gen_mov_tl(cpu_SR[SR_EAR], cpu_R[dc->ra]);
484 break;
485 case 0x5:
486 tcg_gen_mov_tl(cpu_SR[SR_ESR], cpu_R[dc->ra]);
487 break;
488 case 0x7:
97694c57 489 tcg_gen_andi_tl(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
4acb54ba
EI		 490 break;
491 default:
492 cpu_abort(dc->env, "unknown mts reg %x\n", sr);
493 break;
494 }
495 } else {
496 LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm);
497
498 switch (sr) {
499 case 0:
500 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
501 break;
502 case 1:
503 msr_read(dc, cpu_R[dc->rd]);
504 break;
505 case 0x3:
506 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_EAR]);
507 break;
508 case 0x5:
509 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_ESR]);
510 break;
511 case 0x7:
97694c57 512 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_FSR]);
4acb54ba
EI		 513 break;
514 case 0xb:
515 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]);
516 break;
517 case 0x2000:
518 case 0x2001:
519 case 0x2002:
520 case 0x2003:
521 case 0x2004:
522 case 0x2005:
523 case 0x2006:
524 case 0x2007:
525 case 0x2008:
526 case 0x2009:
527 case 0x200a:
528 case 0x200b:
529 case 0x200c:
530 rn = sr & 0xf;
531 tcg_gen_ld_tl(cpu_R[dc->rd],
532 cpu_env, offsetof(CPUState, pvr.regs[rn]));
533 break;
534 default:
535 cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
536 break;
537 }
538 }
ee7dbcf8
EI		 539
540 if (dc->rd == 0) {
541 tcg_gen_movi_tl(cpu_R[0], 0);
542 }
4acb54ba
EI		 543}
544
545/* 64-bit signed mul, lower result in d and upper in d2. */
546static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
547{
548 TCGv_i64 t0, t1;
549
550 t0 = tcg_temp_new_i64();
551 t1 = tcg_temp_new_i64();
552
553 tcg_gen_ext_i32_i64(t0, a);
554 tcg_gen_ext_i32_i64(t1, b);
555 tcg_gen_mul_i64(t0, t0, t1);
556
557 tcg_gen_trunc_i64_i32(d, t0);
558 tcg_gen_shri_i64(t0, t0, 32);
559 tcg_gen_trunc_i64_i32(d2, t0);
560
561 tcg_temp_free_i64(t0);
562 tcg_temp_free_i64(t1);
563}
564
565/* 64-bit unsigned muls, lower result in d and upper in d2. */
566static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
567{
568 TCGv_i64 t0, t1;
569
570 t0 = tcg_temp_new_i64();
571 t1 = tcg_temp_new_i64();
572
573 tcg_gen_extu_i32_i64(t0, a);
574 tcg_gen_extu_i32_i64(t1, b);
575 tcg_gen_mul_i64(t0, t0, t1);
576
577 tcg_gen_trunc_i64_i32(d, t0);
578 tcg_gen_shri_i64(t0, t0, 32);
579 tcg_gen_trunc_i64_i32(d2, t0);
580
581 tcg_temp_free_i64(t0);
582 tcg_temp_free_i64(t1);
583}
584
585/* Multiplier unit. */
586static void dec_mul(DisasContext *dc)
587{
588 TCGv d[2];
589 unsigned int subcode;
590
1567a005 591 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 592 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 593 && !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
594 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
595 t_gen_raise_exception(dc, EXCP_HW_EXCP);
596 return;
597 }
598
4acb54ba
EI		 599 subcode = dc->imm & 3;
600 d[0] = tcg_temp_new();
601 d[1] = tcg_temp_new();
602
603 if (dc->type_b) {
604 LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm);
605 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
606 goto done;
607 }
608
1567a005
EI		 609 /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
610 if (subcode >= 1 && subcode <= 3
611 && !((dc->env->pvr.regs[2] & PVR2_USE_MUL64_MASK))) {
612 /* nop??? */
613 }
614
4acb54ba
EI		 615 switch (subcode) {
616 case 0:
617 LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
618 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], cpu_R[dc->rb]);
619 break;
620 case 1:
621 LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
622 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
623 break;
624 case 2:
625 LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
626 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
627 break;
628 case 3:
629 LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
630 t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
631 break;
632 default:
633 cpu_abort(dc->env, "unknown MUL insn %x\n", subcode);
634 break;
635 }
636done:
637 tcg_temp_free(d[0]);
638 tcg_temp_free(d[1]);
639}
640
641/* Div unit. */
642static void dec_div(DisasContext *dc)
643{
644 unsigned int u;
645
646 u = dc->imm & 2;
647 LOG_DIS("div\n");
648
97f90cbf 649 if ((dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 650 && !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) {
651 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
652 t_gen_raise_exception(dc, EXCP_HW_EXCP);
653 }
654
4acb54ba
EI		 655 if (u)
656 gen_helper_divu(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
657 else
658 gen_helper_divs(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
659 if (!dc->rd)
660 tcg_gen_movi_tl(cpu_R[dc->rd], 0);
661}
662
663static void dec_barrel(DisasContext *dc)
664{
665 TCGv t0;
666 unsigned int s, t;
667
1567a005 668 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 669 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005
EI		 670 && !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
671 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
672 t_gen_raise_exception(dc, EXCP_HW_EXCP);
673 return;
674 }
675
4acb54ba
EI		 676 s = dc->imm & (1 << 10);
677 t = dc->imm & (1 << 9);
678
679 LOG_DIS("bs%s%s r%d r%d r%d\n",
680 s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
681
682 t0 = tcg_temp_new();
683
684 tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
685 tcg_gen_andi_tl(t0, t0, 31);
686
687 if (s)
688 tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
689 else {
690 if (t)
691 tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
692 else
693 tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
694 }
695}
696
697static void dec_bit(DisasContext *dc)
698{
699 TCGv t0, t1;
700 unsigned int op;
1567a005 701 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 702
703 op = dc->ir & ((1 << 8) - 1);
704 switch (op) {
705 case 0x21:
706 /* src. */
707 t0 = tcg_temp_new();
708
709 LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
710 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
711 if (dc->rd) {
712 t1 = tcg_temp_new();
713 read_carry(dc, t1);
714 tcg_gen_shli_tl(t1, t1, 31);
715
716 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
717 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t1);
718 tcg_temp_free(t1);
719 }
720
721 /* Update carry. */
722 write_carry(dc, t0);
723 tcg_temp_free(t0);
724 break;
725
726 case 0x1:
727 case 0x41:
728 /* srl. */
729 t0 = tcg_temp_new();
730 LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
731
732 /* Update carry. */
733 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
734 write_carry(dc, t0);
735 tcg_temp_free(t0);
736 if (dc->rd) {
737 if (op == 0x41)
738 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
739 else
740 tcg_gen_sari_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
741 }
742 break;
743 case 0x60:
744 LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra);
745 tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
746 break;
747 case 0x61:
748 LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra);
749 tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
750 break;
751 case 0x64:
f062a3c7
EI		 752 case 0x66:
753 case 0x74:
754 case 0x76:
4acb54ba
EI		 755 /* wdc. */
756 LOG_DIS("wdc r%d\n", dc->ra);
1567a005
EI		 757 if ((dc->tb_flags & MSR_EE_FLAG)
758 && mem_index == MMU_USER_IDX) {
759 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
760 t_gen_raise_exception(dc, EXCP_HW_EXCP);
761 return;
762 }
4acb54ba
EI		 763 break;
764 case 0x68:
765 /* wic. */
766 LOG_DIS("wic r%d\n", dc->ra);
1567a005
EI		 767 if ((dc->tb_flags & MSR_EE_FLAG)
768 && mem_index == MMU_USER_IDX) {
769 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
770 t_gen_raise_exception(dc, EXCP_HW_EXCP);
771 return;
772 }
4acb54ba
EI		 773 break;
774 default:
775 cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
776 dc->pc, op, dc->rd, dc->ra, dc->rb);
777 break;
778 }
779}
780
781static inline void sync_jmpstate(DisasContext *dc)
782{
844bab60
EI		 783 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
784 if (dc->jmp == JMP_DIRECT) {
785 tcg_gen_movi_tl(env_btaken, 1);
786 }
23979dc5
EI		 787 dc->jmp = JMP_INDIRECT;
788 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
4acb54ba
EI		 789 }
790}
791
792static void dec_imm(DisasContext *dc)
793{
794 LOG_DIS("imm %x\n", dc->imm << 16);
795 tcg_gen_movi_tl(env_imm, (dc->imm << 16));
796 dc->tb_flags |= IMM_FLAG;
797 dc->clear_imm = 0;
798}
799
800static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
801 unsigned int size)
802{
803 int mem_index = cpu_mmu_index(dc->env);
804
805 if (size == 1) {
806 tcg_gen_qemu_ld8u(dst, addr, mem_index);
807 } else if (size == 2) {
808 tcg_gen_qemu_ld16u(dst, addr, mem_index);
809 } else if (size == 4) {
810 tcg_gen_qemu_ld32u(dst, addr, mem_index);
811 } else
812 cpu_abort(dc->env, "Incorrect load size %d\n", size);
813}
814
815static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
816{
817 unsigned int extimm = dc->tb_flags & IMM_FLAG;
818
9ef55357 819 /* Treat the common cases first. */
4acb54ba 820 if (!dc->type_b) {
4b5ef0b5
EI		 821 /* If any of the regs is r0, return a ptr to the other. */
822 if (dc->ra == 0) {
823 return &cpu_R[dc->rb];
824 } else if (dc->rb == 0) {
825 return &cpu_R[dc->ra];
826 }
827
4acb54ba
EI		 828 *t = tcg_temp_new();
829 tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
830 return t;
831 }
832 /* Immediate. */
833 if (!extimm) {
834 if (dc->imm == 0) {
835 return &cpu_R[dc->ra];
836 }
837 *t = tcg_temp_new();
838 tcg_gen_movi_tl(*t, (int32_t)((int16_t)dc->imm));
839 tcg_gen_add_tl(*t, cpu_R[dc->ra], *t);
840 } else {
841 *t = tcg_temp_new();
842 tcg_gen_add_tl(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
843 }
844
845 return t;
846}
847
9f8beb66
EI		 848static inline void dec_byteswap(DisasContext *dc, TCGv dst, TCGv src, int size)
849{
850 if (size == 4) {
851 tcg_gen_bswap32_tl(dst, src);
852 } else if (size == 2) {
853 TCGv t = tcg_temp_new();
854
855 /* bswap16 assumes the high bits are zero. */
856 tcg_gen_andi_tl(t, src, 0xffff);
857 tcg_gen_bswap16_tl(dst, t);
858 tcg_temp_free(t);
859 } else {
860 /* Ignore.
861 cpu_abort(dc->env, "Invalid ldst byteswap size %d\n", size);
862 */
863 }
864}
865
4acb54ba
EI		 866static void dec_load(DisasContext *dc)
867{
868 TCGv t, *addr;
9f8beb66 869 unsigned int size, rev = 0;
4acb54ba
EI		 870
871 size = 1 << (dc->opcode & 3);
9f8beb66
EI		 872
873 if (!dc->type_b) {
874 rev = (dc->ir >> 9) & 1;
875 }
876
0187688f 877 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
97f90cbf 878 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
0187688f
EI		 879 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
880 t_gen_raise_exception(dc, EXCP_HW_EXCP);
881 return;
882 }
4acb54ba 883
9f8beb66
EI		 884 LOG_DIS("l%d%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "");
885
4acb54ba
EI		 886 t_sync_flags(dc);
887 addr = compute_ldst_addr(dc, &t);
888
9f8beb66
EI		 889 /*
890 * When doing reverse accesses we need to do two things.
891 *
892 * 1. Reverse the address wrt endianess.
893 * 2. Byteswap the data lanes on the way back into the CPU core.
894 */
895 if (rev && size != 4) {
896 /* Endian reverse the address. t is addr. */
897 switch (size) {
898 case 1:
899 {
900 /* 00 -> 11
901 01 -> 10
902 10 -> 10
903 11 -> 00 */
904 TCGv low = tcg_temp_new();
905
906 /* Force addr into the temp. */
907 if (addr != &t) {
908 t = tcg_temp_new();
909 tcg_gen_mov_tl(t, *addr);
910 addr = &t;
911 }
912
913 tcg_gen_andi_tl(low, t, 3);
914 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
915 tcg_gen_andi_tl(t, t, ~3);
916 tcg_gen_or_tl(t, t, low);
9f8beb66
EI		 917 tcg_gen_mov_tl(env_imm, t);
918 tcg_temp_free(low);
919 break;
920 }
921
922 case 2:
923 /* 00 -> 10
924 10 -> 00. */
925 /* Force addr into the temp. */
926 if (addr != &t) {
927 t = tcg_temp_new();
928 tcg_gen_xori_tl(t, *addr, 2);
929 addr = &t;
930 } else {
931 tcg_gen_xori_tl(t, t, 2);
932 }
933 break;
934 default:
935 cpu_abort(dc->env, "Invalid reverse size\n");
936 break;
937 }
938 }
939
4acb54ba
EI		 940 /* If we get a fault on a dslot, the jmpstate better be in sync. */
941 sync_jmpstate(dc);
968a40f6
EI		 942
943 /* Verify alignment if needed. */
944 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
a12f6507
EI		 945 TCGv v = tcg_temp_new();
946
947 /*
948 * Microblaze gives MMU faults priority over faults due to
949 * unaligned addresses. That's why we speculatively do the load
950 * into v. If the load succeeds, we verify alignment of the
951 * address and if that succeeds we write into the destination reg.
952 */
953 gen_load(dc, v, *addr, size);
954
955 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
968a40f6 956 gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
3aa80988 957 tcg_const_tl(0), tcg_const_tl(size - 1));
9f8beb66
EI		 958 if (dc->rd) {
959 if (rev) {
960 dec_byteswap(dc, cpu_R[dc->rd], v, size);
961 } else {
962 tcg_gen_mov_tl(cpu_R[dc->rd], v);
963 }
964 }
a12f6507 965 tcg_temp_free(v);
968a40f6 966 } else {
a12f6507
EI		 967 if (dc->rd) {
968 gen_load(dc, cpu_R[dc->rd], *addr, size);
9f8beb66
EI		 969 if (rev) {
970 dec_byteswap(dc, cpu_R[dc->rd], cpu_R[dc->rd], size);
971 }
a12f6507 972 } else {
9f8beb66 973 /* We are loading into r0, no need to reverse. */
a12f6507
EI		 974 gen_load(dc, env_imm, *addr, size);
975 }
4acb54ba
EI		 976 }
977
978 if (addr == &t)
979 tcg_temp_free(t);
980}
981
982static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
983 unsigned int size)
984{
985 int mem_index = cpu_mmu_index(dc->env);
986
987 if (size == 1)
988 tcg_gen_qemu_st8(val, addr, mem_index);
989 else if (size == 2) {
990 tcg_gen_qemu_st16(val, addr, mem_index);
991 } else if (size == 4) {
992 tcg_gen_qemu_st32(val, addr, mem_index);
993 } else
994 cpu_abort(dc->env, "Incorrect store size %d\n", size);
995}
996
997static void dec_store(DisasContext *dc)
998{
999 TCGv t, *addr;
9f8beb66 1000 unsigned int size, rev = 0;
4acb54ba
EI		 1001
1002 size = 1 << (dc->opcode & 3);
9f8beb66
EI		 1003 if (!dc->type_b) {
1004 rev = (dc->ir >> 9) & 1;
1005 }
4acb54ba 1006
0187688f 1007 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
97f90cbf 1008 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
0187688f
EI		 1009 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1010 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1011 return;
1012 }
1013
9f8beb66 1014 LOG_DIS("s%d%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "");
4acb54ba
EI		 1015 t_sync_flags(dc);
1016 /* If we get a fault on a dslot, the jmpstate better be in sync. */
1017 sync_jmpstate(dc);
1018 addr = compute_ldst_addr(dc, &t);
968a40f6 1019
9f8beb66
EI		 1020 if (rev && size != 4) {
1021 /* Endian reverse the address. t is addr. */
1022 switch (size) {
1023 case 1:
1024 {
1025 /* 00 -> 11
1026 01 -> 10
1027 10 -> 10
1028 11 -> 00 */
1029 TCGv low = tcg_temp_new();
1030
1031 /* Force addr into the temp. */
1032 if (addr != &t) {
1033 t = tcg_temp_new();
1034 tcg_gen_mov_tl(t, *addr);
1035 addr = &t;
1036 }
1037
1038 tcg_gen_andi_tl(low, t, 3);
1039 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
1040 tcg_gen_andi_tl(t, t, ~3);
1041 tcg_gen_or_tl(t, t, low);
9f8beb66
EI		 1042 tcg_gen_mov_tl(env_imm, t);
1043 tcg_temp_free(low);
1044 break;
1045 }
1046
1047 case 2:
1048 /* 00 -> 10
1049 10 -> 00. */
1050 /* Force addr into the temp. */
1051 if (addr != &t) {
1052 t = tcg_temp_new();
1053 tcg_gen_xori_tl(t, *addr, 2);
1054 addr = &t;
1055 } else {
1056 tcg_gen_xori_tl(t, t, 2);
1057 }
1058 break;
1059 default:
1060 cpu_abort(dc->env, "Invalid reverse size\n");
1061 break;
1062 }
1063
1064 if (size != 1) {
1065 TCGv bs_data = tcg_temp_new();
1066 dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1067 gen_store(dc, *addr, bs_data, size);
1068 tcg_temp_free(bs_data);
1069 } else {
1070 gen_store(dc, *addr, cpu_R[dc->rd], size);
1071 }
1072 } else {
1073 if (rev) {
1074 TCGv bs_data = tcg_temp_new();
1075 dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1076 gen_store(dc, *addr, bs_data, size);
1077 tcg_temp_free(bs_data);
1078 } else {
1079 gen_store(dc, *addr, cpu_R[dc->rd], size);
1080 }
1081 }
a12f6507 1082
968a40f6
EI		 1083 /* Verify alignment if needed. */
1084 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
a12f6507
EI		 1085 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1086 /* FIXME: if the alignment is wrong, we should restore the value
9f8beb66
EI		 1087 * in memory. One possible way to acheive this is to probe
1088 * the MMU prior to the memaccess, thay way we could put
1089 * the alignment checks in between the probe and the mem
1090 * access.
a12f6507 1091 */
968a40f6 1092 gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
3aa80988 1093 tcg_const_tl(1), tcg_const_tl(size - 1));
968a40f6
EI		 1094 }
1095
4acb54ba
EI		 1096 if (addr == &t)
1097 tcg_temp_free(t);
1098}
1099
1100static inline void eval_cc(DisasContext *dc, unsigned int cc,
1101 TCGv d, TCGv a, TCGv b)
1102{
4acb54ba
EI		 1103 switch (cc) {
1104 case CC_EQ:
b2565c69 1105 tcg_gen_setcond_tl(TCG_COND_EQ, d, a, b);
4acb54ba
EI		 1106 break;
1107 case CC_NE:
b2565c69 1108 tcg_gen_setcond_tl(TCG_COND_NE, d, a, b);
4acb54ba
EI		 1109 break;
1110 case CC_LT:
b2565c69 1111 tcg_gen_setcond_tl(TCG_COND_LT, d, a, b);
4acb54ba
EI		 1112 break;
1113 case CC_LE:
b2565c69 1114 tcg_gen_setcond_tl(TCG_COND_LE, d, a, b);
4acb54ba
EI		 1115 break;
1116 case CC_GE:
b2565c69 1117 tcg_gen_setcond_tl(TCG_COND_GE, d, a, b);
4acb54ba
EI		 1118 break;
1119 case CC_GT:
b2565c69 1120 tcg_gen_setcond_tl(TCG_COND_GT, d, a, b);
4acb54ba
EI		 1121 break;
1122 default:
1123 cpu_abort(dc->env, "Unknown condition code %x.\n", cc);
1124 break;
1125 }
1126}
1127
1128static void eval_cond_jmp(DisasContext *dc, TCGv pc_true, TCGv pc_false)
1129{
1130 int l1;
1131
1132 l1 = gen_new_label();
1133 /* Conditional jmp. */
1134 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_false);
1135 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
1136 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_true);
1137 gen_set_label(l1);
1138}
1139
1140static void dec_bcc(DisasContext *dc)
1141{
1142 unsigned int cc;
1143 unsigned int dslot;
1144
1145 cc = EXTRACT_FIELD(dc->ir, 21, 23);
1146 dslot = dc->ir & (1 << 25);
1147 LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm);
1148
1149 dc->delayed_branch = 1;
1150 if (dslot) {
1151 dc->delayed_branch = 2;
1152 dc->tb_flags |= D_FLAG;
1153 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1154 cpu_env, offsetof(CPUState, bimm));
1155 }
1156
61204ce8
EI		 1157 if (dec_alu_op_b_is_small_imm(dc)) {
1158 int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */
1159
1160 tcg_gen_movi_tl(env_btarget, dc->pc + offset);
844bab60 1161 dc->jmp = JMP_DIRECT_CC;
23979dc5 1162 dc->jmp_pc = dc->pc + offset;
61204ce8 1163 } else {
23979dc5 1164 dc->jmp = JMP_INDIRECT;
61204ce8
EI		 1165 tcg_gen_movi_tl(env_btarget, dc->pc);
1166 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
1167 }
61204ce8 1168 eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_tl(0));
4acb54ba
EI		 1169}
1170
1171static void dec_br(DisasContext *dc)
1172{
1173 unsigned int dslot, link, abs;
ff21f70a 1174 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 1175
1176 dslot = dc->ir & (1 << 20);
1177 abs = dc->ir & (1 << 19);
1178 link = dc->ir & (1 << 18);
1179 LOG_DIS("br%s%s%s%s imm=%x\n",
1180 abs ? "a" : "", link ? "l" : "",
1181 dc->type_b ? "i" : "", dslot ? "d" : "",
1182 dc->imm);
1183
1184 dc->delayed_branch = 1;
1185 if (dslot) {
1186 dc->delayed_branch = 2;
1187 dc->tb_flags |= D_FLAG;
1188 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1189 cpu_env, offsetof(CPUState, bimm));
1190 }
1191 if (link && dc->rd)
1192 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
1193
1194 dc->jmp = JMP_INDIRECT;
1195 if (abs) {
1196 tcg_gen_movi_tl(env_btaken, 1);
1197 tcg_gen_mov_tl(env_btarget, *(dec_alu_op_b(dc)));
ff21f70a
EI		 1198 if (link && !dslot) {
1199 if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18))
1200 t_gen_raise_exception(dc, EXCP_BREAK);
1201 if (dc->imm == 0) {
1202 if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) {
1203 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1204 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1205 return;
1206 }
1207
1208 t_gen_raise_exception(dc, EXCP_DEBUG);
1209 }
1210 }
4acb54ba 1211 } else {
61204ce8
EI		 1212 if (dec_alu_op_b_is_small_imm(dc)) {
1213 dc->jmp = JMP_DIRECT;
1214 dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm);
1215 } else {
4acb54ba
EI		 1216 tcg_gen_movi_tl(env_btaken, 1);
1217 tcg_gen_movi_tl(env_btarget, dc->pc);
1218 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
4acb54ba
EI		 1219 }
1220 }
1221}
1222
1223static inline void do_rti(DisasContext *dc)
1224{
1225 TCGv t0, t1;
1226 t0 = tcg_temp_new();
1227 t1 = tcg_temp_new();
1228 tcg_gen_shri_tl(t0, cpu_SR[SR_MSR], 1);
1229 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_IE);
1230 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1231
1232 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1233 tcg_gen_or_tl(t1, t1, t0);
1234 msr_write(dc, t1);
1235 tcg_temp_free(t1);
1236 tcg_temp_free(t0);
1237 dc->tb_flags &= ~DRTI_FLAG;
1238}
1239
1240static inline void do_rtb(DisasContext *dc)
1241{
1242 TCGv t0, t1;
1243 t0 = tcg_temp_new();
1244 t1 = tcg_temp_new();
1245 tcg_gen_andi_tl(t1, cpu_SR[SR_MSR], ~MSR_BIP);
1246 tcg_gen_shri_tl(t0, t1, 1);
1247 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1248
1249 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1250 tcg_gen_or_tl(t1, t1, t0);
1251 msr_write(dc, t1);
1252 tcg_temp_free(t1);
1253 tcg_temp_free(t0);
1254 dc->tb_flags &= ~DRTB_FLAG;
1255}
1256
1257static inline void do_rte(DisasContext *dc)
1258{
1259 TCGv t0, t1;
1260 t0 = tcg_temp_new();
1261 t1 = tcg_temp_new();
1262
1263 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_EE);
1264 tcg_gen_andi_tl(t1, t1, ~MSR_EIP);
1265 tcg_gen_shri_tl(t0, t1, 1);
1266 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1267
1268 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1269 tcg_gen_or_tl(t1, t1, t0);
1270 msr_write(dc, t1);
1271 tcg_temp_free(t1);
1272 tcg_temp_free(t0);
1273 dc->tb_flags &= ~DRTE_FLAG;
1274}
1275
1276static void dec_rts(DisasContext *dc)
1277{
1278 unsigned int b_bit, i_bit, e_bit;
1567a005 1279 int mem_index = cpu_mmu_index(dc->env);
4acb54ba
EI		 1280
1281 i_bit = dc->ir & (1 << 21);
1282 b_bit = dc->ir & (1 << 22);
1283 e_bit = dc->ir & (1 << 23);
1284
1285 dc->delayed_branch = 2;
1286 dc->tb_flags |= D_FLAG;
1287 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1288 cpu_env, offsetof(CPUState, bimm));
1289
1290 if (i_bit) {
1291 LOG_DIS("rtid ir=%x\n", dc->ir);
1567a005
EI		 1292 if ((dc->tb_flags & MSR_EE_FLAG)
1293 && mem_index == MMU_USER_IDX) {
1294 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1295 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1296 }
4acb54ba
EI		 1297 dc->tb_flags |= DRTI_FLAG;
1298 } else if (b_bit) {
1299 LOG_DIS("rtbd ir=%x\n", dc->ir);
1567a005
EI		 1300 if ((dc->tb_flags & MSR_EE_FLAG)
1301 && mem_index == MMU_USER_IDX) {
1302 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1303 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1304 }
4acb54ba
EI		 1305 dc->tb_flags |= DRTB_FLAG;
1306 } else if (e_bit) {
1307 LOG_DIS("rted ir=%x\n", dc->ir);
1567a005
EI		 1308 if ((dc->tb_flags & MSR_EE_FLAG)
1309 && mem_index == MMU_USER_IDX) {
1310 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1311 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1312 }
4acb54ba
EI		 1313 dc->tb_flags |= DRTE_FLAG;
1314 } else
1315 LOG_DIS("rts ir=%x\n", dc->ir);
1316
23979dc5 1317 dc->jmp = JMP_INDIRECT;
4acb54ba
EI		 1318 tcg_gen_movi_tl(env_btaken, 1);
1319 tcg_gen_add_tl(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
1320}
1321
97694c57
EI		 1322static int dec_check_fpuv2(DisasContext *dc)
1323{
1324 int r;
1325
1326 r = dc->env->pvr.regs[2] & PVR2_USE_FPU2_MASK;
1327
1328 if (!r && (dc->tb_flags & MSR_EE_FLAG)) {
1329 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
1330 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1331 }
1332 return r;
1333}
1334
1567a005
EI		 1335static void dec_fpu(DisasContext *dc)
1336{
97694c57
EI		 1337 unsigned int fpu_insn;
1338
1567a005 1339 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf 1340 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1567a005 1341 && !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) {
97694c57 1342 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1567a005
EI		 1343 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1344 return;
1345 }
1346
97694c57
EI		 1347 fpu_insn = (dc->ir >> 7) & 7;
1348
1349 switch (fpu_insn) {
1350 case 0:
1351 gen_helper_fadd(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1352 break;
1353
1354 case 1:
1355 gen_helper_frsub(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1356 break;
1357
1358 case 2:
1359 gen_helper_fmul(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1360 break;
1361
1362 case 3:
1363 gen_helper_fdiv(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1364 break;
1365
1366 case 4:
1367 switch ((dc->ir >> 4) & 7) {
1368 case 0:
1369 gen_helper_fcmp_un(cpu_R[dc->rd],
1370 cpu_R[dc->ra], cpu_R[dc->rb]);
1371 break;
1372 case 1:
1373 gen_helper_fcmp_lt(cpu_R[dc->rd],
1374 cpu_R[dc->ra], cpu_R[dc->rb]);
1375 break;
1376 case 2:
1377 gen_helper_fcmp_eq(cpu_R[dc->rd],
1378 cpu_R[dc->ra], cpu_R[dc->rb]);
1379 break;
1380 case 3:
1381 gen_helper_fcmp_le(cpu_R[dc->rd],
1382 cpu_R[dc->ra], cpu_R[dc->rb]);
1383 break;
1384 case 4:
1385 gen_helper_fcmp_gt(cpu_R[dc->rd],
1386 cpu_R[dc->ra], cpu_R[dc->rb]);
1387 break;
1388 case 5:
1389 gen_helper_fcmp_ne(cpu_R[dc->rd],
1390 cpu_R[dc->ra], cpu_R[dc->rb]);
1391 break;
1392 case 6:
1393 gen_helper_fcmp_ge(cpu_R[dc->rd],
1394 cpu_R[dc->ra], cpu_R[dc->rb]);
1395 break;
1396 default:
1397 qemu_log ("unimplemented fcmp fpu_insn=%x pc=%x opc=%x\n",
1398 fpu_insn, dc->pc, dc->opcode);
1399 dc->abort_at_next_insn = 1;
1400 break;
1401 }
1402 break;
1403
1404 case 5:
1405 if (!dec_check_fpuv2(dc)) {
1406 return;
1407 }
1408 gen_helper_flt(cpu_R[dc->rd], cpu_R[dc->ra]);
1409 break;
1410
1411 case 6:
1412 if (!dec_check_fpuv2(dc)) {
1413 return;
1414 }
1415 gen_helper_fint(cpu_R[dc->rd], cpu_R[dc->ra]);
1416 break;
1417
1418 case 7:
1419 if (!dec_check_fpuv2(dc)) {
1420 return;
1421 }
1422 gen_helper_fsqrt(cpu_R[dc->rd], cpu_R[dc->ra]);
1423 break;
1424
1425 default:
1426 qemu_log ("unimplemented FPU insn fpu_insn=%x pc=%x opc=%x\n",
1427 fpu_insn, dc->pc, dc->opcode);
1428 dc->abort_at_next_insn = 1;
1429 break;
1430 }
1567a005
EI		 1431}
1432
4acb54ba
EI		 1433static void dec_null(DisasContext *dc)
1434{
02b33596
EI		 1435 if ((dc->tb_flags & MSR_EE_FLAG)
1436 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
1437 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1438 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1439 return;
1440 }
4acb54ba
EI		 1441 qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
1442 dc->abort_at_next_insn = 1;
1443}
1444
1445static struct decoder_info {
1446 struct {
1447 uint32_t bits;
1448 uint32_t mask;
1449 };
1450 void (*dec)(DisasContext *dc);
1451} decinfo[] = {
1452 {DEC_ADD, dec_add},
1453 {DEC_SUB, dec_sub},
1454 {DEC_AND, dec_and},
1455 {DEC_XOR, dec_xor},
1456 {DEC_OR, dec_or},
1457 {DEC_BIT, dec_bit},
1458 {DEC_BARREL, dec_barrel},
1459 {DEC_LD, dec_load},
1460 {DEC_ST, dec_store},
1461 {DEC_IMM, dec_imm},
1462 {DEC_BR, dec_br},
1463 {DEC_BCC, dec_bcc},
1464 {DEC_RTS, dec_rts},
1567a005 1465 {DEC_FPU, dec_fpu},
4acb54ba
EI		 1466 {DEC_MUL, dec_mul},
1467 {DEC_DIV, dec_div},
1468 {DEC_MSR, dec_msr},
1469 {{0, 0}, dec_null}
1470};
1471
1472static inline void decode(DisasContext *dc)
1473{
1474 uint32_t ir;
1475 int i;
1476
1477 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
1478 tcg_gen_debug_insn_start(dc->pc);
1479
1480 dc->ir = ir = ldl_code(dc->pc);
1481 LOG_DIS("%8.8x\t", dc->ir);
1482
1483 if (dc->ir)
1484 dc->nr_nops = 0;
1485 else {
1567a005 1486 if ((dc->tb_flags & MSR_EE_FLAG)
97f90cbf
EI		 1487 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1488 && (dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
1567a005
EI		 1489 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1490 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1491 return;
1492 }
1493
4acb54ba
EI		 1494 LOG_DIS("nr_nops=%d\t", dc->nr_nops);
1495 dc->nr_nops++;
1496 if (dc->nr_nops > 4)
1497 cpu_abort(dc->env, "fetching nop sequence\n");
1498 }
1499 /* bit 2 seems to indicate insn type. */
1500 dc->type_b = ir & (1 << 29);
1501
1502 dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1503 dc->rd = EXTRACT_FIELD(ir, 21, 25);
1504 dc->ra = EXTRACT_FIELD(ir, 16, 20);
1505 dc->rb = EXTRACT_FIELD(ir, 11, 15);
1506 dc->imm = EXTRACT_FIELD(ir, 0, 15);
1507
1508 /* Large switch for all insns. */
1509 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
1510 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
1511 decinfo[i].dec(dc);
1512 break;
1513 }
1514 }
1515}
1516
4acb54ba
EI		 1517static void check_breakpoint(CPUState *env, DisasContext *dc)
1518{
1519 CPUBreakpoint *bp;
1520
72cf2d4f
BS		 1521 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1522 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
4acb54ba
EI		 1523 if (bp->pc == dc->pc) {
1524 t_gen_raise_exception(dc, EXCP_DEBUG);
1525 dc->is_jmp = DISAS_UPDATE;
1526 }
1527 }
1528 }
1529}
1530
1531/* generate intermediate code for basic block 'tb'. */
1532static void
1533gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
1534 int search_pc)
1535{
1536 uint16_t *gen_opc_end;
1537 uint32_t pc_start;
1538 int j, lj;
1539 struct DisasContext ctx;
1540 struct DisasContext *dc = &ctx;
1541 uint32_t next_page_start, org_flags;
1542 target_ulong npc;
1543 int num_insns;
1544 int max_insns;
1545
1546 qemu_log_try_set_file(stderr);
1547
1548 pc_start = tb->pc;
1549 dc->env = env;
1550 dc->tb = tb;
1551 org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
1552
1553 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1554
1555 dc->is_jmp = DISAS_NEXT;
1556 dc->jmp = 0;
1557 dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
23979dc5
EI		 1558 if (dc->delayed_branch) {
1559 dc->jmp = JMP_INDIRECT;
1560 }
4acb54ba 1561 dc->pc = pc_start;
4acb54ba
EI		 1562 dc->singlestep_enabled = env->singlestep_enabled;
1563 dc->cpustate_changed = 0;
1564 dc->abort_at_next_insn = 0;
1565 dc->nr_nops = 0;
1566
1567 if (pc_start & 3)
1568 cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start);
1569
1570 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1571#if !SIM_COMPAT
1572 qemu_log("--------------\n");
1573 log_cpu_state(env, 0);
1574#endif
1575 }
1576
1577 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1578 lj = -1;
1579 num_insns = 0;
1580 max_insns = tb->cflags & CF_COUNT_MASK;
1581 if (max_insns == 0)
1582 max_insns = CF_COUNT_MASK;
1583
1584 gen_icount_start();
1585 do
1586 {
1587#if SIM_COMPAT
1588 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1589 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1590 gen_helper_debug();
1591 }
1592#endif
1593 check_breakpoint(env, dc);
1594
1595 if (search_pc) {
1596 j = gen_opc_ptr - gen_opc_buf;
1597 if (lj < j) {
1598 lj++;
1599 while (lj < j)
1600 gen_opc_instr_start[lj++] = 0;
1601 }
1602 gen_opc_pc[lj] = dc->pc;
1603 gen_opc_instr_start[lj] = 1;
1604 gen_opc_icount[lj] = num_insns;
1605 }
1606
1607 /* Pretty disas. */
1608 LOG_DIS("%8.8x:\t", dc->pc);
1609
1610 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1611 gen_io_start();
1612
1613 dc->clear_imm = 1;
1614 decode(dc);
1615 if (dc->clear_imm)
1616 dc->tb_flags &= ~IMM_FLAG;
4acb54ba
EI		 1617 dc->pc += 4;
1618 num_insns++;
1619
1620 if (dc->delayed_branch) {
1621 dc->delayed_branch--;
1622 if (!dc->delayed_branch) {
1623 if (dc->tb_flags & DRTI_FLAG)
1624 do_rti(dc);
1625 if (dc->tb_flags & DRTB_FLAG)
1626 do_rtb(dc);
1627 if (dc->tb_flags & DRTE_FLAG)
1628 do_rte(dc);
1629 /* Clear the delay slot flag. */
1630 dc->tb_flags &= ~D_FLAG;
1631 /* If it is a direct jump, try direct chaining. */
23979dc5 1632 if (dc->jmp == JMP_INDIRECT) {
4acb54ba
EI		 1633 eval_cond_jmp(dc, env_btarget, tcg_const_tl(dc->pc));
1634 dc->is_jmp = DISAS_JUMP;
23979dc5 1635 } else if (dc->jmp == JMP_DIRECT) {
844bab60
EI		 1636 t_sync_flags(dc);
1637 gen_goto_tb(dc, 0, dc->jmp_pc);
1638 dc->is_jmp = DISAS_TB_JUMP;
1639 } else if (dc->jmp == JMP_DIRECT_CC) {
23979dc5
EI		 1640 int l1;
1641
1642 t_sync_flags(dc);
1643 l1 = gen_new_label();
1644 /* Conditional jmp. */
1645 tcg_gen_brcondi_tl(TCG_COND_NE, env_btaken, 0, l1);
1646 gen_goto_tb(dc, 1, dc->pc);
1647 gen_set_label(l1);
1648 gen_goto_tb(dc, 0, dc->jmp_pc);
1649
1650 dc->is_jmp = DISAS_TB_JUMP;
4acb54ba
EI		 1651 }
1652 break;
1653 }
1654 }
1655 if (env->singlestep_enabled)
1656 break;
1657 } while (!dc->is_jmp && !dc->cpustate_changed
1658 && gen_opc_ptr < gen_opc_end
1659 && !singlestep
1660 && (dc->pc < next_page_start)
1661 && num_insns < max_insns);
1662
1663 npc = dc->pc;
844bab60 1664 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
4acb54ba
EI		 1665 if (dc->tb_flags & D_FLAG) {
1666 dc->is_jmp = DISAS_UPDATE;
1667 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1668 sync_jmpstate(dc);
1669 } else
1670 npc = dc->jmp_pc;
1671 }
1672
1673 if (tb->cflags & CF_LAST_IO)
1674 gen_io_end();
1675 /* Force an update if the per-tb cpu state has changed. */
1676 if (dc->is_jmp == DISAS_NEXT
1677 && (dc->cpustate_changed || org_flags != dc->tb_flags)) {
1678 dc->is_jmp = DISAS_UPDATE;
1679 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1680 }
1681 t_sync_flags(dc);
1682
1683 if (unlikely(env->singlestep_enabled)) {
1684 t_gen_raise_exception(dc, EXCP_DEBUG);
1685 if (dc->is_jmp == DISAS_NEXT)
1686 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1687 } else {
1688 switch(dc->is_jmp) {
1689 case DISAS_NEXT:
1690 gen_goto_tb(dc, 1, npc);
1691 break;
1692 default:
1693 case DISAS_JUMP:
1694 case DISAS_UPDATE:
1695 /* indicate that the hash table must be used
1696 to find the next TB */
1697 tcg_gen_exit_tb(0);
1698 break;
1699 case DISAS_TB_JUMP:
1700 /* nothing more to generate */
1701 break;
1702 }
1703 }
1704 gen_icount_end(tb, num_insns);
1705 *gen_opc_ptr = INDEX_op_end;
1706 if (search_pc) {
1707 j = gen_opc_ptr - gen_opc_buf;
1708 lj++;
1709 while (lj <= j)
1710 gen_opc_instr_start[lj++] = 0;
1711 } else {
1712 tb->size = dc->pc - pc_start;
1713 tb->icount = num_insns;
1714 }
1715
1716#ifdef DEBUG_DISAS
1717#if !SIM_COMPAT
1718 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1719 qemu_log("\n");
1720#if DISAS_GNU
1721 log_target_disas(pc_start, dc->pc - pc_start, 0);
1722#endif
e6aa0f11 1723 qemu_log("\nisize=%d osize=%td\n",
4acb54ba
EI		 1724 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
1725 }
1726#endif
1727#endif
1728 assert(!dc->abort_at_next_insn);
1729}
1730
1731void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
1732{
1733 gen_intermediate_code_internal(env, tb, 0);
1734}
1735
1736void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
1737{
1738 gen_intermediate_code_internal(env, tb, 1);
1739}
1740
9a78eead 1741void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
4acb54ba
EI		 1742 int flags)
1743{
1744 int i;
1745
1746 if (!env || !f)
1747 return;
1748
1749 cpu_fprintf(f, "IN: PC=%x %s\n",
1750 env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC]));
97694c57 1751 cpu_fprintf(f, "rmsr=%x resr=%x rear=%x debug=%x imm=%x iflags=%x fsr=%x\n",
4c24aa0a 1752 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
97694c57 1753 env->debug, env->imm, env->iflags, env->sregs[SR_FSR]);
17c52a43 1754 cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
4acb54ba
EI		 1755 env->btaken, env->btarget,
1756 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
17c52a43
EI		 1757 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
1758 (env->sregs[SR_MSR] & MSR_EIP),
1759 (env->sregs[SR_MSR] & MSR_IE));
1760
4acb54ba
EI		 1761 for (i = 0; i < 32; i++) {
1762 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1763 if ((i + 1) % 4 == 0)
1764 cpu_fprintf(f, "\n");
1765 }
1766 cpu_fprintf(f, "\n\n");
1767}
1768
1769CPUState *cpu_mb_init (const char *cpu_model)
1770{
1771 CPUState *env;
1772 static int tcg_initialized = 0;
1773 int i;
1774
1775 env = qemu_mallocz(sizeof(CPUState));
1776
1777 cpu_exec_init(env);
1778 cpu_reset(env);
97694c57 1779 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
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EI		 1780
1781 if (tcg_initialized)
1782 return env;
1783
1784 tcg_initialized = 1;
1785
1786 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1787
1788 env_debug = tcg_global_mem_new(TCG_AREG0,
1789 offsetof(CPUState, debug),
1790 "debug0");
1791 env_iflags = tcg_global_mem_new(TCG_AREG0,
1792 offsetof(CPUState, iflags),
1793 "iflags");
1794 env_imm = tcg_global_mem_new(TCG_AREG0,
1795 offsetof(CPUState, imm),
1796 "imm");
1797 env_btarget = tcg_global_mem_new(TCG_AREG0,
1798 offsetof(CPUState, btarget),
1799 "btarget");
1800 env_btaken = tcg_global_mem_new(TCG_AREG0,
1801 offsetof(CPUState, btaken),
1802 "btaken");
1803 for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
1804 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
1805 offsetof(CPUState, regs[i]),
1806 regnames[i]);
1807 }
1808 for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) {
1809 cpu_SR[i] = tcg_global_mem_new(TCG_AREG0,
1810 offsetof(CPUState, sregs[i]),
1811 special_regnames[i]);
1812 }
1813#define GEN_HELPER 2
1814#include "helper.h"
1815
1816 return env;
1817}
1818
1819void cpu_reset (CPUState *env)
1820{
1821 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1822 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1823 log_cpu_state(env, 0);
1824 }
1825
1826 memset(env, 0, offsetof(CPUMBState, breakpoints));
1827 tlb_flush(env, 1);
1828
4898427e
EI		 1829 env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
1830 | PVR0_USE_BARREL_MASK \
1831 | PVR0_USE_DIV_MASK \
1832 | PVR0_USE_HW_MUL_MASK \
1833 | PVR0_USE_EXC_MASK \
1834 | PVR0_USE_ICACHE_MASK \
1835 | PVR0_USE_DCACHE_MASK \
1836 | PVR0_USE_MMU \
1837 | (0xb << 8);
1838 env->pvr.regs[2] = PVR2_D_OPB_MASK \
1839 | PVR2_D_LMB_MASK \
1840 | PVR2_I_OPB_MASK \
1841 | PVR2_I_LMB_MASK \
1842 | PVR2_USE_MSR_INSTR \
1843 | PVR2_USE_PCMP_INSTR \
1844 | PVR2_USE_BARREL_MASK \
1845 | PVR2_USE_DIV_MASK \
1846 | PVR2_USE_HW_MUL_MASK \
1847 | PVR2_USE_MUL64_MASK \
97694c57
EI		 1848 | PVR2_USE_FPU_MASK \
1849 | PVR2_USE_FPU2_MASK \
1850 | PVR2_FPU_EXC_MASK \
4898427e
EI		 1851 | 0;
1852 env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
1853 env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
1854
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EI		 1855#if defined(CONFIG_USER_ONLY)
1856 /* start in user mode with interrupts enabled. */
97694c57 1857 env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
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EI		 1858 env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */
1859#else
97694c57 1860 env->sregs[SR_MSR] = 0;
4acb54ba 1861 mmu_init(&env->mmu);
4898427e
EI		 1862 env->mmu.c_mmu = 3;
1863 env->mmu.c_mmu_tlb_access = 3;
1864 env->mmu.c_mmu_zones = 16;
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EI		 1865#endif
1866}
1867
1868void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
1869 unsigned long searched_pc, int pc_pos, void *puc)
1870{
1871 env->sregs[SR_PC] = gen_opc_pc[pc_pos];
1872}
Qemu copy for testing