]> git.proxmox.com Git - qemu.git/blame - target-mips/cpu.c
Merge git://github.com/hw-claudio/qemu-aarch64-queue into tcg-next
[qemu.git] / target-mips / cpu.c
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1/*
2 * QEMU MIPS CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20
21#include "cpu.h"
22#include "qemu-common.h"
23
24
25/* CPUClass::reset() */
26static void mips_cpu_reset(CPUState *s)
27{
28 MIPSCPU *cpu = MIPS_CPU(s);
29 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
30 CPUMIPSState *env = &cpu->env;
31
32 mcc->parent_reset(s);
33
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34 memset(env, 0, offsetof(CPUMIPSState, breakpoints));
35 tlb_flush(env, 1);
36
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37 cpu_state_reset(env);
38}
39
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40static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
41{
42 MIPSCPU *cpu = MIPS_CPU(dev);
43 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
44
45 cpu_reset(CPU(cpu));
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46
47 mcc->parent_realize(dev, errp);
48}
49
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50static void mips_cpu_initfn(Object *obj)
51{
c05efcb1 52 CPUState *cs = CPU(obj);
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53 MIPSCPU *cpu = MIPS_CPU(obj);
54 CPUMIPSState *env = &cpu->env;
55
c05efcb1 56 cs->env_ptr = env;
5b0c40f7 57 cpu_exec_init(env);
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58
59 if (tcg_enabled()) {
60 mips_tcg_init();
61 }
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62}
63
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64static void mips_cpu_class_init(ObjectClass *c, void *data)
65{
66 MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
67 CPUClass *cc = CPU_CLASS(c);
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68 DeviceClass *dc = DEVICE_CLASS(c);
69
70 mcc->parent_realize = dc->realize;
71 dc->realize = mips_cpu_realizefn;
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72
73 mcc->parent_reset = cc->reset;
74 cc->reset = mips_cpu_reset;
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75
76 cc->do_interrupt = mips_cpu_do_interrupt;
878096ee 77 cc->dump_state = mips_cpu_dump_state;
c658b94f 78 cpu_class_set_do_unassigned_access(cc, mips_cpu_unassigned_access);
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79}
80
81static const TypeInfo mips_cpu_type_info = {
82 .name = TYPE_MIPS_CPU,
83 .parent = TYPE_CPU,
84 .instance_size = sizeof(MIPSCPU),
5b0c40f7 85 .instance_init = mips_cpu_initfn,
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86 .abstract = false,
87 .class_size = sizeof(MIPSCPUClass),
88 .class_init = mips_cpu_class_init,
89};
90
91static void mips_cpu_register_types(void)
92{
93 type_register_static(&mips_cpu_type_info);
94}
95
96type_init(mips_cpu_register_types)