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0f71a709 AF |
1 | /* |
2 | * QEMU MIPS CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2.1 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see | |
18 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
19 | */ | |
20 | ||
21 | #include "cpu.h" | |
22 | #include "qemu-common.h" | |
23 | ||
24 | ||
f45748f1 AF |
25 | static void mips_cpu_set_pc(CPUState *cs, vaddr value) |
26 | { | |
27 | MIPSCPU *cpu = MIPS_CPU(cs); | |
28 | CPUMIPSState *env = &cpu->env; | |
29 | ||
30 | env->active_tc.PC = value & ~(target_ulong)1; | |
31 | if (value & 1) { | |
32 | env->hflags |= MIPS_HFLAG_M16; | |
33 | } else { | |
34 | env->hflags &= ~(MIPS_HFLAG_M16); | |
35 | } | |
36 | } | |
37 | ||
bdf7ae5b AF |
38 | static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) |
39 | { | |
40 | MIPSCPU *cpu = MIPS_CPU(cs); | |
41 | CPUMIPSState *env = &cpu->env; | |
42 | ||
43 | env->active_tc.PC = tb->pc; | |
44 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
45 | env->hflags |= tb->flags & MIPS_HFLAG_BMASK; | |
46 | } | |
47 | ||
0f71a709 AF |
48 | /* CPUClass::reset() */ |
49 | static void mips_cpu_reset(CPUState *s) | |
50 | { | |
51 | MIPSCPU *cpu = MIPS_CPU(s); | |
52 | MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu); | |
53 | CPUMIPSState *env = &cpu->env; | |
54 | ||
55 | mcc->parent_reset(s); | |
56 | ||
55e5c285 AF |
57 | memset(env, 0, offsetof(CPUMIPSState, breakpoints)); |
58 | tlb_flush(env, 1); | |
59 | ||
0f71a709 AF |
60 | cpu_state_reset(env); |
61 | } | |
62 | ||
c1caf1d9 AF |
63 | static void mips_cpu_realizefn(DeviceState *dev, Error **errp) |
64 | { | |
65 | MIPSCPU *cpu = MIPS_CPU(dev); | |
66 | MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev); | |
67 | ||
68 | cpu_reset(CPU(cpu)); | |
c1caf1d9 AF |
69 | |
70 | mcc->parent_realize(dev, errp); | |
71 | } | |
72 | ||
5b0c40f7 AF |
73 | static void mips_cpu_initfn(Object *obj) |
74 | { | |
c05efcb1 | 75 | CPUState *cs = CPU(obj); |
5b0c40f7 AF |
76 | MIPSCPU *cpu = MIPS_CPU(obj); |
77 | CPUMIPSState *env = &cpu->env; | |
78 | ||
c05efcb1 | 79 | cs->env_ptr = env; |
5b0c40f7 | 80 | cpu_exec_init(env); |
78ce64f4 AF |
81 | |
82 | if (tcg_enabled()) { | |
83 | mips_tcg_init(); | |
84 | } | |
5b0c40f7 AF |
85 | } |
86 | ||
0f71a709 AF |
87 | static void mips_cpu_class_init(ObjectClass *c, void *data) |
88 | { | |
89 | MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); | |
90 | CPUClass *cc = CPU_CLASS(c); | |
c1caf1d9 AF |
91 | DeviceClass *dc = DEVICE_CLASS(c); |
92 | ||
93 | mcc->parent_realize = dc->realize; | |
94 | dc->realize = mips_cpu_realizefn; | |
0f71a709 AF |
95 | |
96 | mcc->parent_reset = cc->reset; | |
97 | cc->reset = mips_cpu_reset; | |
97a8ea5a AF |
98 | |
99 | cc->do_interrupt = mips_cpu_do_interrupt; | |
878096ee | 100 | cc->dump_state = mips_cpu_dump_state; |
f45748f1 | 101 | cc->set_pc = mips_cpu_set_pc; |
bdf7ae5b | 102 | cc->synchronize_from_tb = mips_cpu_synchronize_from_tb; |
5b50e790 AF |
103 | cc->gdb_read_register = mips_cpu_gdb_read_register; |
104 | cc->gdb_write_register = mips_cpu_gdb_write_register; | |
00b941e5 AF |
105 | #ifndef CONFIG_USER_ONLY |
106 | cc->do_unassigned_access = mips_cpu_unassigned_access; | |
107 | cc->get_phys_page_debug = mips_cpu_get_phys_page_debug; | |
108 | #endif | |
a0e372f0 AF |
109 | |
110 | cc->gdb_num_core_regs = 73; | |
0f71a709 AF |
111 | } |
112 | ||
113 | static const TypeInfo mips_cpu_type_info = { | |
114 | .name = TYPE_MIPS_CPU, | |
115 | .parent = TYPE_CPU, | |
116 | .instance_size = sizeof(MIPSCPU), | |
5b0c40f7 | 117 | .instance_init = mips_cpu_initfn, |
0f71a709 AF |
118 | .abstract = false, |
119 | .class_size = sizeof(MIPSCPUClass), | |
120 | .class_init = mips_cpu_class_init, | |
121 | }; | |
122 | ||
123 | static void mips_cpu_register_types(void) | |
124 | { | |
125 | type_register_static(&mips_cpu_type_info); | |
126 | } | |
127 | ||
128 | type_init(mips_cpu_register_types) |