]> git.proxmox.com Git - qemu.git/blame - target-mips/cpu.h
pci: improve w1c mask handling
[qemu.git] / target-mips / cpu.h
CommitLineData
6af0bf9c
FB
1#if !defined (__MIPS_CPU_H__)
2#define __MIPS_CPU_H__
3
4ad40f36
FB
4#define TARGET_HAS_ICE 1
5
9042c0e2
TS
6#define ELF_MACHINE EM_MIPS
7
c2764719
PB
8#define CPUState struct CPUMIPSState
9
c5d6edc3 10#include "config.h"
6af0bf9c
FB
11#include "mips-defs.h"
12#include "cpu-defs.h"
6af0bf9c
FB
13#include "softfloat.h"
14
fdbb4691
FB
15// uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
16// XXX: move that elsewhere
dfe5fff3 17#if defined(CONFIG_SOLARIS) && CONFIG_SOLARIS_VERSION < 10
fdbb4691
FB
18typedef unsigned char uint_fast8_t;
19typedef unsigned int uint_fast16_t;
20#endif
21
ead9360e 22struct CPUMIPSState;
6af0bf9c 23
c227f099
AL
24typedef struct r4k_tlb_t r4k_tlb_t;
25struct r4k_tlb_t {
6af0bf9c 26 target_ulong VPN;
9c2149c8 27 uint32_t PageMask;
98c1b82b
PB
28 uint_fast8_t ASID;
29 uint_fast16_t G:1;
30 uint_fast16_t C0:3;
31 uint_fast16_t C1:3;
32 uint_fast16_t V0:1;
33 uint_fast16_t V1:1;
34 uint_fast16_t D0:1;
35 uint_fast16_t D1:1;
6af0bf9c
FB
36 target_ulong PFN[2];
37};
6af0bf9c 38
3c7b48b7 39#if !defined(CONFIG_USER_ONLY)
ead9360e
TS
40typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
41struct CPUMIPSTLBContext {
42 uint32_t nb_tlb;
43 uint32_t tlb_in_use;
60c9af07 44 int (*map_address) (struct CPUMIPSState *env, target_phys_addr_t *physical, int *prot, target_ulong address, int rw, int access_type);
c01fccd2
AJ
45 void (*helper_tlbwi) (void);
46 void (*helper_tlbwr) (void);
47 void (*helper_tlbp) (void);
48 void (*helper_tlbr) (void);
ead9360e
TS
49 union {
50 struct {
c227f099 51 r4k_tlb_t tlb[MIPS_TLB_MAX];
ead9360e
TS
52 } r4k;
53 } mmu;
54};
3c7b48b7 55#endif
51b2772f 56
c227f099
AL
57typedef union fpr_t fpr_t;
58union fpr_t {
ead9360e
TS
59 float64 fd; /* ieee double precision */
60 float32 fs[2];/* ieee single precision */
61 uint64_t d; /* binary double fixed-point */
62 uint32_t w[2]; /* binary single fixed-point */
63};
64/* define FP_ENDIAN_IDX to access the same location
65 * in the fpr_t union regardless of the host endianess
66 */
e2542fe2 67#if defined(HOST_WORDS_BIGENDIAN)
ead9360e
TS
68# define FP_ENDIAN_IDX 1
69#else
70# define FP_ENDIAN_IDX 0
c570fd16 71#endif
ead9360e
TS
72
73typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
74struct CPUMIPSFPUContext {
6af0bf9c 75 /* Floating point registers */
c227f099 76 fpr_t fpr[32];
6ea83fed 77 float_status fp_status;
5a5012ec 78 /* fpu implementation/revision register (fir) */
6af0bf9c 79 uint32_t fcr0;
5a5012ec
TS
80#define FCR0_F64 22
81#define FCR0_L 21
82#define FCR0_W 20
83#define FCR0_3D 19
84#define FCR0_PS 18
85#define FCR0_D 17
86#define FCR0_S 16
87#define FCR0_PRID 8
88#define FCR0_REV 0
6ea83fed
FB
89 /* fcsr */
90 uint32_t fcr31;
f01be154
TS
91#define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
92#define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
93#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
5a5012ec
TS
94#define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
95#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
96#define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
97#define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
98#define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
99#define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
100#define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
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101#define FP_INEXACT 1
102#define FP_UNDERFLOW 2
103#define FP_OVERFLOW 4
104#define FP_DIV0 8
105#define FP_INVALID 16
106#define FP_UNIMPLEMENTED 32
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TS
107};
108
623a930e 109#define NB_MMU_MODES 3
6ebbf390 110
ead9360e
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111typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
112struct CPUMIPSMVPContext {
113 int32_t CP0_MVPControl;
114#define CP0MVPCo_CPA 3
115#define CP0MVPCo_STLB 2
116#define CP0MVPCo_VPC 1
117#define CP0MVPCo_EVP 0
118 int32_t CP0_MVPConf0;
119#define CP0MVPC0_M 31
120#define CP0MVPC0_TLBS 29
121#define CP0MVPC0_GS 28
122#define CP0MVPC0_PCP 27
123#define CP0MVPC0_PTLBE 16
124#define CP0MVPC0_TCA 15
125#define CP0MVPC0_PVPE 10
126#define CP0MVPC0_PTC 0
127 int32_t CP0_MVPConf1;
128#define CP0MVPC1_CIM 31
129#define CP0MVPC1_CIF 30
130#define CP0MVPC1_PCX 20
131#define CP0MVPC1_PCP2 10
132#define CP0MVPC1_PCP1 0
133};
134
c227f099 135typedef struct mips_def_t mips_def_t;
ead9360e
TS
136
137#define MIPS_SHADOW_SET_MAX 16
138#define MIPS_TC_MAX 5
f01be154 139#define MIPS_FPU_MAX 1
ead9360e
TS
140#define MIPS_DSP_ACC 4
141
b5dc7732
TS
142typedef struct TCState TCState;
143struct TCState {
144 target_ulong gpr[32];
145 target_ulong PC;
146 target_ulong HI[MIPS_DSP_ACC];
147 target_ulong LO[MIPS_DSP_ACC];
148 target_ulong ACX[MIPS_DSP_ACC];
149 target_ulong DSPControl;
150 int32_t CP0_TCStatus;
151#define CP0TCSt_TCU3 31
152#define CP0TCSt_TCU2 30
153#define CP0TCSt_TCU1 29
154#define CP0TCSt_TCU0 28
155#define CP0TCSt_TMX 27
156#define CP0TCSt_RNST 23
157#define CP0TCSt_TDS 21
158#define CP0TCSt_DT 20
159#define CP0TCSt_DA 15
160#define CP0TCSt_A 13
161#define CP0TCSt_TKSU 11
162#define CP0TCSt_IXMT 10
163#define CP0TCSt_TASID 0
164 int32_t CP0_TCBind;
165#define CP0TCBd_CurTC 21
166#define CP0TCBd_TBE 17
167#define CP0TCBd_CurVPE 0
168 target_ulong CP0_TCHalt;
169 target_ulong CP0_TCContext;
170 target_ulong CP0_TCSchedule;
171 target_ulong CP0_TCScheFBack;
172 int32_t CP0_Debug_tcstatus;
173};
174
ead9360e
TS
175typedef struct CPUMIPSState CPUMIPSState;
176struct CPUMIPSState {
b5dc7732 177 TCState active_tc;
f01be154 178 CPUMIPSFPUContext active_fpu;
b5dc7732 179
ead9360e 180 uint32_t current_tc;
f01be154 181 uint32_t current_fpu;
36d23958 182
e034e2c3 183 uint32_t SEGBITS;
6d35524c 184 uint32_t PABITS;
b6d96bed 185 target_ulong SEGMask;
6d35524c 186 target_ulong PAMask;
29929e34 187
9c2149c8 188 int32_t CP0_Index;
ead9360e 189 /* CP0_MVP* are per MVP registers. */
9c2149c8 190 int32_t CP0_Random;
ead9360e
TS
191 int32_t CP0_VPEControl;
192#define CP0VPECo_YSI 21
193#define CP0VPECo_GSI 20
194#define CP0VPECo_EXCPT 16
195#define CP0VPECo_TE 15
196#define CP0VPECo_TargTC 0
197 int32_t CP0_VPEConf0;
198#define CP0VPEC0_M 31
199#define CP0VPEC0_XTC 21
200#define CP0VPEC0_TCS 19
201#define CP0VPEC0_SCS 18
202#define CP0VPEC0_DSC 17
203#define CP0VPEC0_ICS 16
204#define CP0VPEC0_MVP 1
205#define CP0VPEC0_VPA 0
206 int32_t CP0_VPEConf1;
207#define CP0VPEC1_NCX 20
208#define CP0VPEC1_NCP2 10
209#define CP0VPEC1_NCP1 0
210 target_ulong CP0_YQMask;
211 target_ulong CP0_VPESchedule;
212 target_ulong CP0_VPEScheFBack;
213 int32_t CP0_VPEOpt;
214#define CP0VPEOpt_IWX7 15
215#define CP0VPEOpt_IWX6 14
216#define CP0VPEOpt_IWX5 13
217#define CP0VPEOpt_IWX4 12
218#define CP0VPEOpt_IWX3 11
219#define CP0VPEOpt_IWX2 10
220#define CP0VPEOpt_IWX1 9
221#define CP0VPEOpt_IWX0 8
222#define CP0VPEOpt_DWX7 7
223#define CP0VPEOpt_DWX6 6
224#define CP0VPEOpt_DWX5 5
225#define CP0VPEOpt_DWX4 4
226#define CP0VPEOpt_DWX3 3
227#define CP0VPEOpt_DWX2 2
228#define CP0VPEOpt_DWX1 1
229#define CP0VPEOpt_DWX0 0
9c2149c8
TS
230 target_ulong CP0_EntryLo0;
231 target_ulong CP0_EntryLo1;
232 target_ulong CP0_Context;
233 int32_t CP0_PageMask;
234 int32_t CP0_PageGrain;
235 int32_t CP0_Wired;
ead9360e
TS
236 int32_t CP0_SRSConf0_rw_bitmask;
237 int32_t CP0_SRSConf0;
238#define CP0SRSC0_M 31
239#define CP0SRSC0_SRS3 20
240#define CP0SRSC0_SRS2 10
241#define CP0SRSC0_SRS1 0
242 int32_t CP0_SRSConf1_rw_bitmask;
243 int32_t CP0_SRSConf1;
244#define CP0SRSC1_M 31
245#define CP0SRSC1_SRS6 20
246#define CP0SRSC1_SRS5 10
247#define CP0SRSC1_SRS4 0
248 int32_t CP0_SRSConf2_rw_bitmask;
249 int32_t CP0_SRSConf2;
250#define CP0SRSC2_M 31
251#define CP0SRSC2_SRS9 20
252#define CP0SRSC2_SRS8 10
253#define CP0SRSC2_SRS7 0
254 int32_t CP0_SRSConf3_rw_bitmask;
255 int32_t CP0_SRSConf3;
256#define CP0SRSC3_M 31
257#define CP0SRSC3_SRS12 20
258#define CP0SRSC3_SRS11 10
259#define CP0SRSC3_SRS10 0
260 int32_t CP0_SRSConf4_rw_bitmask;
261 int32_t CP0_SRSConf4;
262#define CP0SRSC4_SRS15 20
263#define CP0SRSC4_SRS14 10
264#define CP0SRSC4_SRS13 0
9c2149c8 265 int32_t CP0_HWREna;
c570fd16 266 target_ulong CP0_BadVAddr;
9c2149c8
TS
267 int32_t CP0_Count;
268 target_ulong CP0_EntryHi;
269 int32_t CP0_Compare;
270 int32_t CP0_Status;
6af0bf9c
FB
271#define CP0St_CU3 31
272#define CP0St_CU2 30
273#define CP0St_CU1 29
274#define CP0St_CU0 28
275#define CP0St_RP 27
6ea83fed 276#define CP0St_FR 26
6af0bf9c 277#define CP0St_RE 25
7a387fff
TS
278#define CP0St_MX 24
279#define CP0St_PX 23
6af0bf9c
FB
280#define CP0St_BEV 22
281#define CP0St_TS 21
282#define CP0St_SR 20
283#define CP0St_NMI 19
284#define CP0St_IM 8
7a387fff
TS
285#define CP0St_KX 7
286#define CP0St_SX 6
287#define CP0St_UX 5
623a930e 288#define CP0St_KSU 3
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FB
289#define CP0St_ERL 2
290#define CP0St_EXL 1
291#define CP0St_IE 0
9c2149c8 292 int32_t CP0_IntCtl;
ead9360e
TS
293#define CP0IntCtl_IPTI 29
294#define CP0IntCtl_IPPC1 26
295#define CP0IntCtl_VS 5
9c2149c8 296 int32_t CP0_SRSCtl;
ead9360e
TS
297#define CP0SRSCtl_HSS 26
298#define CP0SRSCtl_EICSS 18
299#define CP0SRSCtl_ESS 12
300#define CP0SRSCtl_PSS 6
301#define CP0SRSCtl_CSS 0
9c2149c8 302 int32_t CP0_SRSMap;
ead9360e
TS
303#define CP0SRSMap_SSV7 28
304#define CP0SRSMap_SSV6 24
305#define CP0SRSMap_SSV5 20
306#define CP0SRSMap_SSV4 16
307#define CP0SRSMap_SSV3 12
308#define CP0SRSMap_SSV2 8
309#define CP0SRSMap_SSV1 4
310#define CP0SRSMap_SSV0 0
9c2149c8 311 int32_t CP0_Cause;
7a387fff
TS
312#define CP0Ca_BD 31
313#define CP0Ca_TI 30
314#define CP0Ca_CE 28
315#define CP0Ca_DC 27
316#define CP0Ca_PCI 26
6af0bf9c 317#define CP0Ca_IV 23
7a387fff
TS
318#define CP0Ca_WP 22
319#define CP0Ca_IP 8
4de9b249 320#define CP0Ca_IP_mask 0x0000FF00
7a387fff 321#define CP0Ca_EC 2
c570fd16 322 target_ulong CP0_EPC;
9c2149c8 323 int32_t CP0_PRid;
b29a0341 324 int32_t CP0_EBase;
9c2149c8 325 int32_t CP0_Config0;
6af0bf9c
FB
326#define CP0C0_M 31
327#define CP0C0_K23 28
328#define CP0C0_KU 25
329#define CP0C0_MDU 20
330#define CP0C0_MM 17
331#define CP0C0_BM 16
332#define CP0C0_BE 15
333#define CP0C0_AT 13
334#define CP0C0_AR 10
335#define CP0C0_MT 7
7a387fff 336#define CP0C0_VI 3
6af0bf9c 337#define CP0C0_K0 0
9c2149c8 338 int32_t CP0_Config1;
7a387fff 339#define CP0C1_M 31
6af0bf9c
FB
340#define CP0C1_MMU 25
341#define CP0C1_IS 22
342#define CP0C1_IL 19
343#define CP0C1_IA 16
344#define CP0C1_DS 13
345#define CP0C1_DL 10
346#define CP0C1_DA 7
7a387fff
TS
347#define CP0C1_C2 6
348#define CP0C1_MD 5
6af0bf9c
FB
349#define CP0C1_PC 4
350#define CP0C1_WR 3
351#define CP0C1_CA 2
352#define CP0C1_EP 1
353#define CP0C1_FP 0
9c2149c8 354 int32_t CP0_Config2;
7a387fff
TS
355#define CP0C2_M 31
356#define CP0C2_TU 28
357#define CP0C2_TS 24
358#define CP0C2_TL 20
359#define CP0C2_TA 16
360#define CP0C2_SU 12
361#define CP0C2_SS 8
362#define CP0C2_SL 4
363#define CP0C2_SA 0
9c2149c8 364 int32_t CP0_Config3;
7a387fff 365#define CP0C3_M 31
bbfa8f72 366#define CP0C3_ISA_ON_EXC 16
7a387fff
TS
367#define CP0C3_DSPP 10
368#define CP0C3_LPA 7
369#define CP0C3_VEIC 6
370#define CP0C3_VInt 5
371#define CP0C3_SP 4
372#define CP0C3_MT 2
373#define CP0C3_SM 1
374#define CP0C3_TL 0
e397ee33
TS
375 int32_t CP0_Config6;
376 int32_t CP0_Config7;
ead9360e 377 /* XXX: Maybe make LLAddr per-TC? */
5499b6ff 378 target_ulong lladdr;
590bc601
PB
379 target_ulong llval;
380 target_ulong llnewval;
381 target_ulong llreg;
2a6e32dd
AJ
382 target_ulong CP0_LLAddr_rw_bitmask;
383 int CP0_LLAddr_shift;
fd88b6ab
TS
384 target_ulong CP0_WatchLo[8];
385 int32_t CP0_WatchHi[8];
9c2149c8
TS
386 target_ulong CP0_XContext;
387 int32_t CP0_Framemask;
388 int32_t CP0_Debug;
ead9360e 389#define CP0DB_DBD 31
6af0bf9c
FB
390#define CP0DB_DM 30
391#define CP0DB_LSNM 28
392#define CP0DB_Doze 27
393#define CP0DB_Halt 26
394#define CP0DB_CNT 25
395#define CP0DB_IBEP 24
396#define CP0DB_DBEP 21
397#define CP0DB_IEXI 20
398#define CP0DB_VER 15
399#define CP0DB_DEC 10
400#define CP0DB_SSt 8
401#define CP0DB_DINT 5
402#define CP0DB_DIB 4
403#define CP0DB_DDBS 3
404#define CP0DB_DDBL 2
405#define CP0DB_DBp 1
406#define CP0DB_DSS 0
c570fd16 407 target_ulong CP0_DEPC;
9c2149c8
TS
408 int32_t CP0_Performance0;
409 int32_t CP0_TagLo;
410 int32_t CP0_DataLo;
411 int32_t CP0_TagHi;
412 int32_t CP0_DataHi;
c570fd16 413 target_ulong CP0_ErrorEPC;
9c2149c8 414 int32_t CP0_DESAVE;
b5dc7732
TS
415 /* We waste some space so we can handle shadow registers like TCs. */
416 TCState tcs[MIPS_SHADOW_SET_MAX];
f01be154 417 CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
6af0bf9c 418 /* Qemu */
6af0bf9c 419 int error_code;
6af0bf9c
FB
420 uint32_t hflags; /* CPU State */
421 /* TMASK defines different execution modes */
79ef2c4c
NF
422#define MIPS_HFLAG_TMASK 0x007FF
423#define MIPS_HFLAG_MODE 0x00007 /* execution modes */
623a930e
TS
424 /* The KSU flags must be the lowest bits in hflags. The flag order
425 must be the same as defined for CP0 Status. This allows to use
426 the bits as the value of mmu_idx. */
79ef2c4c
NF
427#define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */
428#define MIPS_HFLAG_UM 0x00002 /* user mode flag */
429#define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */
430#define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */
431#define MIPS_HFLAG_DM 0x00004 /* Debug mode */
432#define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */
433#define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */
434#define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */
435#define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */
b8aa4598
TS
436 /* True if the MIPS IV COP1X instructions can be used. This also
437 controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
438 and RSQRT.D. */
79ef2c4c
NF
439#define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */
440#define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */
441#define MIPS_HFLAG_UX 0x00200 /* 64-bit user mode */
442#define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */
443#define MIPS_HFLAG_M16_SHIFT 10
4ad40f36
FB
444 /* If translation is interrupted between the branch instruction and
445 * the delay slot, record what type of branch it is so that we can
446 * resume translation properly. It might be possible to reduce
447 * this from three bits to two. */
79ef2c4c
NF
448#define MIPS_HFLAG_BMASK_BASE 0x03800
449#define MIPS_HFLAG_B 0x00800 /* Unconditional branch */
450#define MIPS_HFLAG_BC 0x01000 /* Conditional branch */
451#define MIPS_HFLAG_BL 0x01800 /* Likely branch */
452#define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */
453 /* Extra flags about the current pending branch. */
454#define MIPS_HFLAG_BMASK_EXT 0x3C000
455#define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */
456#define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */
457#define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */
458#define MIPS_HFLAG_BX 0x20000 /* branch exchanges execution mode */
459#define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
6af0bf9c 460 target_ulong btarget; /* Jump / branch target */
1ba74fb8 461 target_ulong bcond; /* Branch condition (if needed) */
a316d335 462
7a387fff
TS
463 int SYNCI_Step; /* Address step size for SYNCI */
464 int CCRes; /* Cycle count resolution/divisor */
ead9360e
TS
465 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
466 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
e189e748 467 int insn_flags; /* Supported instruction set */
7a387fff 468
0eaef5aa 469 target_ulong tls_value; /* For usermode emulation */
6f5b89a0 470
a316d335 471 CPU_COMMON
6ae81775 472
51cc2e78 473 CPUMIPSMVPContext *mvp;
3c7b48b7 474#if !defined(CONFIG_USER_ONLY)
51cc2e78 475 CPUMIPSTLBContext *tlb;
3c7b48b7 476#endif
51cc2e78 477
c227f099 478 const mips_def_t *cpu_model;
33ac7f16 479 void *irq[8];
6ae81775 480 struct QEMUTimer *timer; /* Internal timer */
6af0bf9c
FB
481};
482
3c7b48b7 483#if !defined(CONFIG_USER_ONLY)
60c9af07 484int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
29929e34 485 target_ulong address, int rw, int access_type);
60c9af07 486int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
29929e34 487 target_ulong address, int rw, int access_type);
60c9af07 488int r4k_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
29929e34 489 target_ulong address, int rw, int access_type);
c01fccd2
AJ
490void r4k_helper_tlbwi (void);
491void r4k_helper_tlbwr (void);
492void r4k_helper_tlbp (void);
493void r4k_helper_tlbr (void);
33d68b5f 494
c227f099 495void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
e18231a3 496 int unused, int size);
3c7b48b7
PB
497#endif
498
499void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
647de6ca 500
9467d44c
TS
501#define cpu_init cpu_mips_init
502#define cpu_exec cpu_mips_exec
503#define cpu_gen_code cpu_mips_gen_code
504#define cpu_signal_handler cpu_mips_signal_handler
c732abe2 505#define cpu_list mips_cpu_list
9467d44c 506
b3c7724c
PB
507#define CPU_SAVE_VERSION 3
508
623a930e
TS
509/* MMU modes definitions. We carefully match the indices with our
510 hflags layout. */
6ebbf390 511#define MMU_MODE0_SUFFIX _kernel
623a930e
TS
512#define MMU_MODE1_SUFFIX _super
513#define MMU_MODE2_SUFFIX _user
514#define MMU_USER_IDX 2
6ebbf390
JM
515static inline int cpu_mmu_index (CPUState *env)
516{
623a930e 517 return env->hflags & MIPS_HFLAG_KSU;
6ebbf390
JM
518}
519
6e68e076
PB
520static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
521{
f8ed7070 522 if (newsp)
b5dc7732
TS
523 env->active_tc.gpr[29] = newsp;
524 env->active_tc.gpr[7] = 0;
525 env->active_tc.gpr[2] = 0;
6e68e076 526}
6e68e076 527
6af0bf9c
FB
528#include "cpu-all.h"
529
530/* Memory access type :
531 * may be needed for precise access rights control and precise exceptions.
532 */
533enum {
534 /* 1 bit to define user level / supervisor access */
535 ACCESS_USER = 0x00,
536 ACCESS_SUPER = 0x01,
537 /* 1 bit to indicate direction */
538 ACCESS_STORE = 0x02,
539 /* Type of instruction that generated the access */
540 ACCESS_CODE = 0x10, /* Code fetch access */
541 ACCESS_INT = 0x20, /* Integer load/store access */
542 ACCESS_FLOAT = 0x30, /* floating point load/store access */
543};
544
545/* Exceptions */
546enum {
547 EXCP_NONE = -1,
548 EXCP_RESET = 0,
549 EXCP_SRESET,
550 EXCP_DSS,
551 EXCP_DINT,
14e51cc7
TS
552 EXCP_DDBL,
553 EXCP_DDBS,
6af0bf9c
FB
554 EXCP_NMI,
555 EXCP_MCHECK,
14e51cc7 556 EXCP_EXT_INTERRUPT, /* 8 */
6af0bf9c 557 EXCP_DFWATCH,
14e51cc7 558 EXCP_DIB,
6af0bf9c
FB
559 EXCP_IWATCH,
560 EXCP_AdEL,
561 EXCP_AdES,
562 EXCP_TLBF,
563 EXCP_IBE,
14e51cc7 564 EXCP_DBp, /* 16 */
6af0bf9c 565 EXCP_SYSCALL,
14e51cc7 566 EXCP_BREAK,
4ad40f36 567 EXCP_CpU,
6af0bf9c
FB
568 EXCP_RI,
569 EXCP_OVERFLOW,
570 EXCP_TRAP,
5a5012ec 571 EXCP_FPE,
14e51cc7 572 EXCP_DWATCH, /* 24 */
6af0bf9c
FB
573 EXCP_LTLBL,
574 EXCP_TLBL,
575 EXCP_TLBS,
576 EXCP_DBE,
ead9360e 577 EXCP_THREAD,
14e51cc7
TS
578 EXCP_MDMX,
579 EXCP_C2E,
580 EXCP_CACHE, /* 32 */
581
582 EXCP_LAST = EXCP_CACHE,
6af0bf9c 583};
590bc601
PB
584/* Dummy exception for conditional stores. */
585#define EXCP_SC 0x100
6af0bf9c 586
6af0bf9c 587int cpu_mips_exec(CPUMIPSState *s);
aaed909a 588CPUMIPSState *cpu_mips_init(const char *cpu_model);
f9480ffc 589//~ uint32_t cpu_mips_get_clock (void);
388bb21a 590int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
6af0bf9c 591
f9480ffc
TS
592/* mips_timer.c */
593uint32_t cpu_mips_get_random (CPUState *env);
594uint32_t cpu_mips_get_count (CPUState *env);
595void cpu_mips_store_count (CPUState *env, uint32_t value);
596void cpu_mips_store_compare (CPUState *env, uint32_t value);
597void cpu_mips_start_count(CPUState *env);
598void cpu_mips_stop_count(CPUState *env);
599
600/* mips_int.c */
601void cpu_mips_update_irq (CPUState *env);
602
603/* helper.c */
604int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
605 int mmu_idx, int is_softmmu);
0b5c1ce8 606#define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
f9480ffc 607void do_interrupt (CPUState *env);
3c7b48b7 608#if !defined(CONFIG_USER_ONLY)
f9480ffc 609void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);
c36bbb28
AJ
610target_phys_addr_t cpu_mips_translate_address (CPUState *env, target_ulong address,
611 int rw);
3c7b48b7 612#endif
f9480ffc 613
6b917547
AL
614static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
615 target_ulong *cs_base, int *flags)
616{
617 *pc = env->active_tc.PC;
618 *cs_base = 0;
619 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
620}
621
ff867ddc
PB
622static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
623{
624 env->tls_value = newtls;
625}
626
6af0bf9c 627#endif /* !defined (__MIPS_CPU_H__) */