[qemu.git] / target-mips / cpu.h

#if !defined (__MIPS_CPU_H__)
#define __MIPS_CPU_H__

#define TARGET_HAS_ICE 1

#include "config.h"
#include "mips-defs.h"
#include "cpu-defs.h"
#include "softfloat.h"

// uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
// XXX: move that elsewhere
#if defined(HOST_SOLARIS) && SOLARISREV < 10
typedef unsigned char           uint_fast8_t;
typedef unsigned int            uint_fast16_t;
#endif

typedef union fpr_t fpr_t;
union fpr_t {
    float64  fd;   /* ieee double precision */
    float32  fs[2];/* ieee single precision */
    uint64_t d;    /* binary single fixed-point */
    uint32_t w[2]; /* binary single fixed-point */
};
/* define FP_ENDIAN_IDX to access the same location
 * in the fpr_t union regardless of the host endianess
 */
#if defined(WORDS_BIGENDIAN)
#  define FP_ENDIAN_IDX 1
#else
#  define FP_ENDIAN_IDX 0
#endif

#if defined(MIPS_USES_R4K_TLB)
typedef struct tlb_t tlb_t;
struct tlb_t {
    target_ulong VPN;
    target_ulong end;
    target_ulong end2;
    uint_fast8_t ASID;
    uint_fast16_t G:1;
    uint_fast16_t C0:3;
    uint_fast16_t C1:3;
    uint_fast16_t V0:1;
    uint_fast16_t V1:1;
    uint_fast16_t D0:1;
    uint_fast16_t D1:1;
    target_ulong PFN[2];
};
#endif

typedef struct CPUMIPSState CPUMIPSState;
struct CPUMIPSState {
    /* General integer registers */
    target_ulong gpr[32];
    /* Special registers */
    target_ulong PC;
    uint32_t HI, LO;
    uint32_t DCR; /* ? */
#if defined(MIPS_USES_FPU)
    /* Floating point registers */
    fpr_t fpr[16];
#define FPR(cpu, n) ((fpr_t*)&(cpu)->fpr[(n) / 2])
#define FPR_FD(cpu, n) (FPR(cpu, n)->fd)
#define FPR_FS(cpu, n) (FPR(cpu, n)->fs[((n) & 1) ^ FP_ENDIAN_IDX])
#define FPR_D(cpu, n)  (FPR(cpu, n)->d)
#define FPR_W(cpu, n)  (FPR(cpu, n)->w[((n) & 1) ^ FP_ENDIAN_IDX])

#ifndef USE_HOST_FLOAT_REGS
    fpr_t ft0;
    fpr_t ft1;
    fpr_t ft2;
#endif
    float_status fp_status;
    /* fpu implementation/revision register */
    uint32_t fcr0;
    /* fcsr */
    uint32_t fcr31;
#define SET_FP_COND(reg)     do { (reg) |= (1<<23); } while(0)
#define CLEAR_FP_COND(reg)   do { (reg) &= ~(1<<23); } while(0)
#define IS_FP_COND_SET(reg)  (((reg) & (1<<23)) != 0)
#define GET_FP_CAUSE(reg)    (((reg) >> 12) & 0x3f)
#define GET_FP_ENABLE(reg)   (((reg) >>  7) & 0x1f)
#define GET_FP_FLAGS(reg)    (((reg) >>  2) & 0x1f)
#define SET_FP_CAUSE(reg,v)  do { (reg) = ((reg) & ~(0x3f << 12)) | ((v) << 12); } while(0)
#define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v) << 7); } while(0)
#define SET_FP_FLAGS(reg,v)  do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v) << 2); } while(0)
#define FP_INEXACT        1
#define FP_UNDERFLOW      2
#define FP_OVERFLOW       4
#define FP_DIV0           8
#define FP_INVALID        16
#define FP_UNIMPLEMENTED  32
		
#endif
#if defined(MIPS_USES_R4K_TLB)
    tlb_t tlb[MIPS_TLB_MAX];
    uint32_t tlb_in_use;
#endif
    uint32_t CP0_index;
    uint32_t CP0_random;
    uint32_t CP0_EntryLo0;
    uint32_t CP0_EntryLo1;
    uint32_t CP0_Context;
    uint32_t CP0_PageMask;
    uint32_t CP0_Wired;
    uint32_t CP0_BadVAddr;
    uint32_t CP0_Count;
    uint32_t CP0_EntryHi;
    uint32_t CP0_Compare;
    uint32_t CP0_Status;
#define CP0St_CU3   31
#define CP0St_CU2   30
#define CP0St_CU1   29
#define CP0St_CU0   28
#define CP0St_RP    27
#define CP0St_FR    26
#define CP0St_RE    25
#define CP0St_BEV   22
#define CP0St_TS    21
#define CP0St_SR    20
#define CP0St_NMI   19
#define CP0St_IM    8
#define CP0St_UM    4
#define CP0St_ERL   2
#define CP0St_EXL   1
#define CP0St_IE    0
    uint32_t CP0_Cause;
#define CP0Ca_IV   23
    uint32_t CP0_EPC;
    uint32_t CP0_PRid;
    uint32_t CP0_Config0;
#define CP0C0_M    31
#define CP0C0_K23  28
#define CP0C0_KU   25
#define CP0C0_MDU  20
#define CP0C0_MM   17
#define CP0C0_BM   16
#define CP0C0_BE   15
#define CP0C0_AT   13
#define CP0C0_AR   10
#define CP0C0_MT   7
#define CP0C0_K0   0
    uint32_t CP0_Config1;
#define CP0C1_MMU  25
#define CP0C1_IS   22
#define CP0C1_IL   19
#define CP0C1_IA   16
#define CP0C1_DS   13
#define CP0C1_DL   10
#define CP0C1_DA   7
#define CP0C1_PC   4
#define CP0C1_WR   3
#define CP0C1_CA   2
#define CP0C1_EP   1
#define CP0C1_FP   0
    uint32_t CP0_LLAddr;
    uint32_t CP0_WatchLo;
    uint32_t CP0_WatchHi;
    uint32_t CP0_Debug;
#define CPDB_DBD   31
#define CP0DB_DM   30
#define CP0DB_LSNM 28
#define CP0DB_Doze 27
#define CP0DB_Halt 26
#define CP0DB_CNT  25
#define CP0DB_IBEP 24
#define CP0DB_DBEP 21
#define CP0DB_IEXI 20
#define CP0DB_VER  15
#define CP0DB_DEC  10
#define CP0DB_SSt  8
#define CP0DB_DINT 5
#define CP0DB_DIB  4
#define CP0DB_DDBS 3
#define CP0DB_DDBL 2
#define CP0DB_DBp  1
#define CP0DB_DSS  0
    uint32_t CP0_DEPC;
    uint32_t CP0_TagLo;
    uint32_t CP0_DataLo;
    uint32_t CP0_ErrorEPC;
    uint32_t CP0_DESAVE;
    /* Qemu */
    struct QEMUTimer *timer; /* Internal timer */
    int interrupt_request;
    jmp_buf jmp_env;
    int exception_index;
    int error_code;
    int user_mode_only; /* user mode only simulation */
    uint32_t hflags;    /* CPU State */
    /* TMASK defines different execution modes */
#define MIPS_HFLAG_TMASK  0x007F
#define MIPS_HFLAG_MODE   0x001F /* execution modes                    */
#define MIPS_HFLAG_UM     0x0001 /* user mode                          */
#define MIPS_HFLAG_ERL    0x0002 /* Error mode                         */
#define MIPS_HFLAG_EXL    0x0004 /* Exception mode                     */
#define MIPS_HFLAG_DM     0x0008 /* Debug mode                         */
#define MIPS_HFLAG_SM     0x0010 /* Supervisor mode                    */
#define MIPS_HFLAG_RE     0x0040 /* Reversed endianness                */
    /* If translation is interrupted between the branch instruction and
     * the delay slot, record what type of branch it is so that we can
     * resume translation properly.  It might be possible to reduce
     * this from three bits to two.  */
#define MIPS_HFLAG_BMASK  0x0380
#define MIPS_HFLAG_B      0x0080 /* Unconditional branch               */
#define MIPS_HFLAG_BC     0x0100 /* Conditional branch                 */
#define MIPS_HFLAG_BL     0x0180 /* Likely branch                      */
#define MIPS_HFLAG_BR     0x0200 /* branch to register (can't link TB) */
    target_ulong btarget;        /* Jump / branch target               */
    int bcond;                   /* Branch condition (if needed)       */

    int halted; /* TRUE if the CPU is in suspend state */

    CPU_COMMON
};

#include "cpu-all.h"

/* Memory access type :
 * may be needed for precise access rights control and precise exceptions.
 */
enum {
    /* 1 bit to define user level / supervisor access */
    ACCESS_USER  = 0x00,
    ACCESS_SUPER = 0x01,
    /* 1 bit to indicate direction */
    ACCESS_STORE = 0x02,
    /* Type of instruction that generated the access */
    ACCESS_CODE  = 0x10, /* Code fetch access                */
    ACCESS_INT   = 0x20, /* Integer load/store access        */
    ACCESS_FLOAT = 0x30, /* floating point load/store access */
};

/* Exceptions */
enum {
    EXCP_NONE          = -1,
    EXCP_RESET         = 0,
    EXCP_SRESET,
    EXCP_DSS,
    EXCP_DINT,
    EXCP_NMI,
    EXCP_MCHECK,
    EXCP_EXT_INTERRUPT,
    EXCP_DFWATCH,
    EXCP_DIB, /* 8 */
    EXCP_IWATCH,
    EXCP_AdEL,
    EXCP_AdES,
    EXCP_TLBF,
    EXCP_IBE,
    EXCP_DBp,
    EXCP_SYSCALL,
    EXCP_BREAK, /* 16 */
    EXCP_CpU,
    EXCP_RI,
    EXCP_OVERFLOW,
    EXCP_TRAP,
    EXCP_DDBS,
    EXCP_DWATCH,
    EXCP_LAE,
    EXCP_SAE, /* 24 */
    EXCP_LTLBL,
    EXCP_TLBL,
    EXCP_TLBS,
    EXCP_DBE,
    EXCP_DDBL,
    EXCP_MTCP0         = 0x104, /* mtmsr instruction:               */
                                /* may change privilege level       */
    EXCP_BRANCH        = 0x108, /* branch instruction               */
    EXCP_ERET          = 0x10C, /* return from interrupt            */
    EXCP_SYSCALL_USER  = 0x110, /* System call in user mode only    */
    EXCP_FLUSH         = 0x109,
};

int cpu_mips_exec(CPUMIPSState *s);
CPUMIPSState *cpu_mips_init(void);
uint32_t cpu_mips_get_clock (void);

#endif /* !defined (__MIPS_CPU_H__) */
Commit	Line	Data
6af0bf9c FB	1	#if !defined (__MIPS_CPU_H__)
	2	#define __MIPS_CPU_H__
	3
4ad40f36 FB	4	#define TARGET_HAS_ICE 1
4ad40f36 FB	5
c5d6edc3	6	#include "config.h"
6af0bf9c FB	7	#include "mips-defs.h"
6af0bf9c FB	8	#include "cpu-defs.h"
6af0bf9c FB	9	#include "softfloat.h"
6af0bf9c FB	10
fdbb4691 FB	11	// uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
	12	// XXX: move that elsewhere
	13	#if defined(HOST_SOLARIS) && SOLARISREV < 10
	14	typedef unsigned char uint_fast8_t;
	15	typedef unsigned int uint_fast16_t;
	16	#endif
	17
6af0bf9c FB	18	typedef union fpr_t fpr_t;
6af0bf9c FB	19	union fpr_t {
6ea83fed FB	20	float64 fd; /* ieee double precision */
	21	float32 fs[2];/* ieee single precision */
	22	uint64_t d; /* binary single fixed-point */
	23	uint32_t w[2]; /* binary single fixed-point */
6af0bf9c	24	};
6ea83fed FB	25	/* define FP_ENDIAN_IDX to access the same location
	26	* in the fpr_t union regardless of the host endianess
	27	*/
	28	#if defined(WORDS_BIGENDIAN)
	29	# define FP_ENDIAN_IDX 1
	30	#else
	31	# define FP_ENDIAN_IDX 0
	32	#endif
6af0bf9c FB	33
	34	#if defined(MIPS_USES_R4K_TLB)
	35	typedef struct tlb_t tlb_t;
	36	struct tlb_t {
	37	target_ulong VPN;
	38	target_ulong end;
4ad40f36	39	target_ulong end2;
98c1b82b PB	40	uint_fast8_t ASID;
	41	uint_fast16_t G:1;
	42	uint_fast16_t C0:3;
	43	uint_fast16_t C1:3;
	44	uint_fast16_t V0:1;
	45	uint_fast16_t V1:1;
	46	uint_fast16_t D0:1;
	47	uint_fast16_t D1:1;
6af0bf9c FB	48	target_ulong PFN[2];
	49	};
	50	#endif
	51
	52	typedef struct CPUMIPSState CPUMIPSState;
	53	struct CPUMIPSState {
	54	/* General integer registers */
	55	target_ulong gpr[32];
	56	/* Special registers */
	57	target_ulong PC;
	58	uint32_t HI, LO;
	59	uint32_t DCR; /* ? */
	60	#if defined(MIPS_USES_FPU)
	61	/* Floating point registers */
	62	fpr_t fpr[16];
6ea83fed FB	63	#define FPR(cpu, n) ((fpr_t*)&(cpu)->fpr[(n) / 2])
	64	#define FPR_FD(cpu, n) (FPR(cpu, n)->fd)
	65	#define FPR_FS(cpu, n) (FPR(cpu, n)->fs[((n) & 1) ^ FP_ENDIAN_IDX])
	66	#define FPR_D(cpu, n) (FPR(cpu, n)->d)
	67	#define FPR_W(cpu, n) (FPR(cpu, n)->w[((n) & 1) ^ FP_ENDIAN_IDX])
	68
	69	#ifndef USE_HOST_FLOAT_REGS
	70	fpr_t ft0;
	71	fpr_t ft1;
	72	fpr_t ft2;
	73	#endif
	74	float_status fp_status;
	75	/* fpu implementation/revision register */
6af0bf9c	76	uint32_t fcr0;
6ea83fed FB	77	/* fcsr */
	78	uint32_t fcr31;
	79	#define SET_FP_COND(reg) do { (reg) \|= (1<<23); } while(0)
	80	#define CLEAR_FP_COND(reg) do { (reg) &= ~(1<<23); } while(0)
	81	#define IS_FP_COND_SET(reg) (((reg) & (1<<23)) != 0)
	82	#define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
	83	#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
	84	#define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
	85	#define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) \| ((v) << 12); } while(0)
	86	#define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) \| ((v) << 7); } while(0)
	87	#define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) \| ((v) << 2); } while(0)
	88	#define FP_INEXACT 1
	89	#define FP_UNDERFLOW 2
	90	#define FP_OVERFLOW 4
	91	#define FP_DIV0 8
	92	#define FP_INVALID 16
	93	#define FP_UNIMPLEMENTED 32
	94
6af0bf9c FB	95	#endif
6af0bf9c FB	96	#if defined(MIPS_USES_R4K_TLB)
814b9a47 TS	97	tlb_t tlb[MIPS_TLB_MAX];
814b9a47 TS	98	uint32_t tlb_in_use;
6af0bf9c FB	99	#endif
	100	uint32_t CP0_index;
	101	uint32_t CP0_random;
	102	uint32_t CP0_EntryLo0;
	103	uint32_t CP0_EntryLo1;
	104	uint32_t CP0_Context;
	105	uint32_t CP0_PageMask;
	106	uint32_t CP0_Wired;
	107	uint32_t CP0_BadVAddr;
	108	uint32_t CP0_Count;
	109	uint32_t CP0_EntryHi;
	110	uint32_t CP0_Compare;
	111	uint32_t CP0_Status;
	112	#define CP0St_CU3 31
	113	#define CP0St_CU2 30
	114	#define CP0St_CU1 29
	115	#define CP0St_CU0 28
	116	#define CP0St_RP 27
6ea83fed	117	#define CP0St_FR 26
6af0bf9c FB	118	#define CP0St_RE 25
	119	#define CP0St_BEV 22
	120	#define CP0St_TS 21
	121	#define CP0St_SR 20
	122	#define CP0St_NMI 19
	123	#define CP0St_IM 8
	124	#define CP0St_UM 4
	125	#define CP0St_ERL 2
	126	#define CP0St_EXL 1
	127	#define CP0St_IE 0
	128	uint32_t CP0_Cause;
	129	#define CP0Ca_IV 23
	130	uint32_t CP0_EPC;
	131	uint32_t CP0_PRid;
	132	uint32_t CP0_Config0;
	133	#define CP0C0_M 31
	134	#define CP0C0_K23 28
	135	#define CP0C0_KU 25
	136	#define CP0C0_MDU 20
	137	#define CP0C0_MM 17
	138	#define CP0C0_BM 16
	139	#define CP0C0_BE 15
	140	#define CP0C0_AT 13
	141	#define CP0C0_AR 10
	142	#define CP0C0_MT 7
	143	#define CP0C0_K0 0
	144	uint32_t CP0_Config1;
	145	#define CP0C1_MMU 25
	146	#define CP0C1_IS 22
	147	#define CP0C1_IL 19
	148	#define CP0C1_IA 16
	149	#define CP0C1_DS 13
	150	#define CP0C1_DL 10
	151	#define CP0C1_DA 7
	152	#define CP0C1_PC 4
	153	#define CP0C1_WR 3
	154	#define CP0C1_CA 2
	155	#define CP0C1_EP 1
	156	#define CP0C1_FP 0
	157	uint32_t CP0_LLAddr;
	158	uint32_t CP0_WatchLo;
	159	uint32_t CP0_WatchHi;
	160	uint32_t CP0_Debug;
	161	#define CPDB_DBD 31
	162	#define CP0DB_DM 30
	163	#define CP0DB_LSNM 28
	164	#define CP0DB_Doze 27
	165	#define CP0DB_Halt 26
	166	#define CP0DB_CNT 25
	167	#define CP0DB_IBEP 24
	168	#define CP0DB_DBEP 21
	169	#define CP0DB_IEXI 20
	170	#define CP0DB_VER 15
	171	#define CP0DB_DEC 10
	172	#define CP0DB_SSt 8
	173	#define CP0DB_DINT 5
	174	#define CP0DB_DIB 4
	175	#define CP0DB_DDBS 3
	176	#define CP0DB_DDBL 2
	177	#define CP0DB_DBp 1
	178	#define CP0DB_DSS 0
	179	uint32_t CP0_DEPC;
	180	uint32_t CP0_TagLo;
	181	uint32_t CP0_DataLo;
182	uint32_t CP0_ErrorEPC;
183	uint32_t CP0_DESAVE;
184	/* Qemu */
6af0bf9c FB	185	struct QEMUTimer timer; / Internal timer */
	186	int interrupt_request;
	187	jmp_buf jmp_env;
	188	int exception_index;
	189	int error_code;
	190	int user_mode_only; /* user mode only simulation */
	191	uint32_t hflags; /* CPU State */
	192	/* TMASK defines different execution modes */
56b19403	193	#define MIPS_HFLAG_TMASK 0x007F
6af0bf9c FB	194	#define MIPS_HFLAG_MODE 0x001F /* execution modes */
	195	#define MIPS_HFLAG_UM 0x0001 /* user mode */
	196	#define MIPS_HFLAG_ERL 0x0002 /* Error mode */
	197	#define MIPS_HFLAG_EXL 0x0004 /* Exception mode */
	198	#define MIPS_HFLAG_DM 0x0008 /* Debug mode */
	199	#define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */
	200	#define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */
4ad40f36 FB	201	/* If translation is interrupted between the branch instruction and
	202	* the delay slot, record what type of branch it is so that we can
	203	* resume translation properly. It might be possible to reduce
	204	* this from three bits to two. */
	205	#define MIPS_HFLAG_BMASK 0x0380
	206	#define MIPS_HFLAG_B 0x0080 /* Unconditional branch */
	207	#define MIPS_HFLAG_BC 0x0100 /* Conditional branch */
	208	#define MIPS_HFLAG_BL 0x0180 /* Likely branch */
	209	#define MIPS_HFLAG_BR 0x0200 /* branch to register (can't link TB) */
6af0bf9c FB	210	target_ulong btarget; /* Jump / branch target */
6af0bf9c FB	211	int bcond; /* Branch condition (if needed) */
a316d335	212
4ad40f36 FB	213	int halted; /* TRUE if the CPU is in suspend state */
4ad40f36 FB	214
a316d335	215	CPU_COMMON
6af0bf9c FB	216	};
	217
	218	#include "cpu-all.h"
	219
	220	/* Memory access type :
	221	* may be needed for precise access rights control and precise exceptions.
	222	*/
	223	enum {
	224	/* 1 bit to define user level / supervisor access */
	225	ACCESS_USER = 0x00,
	226	ACCESS_SUPER = 0x01,
	227	/* 1 bit to indicate direction */
	228	ACCESS_STORE = 0x02,
	229	/* Type of instruction that generated the access */
	230	ACCESS_CODE = 0x10, /* Code fetch access */
	231	ACCESS_INT = 0x20, /* Integer load/store access */
	232	ACCESS_FLOAT = 0x30, /* floating point load/store access */
	233	};
	234
	235	/* Exceptions */
	236	enum {
	237	EXCP_NONE = -1,
	238	EXCP_RESET = 0,
	239	EXCP_SRESET,
	240	EXCP_DSS,
	241	EXCP_DINT,
	242	EXCP_NMI,
	243	EXCP_MCHECK,
	244	EXCP_EXT_INTERRUPT,
	245	EXCP_DFWATCH,
	246	EXCP_DIB, /* 8 */
	247	EXCP_IWATCH,
	248	EXCP_AdEL,
	249	EXCP_AdES,
	250	EXCP_TLBF,
	251	EXCP_IBE,
	252	EXCP_DBp,
	253	EXCP_SYSCALL,
4ad40f36 FB	254	EXCP_BREAK, /* 16 */
4ad40f36 FB	255	EXCP_CpU,
6af0bf9c FB	256	EXCP_RI,
	257	EXCP_OVERFLOW,
	258	EXCP_TRAP,
	259	EXCP_DDBS,
	260	EXCP_DWATCH,
4ad40f36 FB	261	EXCP_LAE,
4ad40f36 FB	262	EXCP_SAE, /* 24 */
6af0bf9c FB	263	EXCP_LTLBL,
	264	EXCP_TLBL,
	265	EXCP_TLBS,
	266	EXCP_DBE,
	267	EXCP_DDBL,
	268	EXCP_MTCP0 = 0x104, /* mtmsr instruction: */
	269	/* may change privilege level */
	270	EXCP_BRANCH = 0x108, /* branch instruction */
	271	EXCP_ERET = 0x10C, /* return from interrupt */
	272	EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
	273	EXCP_FLUSH = 0x109,
	274	};
	275
6af0bf9c FB	276	int cpu_mips_exec(CPUMIPSState *s);
	277	CPUMIPSState *cpu_mips_init(void);
	278	uint32_t cpu_mips_get_clock (void);
	279
	280	#endif /* !defined (__MIPS_CPU_H__) */