[qemu.git] / target-mips / cpu.h

#if !defined (__MIPS_CPU_H__)
#define __MIPS_CPU_H__

#define TARGET_HAS_ICE 1

#define ELF_MACHINE	EM_MIPS

#define CPUState struct CPUMIPSState

#include "config.h"
#include "mips-defs.h"
#include "cpu-defs.h"
#include "softfloat.h"

// uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
// XXX: move that elsewhere
#if defined(HOST_SOLARIS) && HOST_SOLARIS < 10
typedef unsigned char           uint_fast8_t;
typedef unsigned int            uint_fast16_t;
#endif

struct CPUMIPSState;

typedef struct r4k_tlb_t r4k_tlb_t;
struct r4k_tlb_t {
    target_ulong VPN;
    uint32_t PageMask;
    uint_fast8_t ASID;
    uint_fast16_t G:1;
    uint_fast16_t C0:3;
    uint_fast16_t C1:3;
    uint_fast16_t V0:1;
    uint_fast16_t V1:1;
    uint_fast16_t D0:1;
    uint_fast16_t D1:1;
    target_ulong PFN[2];
};

typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
struct CPUMIPSTLBContext {
    uint32_t nb_tlb;
    uint32_t tlb_in_use;
    int (*map_address) (struct CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type);
    void (*helper_tlbwi) (void);
    void (*helper_tlbwr) (void);
    void (*helper_tlbp) (void);
    void (*helper_tlbr) (void);
    union {
        struct {
            r4k_tlb_t tlb[MIPS_TLB_MAX];
        } r4k;
    } mmu;
};

typedef union fpr_t fpr_t;
union fpr_t {
    float64  fd;   /* ieee double precision */
    float32  fs[2];/* ieee single precision */
    uint64_t d;    /* binary double fixed-point */
    uint32_t w[2]; /* binary single fixed-point */
};
/* define FP_ENDIAN_IDX to access the same location
 * in the fpr_t union regardless of the host endianess
 */
#if defined(WORDS_BIGENDIAN)
#  define FP_ENDIAN_IDX 1
#else
#  define FP_ENDIAN_IDX 0
#endif

typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
struct CPUMIPSFPUContext {
    /* Floating point registers */
    fpr_t fpr[32];
    float_status fp_status;
    /* fpu implementation/revision register (fir) */
    uint32_t fcr0;
#define FCR0_F64 22
#define FCR0_L 21
#define FCR0_W 20
#define FCR0_3D 19
#define FCR0_PS 18
#define FCR0_D 17
#define FCR0_S 16
#define FCR0_PRID 8
#define FCR0_REV 0
    /* fcsr */
    uint32_t fcr31;
#define SET_FP_COND(num,env)     do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
#define CLEAR_FP_COND(num,env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
#define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
#define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
#define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
#define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
#define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
#define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
#define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
#define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
#define FP_INEXACT        1
#define FP_UNDERFLOW      2
#define FP_OVERFLOW       4
#define FP_DIV0           8
#define FP_INVALID        16
#define FP_UNIMPLEMENTED  32
};

#define NB_MMU_MODES 3

typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
struct CPUMIPSMVPContext {
    int32_t CP0_MVPControl;
#define CP0MVPCo_CPA	3
#define CP0MVPCo_STLB	2
#define CP0MVPCo_VPC	1
#define CP0MVPCo_EVP	0
    int32_t CP0_MVPConf0;
#define CP0MVPC0_M	31
#define CP0MVPC0_TLBS	29
#define CP0MVPC0_GS	28
#define CP0MVPC0_PCP	27
#define CP0MVPC0_PTLBE	16
#define CP0MVPC0_TCA	15
#define CP0MVPC0_PVPE	10
#define CP0MVPC0_PTC	0
    int32_t CP0_MVPConf1;
#define CP0MVPC1_CIM	31
#define CP0MVPC1_CIF	30
#define CP0MVPC1_PCX	20
#define CP0MVPC1_PCP2	10
#define CP0MVPC1_PCP1	0
};

typedef struct mips_def_t mips_def_t;

#define MIPS_SHADOW_SET_MAX 16
#define MIPS_TC_MAX 5
#define MIPS_FPU_MAX 1
#define MIPS_DSP_ACC 4

typedef struct TCState TCState;
struct TCState {
    target_ulong gpr[32];
    target_ulong PC;
    target_ulong HI[MIPS_DSP_ACC];
    target_ulong LO[MIPS_DSP_ACC];
    target_ulong ACX[MIPS_DSP_ACC];
    target_ulong DSPControl;
    int32_t CP0_TCStatus;
#define CP0TCSt_TCU3	31
#define CP0TCSt_TCU2	30
#define CP0TCSt_TCU1	29
#define CP0TCSt_TCU0	28
#define CP0TCSt_TMX	27
#define CP0TCSt_RNST	23
#define CP0TCSt_TDS	21
#define CP0TCSt_DT	20
#define CP0TCSt_DA	15
#define CP0TCSt_A	13
#define CP0TCSt_TKSU	11
#define CP0TCSt_IXMT	10
#define CP0TCSt_TASID	0
    int32_t CP0_TCBind;
#define CP0TCBd_CurTC	21
#define CP0TCBd_TBE	17
#define CP0TCBd_CurVPE	0
    target_ulong CP0_TCHalt;
    target_ulong CP0_TCContext;
    target_ulong CP0_TCSchedule;
    target_ulong CP0_TCScheFBack;
    int32_t CP0_Debug_tcstatus;
};

typedef struct CPUMIPSState CPUMIPSState;
struct CPUMIPSState {
    TCState active_tc;
    CPUMIPSFPUContext active_fpu;

    CPUMIPSMVPContext *mvp;
    CPUMIPSTLBContext *tlb;
    uint32_t current_tc;
    uint32_t current_fpu;

    uint32_t SEGBITS;
    uint32_t PABITS;
    target_ulong SEGMask;
    target_ulong PAMask;

    int32_t CP0_Index;
    /* CP0_MVP* are per MVP registers. */
    int32_t CP0_Random;
    int32_t CP0_VPEControl;
#define CP0VPECo_YSI	21
#define CP0VPECo_GSI	20
#define CP0VPECo_EXCPT	16
#define CP0VPECo_TE	15
#define CP0VPECo_TargTC	0
    int32_t CP0_VPEConf0;
#define CP0VPEC0_M	31
#define CP0VPEC0_XTC	21
#define CP0VPEC0_TCS	19
#define CP0VPEC0_SCS	18
#define CP0VPEC0_DSC	17
#define CP0VPEC0_ICS	16
#define CP0VPEC0_MVP	1
#define CP0VPEC0_VPA	0
    int32_t CP0_VPEConf1;
#define CP0VPEC1_NCX	20
#define CP0VPEC1_NCP2	10
#define CP0VPEC1_NCP1	0
    target_ulong CP0_YQMask;
    target_ulong CP0_VPESchedule;
    target_ulong CP0_VPEScheFBack;
    int32_t CP0_VPEOpt;
#define CP0VPEOpt_IWX7	15
#define CP0VPEOpt_IWX6	14
#define CP0VPEOpt_IWX5	13
#define CP0VPEOpt_IWX4	12
#define CP0VPEOpt_IWX3	11
#define CP0VPEOpt_IWX2	10
#define CP0VPEOpt_IWX1	9
#define CP0VPEOpt_IWX0	8
#define CP0VPEOpt_DWX7	7
#define CP0VPEOpt_DWX6	6
#define CP0VPEOpt_DWX5	5
#define CP0VPEOpt_DWX4	4
#define CP0VPEOpt_DWX3	3
#define CP0VPEOpt_DWX2	2
#define CP0VPEOpt_DWX1	1
#define CP0VPEOpt_DWX0	0
    target_ulong CP0_EntryLo0;
    target_ulong CP0_EntryLo1;
    target_ulong CP0_Context;
    int32_t CP0_PageMask;
    int32_t CP0_PageGrain;
    int32_t CP0_Wired;
    int32_t CP0_SRSConf0_rw_bitmask;
    int32_t CP0_SRSConf0;
#define CP0SRSC0_M	31
#define CP0SRSC0_SRS3	20
#define CP0SRSC0_SRS2	10
#define CP0SRSC0_SRS1	0
    int32_t CP0_SRSConf1_rw_bitmask;
    int32_t CP0_SRSConf1;
#define CP0SRSC1_M	31
#define CP0SRSC1_SRS6	20
#define CP0SRSC1_SRS5	10
#define CP0SRSC1_SRS4	0
    int32_t CP0_SRSConf2_rw_bitmask;
    int32_t CP0_SRSConf2;
#define CP0SRSC2_M	31
#define CP0SRSC2_SRS9	20
#define CP0SRSC2_SRS8	10
#define CP0SRSC2_SRS7	0
    int32_t CP0_SRSConf3_rw_bitmask;
    int32_t CP0_SRSConf3;
#define CP0SRSC3_M	31
#define CP0SRSC3_SRS12	20
#define CP0SRSC3_SRS11	10
#define CP0SRSC3_SRS10	0
    int32_t CP0_SRSConf4_rw_bitmask;
    int32_t CP0_SRSConf4;
#define CP0SRSC4_SRS15	20
#define CP0SRSC4_SRS14	10
#define CP0SRSC4_SRS13	0
    int32_t CP0_HWREna;
    target_ulong CP0_BadVAddr;
    int32_t CP0_Count;
    target_ulong CP0_EntryHi;
    int32_t CP0_Compare;
    int32_t CP0_Status;
#define CP0St_CU3   31
#define CP0St_CU2   30
#define CP0St_CU1   29
#define CP0St_CU0   28
#define CP0St_RP    27
#define CP0St_FR    26
#define CP0St_RE    25
#define CP0St_MX    24
#define CP0St_PX    23
#define CP0St_BEV   22
#define CP0St_TS    21
#define CP0St_SR    20
#define CP0St_NMI   19
#define CP0St_IM    8
#define CP0St_KX    7
#define CP0St_SX    6
#define CP0St_UX    5
#define CP0St_KSU   3
#define CP0St_ERL   2
#define CP0St_EXL   1
#define CP0St_IE    0
    int32_t CP0_IntCtl;
#define CP0IntCtl_IPTI 29
#define CP0IntCtl_IPPC1 26
#define CP0IntCtl_VS 5
    int32_t CP0_SRSCtl;
#define CP0SRSCtl_HSS 26
#define CP0SRSCtl_EICSS 18
#define CP0SRSCtl_ESS 12
#define CP0SRSCtl_PSS 6
#define CP0SRSCtl_CSS 0
    int32_t CP0_SRSMap;
#define CP0SRSMap_SSV7 28
#define CP0SRSMap_SSV6 24
#define CP0SRSMap_SSV5 20
#define CP0SRSMap_SSV4 16
#define CP0SRSMap_SSV3 12
#define CP0SRSMap_SSV2 8
#define CP0SRSMap_SSV1 4
#define CP0SRSMap_SSV0 0
    int32_t CP0_Cause;
#define CP0Ca_BD   31
#define CP0Ca_TI   30
#define CP0Ca_CE   28
#define CP0Ca_DC   27
#define CP0Ca_PCI  26
#define CP0Ca_IV   23
#define CP0Ca_WP   22
#define CP0Ca_IP    8
#define CP0Ca_IP_mask 0x0000FF00
#define CP0Ca_EC    2
    target_ulong CP0_EPC;
    int32_t CP0_PRid;
    int32_t CP0_EBase;
    int32_t CP0_Config0;
#define CP0C0_M    31
#define CP0C0_K23  28
#define CP0C0_KU   25
#define CP0C0_MDU  20
#define CP0C0_MM   17
#define CP0C0_BM   16
#define CP0C0_BE   15
#define CP0C0_AT   13
#define CP0C0_AR   10
#define CP0C0_MT   7
#define CP0C0_VI   3
#define CP0C0_K0   0
    int32_t CP0_Config1;
#define CP0C1_M    31
#define CP0C1_MMU  25
#define CP0C1_IS   22
#define CP0C1_IL   19
#define CP0C1_IA   16
#define CP0C1_DS   13
#define CP0C1_DL   10
#define CP0C1_DA   7
#define CP0C1_C2   6
#define CP0C1_MD   5
#define CP0C1_PC   4
#define CP0C1_WR   3
#define CP0C1_CA   2
#define CP0C1_EP   1
#define CP0C1_FP   0
    int32_t CP0_Config2;
#define CP0C2_M    31
#define CP0C2_TU   28
#define CP0C2_TS   24
#define CP0C2_TL   20
#define CP0C2_TA   16
#define CP0C2_SU   12
#define CP0C2_SS   8
#define CP0C2_SL   4
#define CP0C2_SA   0
    int32_t CP0_Config3;
#define CP0C3_M    31
#define CP0C3_DSPP 10
#define CP0C3_LPA  7
#define CP0C3_VEIC 6
#define CP0C3_VInt 5
#define CP0C3_SP   4
#define CP0C3_MT   2
#define CP0C3_SM   1
#define CP0C3_TL   0
    int32_t CP0_Config6;
    int32_t CP0_Config7;
    /* XXX: Maybe make LLAddr per-TC? */
    target_ulong CP0_LLAddr;
    target_ulong CP0_WatchLo[8];
    int32_t CP0_WatchHi[8];
    target_ulong CP0_XContext;
    int32_t CP0_Framemask;
    int32_t CP0_Debug;
#define CP0DB_DBD  31
#define CP0DB_DM   30
#define CP0DB_LSNM 28
#define CP0DB_Doze 27
#define CP0DB_Halt 26
#define CP0DB_CNT  25
#define CP0DB_IBEP 24
#define CP0DB_DBEP 21
#define CP0DB_IEXI 20
#define CP0DB_VER  15
#define CP0DB_DEC  10
#define CP0DB_SSt  8
#define CP0DB_DINT 5
#define CP0DB_DIB  4
#define CP0DB_DDBS 3
#define CP0DB_DDBL 2
#define CP0DB_DBp  1
#define CP0DB_DSS  0
    target_ulong CP0_DEPC;
    int32_t CP0_Performance0;
    int32_t CP0_TagLo;
    int32_t CP0_DataLo;
    int32_t CP0_TagHi;
    int32_t CP0_DataHi;
    target_ulong CP0_ErrorEPC;
    int32_t CP0_DESAVE;
    /* We waste some space so we can handle shadow registers like TCs. */
    TCState tcs[MIPS_SHADOW_SET_MAX];
    CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
    /* Qemu */
    int error_code;
    uint32_t hflags;    /* CPU State */
    /* TMASK defines different execution modes */
#define MIPS_HFLAG_TMASK  0x03FF
#define MIPS_HFLAG_MODE   0x0007 /* execution modes                    */
    /* The KSU flags must be the lowest bits in hflags. The flag order
       must be the same as defined for CP0 Status. This allows to use
       the bits as the value of mmu_idx. */
#define MIPS_HFLAG_KSU    0x0003 /* kernel/supervisor/user mode mask   */
#define MIPS_HFLAG_UM       0x0002 /* user mode flag */
#define MIPS_HFLAG_SM       0x0001 /* supervisor mode flag */
#define MIPS_HFLAG_KM       0x0000 /* kernel mode flag */
#define MIPS_HFLAG_DM     0x0004 /* Debug mode                         */
#define MIPS_HFLAG_64     0x0008 /* 64-bit instructions enabled        */
#define MIPS_HFLAG_CP0    0x0010 /* CP0 enabled                        */
#define MIPS_HFLAG_FPU    0x0020 /* FPU enabled                        */
#define MIPS_HFLAG_F64    0x0040 /* 64-bit FPU enabled                 */
    /* True if the MIPS IV COP1X instructions can be used.  This also
       controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
       and RSQRT.D.  */
#define MIPS_HFLAG_COP1X  0x0080 /* COP1X instructions enabled         */
#define MIPS_HFLAG_RE     0x0100 /* Reversed endianness                */
#define MIPS_HFLAG_UX     0x0200 /* 64-bit user mode                   */
    /* If translation is interrupted between the branch instruction and
     * the delay slot, record what type of branch it is so that we can
     * resume translation properly.  It might be possible to reduce
     * this from three bits to two.  */
#define MIPS_HFLAG_BMASK  0x1C00
#define MIPS_HFLAG_B      0x0400 /* Unconditional branch               */
#define MIPS_HFLAG_BC     0x0800 /* Conditional branch                 */
#define MIPS_HFLAG_BL     0x0C00 /* Likely branch                      */
#define MIPS_HFLAG_BR     0x1000 /* branch to register (can't link TB) */
    target_ulong btarget;        /* Jump / branch target               */
    int bcond;                   /* Branch condition (if needed)       */

    int SYNCI_Step; /* Address step size for SYNCI */
    int CCRes; /* Cycle count resolution/divisor */
    uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
    uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
    int insn_flags; /* Supported instruction set */

    target_ulong tls_value; /* For usermode emulation */

    CPU_COMMON

    const mips_def_t *cpu_model;
    void *irq[8];
    struct QEMUTimer *timer; /* Internal timer */
};

int no_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
                        target_ulong address, int rw, int access_type);
int fixed_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
                           target_ulong address, int rw, int access_type);
int r4k_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
                     target_ulong address, int rw, int access_type);
void r4k_helper_tlbwi (void);
void r4k_helper_tlbwr (void);
void r4k_helper_tlbp (void);
void r4k_helper_tlbr (void);
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));

void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
                          int unused, int size);

#define cpu_init cpu_mips_init
#define cpu_exec cpu_mips_exec
#define cpu_gen_code cpu_mips_gen_code
#define cpu_signal_handler cpu_mips_signal_handler
#define cpu_list mips_cpu_list

#define CPU_SAVE_VERSION 3

/* MMU modes definitions. We carefully match the indices with our
   hflags layout. */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _super
#define MMU_MODE2_SUFFIX _user
#define MMU_USER_IDX 2
static inline int cpu_mmu_index (CPUState *env)
{
    return env->hflags & MIPS_HFLAG_KSU;
}

static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
{
    if (newsp)
        env->active_tc.gpr[29] = newsp;
    env->active_tc.gpr[7] = 0;
    env->active_tc.gpr[2] = 0;
}

#include "cpu-all.h"
#include "exec-all.h"

/* Memory access type :
 * may be needed for precise access rights control and precise exceptions.
 */
enum {
    /* 1 bit to define user level / supervisor access */
    ACCESS_USER  = 0x00,
    ACCESS_SUPER = 0x01,
    /* 1 bit to indicate direction */
    ACCESS_STORE = 0x02,
    /* Type of instruction that generated the access */
    ACCESS_CODE  = 0x10, /* Code fetch access                */
    ACCESS_INT   = 0x20, /* Integer load/store access        */
    ACCESS_FLOAT = 0x30, /* floating point load/store access */
};

/* Exceptions */
enum {
    EXCP_NONE          = -1,
    EXCP_RESET         = 0,
    EXCP_SRESET,
    EXCP_DSS,
    EXCP_DINT,
    EXCP_DDBL,
    EXCP_DDBS,
    EXCP_NMI,
    EXCP_MCHECK,
    EXCP_EXT_INTERRUPT, /* 8 */
    EXCP_DFWATCH,
    EXCP_DIB,
    EXCP_IWATCH,
    EXCP_AdEL,
    EXCP_AdES,
    EXCP_TLBF,
    EXCP_IBE,
    EXCP_DBp, /* 16 */
    EXCP_SYSCALL,
    EXCP_BREAK,
    EXCP_CpU,
    EXCP_RI,
    EXCP_OVERFLOW,
    EXCP_TRAP,
    EXCP_FPE,
    EXCP_DWATCH, /* 24 */
    EXCP_LTLBL,
    EXCP_TLBL,
    EXCP_TLBS,
    EXCP_DBE,
    EXCP_THREAD,
    EXCP_MDMX,
    EXCP_C2E,
    EXCP_CACHE, /* 32 */

    EXCP_LAST = EXCP_CACHE,
};

int cpu_mips_exec(CPUMIPSState *s);
CPUMIPSState *cpu_mips_init(const char *cpu_model);
//~ uint32_t cpu_mips_get_clock (void);
int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);

/* mips_timer.c */
uint32_t cpu_mips_get_random (CPUState *env);
uint32_t cpu_mips_get_count (CPUState *env);
void cpu_mips_store_count (CPUState *env, uint32_t value);
void cpu_mips_store_compare (CPUState *env, uint32_t value);
void cpu_mips_start_count(CPUState *env);
void cpu_mips_stop_count(CPUState *env);

/* mips_int.c */
void cpu_mips_update_irq (CPUState *env);

/* helper.c */
int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                               int mmu_idx, int is_softmmu);
void do_interrupt (CPUState *env);
void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);

static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
    env->active_tc.PC = tb->pc;
    env->hflags &= ~MIPS_HFLAG_BMASK;
    env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
}

static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
                                        target_ulong *cs_base, int *flags)
{
    *pc = env->active_tc.PC;
    *cs_base = 0;
    *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
}

#endif /* !defined (__MIPS_CPU_H__) */
Commit	Line	Data
6af0bf9c FB	1	#if !defined (__MIPS_CPU_H__)
	2	#define __MIPS_CPU_H__
	3
4ad40f36 FB	4	#define TARGET_HAS_ICE 1
4ad40f36 FB	5
9042c0e2 TS	6	#define ELF_MACHINE EM_MIPS
9042c0e2 TS	7
c2764719 PB	8	#define CPUState struct CPUMIPSState
c2764719 PB	9
c5d6edc3	10	#include "config.h"
6af0bf9c FB	11	#include "mips-defs.h"
6af0bf9c FB	12	#include "cpu-defs.h"
6af0bf9c FB	13	#include "softfloat.h"
6af0bf9c FB	14
fdbb4691 FB	15	// uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
fdbb4691 FB	16	// XXX: move that elsewhere
36bb244b	17	#if defined(HOST_SOLARIS) && HOST_SOLARIS < 10
fdbb4691 FB	18	typedef unsigned char uint_fast8_t;
	19	typedef unsigned int uint_fast16_t;
	20	#endif
	21
ead9360e	22	struct CPUMIPSState;
6af0bf9c	23
29929e34 TS	24	typedef struct r4k_tlb_t r4k_tlb_t;
29929e34 TS	25	struct r4k_tlb_t {
6af0bf9c	26	target_ulong VPN;
9c2149c8	27	uint32_t PageMask;
98c1b82b PB	28	uint_fast8_t ASID;
	29	uint_fast16_t G:1;
	30	uint_fast16_t C0:3;
	31	uint_fast16_t C1:3;
	32	uint_fast16_t V0:1;
	33	uint_fast16_t V1:1;
	34	uint_fast16_t D0:1;
	35	uint_fast16_t D1:1;
6af0bf9c FB	36	target_ulong PFN[2];
6af0bf9c FB	37	};
6af0bf9c	38
ead9360e TS	39	typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
	40	struct CPUMIPSTLBContext {
	41	uint32_t nb_tlb;
	42	uint32_t tlb_in_use;
	43	int (map_address) (struct CPUMIPSState env, target_ulong physical, int prot, target_ulong address, int rw, int access_type);
c01fccd2 AJ	44	void (*helper_tlbwi) (void);
	45	void (*helper_tlbwr) (void);
	46	void (*helper_tlbp) (void);
	47	void (*helper_tlbr) (void);
ead9360e TS	48	union {
	49	struct {
	50	r4k_tlb_t tlb[MIPS_TLB_MAX];
	51	} r4k;
	52	} mmu;
	53	};
51b2772f	54
ead9360e TS	55	typedef union fpr_t fpr_t;
	56	union fpr_t {
	57	float64 fd; /* ieee double precision */
	58	float32 fs[2];/* ieee single precision */
	59	uint64_t d; /* binary double fixed-point */
	60	uint32_t w[2]; /* binary single fixed-point */
	61	};
	62	/* define FP_ENDIAN_IDX to access the same location
	63	* in the fpr_t union regardless of the host endianess
	64	*/
	65	#if defined(WORDS_BIGENDIAN)
	66	# define FP_ENDIAN_IDX 1
	67	#else
	68	# define FP_ENDIAN_IDX 0
c570fd16	69	#endif
ead9360e TS	70
	71	typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
	72	struct CPUMIPSFPUContext {
6af0bf9c	73	/* Floating point registers */
f7cfb2a1	74	fpr_t fpr[32];
6ea83fed	75	float_status fp_status;
5a5012ec	76	/* fpu implementation/revision register (fir) */
6af0bf9c	77	uint32_t fcr0;
5a5012ec TS	78	#define FCR0_F64 22
	79	#define FCR0_L 21
	80	#define FCR0_W 20
	81	#define FCR0_3D 19
	82	#define FCR0_PS 18
	83	#define FCR0_D 17
	84	#define FCR0_S 16
	85	#define FCR0_PRID 8
	86	#define FCR0_REV 0
6ea83fed FB	87	/* fcsr */
6ea83fed FB	88	uint32_t fcr31;
f01be154 TS	89	#define SET_FP_COND(num,env) do { ((env).fcr31) \|= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
	90	#define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
	91	#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) \| (((env).fcr31 >> 23) & 0x1))
5a5012ec TS	92	#define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
	93	#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
	94	#define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
	95	#define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) \| ((v & 0x3f) << 12); } while(0)
	96	#define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) \| ((v & 0x1f) << 7); } while(0)
	97	#define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) \| ((v & 0x1f) << 2); } while(0)
	98	#define UPDATE_FP_FLAGS(reg,v) do { (reg) \|= ((v & 0x1f) << 2); } while(0)
6ea83fed FB	99	#define FP_INEXACT 1
	100	#define FP_UNDERFLOW 2
	101	#define FP_OVERFLOW 4
	102	#define FP_DIV0 8
	103	#define FP_INVALID 16
	104	#define FP_UNIMPLEMENTED 32
ead9360e TS	105	};
ead9360e TS	106
623a930e	107	#define NB_MMU_MODES 3
6ebbf390	108
ead9360e TS	109	typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
	110	struct CPUMIPSMVPContext {
	111	int32_t CP0_MVPControl;
	112	#define CP0MVPCo_CPA 3
	113	#define CP0MVPCo_STLB 2
	114	#define CP0MVPCo_VPC 1
	115	#define CP0MVPCo_EVP 0
	116	int32_t CP0_MVPConf0;
	117	#define CP0MVPC0_M 31
	118	#define CP0MVPC0_TLBS 29
	119	#define CP0MVPC0_GS 28
	120	#define CP0MVPC0_PCP 27
	121	#define CP0MVPC0_PTLBE 16
	122	#define CP0MVPC0_TCA 15
	123	#define CP0MVPC0_PVPE 10
	124	#define CP0MVPC0_PTC 0
	125	int32_t CP0_MVPConf1;
	126	#define CP0MVPC1_CIM 31
	127	#define CP0MVPC1_CIF 30
	128	#define CP0MVPC1_PCX 20
	129	#define CP0MVPC1_PCP2 10
	130	#define CP0MVPC1_PCP1 0
	131	};
	132
	133	typedef struct mips_def_t mips_def_t;
	134
	135	#define MIPS_SHADOW_SET_MAX 16
	136	#define MIPS_TC_MAX 5
f01be154	137	#define MIPS_FPU_MAX 1
ead9360e TS	138	#define MIPS_DSP_ACC 4
ead9360e TS	139
b5dc7732 TS	140	typedef struct TCState TCState;
	141	struct TCState {
	142	target_ulong gpr[32];
	143	target_ulong PC;
	144	target_ulong HI[MIPS_DSP_ACC];
	145	target_ulong LO[MIPS_DSP_ACC];
	146	target_ulong ACX[MIPS_DSP_ACC];
	147	target_ulong DSPControl;
	148	int32_t CP0_TCStatus;
	149	#define CP0TCSt_TCU3 31
	150	#define CP0TCSt_TCU2 30
	151	#define CP0TCSt_TCU1 29
	152	#define CP0TCSt_TCU0 28
	153	#define CP0TCSt_TMX 27
	154	#define CP0TCSt_RNST 23
	155	#define CP0TCSt_TDS 21
	156	#define CP0TCSt_DT 20
	157	#define CP0TCSt_DA 15
	158	#define CP0TCSt_A 13
	159	#define CP0TCSt_TKSU 11
	160	#define CP0TCSt_IXMT 10
	161	#define CP0TCSt_TASID 0
	162	int32_t CP0_TCBind;
	163	#define CP0TCBd_CurTC 21
	164	#define CP0TCBd_TBE 17
	165	#define CP0TCBd_CurVPE 0
	166	target_ulong CP0_TCHalt;
	167	target_ulong CP0_TCContext;
	168	target_ulong CP0_TCSchedule;
	169	target_ulong CP0_TCScheFBack;
	170	int32_t CP0_Debug_tcstatus;
	171	};
	172
ead9360e TS	173	typedef struct CPUMIPSState CPUMIPSState;
ead9360e TS	174	struct CPUMIPSState {
b5dc7732	175	TCState active_tc;
f01be154	176	CPUMIPSFPUContext active_fpu;
b5dc7732	177
ead9360e TS	178	CPUMIPSMVPContext *mvp;
ead9360e TS	179	CPUMIPSTLBContext *tlb;
ead9360e	180	uint32_t current_tc;
f01be154	181	uint32_t current_fpu;
36d23958	182
e034e2c3	183	uint32_t SEGBITS;
6d35524c	184	uint32_t PABITS;
b6d96bed	185	target_ulong SEGMask;
6d35524c	186	target_ulong PAMask;
29929e34	187
9c2149c8	188	int32_t CP0_Index;
ead9360e	189	/* CP0_MVP* are per MVP registers. */
9c2149c8	190	int32_t CP0_Random;
ead9360e TS	191	int32_t CP0_VPEControl;
	192	#define CP0VPECo_YSI 21
	193	#define CP0VPECo_GSI 20
	194	#define CP0VPECo_EXCPT 16
	195	#define CP0VPECo_TE 15
	196	#define CP0VPECo_TargTC 0
	197	int32_t CP0_VPEConf0;
	198	#define CP0VPEC0_M 31
	199	#define CP0VPEC0_XTC 21
	200	#define CP0VPEC0_TCS 19
	201	#define CP0VPEC0_SCS 18
	202	#define CP0VPEC0_DSC 17
	203	#define CP0VPEC0_ICS 16
	204	#define CP0VPEC0_MVP 1
	205	#define CP0VPEC0_VPA 0
	206	int32_t CP0_VPEConf1;
	207	#define CP0VPEC1_NCX 20
	208	#define CP0VPEC1_NCP2 10
	209	#define CP0VPEC1_NCP1 0
	210	target_ulong CP0_YQMask;
	211	target_ulong CP0_VPESchedule;
	212	target_ulong CP0_VPEScheFBack;
	213	int32_t CP0_VPEOpt;
	214	#define CP0VPEOpt_IWX7 15
	215	#define CP0VPEOpt_IWX6 14
	216	#define CP0VPEOpt_IWX5 13
	217	#define CP0VPEOpt_IWX4 12
	218	#define CP0VPEOpt_IWX3 11
	219	#define CP0VPEOpt_IWX2 10
	220	#define CP0VPEOpt_IWX1 9
	221	#define CP0VPEOpt_IWX0 8
	222	#define CP0VPEOpt_DWX7 7
	223	#define CP0VPEOpt_DWX6 6
	224	#define CP0VPEOpt_DWX5 5
	225	#define CP0VPEOpt_DWX4 4
	226	#define CP0VPEOpt_DWX3 3
	227	#define CP0VPEOpt_DWX2 2
	228	#define CP0VPEOpt_DWX1 1
	229	#define CP0VPEOpt_DWX0 0
9c2149c8 TS	230	target_ulong CP0_EntryLo0;
	231	target_ulong CP0_EntryLo1;
	232	target_ulong CP0_Context;
	233	int32_t CP0_PageMask;
	234	int32_t CP0_PageGrain;
	235	int32_t CP0_Wired;
ead9360e TS	236	int32_t CP0_SRSConf0_rw_bitmask;
	237	int32_t CP0_SRSConf0;
	238	#define CP0SRSC0_M 31
	239	#define CP0SRSC0_SRS3 20
	240	#define CP0SRSC0_SRS2 10
	241	#define CP0SRSC0_SRS1 0
	242	int32_t CP0_SRSConf1_rw_bitmask;
	243	int32_t CP0_SRSConf1;
	244	#define CP0SRSC1_M 31
	245	#define CP0SRSC1_SRS6 20
	246	#define CP0SRSC1_SRS5 10
	247	#define CP0SRSC1_SRS4 0
	248	int32_t CP0_SRSConf2_rw_bitmask;
	249	int32_t CP0_SRSConf2;
	250	#define CP0SRSC2_M 31
	251	#define CP0SRSC2_SRS9 20
	252	#define CP0SRSC2_SRS8 10
	253	#define CP0SRSC2_SRS7 0
	254	int32_t CP0_SRSConf3_rw_bitmask;
	255	int32_t CP0_SRSConf3;
	256	#define CP0SRSC3_M 31
	257	#define CP0SRSC3_SRS12 20
	258	#define CP0SRSC3_SRS11 10
	259	#define CP0SRSC3_SRS10 0
	260	int32_t CP0_SRSConf4_rw_bitmask;
	261	int32_t CP0_SRSConf4;
	262	#define CP0SRSC4_SRS15 20
	263	#define CP0SRSC4_SRS14 10
	264	#define CP0SRSC4_SRS13 0
9c2149c8	265	int32_t CP0_HWREna;
c570fd16	266	target_ulong CP0_BadVAddr;
9c2149c8 TS	267	int32_t CP0_Count;
	268	target_ulong CP0_EntryHi;
	269	int32_t CP0_Compare;
	270	int32_t CP0_Status;
6af0bf9c FB	271	#define CP0St_CU3 31
	272	#define CP0St_CU2 30
	273	#define CP0St_CU1 29
	274	#define CP0St_CU0 28
	275	#define CP0St_RP 27
6ea83fed	276	#define CP0St_FR 26
6af0bf9c	277	#define CP0St_RE 25
7a387fff TS	278	#define CP0St_MX 24
7a387fff TS	279	#define CP0St_PX 23
6af0bf9c FB	280	#define CP0St_BEV 22
	281	#define CP0St_TS 21
	282	#define CP0St_SR 20
	283	#define CP0St_NMI 19
	284	#define CP0St_IM 8
7a387fff TS	285	#define CP0St_KX 7
	286	#define CP0St_SX 6
	287	#define CP0St_UX 5
623a930e	288	#define CP0St_KSU 3
6af0bf9c FB	289	#define CP0St_ERL 2
	290	#define CP0St_EXL 1
	291	#define CP0St_IE 0
9c2149c8	292	int32_t CP0_IntCtl;
ead9360e TS	293	#define CP0IntCtl_IPTI 29
	294	#define CP0IntCtl_IPPC1 26
	295	#define CP0IntCtl_VS 5
9c2149c8	296	int32_t CP0_SRSCtl;
ead9360e TS	297	#define CP0SRSCtl_HSS 26
	298	#define CP0SRSCtl_EICSS 18
	299	#define CP0SRSCtl_ESS 12
	300	#define CP0SRSCtl_PSS 6
	301	#define CP0SRSCtl_CSS 0
9c2149c8	302	int32_t CP0_SRSMap;
ead9360e TS	303	#define CP0SRSMap_SSV7 28
	304	#define CP0SRSMap_SSV6 24
	305	#define CP0SRSMap_SSV5 20
	306	#define CP0SRSMap_SSV4 16
	307	#define CP0SRSMap_SSV3 12
	308	#define CP0SRSMap_SSV2 8
	309	#define CP0SRSMap_SSV1 4
	310	#define CP0SRSMap_SSV0 0
9c2149c8	311	int32_t CP0_Cause;
7a387fff TS	312	#define CP0Ca_BD 31
	313	#define CP0Ca_TI 30
	314	#define CP0Ca_CE 28
	315	#define CP0Ca_DC 27
	316	#define CP0Ca_PCI 26
6af0bf9c	317	#define CP0Ca_IV 23
7a387fff TS	318	#define CP0Ca_WP 22
7a387fff TS	319	#define CP0Ca_IP 8
4de9b249	320	#define CP0Ca_IP_mask 0x0000FF00
7a387fff	321	#define CP0Ca_EC 2
c570fd16	322	target_ulong CP0_EPC;
9c2149c8	323	int32_t CP0_PRid;
b29a0341	324	int32_t CP0_EBase;
9c2149c8	325	int32_t CP0_Config0;
6af0bf9c FB	326	#define CP0C0_M 31
	327	#define CP0C0_K23 28
	328	#define CP0C0_KU 25
	329	#define CP0C0_MDU 20
	330	#define CP0C0_MM 17
	331	#define CP0C0_BM 16
	332	#define CP0C0_BE 15
	333	#define CP0C0_AT 13
	334	#define CP0C0_AR 10
	335	#define CP0C0_MT 7
7a387fff	336	#define CP0C0_VI 3
6af0bf9c	337	#define CP0C0_K0 0
9c2149c8	338	int32_t CP0_Config1;
7a387fff	339	#define CP0C1_M 31
6af0bf9c FB	340	#define CP0C1_MMU 25
	341	#define CP0C1_IS 22
	342	#define CP0C1_IL 19
	343	#define CP0C1_IA 16
	344	#define CP0C1_DS 13
	345	#define CP0C1_DL 10
	346	#define CP0C1_DA 7
7a387fff TS	347	#define CP0C1_C2 6
7a387fff TS	348	#define CP0C1_MD 5
6af0bf9c FB	349	#define CP0C1_PC 4
	350	#define CP0C1_WR 3
	351	#define CP0C1_CA 2
	352	#define CP0C1_EP 1
	353	#define CP0C1_FP 0
9c2149c8	354	int32_t CP0_Config2;
7a387fff TS	355	#define CP0C2_M 31
	356	#define CP0C2_TU 28
	357	#define CP0C2_TS 24
	358	#define CP0C2_TL 20
	359	#define CP0C2_TA 16
	360	#define CP0C2_SU 12
	361	#define CP0C2_SS 8
	362	#define CP0C2_SL 4
	363	#define CP0C2_SA 0
9c2149c8	364	int32_t CP0_Config3;
7a387fff TS	365	#define CP0C3_M 31
	366	#define CP0C3_DSPP 10
	367	#define CP0C3_LPA 7
	368	#define CP0C3_VEIC 6
	369	#define CP0C3_VInt 5
	370	#define CP0C3_SP 4
	371	#define CP0C3_MT 2
	372	#define CP0C3_SM 1
	373	#define CP0C3_TL 0
e397ee33 TS	374	int32_t CP0_Config6;
e397ee33 TS	375	int32_t CP0_Config7;
ead9360e	376	/* XXX: Maybe make LLAddr per-TC? */
c570fd16	377	target_ulong CP0_LLAddr;
fd88b6ab TS	378	target_ulong CP0_WatchLo[8];
fd88b6ab TS	379	int32_t CP0_WatchHi[8];
9c2149c8 TS	380	target_ulong CP0_XContext;
	381	int32_t CP0_Framemask;
	382	int32_t CP0_Debug;
ead9360e	383	#define CP0DB_DBD 31
6af0bf9c FB	384	#define CP0DB_DM 30
	385	#define CP0DB_LSNM 28
	386	#define CP0DB_Doze 27
	387	#define CP0DB_Halt 26
	388	#define CP0DB_CNT 25
	389	#define CP0DB_IBEP 24
	390	#define CP0DB_DBEP 21
	391	#define CP0DB_IEXI 20
	392	#define CP0DB_VER 15
	393	#define CP0DB_DEC 10
	394	#define CP0DB_SSt 8
	395	#define CP0DB_DINT 5
	396	#define CP0DB_DIB 4
	397	#define CP0DB_DDBS 3
	398	#define CP0DB_DDBL 2
	399	#define CP0DB_DBp 1
	400	#define CP0DB_DSS 0
c570fd16	401	target_ulong CP0_DEPC;
9c2149c8 TS	402	int32_t CP0_Performance0;
	403	int32_t CP0_TagLo;
	404	int32_t CP0_DataLo;
	405	int32_t CP0_TagHi;
	406	int32_t CP0_DataHi;
c570fd16	407	target_ulong CP0_ErrorEPC;
9c2149c8	408	int32_t CP0_DESAVE;
b5dc7732 TS	409	/* We waste some space so we can handle shadow registers like TCs. */
b5dc7732 TS	410	TCState tcs[MIPS_SHADOW_SET_MAX];
f01be154	411	CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
6af0bf9c	412	/* Qemu */
6af0bf9c	413	int error_code;
6af0bf9c FB	414	uint32_t hflags; /* CPU State */
6af0bf9c FB	415	/* TMASK defines different execution modes */
2623c1ec	416	#define MIPS_HFLAG_TMASK 0x03FF
78749ba8	417	#define MIPS_HFLAG_MODE 0x0007 /* execution modes */
623a930e TS	418	/* The KSU flags must be the lowest bits in hflags. The flag order
	419	must be the same as defined for CP0 Status. This allows to use
	420	the bits as the value of mmu_idx. */
	421	#define MIPS_HFLAG_KSU 0x0003 /* kernel/supervisor/user mode mask */
	422	#define MIPS_HFLAG_UM 0x0002 /* user mode flag */
	423	#define MIPS_HFLAG_SM 0x0001 /* supervisor mode flag */
	424	#define MIPS_HFLAG_KM 0x0000 /* kernel mode flag */
	425	#define MIPS_HFLAG_DM 0x0004 /* Debug mode */
5e755519	426	#define MIPS_HFLAG_64 0x0008 /* 64-bit instructions enabled */
387a8fe5 TS	427	#define MIPS_HFLAG_CP0 0x0010 /* CP0 enabled */
	428	#define MIPS_HFLAG_FPU 0x0020 /* FPU enabled */
	429	#define MIPS_HFLAG_F64 0x0040 /* 64-bit FPU enabled */
b8aa4598 TS	430	/* True if the MIPS IV COP1X instructions can be used. This also
	431	controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
	432	and RSQRT.D. */
	433	#define MIPS_HFLAG_COP1X 0x0080 /* COP1X instructions enabled */
	434	#define MIPS_HFLAG_RE 0x0100 /* Reversed endianness */
2623c1ec	435	#define MIPS_HFLAG_UX 0x0200 /* 64-bit user mode */
4ad40f36 FB	436	/* If translation is interrupted between the branch instruction and
	437	* the delay slot, record what type of branch it is so that we can
	438	* resume translation properly. It might be possible to reduce
	439	* this from three bits to two. */
2623c1ec AJ	440	#define MIPS_HFLAG_BMASK 0x1C00
	441	#define MIPS_HFLAG_B 0x0400 /* Unconditional branch */
	442	#define MIPS_HFLAG_BC 0x0800 /* Conditional branch */
	443	#define MIPS_HFLAG_BL 0x0C00 /* Likely branch */
	444	#define MIPS_HFLAG_BR 0x1000 /* branch to register (can't link TB) */
6af0bf9c FB	445	target_ulong btarget; /* Jump / branch target */
6af0bf9c FB	446	int bcond; /* Branch condition (if needed) */
a316d335	447
7a387fff TS	448	int SYNCI_Step; /* Address step size for SYNCI */
7a387fff TS	449	int CCRes; /* Cycle count resolution/divisor */
ead9360e TS	450	uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
ead9360e TS	451	uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
e189e748	452	int insn_flags; /* Supported instruction set */
7a387fff	453
0eaef5aa	454	target_ulong tls_value; /* For usermode emulation */
6f5b89a0	455
a316d335	456	CPU_COMMON
6ae81775	457
aaed909a	458	const mips_def_t *cpu_model;
33ac7f16	459	void *irq[8];
6ae81775	460	struct QEMUTimer timer; / Internal timer */
6af0bf9c FB	461	};
6af0bf9c FB	462
29929e34 TS	463	int no_mmu_map_address (CPUMIPSState env, target_ulong physical, int *prot,
	464	target_ulong address, int rw, int access_type);
	465	int fixed_mmu_map_address (CPUMIPSState env, target_ulong physical, int *prot,
	466	target_ulong address, int rw, int access_type);
	467	int r4k_map_address (CPUMIPSState env, target_ulong physical, int *prot,
	468	target_ulong address, int rw, int access_type);
c01fccd2 AJ	469	void r4k_helper_tlbwi (void);
	470	void r4k_helper_tlbwr (void);
	471	void r4k_helper_tlbp (void);
	472	void r4k_helper_tlbr (void);
33d68b5f	473	void mips_cpu_list (FILE f, int (cpu_fprintf)(FILE f, const char fmt, ...));
33d68b5f	474
647de6ca	475	void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
e18231a3	476	int unused, int size);
647de6ca	477
9467d44c TS	478	#define cpu_init cpu_mips_init
	479	#define cpu_exec cpu_mips_exec
	480	#define cpu_gen_code cpu_mips_gen_code
	481	#define cpu_signal_handler cpu_mips_signal_handler
c732abe2	482	#define cpu_list mips_cpu_list
9467d44c	483
b3c7724c PB	484	#define CPU_SAVE_VERSION 3
b3c7724c PB	485
623a930e TS	486	/* MMU modes definitions. We carefully match the indices with our
623a930e TS	487	hflags layout. */
6ebbf390	488	#define MMU_MODE0_SUFFIX _kernel
623a930e TS	489	#define MMU_MODE1_SUFFIX _super
	490	#define MMU_MODE2_SUFFIX _user
	491	#define MMU_USER_IDX 2
6ebbf390 JM	492	static inline int cpu_mmu_index (CPUState *env)
6ebbf390 JM	493	{
623a930e	494	return env->hflags & MIPS_HFLAG_KSU;
6ebbf390 JM	495	}
6ebbf390 JM	496
6e68e076 PB	497	static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
6e68e076 PB	498	{
f8ed7070	499	if (newsp)
b5dc7732 TS	500	env->active_tc.gpr[29] = newsp;
	501	env->active_tc.gpr[7] = 0;
	502	env->active_tc.gpr[2] = 0;
6e68e076	503	}
6e68e076	504
6af0bf9c	505	#include "cpu-all.h"
622ed360	506	#include "exec-all.h"
6af0bf9c FB	507
	508	/* Memory access type :
	509	* may be needed for precise access rights control and precise exceptions.
	510	*/
	511	enum {
	512	/* 1 bit to define user level / supervisor access */
	513	ACCESS_USER = 0x00,
	514	ACCESS_SUPER = 0x01,
	515	/* 1 bit to indicate direction */
	516	ACCESS_STORE = 0x02,
	517	/* Type of instruction that generated the access */
	518	ACCESS_CODE = 0x10, /* Code fetch access */
	519	ACCESS_INT = 0x20, /* Integer load/store access */
	520	ACCESS_FLOAT = 0x30, /* floating point load/store access */
	521	};
	522
	523	/* Exceptions */
	524	enum {
	525	EXCP_NONE = -1,
	526	EXCP_RESET = 0,
	527	EXCP_SRESET,
	528	EXCP_DSS,
	529	EXCP_DINT,
14e51cc7 TS	530	EXCP_DDBL,
14e51cc7 TS	531	EXCP_DDBS,
6af0bf9c FB	532	EXCP_NMI,
6af0bf9c FB	533	EXCP_MCHECK,
14e51cc7	534	EXCP_EXT_INTERRUPT, /* 8 */
6af0bf9c	535	EXCP_DFWATCH,
14e51cc7	536	EXCP_DIB,
6af0bf9c FB	537	EXCP_IWATCH,
	538	EXCP_AdEL,
	539	EXCP_AdES,
	540	EXCP_TLBF,
	541	EXCP_IBE,
14e51cc7	542	EXCP_DBp, /* 16 */
6af0bf9c	543	EXCP_SYSCALL,
14e51cc7	544	EXCP_BREAK,
4ad40f36	545	EXCP_CpU,
6af0bf9c FB	546	EXCP_RI,
	547	EXCP_OVERFLOW,
	548	EXCP_TRAP,
5a5012ec	549	EXCP_FPE,
14e51cc7	550	EXCP_DWATCH, /* 24 */
6af0bf9c FB	551	EXCP_LTLBL,
	552	EXCP_TLBL,
	553	EXCP_TLBS,
	554	EXCP_DBE,
ead9360e	555	EXCP_THREAD,
14e51cc7 TS	556	EXCP_MDMX,
	557	EXCP_C2E,
	558	EXCP_CACHE, /* 32 */
	559
	560	EXCP_LAST = EXCP_CACHE,
6af0bf9c FB	561	};
6af0bf9c FB	562
6af0bf9c	563	int cpu_mips_exec(CPUMIPSState *s);
aaed909a	564	CPUMIPSState cpu_mips_init(const char cpu_model);
f9480ffc	565	//~ uint32_t cpu_mips_get_clock (void);
388bb21a	566	int cpu_mips_signal_handler(int host_signum, void pinfo, void puc);
6af0bf9c	567
f9480ffc TS	568	/* mips_timer.c */
	569	uint32_t cpu_mips_get_random (CPUState *env);
	570	uint32_t cpu_mips_get_count (CPUState *env);
	571	void cpu_mips_store_count (CPUState *env, uint32_t value);
	572	void cpu_mips_store_compare (CPUState *env, uint32_t value);
	573	void cpu_mips_start_count(CPUState *env);
	574	void cpu_mips_stop_count(CPUState *env);
	575
	576	/* mips_int.c */
	577	void cpu_mips_update_irq (CPUState *env);
	578
	579	/* helper.c */
	580	int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
	581	int mmu_idx, int is_softmmu);
	582	void do_interrupt (CPUState *env);
	583	void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);
	584
622ed360 AL	585	static inline void cpu_pc_from_tb(CPUState env, TranslationBlock tb)
	586	{
	587	env->active_tc.PC = tb->pc;
	588	env->hflags &= ~MIPS_HFLAG_BMASK;
	589	env->hflags \|= tb->flags & MIPS_HFLAG_BMASK;
	590	}
2e70f6ef	591
6b917547 AL	592	static inline void cpu_get_tb_cpu_state(CPUState env, target_ulong pc,
	593	target_ulong cs_base, int flags)
	594	{
	595	*pc = env->active_tc.PC;
	596	*cs_base = 0;
	597	*flags = env->hflags & (MIPS_HFLAG_TMASK \| MIPS_HFLAG_BMASK);
	598	}
	599
6af0bf9c	600	#endif /* !defined (__MIPS_CPU_H__) */