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6af0bf9c FB |
1 | #if !defined (__MIPS_CPU_H__) |
2 | #define __MIPS_CPU_H__ | |
3 | ||
4ad40f36 FB |
4 | #define TARGET_HAS_ICE 1 |
5 | ||
9042c0e2 TS |
6 | #define ELF_MACHINE EM_MIPS |
7 | ||
c5d6edc3 | 8 | #include "config.h" |
6af0bf9c FB |
9 | #include "mips-defs.h" |
10 | #include "cpu-defs.h" | |
6af0bf9c FB |
11 | #include "softfloat.h" |
12 | ||
fdbb4691 FB |
13 | // uint_fast8_t and uint_fast16_t not in <sys/int_types.h> |
14 | // XXX: move that elsewhere | |
15 | #if defined(HOST_SOLARIS) && SOLARISREV < 10 | |
16 | typedef unsigned char uint_fast8_t; | |
17 | typedef unsigned int uint_fast16_t; | |
18 | #endif | |
19 | ||
c570fd16 | 20 | /* target_ulong size spec */ |
5dc4b744 | 21 | #ifdef MIPS_HAS_MIPS64 |
c570fd16 TS |
22 | #define TLSZ "%016llx" |
23 | #else | |
c570fd16 TS |
24 | #define TLSZ "%08x" |
25 | #endif | |
26 | ||
6af0bf9c FB |
27 | typedef union fpr_t fpr_t; |
28 | union fpr_t { | |
6ea83fed FB |
29 | float64 fd; /* ieee double precision */ |
30 | float32 fs[2];/* ieee single precision */ | |
31 | uint64_t d; /* binary single fixed-point */ | |
32 | uint32_t w[2]; /* binary single fixed-point */ | |
6af0bf9c | 33 | }; |
6ea83fed FB |
34 | /* define FP_ENDIAN_IDX to access the same location |
35 | * in the fpr_t union regardless of the host endianess | |
36 | */ | |
37 | #if defined(WORDS_BIGENDIAN) | |
38 | # define FP_ENDIAN_IDX 1 | |
39 | #else | |
40 | # define FP_ENDIAN_IDX 0 | |
41 | #endif | |
6af0bf9c FB |
42 | |
43 | #if defined(MIPS_USES_R4K_TLB) | |
44 | typedef struct tlb_t tlb_t; | |
45 | struct tlb_t { | |
46 | target_ulong VPN; | |
9c2149c8 | 47 | uint32_t PageMask; |
98c1b82b PB |
48 | uint_fast8_t ASID; |
49 | uint_fast16_t G:1; | |
50 | uint_fast16_t C0:3; | |
51 | uint_fast16_t C1:3; | |
52 | uint_fast16_t V0:1; | |
53 | uint_fast16_t V1:1; | |
54 | uint_fast16_t D0:1; | |
55 | uint_fast16_t D1:1; | |
6af0bf9c FB |
56 | target_ulong PFN[2]; |
57 | }; | |
58 | #endif | |
59 | ||
60 | typedef struct CPUMIPSState CPUMIPSState; | |
61 | struct CPUMIPSState { | |
62 | /* General integer registers */ | |
63 | target_ulong gpr[32]; | |
64 | /* Special registers */ | |
65 | target_ulong PC; | |
c570fd16 TS |
66 | #if TARGET_LONG_BITS > HOST_LONG_BITS |
67 | target_ulong t0; | |
68 | target_ulong t1; | |
69 | target_ulong t2; | |
70 | #endif | |
71 | target_ulong HI, LO; | |
6af0bf9c FB |
72 | uint32_t DCR; /* ? */ |
73 | #if defined(MIPS_USES_FPU) | |
74 | /* Floating point registers */ | |
75 | fpr_t fpr[16]; | |
6ea83fed FB |
76 | #define FPR(cpu, n) ((fpr_t*)&(cpu)->fpr[(n) / 2]) |
77 | #define FPR_FD(cpu, n) (FPR(cpu, n)->fd) | |
78 | #define FPR_FS(cpu, n) (FPR(cpu, n)->fs[((n) & 1) ^ FP_ENDIAN_IDX]) | |
79 | #define FPR_D(cpu, n) (FPR(cpu, n)->d) | |
80 | #define FPR_W(cpu, n) (FPR(cpu, n)->w[((n) & 1) ^ FP_ENDIAN_IDX]) | |
81 | ||
82 | #ifndef USE_HOST_FLOAT_REGS | |
83 | fpr_t ft0; | |
84 | fpr_t ft1; | |
85 | fpr_t ft2; | |
86 | #endif | |
87 | float_status fp_status; | |
88 | /* fpu implementation/revision register */ | |
6af0bf9c | 89 | uint32_t fcr0; |
6ea83fed FB |
90 | /* fcsr */ |
91 | uint32_t fcr31; | |
92 | #define SET_FP_COND(reg) do { (reg) |= (1<<23); } while(0) | |
93 | #define CLEAR_FP_COND(reg) do { (reg) &= ~(1<<23); } while(0) | |
94 | #define IS_FP_COND_SET(reg) (((reg) & (1<<23)) != 0) | |
95 | #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) | |
96 | #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) | |
97 | #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) | |
98 | #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v) << 12); } while(0) | |
99 | #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v) << 7); } while(0) | |
100 | #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v) << 2); } while(0) | |
101 | #define FP_INEXACT 1 | |
102 | #define FP_UNDERFLOW 2 | |
103 | #define FP_OVERFLOW 4 | |
104 | #define FP_DIV0 8 | |
105 | #define FP_INVALID 16 | |
106 | #define FP_UNIMPLEMENTED 32 | |
107 | ||
6af0bf9c FB |
108 | #endif |
109 | #if defined(MIPS_USES_R4K_TLB) | |
814b9a47 TS |
110 | tlb_t tlb[MIPS_TLB_MAX]; |
111 | uint32_t tlb_in_use; | |
6af0bf9c | 112 | #endif |
9c2149c8 TS |
113 | int32_t CP0_Index; |
114 | int32_t CP0_Random; | |
115 | target_ulong CP0_EntryLo0; | |
116 | target_ulong CP0_EntryLo1; | |
117 | target_ulong CP0_Context; | |
118 | int32_t CP0_PageMask; | |
119 | int32_t CP0_PageGrain; | |
120 | int32_t CP0_Wired; | |
121 | int32_t CP0_HWREna; | |
c570fd16 | 122 | target_ulong CP0_BadVAddr; |
9c2149c8 TS |
123 | int32_t CP0_Count; |
124 | target_ulong CP0_EntryHi; | |
125 | int32_t CP0_Compare; | |
126 | int32_t CP0_Status; | |
6af0bf9c FB |
127 | #define CP0St_CU3 31 |
128 | #define CP0St_CU2 30 | |
129 | #define CP0St_CU1 29 | |
130 | #define CP0St_CU0 28 | |
131 | #define CP0St_RP 27 | |
6ea83fed | 132 | #define CP0St_FR 26 |
6af0bf9c | 133 | #define CP0St_RE 25 |
7a387fff TS |
134 | #define CP0St_MX 24 |
135 | #define CP0St_PX 23 | |
6af0bf9c FB |
136 | #define CP0St_BEV 22 |
137 | #define CP0St_TS 21 | |
138 | #define CP0St_SR 20 | |
139 | #define CP0St_NMI 19 | |
140 | #define CP0St_IM 8 | |
7a387fff TS |
141 | #define CP0St_KX 7 |
142 | #define CP0St_SX 6 | |
143 | #define CP0St_UX 5 | |
6af0bf9c | 144 | #define CP0St_UM 4 |
7a387fff | 145 | #define CP0St_R0 3 |
6af0bf9c FB |
146 | #define CP0St_ERL 2 |
147 | #define CP0St_EXL 1 | |
148 | #define CP0St_IE 0 | |
9c2149c8 TS |
149 | int32_t CP0_IntCtl; |
150 | int32_t CP0_SRSCtl; | |
151 | int32_t CP0_SRSMap; | |
152 | int32_t CP0_Cause; | |
7a387fff TS |
153 | #define CP0Ca_BD 31 |
154 | #define CP0Ca_TI 30 | |
155 | #define CP0Ca_CE 28 | |
156 | #define CP0Ca_DC 27 | |
157 | #define CP0Ca_PCI 26 | |
6af0bf9c | 158 | #define CP0Ca_IV 23 |
7a387fff TS |
159 | #define CP0Ca_WP 22 |
160 | #define CP0Ca_IP 8 | |
4de9b249 | 161 | #define CP0Ca_IP_mask 0x0000FF00 |
7a387fff | 162 | #define CP0Ca_EC 2 |
c570fd16 | 163 | target_ulong CP0_EPC; |
9c2149c8 | 164 | int32_t CP0_PRid; |
b29a0341 | 165 | int32_t CP0_EBase; |
9c2149c8 | 166 | int32_t CP0_Config0; |
6af0bf9c FB |
167 | #define CP0C0_M 31 |
168 | #define CP0C0_K23 28 | |
169 | #define CP0C0_KU 25 | |
170 | #define CP0C0_MDU 20 | |
171 | #define CP0C0_MM 17 | |
172 | #define CP0C0_BM 16 | |
173 | #define CP0C0_BE 15 | |
174 | #define CP0C0_AT 13 | |
175 | #define CP0C0_AR 10 | |
176 | #define CP0C0_MT 7 | |
7a387fff | 177 | #define CP0C0_VI 3 |
6af0bf9c | 178 | #define CP0C0_K0 0 |
9c2149c8 | 179 | int32_t CP0_Config1; |
7a387fff | 180 | #define CP0C1_M 31 |
6af0bf9c FB |
181 | #define CP0C1_MMU 25 |
182 | #define CP0C1_IS 22 | |
183 | #define CP0C1_IL 19 | |
184 | #define CP0C1_IA 16 | |
185 | #define CP0C1_DS 13 | |
186 | #define CP0C1_DL 10 | |
187 | #define CP0C1_DA 7 | |
7a387fff TS |
188 | #define CP0C1_C2 6 |
189 | #define CP0C1_MD 5 | |
6af0bf9c FB |
190 | #define CP0C1_PC 4 |
191 | #define CP0C1_WR 3 | |
192 | #define CP0C1_CA 2 | |
193 | #define CP0C1_EP 1 | |
194 | #define CP0C1_FP 0 | |
9c2149c8 | 195 | int32_t CP0_Config2; |
7a387fff TS |
196 | #define CP0C2_M 31 |
197 | #define CP0C2_TU 28 | |
198 | #define CP0C2_TS 24 | |
199 | #define CP0C2_TL 20 | |
200 | #define CP0C2_TA 16 | |
201 | #define CP0C2_SU 12 | |
202 | #define CP0C2_SS 8 | |
203 | #define CP0C2_SL 4 | |
204 | #define CP0C2_SA 0 | |
9c2149c8 | 205 | int32_t CP0_Config3; |
7a387fff TS |
206 | #define CP0C3_M 31 |
207 | #define CP0C3_DSPP 10 | |
208 | #define CP0C3_LPA 7 | |
209 | #define CP0C3_VEIC 6 | |
210 | #define CP0C3_VInt 5 | |
211 | #define CP0C3_SP 4 | |
212 | #define CP0C3_MT 2 | |
213 | #define CP0C3_SM 1 | |
214 | #define CP0C3_TL 0 | |
c570fd16 | 215 | target_ulong CP0_LLAddr; |
9c2149c8 TS |
216 | target_ulong CP0_WatchLo; |
217 | int32_t CP0_WatchHi; | |
218 | target_ulong CP0_XContext; | |
219 | int32_t CP0_Framemask; | |
220 | int32_t CP0_Debug; | |
6af0bf9c FB |
221 | #define CPDB_DBD 31 |
222 | #define CP0DB_DM 30 | |
223 | #define CP0DB_LSNM 28 | |
224 | #define CP0DB_Doze 27 | |
225 | #define CP0DB_Halt 26 | |
226 | #define CP0DB_CNT 25 | |
227 | #define CP0DB_IBEP 24 | |
228 | #define CP0DB_DBEP 21 | |
229 | #define CP0DB_IEXI 20 | |
230 | #define CP0DB_VER 15 | |
231 | #define CP0DB_DEC 10 | |
232 | #define CP0DB_SSt 8 | |
233 | #define CP0DB_DINT 5 | |
234 | #define CP0DB_DIB 4 | |
235 | #define CP0DB_DDBS 3 | |
236 | #define CP0DB_DDBL 2 | |
237 | #define CP0DB_DBp 1 | |
238 | #define CP0DB_DSS 0 | |
c570fd16 | 239 | target_ulong CP0_DEPC; |
9c2149c8 TS |
240 | int32_t CP0_Performance0; |
241 | int32_t CP0_TagLo; | |
242 | int32_t CP0_DataLo; | |
243 | int32_t CP0_TagHi; | |
244 | int32_t CP0_DataHi; | |
c570fd16 | 245 | target_ulong CP0_ErrorEPC; |
9c2149c8 | 246 | int32_t CP0_DESAVE; |
6af0bf9c | 247 | /* Qemu */ |
6af0bf9c FB |
248 | int interrupt_request; |
249 | jmp_buf jmp_env; | |
250 | int exception_index; | |
251 | int error_code; | |
252 | int user_mode_only; /* user mode only simulation */ | |
253 | uint32_t hflags; /* CPU State */ | |
254 | /* TMASK defines different execution modes */ | |
56b19403 | 255 | #define MIPS_HFLAG_TMASK 0x007F |
6af0bf9c FB |
256 | #define MIPS_HFLAG_MODE 0x001F /* execution modes */ |
257 | #define MIPS_HFLAG_UM 0x0001 /* user mode */ | |
258 | #define MIPS_HFLAG_ERL 0x0002 /* Error mode */ | |
259 | #define MIPS_HFLAG_EXL 0x0004 /* Exception mode */ | |
260 | #define MIPS_HFLAG_DM 0x0008 /* Debug mode */ | |
261 | #define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */ | |
262 | #define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */ | |
4ad40f36 FB |
263 | /* If translation is interrupted between the branch instruction and |
264 | * the delay slot, record what type of branch it is so that we can | |
265 | * resume translation properly. It might be possible to reduce | |
266 | * this from three bits to two. */ | |
267 | #define MIPS_HFLAG_BMASK 0x0380 | |
268 | #define MIPS_HFLAG_B 0x0080 /* Unconditional branch */ | |
269 | #define MIPS_HFLAG_BC 0x0100 /* Conditional branch */ | |
270 | #define MIPS_HFLAG_BL 0x0180 /* Likely branch */ | |
271 | #define MIPS_HFLAG_BR 0x0200 /* branch to register (can't link TB) */ | |
6af0bf9c FB |
272 | target_ulong btarget; /* Jump / branch target */ |
273 | int bcond; /* Branch condition (if needed) */ | |
a316d335 | 274 | |
4ad40f36 FB |
275 | int halted; /* TRUE if the CPU is in suspend state */ |
276 | ||
7a387fff TS |
277 | int SYNCI_Step; /* Address step size for SYNCI */ |
278 | int CCRes; /* Cycle count resolution/divisor */ | |
279 | ||
a316d335 | 280 | CPU_COMMON |
6ae81775 TS |
281 | |
282 | int ram_size; | |
283 | const char *kernel_filename; | |
284 | const char *kernel_cmdline; | |
285 | const char *initrd_filename; | |
286 | ||
287 | struct QEMUTimer *timer; /* Internal timer */ | |
6af0bf9c FB |
288 | }; |
289 | ||
290 | #include "cpu-all.h" | |
291 | ||
292 | /* Memory access type : | |
293 | * may be needed for precise access rights control and precise exceptions. | |
294 | */ | |
295 | enum { | |
296 | /* 1 bit to define user level / supervisor access */ | |
297 | ACCESS_USER = 0x00, | |
298 | ACCESS_SUPER = 0x01, | |
299 | /* 1 bit to indicate direction */ | |
300 | ACCESS_STORE = 0x02, | |
301 | /* Type of instruction that generated the access */ | |
302 | ACCESS_CODE = 0x10, /* Code fetch access */ | |
303 | ACCESS_INT = 0x20, /* Integer load/store access */ | |
304 | ACCESS_FLOAT = 0x30, /* floating point load/store access */ | |
305 | }; | |
306 | ||
307 | /* Exceptions */ | |
308 | enum { | |
309 | EXCP_NONE = -1, | |
310 | EXCP_RESET = 0, | |
311 | EXCP_SRESET, | |
312 | EXCP_DSS, | |
313 | EXCP_DINT, | |
314 | EXCP_NMI, | |
315 | EXCP_MCHECK, | |
316 | EXCP_EXT_INTERRUPT, | |
317 | EXCP_DFWATCH, | |
318 | EXCP_DIB, /* 8 */ | |
319 | EXCP_IWATCH, | |
320 | EXCP_AdEL, | |
321 | EXCP_AdES, | |
322 | EXCP_TLBF, | |
323 | EXCP_IBE, | |
324 | EXCP_DBp, | |
325 | EXCP_SYSCALL, | |
4ad40f36 FB |
326 | EXCP_BREAK, /* 16 */ |
327 | EXCP_CpU, | |
6af0bf9c FB |
328 | EXCP_RI, |
329 | EXCP_OVERFLOW, | |
330 | EXCP_TRAP, | |
331 | EXCP_DDBS, | |
332 | EXCP_DWATCH, | |
4ad40f36 FB |
333 | EXCP_LAE, |
334 | EXCP_SAE, /* 24 */ | |
6af0bf9c FB |
335 | EXCP_LTLBL, |
336 | EXCP_TLBL, | |
337 | EXCP_TLBS, | |
338 | EXCP_DBE, | |
339 | EXCP_DDBL, | |
340 | EXCP_MTCP0 = 0x104, /* mtmsr instruction: */ | |
341 | /* may change privilege level */ | |
342 | EXCP_BRANCH = 0x108, /* branch instruction */ | |
343 | EXCP_ERET = 0x10C, /* return from interrupt */ | |
344 | EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */ | |
345 | EXCP_FLUSH = 0x109, | |
346 | }; | |
347 | ||
6af0bf9c FB |
348 | int cpu_mips_exec(CPUMIPSState *s); |
349 | CPUMIPSState *cpu_mips_init(void); | |
350 | uint32_t cpu_mips_get_clock (void); | |
351 | ||
352 | #endif /* !defined (__MIPS_CPU_H__) */ |