[qemu.git] / target-mips / helper.c

/*
 *  MIPS emulation helpers for qemu.
 * 
 *  Copyright (c) 2004-2005 Jocelyn Mayer
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <signal.h>
#include <assert.h>

#include "cpu.h"
#include "exec-all.h"

enum {
    TLBRET_DIRTY = -4,
    TLBRET_INVALID = -3,
    TLBRET_NOMATCH = -2,
    TLBRET_BADADDR = -1,
    TLBRET_MATCH = 0
};

/* MIPS32 4K MMU emulation */
#ifdef MIPS_USES_R4K_TLB
static int map_address (CPUState *env, target_ulong *physical, int *prot,
                        target_ulong address, int rw, int access_type)
{
    uint8_t ASID = env->CP0_EntryHi & 0xFF;
    int i;

    for (i = 0; i < env->tlb_in_use; i++) {
        tlb_t *tlb = &env->tlb[i];
        /* 1k pages are not supported. */
        target_ulong mask = tlb->PageMask | 0x1FFF;
        target_ulong tag = address & ~mask;
        int n;

        /* Check ASID, virtual page number & size */
        if ((tlb->G == 1 || tlb->ASID == ASID) &&
            tlb->VPN == tag) {
            /* TLB match */
            n = !!(address & mask & ~(mask >> 1));
            /* Check access rights */
           if (!(n ? tlb->V1 : tlb->V0))
                return TLBRET_INVALID;
           if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
                *physical = tlb->PFN[n] | (address & (mask >> 1));
                *prot = PAGE_READ;
                if (n ? tlb->D1 : tlb->D0)
                    *prot |= PAGE_WRITE;
                return TLBRET_MATCH;
            }
            return TLBRET_DIRTY;
        }
    }
    return TLBRET_NOMATCH;
}
#endif

static int get_physical_address (CPUState *env, target_ulong *physical,
                                int *prot, target_ulong address,
                                int rw, int access_type)
{
    /* User mode can only access useg */
    int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
    int ret = TLBRET_MATCH;

#if 0
    if (logfile) {
        fprintf(logfile, "user mode %d h %08x\n",
                user_mode, env->hflags);
    }
#endif
    if (user_mode && address > 0x7FFFFFFFUL)
        return TLBRET_BADADDR;
    if (address < (int32_t)0x80000000UL) {
        if (!(env->CP0_Status & (1 << CP0St_ERL))) {
#ifdef MIPS_USES_R4K_TLB
            ret = map_address(env, physical, prot, address, rw, access_type);
#else
            *physical = address + 0x40000000UL;
            *prot = PAGE_READ | PAGE_WRITE;
#endif
        } else {
            *physical = address;
            *prot = PAGE_READ | PAGE_WRITE;
        }
    } else if (address < (int32_t)0xA0000000UL) {
        /* kseg0 */
        /* XXX: check supervisor mode */
        *physical = address - (int32_t)0x80000000UL;
        *prot = PAGE_READ | PAGE_WRITE;
    } else if (address < (int32_t)0xC0000000UL) {
        /* kseg1 */
        /* XXX: check supervisor mode */
        *physical = address - (int32_t)0xA0000000UL;
        *prot = PAGE_READ | PAGE_WRITE;
    } else if (address < (int32_t)0xE0000000UL) {
        /* kseg2 */
#ifdef MIPS_USES_R4K_TLB
        ret = map_address(env, physical, prot, address, rw, access_type);
#else
        *physical = address;
        *prot = PAGE_READ | PAGE_WRITE;
#endif
    } else {
        /* kseg3 */
        /* XXX: check supervisor mode */
        /* XXX: debug segment is not emulated */
#ifdef MIPS_USES_R4K_TLB
        ret = map_address(env, physical, prot, address, rw, access_type);
#else
        *physical = address;
        *prot = PAGE_READ | PAGE_WRITE;
#endif
    }
#if 0
    if (logfile) {
        fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
		address, rw, access_type, *physical, *prot, ret);
    }
#endif

    return ret;
}

#if defined(CONFIG_USER_ONLY) 
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
    return addr;
}
#else
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
    target_ulong phys_addr;
    int prot;

    if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
        return -1;
    return phys_addr;
}

void cpu_mips_init_mmu (CPUState *env)
{
}
#endif /* !defined(CONFIG_USER_ONLY) */

int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                               int is_user, int is_softmmu)
{
    target_ulong physical;
    int prot;
    int exception = 0, error_code = 0;
    int access_type;
    int ret = 0;

    if (logfile) {
#if 0
        cpu_dump_state(env, logfile, fprintf, 0);
#endif
        fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d is_user %d smmu %d\n",
                __func__, env->PC, address, rw, is_user, is_softmmu);
    }

    rw &= 1;

    /* data access */
    /* XXX: put correct access by using cpu_restore_state()
       correctly */
    access_type = ACCESS_INT;
    if (env->user_mode_only) {
        /* user mode only emulation */
        ret = TLBRET_NOMATCH;
        goto do_fault;
    }
    ret = get_physical_address(env, &physical, &prot,
                               address, rw, access_type);
    if (logfile) {
        fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n",
                __func__, address, ret, physical, prot);
    }
    if (ret == TLBRET_MATCH) {
       ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
                          physical & TARGET_PAGE_MASK, prot,
                          is_user, is_softmmu);
    } else if (ret < 0) {
    do_fault:
        switch (ret) {
        default:
        case TLBRET_BADADDR:
            /* Reference to kernel address from user mode or supervisor mode */
            /* Reference to supervisor address from user mode */
            if (rw)
                exception = EXCP_AdES;
            else
                exception = EXCP_AdEL;
            break;
        case TLBRET_NOMATCH:
            /* No TLB match for a mapped address */
            if (rw)
                exception = EXCP_TLBS;
            else
                exception = EXCP_TLBL;
            error_code = 1;
            break;
        case TLBRET_INVALID:
            /* TLB match with no valid bit */
            if (rw)
                exception = EXCP_TLBS;
            else
                exception = EXCP_TLBL;
            break;
        case TLBRET_DIRTY:
            /* TLB match but 'D' bit is cleared */
            exception = EXCP_LTLBL;
            break;
                
        }
        /* Raise exception */
        env->CP0_BadVAddr = address;
        env->CP0_Context = (env->CP0_Context & 0xff800000) |
	                   ((address >> 9) &   0x007ffff0);
        env->CP0_EntryHi =
            (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
        env->exception_index = exception;
        env->error_code = error_code;
        ret = 1;
    }

    return ret;
}

#if defined(CONFIG_USER_ONLY)
void do_interrupt (CPUState *env)
{
    env->exception_index = EXCP_NONE;
}
#else
void do_interrupt (CPUState *env)
{
    target_ulong offset;
    int cause = -1;

    if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
        fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n",
                __func__, env->PC, env->CP0_EPC, cause, env->exception_index);
    }
    if (env->exception_index == EXCP_EXT_INTERRUPT &&
        (env->hflags & MIPS_HFLAG_DM))
        env->exception_index = EXCP_DINT;
    offset = 0x180;
    switch (env->exception_index) {
    case EXCP_DSS:
        env->CP0_Debug |= 1 << CP0DB_DSS;
        /* Debug single step cannot be raised inside a delay slot and
         * resume will always occur on the next instruction
         * (but we assume the pc has always been updated during
         *  code translation).
         */
        env->CP0_DEPC = env->PC;
        goto enter_debug_mode;
    case EXCP_DINT:
        env->CP0_Debug |= 1 << CP0DB_DINT;
        goto set_DEPC;
    case EXCP_DIB:
        env->CP0_Debug |= 1 << CP0DB_DIB;
        goto set_DEPC;
    case EXCP_DBp:
        env->CP0_Debug |= 1 << CP0DB_DBp;
        goto set_DEPC;
    case EXCP_DDBS:
        env->CP0_Debug |= 1 << CP0DB_DDBS;
        goto set_DEPC;
    case EXCP_DDBL:
        env->CP0_Debug |= 1 << CP0DB_DDBL;
    set_DEPC:
        if (env->hflags & MIPS_HFLAG_BMASK) {
            /* If the exception was raised from a delay slot,
               come back to the jump.  */
            env->CP0_DEPC = env->PC - 4;
            env->hflags &= ~MIPS_HFLAG_BMASK;
        } else {
            env->CP0_DEPC = env->PC;
        }
    enter_debug_mode:
        env->hflags |= MIPS_HFLAG_DM;
        env->hflags &= ~MIPS_HFLAG_UM;
        /* EJTAG probe trap enable is not implemented... */
        if (!(env->CP0_Status & (1 << CP0St_EXL)))
            env->CP0_Cause &= ~(1 << CP0Ca_BD);
        env->PC = (int32_t)0xBFC00480;
        break;
    case EXCP_RESET:
        cpu_reset(env);
        break;
    case EXCP_SRESET:
        env->CP0_Status |= (1 << CP0St_SR);
        env->CP0_WatchLo = 0;
        goto set_error_EPC;
    case EXCP_NMI:
        env->CP0_Status |= (1 << CP0St_NMI);
    set_error_EPC:
        if (env->hflags & MIPS_HFLAG_BMASK) {
            /* If the exception was raised from a delay slot,
               come back to the jump.  */
            env->CP0_ErrorEPC = env->PC - 4;
            env->hflags &= ~MIPS_HFLAG_BMASK;
        } else {
            env->CP0_ErrorEPC = env->PC;
        }
        env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
        env->hflags &= ~MIPS_HFLAG_UM;
        if (!(env->CP0_Status & (1 << CP0St_EXL)))
            env->CP0_Cause &= ~(1 << CP0Ca_BD);
        env->PC = (int32_t)0xBFC00000;
        break;
    case EXCP_MCHECK:
        cause = 24;
        goto set_EPC;
    case EXCP_EXT_INTERRUPT:
        cause = 0;
        if (env->CP0_Cause & (1 << CP0Ca_IV))
            offset = 0x200;
        goto set_EPC;
    case EXCP_DWATCH:
        cause = 23;
        /* XXX: TODO: manage defered watch exceptions */
        goto set_EPC;
    case EXCP_AdEL:
        cause = 4;
        goto set_EPC;
    case EXCP_AdES:
        cause = 5;
        goto set_EPC;
    case EXCP_TLBL:
        cause = 2;
        if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL)))
            offset = 0x000;
        goto set_EPC;
    case EXCP_IBE:
        cause = 6;
        goto set_EPC;
    case EXCP_DBE:
        cause = 7;
        goto set_EPC;
    case EXCP_SYSCALL:
        cause = 8;
        goto set_EPC;
    case EXCP_BREAK:
        cause = 9;
        goto set_EPC;
    case EXCP_RI:
        cause = 10;
        goto set_EPC;
    case EXCP_CpU:
        cause = 11;
        env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
                         (env->error_code << CP0Ca_CE);
        goto set_EPC;
    case EXCP_OVERFLOW:
        cause = 12;
        goto set_EPC;
    case EXCP_TRAP:
        cause = 13;
        goto set_EPC;
    case EXCP_FPE:
        cause = 15;
        goto set_EPC;
    case EXCP_LTLBL:
        cause = 1;
        goto set_EPC;
    case EXCP_TLBS:
        cause = 3;
        if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL)))
            offset = 0x000;
    set_EPC:
        if (!(env->CP0_Status & (1 << CP0St_EXL))) {
            if (env->hflags & MIPS_HFLAG_BMASK) {
                /* If the exception was raised from a delay slot,
                   come back to the jump.  */
                env->CP0_EPC = env->PC - 4;
                env->CP0_Cause |= (1 << CP0Ca_BD);
            } else {
                env->CP0_EPC = env->PC;
                env->CP0_Cause &= ~(1 << CP0Ca_BD);
            }
            env->CP0_Status |= (1 << CP0St_EXL);
            env->hflags &= ~MIPS_HFLAG_UM;
        }
        env->hflags &= ~MIPS_HFLAG_BMASK;
        if (env->CP0_Status & (1 << CP0St_BEV)) {
            env->PC = (int32_t)0xBFC00200;
        } else {
            env->PC = (int32_t)(env->CP0_EBase & ~0x3ff);
        }
        env->PC += offset;
        env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
        break;
    default:
        if (logfile) {
            fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
                    env->exception_index);
        }
        printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
        exit(1);
    }
    if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
        fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n"
                "    S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
                __func__, env->PC, env->CP0_EPC, cause, env->exception_index,
                env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
                env->CP0_DEPC);
    }
    env->exception_index = EXCP_NONE;
}
#endif /* !defined(CONFIG_USER_ONLY) */

void invalidate_tlb (CPUState *env, int idx, int use_extra)
{
    tlb_t *tlb;
    target_ulong addr;
    target_ulong end;
    uint8_t ASID = env->CP0_EntryHi & 0xFF;
    target_ulong mask;

    tlb = &env->tlb[idx];
    /* The qemu TLB is flushed then the ASID changes, so no need to
       flush these entries again.  */
    if (tlb->G == 0 && tlb->ASID != ASID) {
        return;
    }

    if (use_extra && env->tlb_in_use < MIPS_TLB_MAX) {
        /* For tlbwr, we can shadow the discarded entry into
	   a new (fake) TLB entry, as long as the guest can not
	   tell that it's there.  */
        env->tlb[env->tlb_in_use] = *tlb;
        env->tlb_in_use++;
        return;
    }

    /* 1k pages are not supported. */
    mask = tlb->PageMask | 0x1FFF;
    if (tlb->V0) {
        addr = tlb->VPN;
        end = addr | (mask >> 1);
        while (addr < end) {
            tlb_flush_page (env, addr);
            addr += TARGET_PAGE_SIZE;
        }
    }
    if (tlb->V1) {
        addr = tlb->VPN | ((mask >> 1) + 1);
        addr = tlb->VPN + TARGET_PAGE_SIZE;
        end = addr | mask;
        while (addr < end) {
            tlb_flush_page (env, addr);
            addr += TARGET_PAGE_SIZE;
        }
    }
}
Commit	Line	Data
6af0bf9c FB	1	/*
	2	* MIPS emulation helpers for qemu.
	3	*
	4	* Copyright (c) 2004-2005 Jocelyn Mayer
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
e37e863f FB	20	#include <stdarg.h>
	21	#include <stdlib.h>
	22	#include <stdio.h>
	23	#include <string.h>
	24	#include <inttypes.h>
	25	#include <signal.h>
	26	#include <assert.h>
	27
	28	#include "cpu.h"
	29	#include "exec-all.h"
6af0bf9c	30
43057ab1 FB	31	enum {
	32	TLBRET_DIRTY = -4,
	33	TLBRET_INVALID = -3,
	34	TLBRET_NOMATCH = -2,
	35	TLBRET_BADADDR = -1,
	36	TLBRET_MATCH = 0
	37	};
	38
6af0bf9c	39	/* MIPS32 4K MMU emulation */
9fb63ac2	40	#ifdef MIPS_USES_R4K_TLB
6af0bf9c FB	41	static int map_address (CPUState env, target_ulong physical, int *prot,
	42	target_ulong address, int rw, int access_type)
	43	{
925fd0f2	44	uint8_t ASID = env->CP0_EntryHi & 0xFF;
3b1c8be4	45	int i;
6af0bf9c	46
814b9a47	47	for (i = 0; i < env->tlb_in_use; i++) {
3b1c8be4 TS	48	tlb_t *tlb = &env->tlb[i];
3b1c8be4 TS	49	/* 1k pages are not supported. */
3b1c8be4 TS	50	target_ulong mask = tlb->PageMask \| 0x1FFF;
	51	target_ulong tag = address & ~mask;
	52	int n;
	53
6af0bf9c FB	54	/* Check ASID, virtual page number & size */
6af0bf9c FB	55	if ((tlb->G == 1 \|\| tlb->ASID == ASID) &&
bc814401	56	tlb->VPN == tag) {
6af0bf9c	57	/* TLB match */
3b1c8be4	58	n = !!(address & mask & ~(mask >> 1));
6af0bf9c	59	/* Check access rights */
43057ab1 FB	60	if (!(n ? tlb->V1 : tlb->V0))
	61	return TLBRET_INVALID;
	62	if (rw == 0 \|\| (n ? tlb->D1 : tlb->D0)) {
3b1c8be4	63	*physical = tlb->PFN[n] \| (address & (mask >> 1));
9fb63ac2	64	*prot = PAGE_READ;
98c1b82b	65	if (n ? tlb->D1 : tlb->D0)
9fb63ac2	66	*prot \|= PAGE_WRITE;
43057ab1	67	return TLBRET_MATCH;
6af0bf9c	68	}
43057ab1	69	return TLBRET_DIRTY;
6af0bf9c FB	70	}
6af0bf9c FB	71	}
43057ab1	72	return TLBRET_NOMATCH;
6af0bf9c FB	73	}
	74	#endif
	75
43057ab1 FB	76	static int get_physical_address (CPUState env, target_ulong physical,
	77	int *prot, target_ulong address,
	78	int rw, int access_type)
6af0bf9c	79	{
6af0bf9c	80	/* User mode can only access useg */
43057ab1 FB	81	int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
	82	int ret = TLBRET_MATCH;
	83
6af0bf9c FB	84	#if 0
	85	if (logfile) {
	86	fprintf(logfile, "user mode %d h %08x\n",
	87	user_mode, env->hflags);
	88	}
	89	#endif
	90	if (user_mode && address > 0x7FFFFFFFUL)
43057ab1	91	return TLBRET_BADADDR;
5dc4b744	92	if (address < (int32_t)0x80000000UL) {
24c7b0e3	93	if (!(env->CP0_Status & (1 << CP0St_ERL))) {
9fb63ac2 FB	94	#ifdef MIPS_USES_R4K_TLB
9fb63ac2 FB	95	ret = map_address(env, physical, prot, address, rw, access_type);
6af0bf9c FB	96	#else
	97	*physical = address + 0x40000000UL;
	98	*prot = PAGE_READ \| PAGE_WRITE;
	99	#endif
	100	} else {
	101	*physical = address;
	102	*prot = PAGE_READ \| PAGE_WRITE;
	103	}
5dc4b744	104	} else if (address < (int32_t)0xA0000000UL) {
6af0bf9c FB	105	/* kseg0 */
6af0bf9c FB	106	/* XXX: check supervisor mode */
5dc4b744	107	*physical = address - (int32_t)0x80000000UL;
6af0bf9c	108	*prot = PAGE_READ \| PAGE_WRITE;
5dc4b744	109	} else if (address < (int32_t)0xC0000000UL) {
6af0bf9c FB	110	/* kseg1 */
6af0bf9c FB	111	/* XXX: check supervisor mode */
5dc4b744	112	*physical = address - (int32_t)0xA0000000UL;
6af0bf9c	113	*prot = PAGE_READ \| PAGE_WRITE;
5dc4b744	114	} else if (address < (int32_t)0xE0000000UL) {
6af0bf9c	115	/* kseg2 */
9fb63ac2 FB	116	#ifdef MIPS_USES_R4K_TLB
9fb63ac2 FB	117	ret = map_address(env, physical, prot, address, rw, access_type);
6af0bf9c FB	118	#else
	119	*physical = address;
	120	*prot = PAGE_READ \| PAGE_WRITE;
	121	#endif
	122	} else {
	123	/* kseg3 */
	124	/* XXX: check supervisor mode */
	125	/* XXX: debug segment is not emulated */
9fb63ac2 FB	126	#ifdef MIPS_USES_R4K_TLB
9fb63ac2 FB	127	ret = map_address(env, physical, prot, address, rw, access_type);
6af0bf9c FB	128	#else
	129	*physical = address;
	130	*prot = PAGE_READ \| PAGE_WRITE;
	131	#endif
	132	}
	133	#if 0
	134	if (logfile) {
3594c774	135	fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
c570fd16	136	address, rw, access_type, physical, prot, ret);
6af0bf9c FB	137	}
	138	#endif
	139
	140	return ret;
	141	}
	142
	143	#if defined(CONFIG_USER_ONLY)
9b3c35e0	144	target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
6af0bf9c FB	145	{
	146	return addr;
	147	}
	148	#else
9b3c35e0	149	target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
6af0bf9c FB	150	{
	151	target_ulong phys_addr;
	152	int prot;
	153
	154	if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
	155	return -1;
	156	return phys_addr;
	157	}
6af0bf9c FB	158
	159	void cpu_mips_init_mmu (CPUState *env)
	160	{
	161	}
6af0bf9c FB	162	#endif /* !defined(CONFIG_USER_ONLY) */
	163
	164	int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
	165	int is_user, int is_softmmu)
	166	{
	167	target_ulong physical;
	168	int prot;
	169	int exception = 0, error_code = 0;
	170	int access_type;
	171	int ret = 0;
	172
	173	if (logfile) {
4ad40f36	174	#if 0
6af0bf9c	175	cpu_dump_state(env, logfile, fprintf, 0);
4ad40f36	176	#endif
3594c774	177	fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d is_user %d smmu %d\n",
6af0bf9c FB	178	__func__, env->PC, address, rw, is_user, is_softmmu);
6af0bf9c FB	179	}
4ad40f36 FB	180
	181	rw &= 1;
	182
6af0bf9c FB	183	/* data access */
	184	/* XXX: put correct access by using cpu_restore_state()
	185	correctly */
	186	access_type = ACCESS_INT;
	187	if (env->user_mode_only) {
	188	/* user mode only emulation */
43057ab1	189	ret = TLBRET_NOMATCH;
6af0bf9c FB	190	goto do_fault;
	191	}
	192	ret = get_physical_address(env, &physical, &prot,
	193	address, rw, access_type);
	194	if (logfile) {
3594c774	195	fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n",
6af0bf9c FB	196	__func__, address, ret, physical, prot);
6af0bf9c FB	197	}
43057ab1 FB	198	if (ret == TLBRET_MATCH) {
	199	ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
	200	physical & TARGET_PAGE_MASK, prot,
	201	is_user, is_softmmu);
6af0bf9c FB	202	} else if (ret < 0) {
	203	do_fault:
	204	switch (ret) {
	205	default:
43057ab1	206	case TLBRET_BADADDR:
6af0bf9c FB	207	/* Reference to kernel address from user mode or supervisor mode */
	208	/* Reference to supervisor address from user mode */
	209	if (rw)
	210	exception = EXCP_AdES;
	211	else
	212	exception = EXCP_AdEL;
	213	break;
43057ab1	214	case TLBRET_NOMATCH:
6af0bf9c FB	215	/* No TLB match for a mapped address */
	216	if (rw)
	217	exception = EXCP_TLBS;
	218	else
	219	exception = EXCP_TLBL;
	220	error_code = 1;
	221	break;
43057ab1	222	case TLBRET_INVALID:
6af0bf9c FB	223	/* TLB match with no valid bit */
	224	if (rw)
	225	exception = EXCP_TLBS;
	226	else
	227	exception = EXCP_TLBL;
6af0bf9c	228	break;
43057ab1	229	case TLBRET_DIRTY:
6af0bf9c FB	230	/* TLB match but 'D' bit is cleared */
	231	exception = EXCP_LTLBL;
	232	break;
	233
	234	}
6af0bf9c FB	235	/* Raise exception */
6af0bf9c FB	236	env->CP0_BadVAddr = address;
85498508	237	env->CP0_Context = (env->CP0_Context & 0xff800000) \|
4ad40f36	238	((address >> 9) & 0x007ffff0);
6af0bf9c	239	env->CP0_EntryHi =
43057ab1	240	(env->CP0_EntryHi & 0xFF) \| (address & (TARGET_PAGE_MASK << 1));
6af0bf9c FB	241	env->exception_index = exception;
	242	env->error_code = error_code;
	243	ret = 1;
	244	}
	245
	246	return ret;
	247	}
	248
ca7c2b1b TS	249	#if defined(CONFIG_USER_ONLY)
	250	void do_interrupt (CPUState *env)
	251	{
	252	env->exception_index = EXCP_NONE;
	253	}
	254	#else
6af0bf9c FB	255	void do_interrupt (CPUState *env)
6af0bf9c FB	256	{
aa328add	257	target_ulong offset;
6af0bf9c FB	258	int cause = -1;
	259
	260	if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
3594c774	261	fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n",
6af0bf9c FB	262	__func__, env->PC, env->CP0_EPC, cause, env->exception_index);
	263	}
	264	if (env->exception_index == EXCP_EXT_INTERRUPT &&
	265	(env->hflags & MIPS_HFLAG_DM))
	266	env->exception_index = EXCP_DINT;
	267	offset = 0x180;
	268	switch (env->exception_index) {
	269	case EXCP_DSS:
	270	env->CP0_Debug \|= 1 << CP0DB_DSS;
	271	/* Debug single step cannot be raised inside a delay slot and
	272	* resume will always occur on the next instruction
	273	* (but we assume the pc has always been updated during
	274	* code translation).
	275	*/
	276	env->CP0_DEPC = env->PC;
	277	goto enter_debug_mode;
	278	case EXCP_DINT:
	279	env->CP0_Debug \|= 1 << CP0DB_DINT;
	280	goto set_DEPC;
	281	case EXCP_DIB:
	282	env->CP0_Debug \|= 1 << CP0DB_DIB;
	283	goto set_DEPC;
	284	case EXCP_DBp:
	285	env->CP0_Debug \|= 1 << CP0DB_DBp;
	286	goto set_DEPC;
	287	case EXCP_DDBS:
	288	env->CP0_Debug \|= 1 << CP0DB_DDBS;
	289	goto set_DEPC;
	290	case EXCP_DDBL:
	291	env->CP0_Debug \|= 1 << CP0DB_DDBL;
6af0bf9c	292	set_DEPC:
4ad40f36	293	if (env->hflags & MIPS_HFLAG_BMASK) {
6af0bf9c	294	/* If the exception was raised from a delay slot,
aa328add	295	come back to the jump. */
6af0bf9c	296	env->CP0_DEPC = env->PC - 4;
4ad40f36	297	env->hflags &= ~MIPS_HFLAG_BMASK;
6af0bf9c FB	298	} else {
	299	env->CP0_DEPC = env->PC;
	300	}
	301	enter_debug_mode:
	302	env->hflags \|= MIPS_HFLAG_DM;
24c7b0e3	303	env->hflags &= ~MIPS_HFLAG_UM;
6af0bf9c	304	/* EJTAG probe trap enable is not implemented... */
0a6de750 TS	305	if (!(env->CP0_Status & (1 << CP0St_EXL)))
0a6de750 TS	306	env->CP0_Cause &= ~(1 << CP0Ca_BD);
5dc4b744	307	env->PC = (int32_t)0xBFC00480;
6af0bf9c FB	308	break;
6af0bf9c FB	309	case EXCP_RESET:
aa328add TS	310	cpu_reset(env);
aa328add TS	311	break;
6af0bf9c	312	case EXCP_SRESET:
24c7b0e3	313	env->CP0_Status \|= (1 << CP0St_SR);
6af0bf9c FB	314	env->CP0_WatchLo = 0;
	315	goto set_error_EPC;
	316	case EXCP_NMI:
24c7b0e3	317	env->CP0_Status \|= (1 << CP0St_NMI);
6af0bf9c	318	set_error_EPC:
4ad40f36	319	if (env->hflags & MIPS_HFLAG_BMASK) {
6af0bf9c	320	/* If the exception was raised from a delay slot,
aa328add	321	come back to the jump. */
6af0bf9c	322	env->CP0_ErrorEPC = env->PC - 4;
ecd78a0a	323	env->hflags &= ~MIPS_HFLAG_BMASK;
6af0bf9c FB	324	} else {
	325	env->CP0_ErrorEPC = env->PC;
	326	}
24c7b0e3 TS	327	env->CP0_Status \|= (1 << CP0St_ERL) \| (1 << CP0St_BEV);
24c7b0e3 TS	328	env->hflags &= ~MIPS_HFLAG_UM;
0a6de750 TS	329	if (!(env->CP0_Status & (1 << CP0St_EXL)))
0a6de750 TS	330	env->CP0_Cause &= ~(1 << CP0Ca_BD);
5dc4b744	331	env->PC = (int32_t)0xBFC00000;
6af0bf9c FB	332	break;
	333	case EXCP_MCHECK:
	334	cause = 24;
	335	goto set_EPC;
	336	case EXCP_EXT_INTERRUPT:
	337	cause = 0;
	338	if (env->CP0_Cause & (1 << CP0Ca_IV))
	339	offset = 0x200;
	340	goto set_EPC;
	341	case EXCP_DWATCH:
	342	cause = 23;
	343	/* XXX: TODO: manage defered watch exceptions */
	344	goto set_EPC;
	345	case EXCP_AdEL:
6af0bf9c FB	346	cause = 4;
6af0bf9c FB	347	goto set_EPC;
beb811bd TS	348	case EXCP_AdES:
	349	cause = 5;
	350	goto set_EPC;
6af0bf9c	351	case EXCP_TLBL:
6af0bf9c	352	cause = 2;
24c7b0e3	353	if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL)))
6af0bf9c FB	354	offset = 0x000;
	355	goto set_EPC;
	356	case EXCP_IBE:
	357	cause = 6;
	358	goto set_EPC;
	359	case EXCP_DBE:
	360	cause = 7;
	361	goto set_EPC;
	362	case EXCP_SYSCALL:
	363	cause = 8;
	364	goto set_EPC;
	365	case EXCP_BREAK:
	366	cause = 9;
	367	goto set_EPC;
	368	case EXCP_RI:
	369	cause = 10;
	370	goto set_EPC;
	371	case EXCP_CpU:
	372	cause = 11;
39d51eb8 TS	373	env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) \|
39d51eb8 TS	374	(env->error_code << CP0Ca_CE);
6af0bf9c FB	375	goto set_EPC;
	376	case EXCP_OVERFLOW:
	377	cause = 12;
	378	goto set_EPC;
	379	case EXCP_TRAP:
	380	cause = 13;
	381	goto set_EPC;
5a5012ec TS	382	case EXCP_FPE:
	383	cause = 15;
	384	goto set_EPC;
6af0bf9c FB	385	case EXCP_LTLBL:
	386	cause = 1;
	387	goto set_EPC;
	388	case EXCP_TLBS:
	389	cause = 3;
24c7b0e3	390	if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL)))
0d8aca8c	391	offset = 0x000;
6af0bf9c	392	set_EPC:
24c7b0e3 TS	393	if (!(env->CP0_Status & (1 << CP0St_EXL))) {
	394	if (env->hflags & MIPS_HFLAG_BMASK) {
	395	/* If the exception was raised from a delay slot,
	396	come back to the jump. */
	397	env->CP0_EPC = env->PC - 4;
39d51eb8	398	env->CP0_Cause \|= (1 << CP0Ca_BD);
24c7b0e3 TS	399	} else {
	400	env->CP0_EPC = env->PC;
	401	env->CP0_Cause &= ~(1 << CP0Ca_BD);
	402	}
24c7b0e3 TS	403	env->CP0_Status \|= (1 << CP0St_EXL);
24c7b0e3 TS	404	env->hflags &= ~MIPS_HFLAG_UM;
6af0bf9c	405	}
c53f4a62	406	env->hflags &= ~MIPS_HFLAG_BMASK;
aa328add	407	if (env->CP0_Status & (1 << CP0St_BEV)) {
5dc4b744	408	env->PC = (int32_t)0xBFC00200;
aa328add	409	} else {
acd858d9	410	env->PC = (int32_t)(env->CP0_EBase & ~0x3ff);
aa328add	411	}
aa328add	412	env->PC += offset;
e58c8ba5	413	env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) \| (cause << CP0Ca_EC);
6af0bf9c FB	414	break;
	415	default:
	416	if (logfile) {
	417	fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
	418	env->exception_index);
	419	}
	420	printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
	421	exit(1);
	422	}
6af0bf9c	423	if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
3594c774 TS	424	fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n"
3594c774 TS	425	" S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
6af0bf9c FB	426	__func__, env->PC, env->CP0_EPC, cause, env->exception_index,
	427	env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
	428	env->CP0_DEPC);
	429	}
	430	env->exception_index = EXCP_NONE;
	431	}
ca7c2b1b	432	#endif /* !defined(CONFIG_USER_ONLY) */
2ee4aed8 FB	433
	434	void invalidate_tlb (CPUState *env, int idx, int use_extra)
	435	{
	436	tlb_t *tlb;
3b1c8be4 TS	437	target_ulong addr;
	438	target_ulong end;
	439	uint8_t ASID = env->CP0_EntryHi & 0xFF;
	440	target_ulong mask;
2ee4aed8 FB	441
	442	tlb = &env->tlb[idx];
	443	/* The qemu TLB is flushed then the ASID changes, so no need to
	444	flush these entries again. */
	445	if (tlb->G == 0 && tlb->ASID != ASID) {
	446	return;
	447	}
	448
	449	if (use_extra && env->tlb_in_use < MIPS_TLB_MAX) {
	450	/* For tlbwr, we can shadow the discarded entry into
	451	a new (fake) TLB entry, as long as the guest can not
	452	tell that it's there. */
	453	env->tlb[env->tlb_in_use] = *tlb;
	454	env->tlb_in_use++;
	455	return;
	456	}
	457
3b1c8be4 TS	458	/* 1k pages are not supported. */
	459	mask = tlb->PageMask \| 0x1FFF;
	460	if (tlb->V0) {
	461	addr = tlb->VPN;
	462	end = addr \| (mask >> 1);
	463	while (addr < end) {
	464	tlb_flush_page (env, addr);
	465	addr += TARGET_PAGE_SIZE;
	466	}
	467	}
	468	if (tlb->V1) {
	469	addr = tlb->VPN \| ((mask >> 1) + 1);
	470	addr = tlb->VPN + TARGET_PAGE_SIZE;
	471	end = addr \| mask;
	472	while (addr < end) {
	473	tlb_flush_page (env, addr);
	474	addr += TARGET_PAGE_SIZE;
	475	}
	476	}
2ee4aed8	477	}