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1 | #if !defined (__QEMU_MIPS_DEFS_H__) |
2 | #define __QEMU_MIPS_DEFS_H__ | |
3 | ||
4 | /* If we want to use 64 bits host regs... */ | |
5 | //#define USE_64BITS_REGS | |
6 | /* If we want to use host float regs... */ | |
7 | //#define USE_HOST_FLOAT_REGS | |
8 | ||
9 | enum { | |
10 | MIPS_R4Kc = 0x00018000, | |
11 | MIPS_R4Kp = 0x00018300, | |
12 | }; | |
13 | ||
14 | /* Emulate MIPS R4Kc for now */ | |
15 | #define MIPS_CPU MIPS_R4Kc | |
16 | ||
17 | #if (MIPS_CPU == MIPS_R4Kc) | |
18 | /* 32 bits target */ | |
19 | #define TARGET_LONG_BITS 32 | |
20 | /* real pages are variable size... */ | |
21 | #define TARGET_PAGE_BITS 12 | |
22 | /* Uses MIPS R4Kx ehancements to MIPS32 architecture */ | |
23 | #define MIPS_USES_R4K_EXT | |
24 | /* Uses MIPS R4Kc TLB model */ | |
25 | #define MIPS_USES_R4K_TLB | |
26 | #define MIPS_TLB_NB 16 | |
6ea83fed FB |
27 | /* basic FPU register support */ |
28 | #define MIPS_USES_FPU 1 | |
29 | /* Define a implementation number of 1. | |
30 | * Define a major version 1, minor version 0. | |
31 | */ | |
32 | #define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0) | |
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33 | /* Have config1, runs in big-endian mode, uses TLB */ |
34 | #define MIPS_CONFIG0 \ | |
35 | ((1 << CP0C0_M) | (0x000 << CP0C0_K23) | (0x000 << CP0C0_KU) | \ | |
36 | (1 << CP0C0_BE) | (0x001 << CP0C0_MT) | (0x010 << CP0C0_K0)) | |
37 | /* 16 TLBs, 64 sets Icache, 16 bytes Icache line, 2-way Icache, | |
38 | * 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache, | |
39 | * no performance counters, watch registers present, no code compression, | |
6ea83fed | 40 | * EJTAG present, FPU enable bit depending on MIPS_USES_FPU |
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41 | */ |
42 | #define MIPS_CONFIG1 \ | |
43 | ((15 << CP0C1_MMU) | \ | |
44 | (0x000 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x01 << CP0C1_IA) | \ | |
45 | (0x000 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x01 << CP0C1_DA) | \ | |
46 | (0 << CP0C1_PC) | (1 << CP0C1_WR) | (0 << CP0C1_CA) | \ | |
6ea83fed | 47 | (1 << CP0C1_EP) | (MIPS_USES_FPU << CP0C1_FP)) |
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48 | #elif defined (MIPS_CPU == MIPS_R4Kp) |
49 | /* 32 bits target */ | |
50 | #define TARGET_LONG_BITS 32 | |
51 | /* real pages are variable size... */ | |
52 | #define TARGET_PAGE_BITS 12 | |
53 | /* Uses MIPS R4Kx ehancements to MIPS32 architecture */ | |
54 | #define MIPS_USES_R4K_EXT | |
55 | /* Uses MIPS R4Km FPM MMU model */ | |
56 | #define MIPS_USES_R4K_FPM | |
57 | #else | |
58 | #error "MIPS CPU not defined" | |
59 | /* Remainder for other flags */ | |
60 | //#define TARGET_MIPS64 | |
6ea83fed | 61 | //#define MIPS_USES_FPU |
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62 | #endif |
63 | ||
64 | #endif /* !defined (__QEMU_MIPS_DEFS_H__) */ |