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Merge remote branch 'markus/qerror' into staging
[qemu.git] / target-mips / op_helper.c
CommitLineData
6af0bf9c
FB		 1/*
2 * MIPS emulation helpers for qemu.
5fafdf24 3 *
6af0bf9c
FB		 4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
6af0bf9c 18 */
2d0e944d 19#include <stdlib.h>
6af0bf9c
FB		 20#include "exec.h"
21
05f778c8
TS		 22#include "host-utils.h"
23
a7812ae4 24#include "helper.h"
6af0bf9c
FB		 25/*****************************************************************************/
26/* Exceptions processing helpers */
6af0bf9c 27
c01fccd2 28void helper_raise_exception_err (uint32_t exception, int error_code)
6af0bf9c
FB		 29{
30#if 1
93fcfe39
AL		 31 if (exception < 0x100)
32 qemu_log("%s: %d %d\n", __func__, exception, error_code);
6af0bf9c
FB		 33#endif
34 env->exception_index = exception;
35 env->error_code = error_code;
6af0bf9c
FB		 36 cpu_loop_exit();
37}
38
c01fccd2 39void helper_raise_exception (uint32_t exception)
6af0bf9c 40{
c01fccd2 41 helper_raise_exception_err(exception, 0);
6af0bf9c
FB		 42}
43
c01fccd2 44void helper_interrupt_restart (void)
48d38ca5
TS		 45{
46 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
47 !(env->CP0_Status & (1 << CP0St_ERL)) &&
48 !(env->hflags & MIPS_HFLAG_DM) &&
49 (env->CP0_Status & (1 << CP0St_IE)) &&
50 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
51 env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
c01fccd2 52 helper_raise_exception(EXCP_EXT_INTERRUPT);
48d38ca5
TS		 53 }
54}
55
f9480ffc
TS		 56#if !defined(CONFIG_USER_ONLY)
57static void do_restore_state (void *pc_ptr)
4ad40f36 58{
a607922c
FB		 59 TranslationBlock *tb;
60 unsigned long pc = (unsigned long) pc_ptr;
61
62 tb = tb_find_pc (pc);
63 if (tb) {
64 cpu_restore_state (tb, env, pc, NULL);
65 }
4ad40f36 66}
f9480ffc 67#endif
4ad40f36 68
0ae43045
AJ		 69#if defined(CONFIG_USER_ONLY)
70#define HELPER_LD(name, insn, type) \
71static inline type do_##name(target_ulong addr, int mem_idx) \
72{ \
73 return (type) insn##_raw(addr); \
74}
75#else
76#define HELPER_LD(name, insn, type) \
77static inline type do_##name(target_ulong addr, int mem_idx) \
78{ \
79 switch (mem_idx) \
80 { \
81 case 0: return (type) insn##_kernel(addr); break; \
82 case 1: return (type) insn##_super(addr); break; \
83 default: \
84 case 2: return (type) insn##_user(addr); break; \
85 } \
86}
87#endif
88HELPER_LD(lbu, ldub, uint8_t)
89HELPER_LD(lw, ldl, int32_t)
90#ifdef TARGET_MIPS64
91HELPER_LD(ld, ldq, int64_t)
92#endif
93#undef HELPER_LD
94
95#if defined(CONFIG_USER_ONLY)
96#define HELPER_ST(name, insn, type) \
97static inline void do_##name(target_ulong addr, type val, int mem_idx) \
98{ \
99 insn##_raw(addr, val); \
100}
101#else
102#define HELPER_ST(name, insn, type) \
103static inline void do_##name(target_ulong addr, type val, int mem_idx) \
104{ \
105 switch (mem_idx) \
106 { \
107 case 0: insn##_kernel(addr, val); break; \
108 case 1: insn##_super(addr, val); break; \
109 default: \
110 case 2: insn##_user(addr, val); break; \
111 } \
112}
113#endif
114HELPER_ST(sb, stb, uint8_t)
115HELPER_ST(sw, stl, uint32_t)
116#ifdef TARGET_MIPS64
117HELPER_ST(sd, stq, uint64_t)
118#endif
119#undef HELPER_ST
120
d9bea114 121target_ulong helper_clo (target_ulong arg1)
30898801 122{
d9bea114 123 return clo32(arg1);
30898801
TS		 124}
125
d9bea114 126target_ulong helper_clz (target_ulong arg1)
30898801 127{
d9bea114 128 return clz32(arg1);
30898801
TS		 129}
130
d26bc211 131#if defined(TARGET_MIPS64)
d9bea114 132target_ulong helper_dclo (target_ulong arg1)
05f778c8 133{
d9bea114 134 return clo64(arg1);
05f778c8
TS		 135}
136
d9bea114 137target_ulong helper_dclz (target_ulong arg1)
05f778c8 138{
d9bea114 139 return clz64(arg1);
05f778c8 140}
d26bc211 141#endif /* TARGET_MIPS64 */
c570fd16 142
6af0bf9c 143/* 64 bits arithmetic for 32 bits hosts */
c904ef0e 144static inline uint64_t get_HILO (void)
6af0bf9c 145{
b5dc7732 146 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
6af0bf9c
FB		 147}
148
c904ef0e 149static inline void set_HILO (uint64_t HILO)
6af0bf9c 150{
b5dc7732
TS		 151 env->active_tc.LO[0] = (int32_t)HILO;
152 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
6af0bf9c
FB		 153}
154
d9bea114 155static inline void set_HIT0_LO (target_ulong arg1, uint64_t HILO)
e9c71dd1 156{
b5dc7732 157 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
d9bea114 158 arg1 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
e9c71dd1
TS		 159}
160
d9bea114 161static inline void set_HI_LOT0 (target_ulong arg1, uint64_t HILO)
e9c71dd1 162{
d9bea114 163 arg1 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
b5dc7732 164 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
e9c71dd1
TS		 165}
166
e9c71dd1 167/* Multiplication variants of the vr54xx. */
d9bea114 168target_ulong helper_muls (target_ulong arg1, target_ulong arg2)
e9c71dd1 169{
d9bea114 170 set_HI_LOT0(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 171
d9bea114 172 return arg1;
e9c71dd1
TS		 173}
174
d9bea114 175target_ulong helper_mulsu (target_ulong arg1, target_ulong arg2)
e9c71dd1 176{
d9bea114 177 set_HI_LOT0(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 178
d9bea114 179 return arg1;
e9c71dd1
TS		 180}
181
d9bea114 182target_ulong helper_macc (target_ulong arg1, target_ulong arg2)
e9c71dd1 183{
d9bea114 184 set_HI_LOT0(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 185
d9bea114 186 return arg1;
e9c71dd1
TS		 187}
188
d9bea114 189target_ulong helper_macchi (target_ulong arg1, target_ulong arg2)
e9c71dd1 190{
d9bea114 191 set_HIT0_LO(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 192
d9bea114 193 return arg1;
e9c71dd1
TS		 194}
195
d9bea114 196target_ulong helper_maccu (target_ulong arg1, target_ulong arg2)
e9c71dd1 197{
d9bea114 198 set_HI_LOT0(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 199
d9bea114 200 return arg1;
e9c71dd1
TS		 201}
202
d9bea114 203target_ulong helper_macchiu (target_ulong arg1, target_ulong arg2)
e9c71dd1 204{
d9bea114 205 set_HIT0_LO(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 206
d9bea114 207 return arg1;
e9c71dd1
TS		 208}
209
d9bea114 210target_ulong helper_msac (target_ulong arg1, target_ulong arg2)
e9c71dd1 211{
d9bea114 212 set_HI_LOT0(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 213
d9bea114 214 return arg1;
e9c71dd1
TS		 215}
216
d9bea114 217target_ulong helper_msachi (target_ulong arg1, target_ulong arg2)
e9c71dd1 218{
d9bea114 219 set_HIT0_LO(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 220
d9bea114 221 return arg1;
e9c71dd1
TS		 222}
223
d9bea114 224target_ulong helper_msacu (target_ulong arg1, target_ulong arg2)
e9c71dd1 225{
d9bea114 226 set_HI_LOT0(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 227
d9bea114 228 return arg1;
e9c71dd1
TS		 229}
230
d9bea114 231target_ulong helper_msachiu (target_ulong arg1, target_ulong arg2)
e9c71dd1 232{
d9bea114 233 set_HIT0_LO(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 234
d9bea114 235 return arg1;
e9c71dd1
TS		 236}
237
d9bea114 238target_ulong helper_mulhi (target_ulong arg1, target_ulong arg2)
e9c71dd1 239{
d9bea114 240 set_HIT0_LO(arg1, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
be24bb4f 241
d9bea114 242 return arg1;
e9c71dd1
TS		 243}
244
d9bea114 245target_ulong helper_mulhiu (target_ulong arg1, target_ulong arg2)
e9c71dd1 246{
d9bea114 247 set_HIT0_LO(arg1, (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
be24bb4f 248
d9bea114 249 return arg1;
e9c71dd1
TS		 250}
251
d9bea114 252target_ulong helper_mulshi (target_ulong arg1, target_ulong arg2)
e9c71dd1 253{
d9bea114 254 set_HIT0_LO(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 255
d9bea114 256 return arg1;
e9c71dd1
TS		 257}
258
d9bea114 259target_ulong helper_mulshiu (target_ulong arg1, target_ulong arg2)
e9c71dd1 260{
d9bea114 261 set_HIT0_LO(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 262
d9bea114 263 return arg1;
e9c71dd1 264}
6af0bf9c 265
214c465f 266#ifdef TARGET_MIPS64
d9bea114 267void helper_dmult (target_ulong arg1, target_ulong arg2)
214c465f 268{
d9bea114 269 muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
214c465f
TS		 270}
271
d9bea114 272void helper_dmultu (target_ulong arg1, target_ulong arg2)
214c465f 273{
d9bea114 274 mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
214c465f
TS		 275}
276#endif
277
e7139c44 278#ifndef CONFIG_USER_ONLY
c36bbb28
AJ		 279
280static inline target_phys_addr_t do_translate_address(target_ulong address, int rw)
281{
282 target_phys_addr_t lladdr;
283
284 lladdr = cpu_mips_translate_address(env, address, rw);
285
286 if (lladdr == -1LL) {
287 cpu_loop_exit();
288 } else {
289 return lladdr;
290 }
291}
292
e7139c44
AJ		 293#define HELPER_LD_ATOMIC(name, insn) \
294target_ulong helper_##name(target_ulong arg, int mem_idx) \
295{ \
c36bbb28 296 env->lladdr = do_translate_address(arg, 0); \
e7139c44
AJ		 297 env->llval = do_##insn(arg, mem_idx); \
298 return env->llval; \
299}
300HELPER_LD_ATOMIC(ll, lw)
301#ifdef TARGET_MIPS64
302HELPER_LD_ATOMIC(lld, ld)
303#endif
304#undef HELPER_LD_ATOMIC
305
306#define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
307target_ulong helper_##name(target_ulong arg1, target_ulong arg2, int mem_idx) \
308{ \
309 target_long tmp; \
310 \
311 if (arg2 & almask) { \
312 env->CP0_BadVAddr = arg2; \
313 helper_raise_exception(EXCP_AdES); \
314 } \
c36bbb28 315 if (do_translate_address(arg2, 1) == env->lladdr) { \
e7139c44
AJ		 316 tmp = do_##ld_insn(arg2, mem_idx); \
317 if (tmp == env->llval) { \
318 do_##st_insn(arg2, arg1, mem_idx); \
319 return 1; \
320 } \
321 } \
322 return 0; \
323}
324HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
325#ifdef TARGET_MIPS64
326HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
327#endif
328#undef HELPER_ST_ATOMIC
329#endif
330
c8c2227e
TS		 331#ifdef TARGET_WORDS_BIGENDIAN
332#define GET_LMASK(v) ((v) & 3)
333#define GET_OFFSET(addr, offset) (addr + (offset))
334#else
335#define GET_LMASK(v) (((v) & 3) ^ 3)
336#define GET_OFFSET(addr, offset) (addr - (offset))
337#endif
338
d9bea114 339target_ulong helper_lwl(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e
TS		 340{
341 target_ulong tmp;
342
0ae43045 343 tmp = do_lbu(arg2, mem_idx);
d9bea114 344 arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
c8c2227e 345
d9bea114 346 if (GET_LMASK(arg2) <= 2) {
0ae43045 347 tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx);
d9bea114 348 arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
c8c2227e
TS		 349 }
350
d9bea114 351 if (GET_LMASK(arg2) <= 1) {
0ae43045 352 tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx);
d9bea114 353 arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
c8c2227e
TS		 354 }
355
d9bea114 356 if (GET_LMASK(arg2) == 0) {
0ae43045 357 tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx);
d9bea114 358 arg1 = (arg1 & 0xFFFFFF00) | tmp;
c8c2227e 359 }
d9bea114 360 return (int32_t)arg1;
c8c2227e
TS		 361}
362
d9bea114 363target_ulong helper_lwr(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e
TS		 364{
365 target_ulong tmp;
366
0ae43045 367 tmp = do_lbu(arg2, mem_idx);
d9bea114 368 arg1 = (arg1 & 0xFFFFFF00) | tmp;
c8c2227e 369
d9bea114 370 if (GET_LMASK(arg2) >= 1) {
0ae43045 371 tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx);
d9bea114 372 arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
c8c2227e
TS		 373 }
374
d9bea114 375 if (GET_LMASK(arg2) >= 2) {
0ae43045 376 tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx);
d9bea114 377 arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
c8c2227e
TS		 378 }
379
d9bea114 380 if (GET_LMASK(arg2) == 3) {
0ae43045 381 tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx);
d9bea114 382 arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
c8c2227e 383 }
d9bea114 384 return (int32_t)arg1;
c8c2227e
TS		 385}
386
d9bea114 387void helper_swl(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e 388{
0ae43045 389 do_sb(arg2, (uint8_t)(arg1 >> 24), mem_idx);
c8c2227e 390
d9bea114 391 if (GET_LMASK(arg2) <= 2)
0ae43045 392 do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
c8c2227e 393
d9bea114 394 if (GET_LMASK(arg2) <= 1)
0ae43045 395 do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
c8c2227e 396
d9bea114 397 if (GET_LMASK(arg2) == 0)
0ae43045 398 do_sb(GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
c8c2227e
TS		 399}
400
d9bea114 401void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e 402{
0ae43045 403 do_sb(arg2, (uint8_t)arg1, mem_idx);
c8c2227e 404
d9bea114 405 if (GET_LMASK(arg2) >= 1)
0ae43045 406 do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
c8c2227e 407
d9bea114 408 if (GET_LMASK(arg2) >= 2)
0ae43045 409 do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
c8c2227e 410
d9bea114 411 if (GET_LMASK(arg2) == 3)
0ae43045 412 do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
c8c2227e
TS		 413}
414
415#if defined(TARGET_MIPS64)
416/* "half" load and stores. We must do the memory access inline,
417 or fault handling won't work. */
418
419#ifdef TARGET_WORDS_BIGENDIAN
420#define GET_LMASK64(v) ((v) & 7)
421#else
422#define GET_LMASK64(v) (((v) & 7) ^ 7)
423#endif
424
d9bea114 425target_ulong helper_ldl(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e
TS		 426{
427 uint64_t tmp;
428
0ae43045 429 tmp = do_lbu(arg2, mem_idx);
d9bea114 430 arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
c8c2227e 431
d9bea114 432 if (GET_LMASK64(arg2) <= 6) {
0ae43045 433 tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx);
d9bea114 434 arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
c8c2227e
TS		 435 }
436
d9bea114 437 if (GET_LMASK64(arg2) <= 5) {
0ae43045 438 tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx);
d9bea114 439 arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
c8c2227e
TS		 440 }
441
d9bea114 442 if (GET_LMASK64(arg2) <= 4) {
0ae43045 443 tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx);
d9bea114 444 arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
c8c2227e
TS		 445 }
446
d9bea114 447 if (GET_LMASK64(arg2) <= 3) {
0ae43045 448 tmp = do_lbu(GET_OFFSET(arg2, 4), mem_idx);
d9bea114 449 arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
c8c2227e
TS		 450 }
451
d9bea114 452 if (GET_LMASK64(arg2) <= 2) {
0ae43045 453 tmp = do_lbu(GET_OFFSET(arg2, 5), mem_idx);
d9bea114 454 arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
c8c2227e
TS		 455 }
456
d9bea114 457 if (GET_LMASK64(arg2) <= 1) {
0ae43045 458 tmp = do_lbu(GET_OFFSET(arg2, 6), mem_idx);
d9bea114 459 arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
c8c2227e
TS		 460 }
461
d9bea114 462 if (GET_LMASK64(arg2) == 0) {
0ae43045 463 tmp = do_lbu(GET_OFFSET(arg2, 7), mem_idx);
d9bea114 464 arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
c8c2227e 465 }
be24bb4f 466
d9bea114 467 return arg1;
c8c2227e
TS		 468}
469
d9bea114 470target_ulong helper_ldr(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e
TS		 471{
472 uint64_t tmp;
473
0ae43045 474 tmp = do_lbu(arg2, mem_idx);
d9bea114 475 arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
c8c2227e 476
d9bea114 477 if (GET_LMASK64(arg2) >= 1) {
0ae43045 478 tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx);
d9bea114 479 arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
c8c2227e
TS		 480 }
481
d9bea114 482 if (GET_LMASK64(arg2) >= 2) {
0ae43045 483 tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx);
d9bea114 484 arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
c8c2227e
TS		 485 }
486
d9bea114 487 if (GET_LMASK64(arg2) >= 3) {
0ae43045 488 tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx);
d9bea114 489 arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
c8c2227e
TS		 490 }
491
d9bea114 492 if (GET_LMASK64(arg2) >= 4) {
0ae43045 493 tmp = do_lbu(GET_OFFSET(arg2, -4), mem_idx);
d9bea114 494 arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
c8c2227e
TS		 495 }
496
d9bea114 497 if (GET_LMASK64(arg2) >= 5) {
0ae43045 498 tmp = do_lbu(GET_OFFSET(arg2, -5), mem_idx);
d9bea114 499 arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
c8c2227e
TS		 500 }
501
d9bea114 502 if (GET_LMASK64(arg2) >= 6) {
0ae43045 503 tmp = do_lbu(GET_OFFSET(arg2, -6), mem_idx);
d9bea114 504 arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
c8c2227e
TS		 505 }
506
d9bea114 507 if (GET_LMASK64(arg2) == 7) {
0ae43045 508 tmp = do_lbu(GET_OFFSET(arg2, -7), mem_idx);
d9bea114 509 arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
c8c2227e 510 }
be24bb4f 511
d9bea114 512 return arg1;
c8c2227e
TS		 513}
514
d9bea114 515void helper_sdl(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e 516{
0ae43045 517 do_sb(arg2, (uint8_t)(arg1 >> 56), mem_idx);
c8c2227e 518
d9bea114 519 if (GET_LMASK64(arg2) <= 6)
0ae43045 520 do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
c8c2227e 521
d9bea114 522 if (GET_LMASK64(arg2) <= 5)
0ae43045 523 do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
c8c2227e 524
d9bea114 525 if (GET_LMASK64(arg2) <= 4)
0ae43045 526 do_sb(GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
c8c2227e 527
d9bea114 528 if (GET_LMASK64(arg2) <= 3)
0ae43045 529 do_sb(GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
c8c2227e 530
d9bea114 531 if (GET_LMASK64(arg2) <= 2)
0ae43045 532 do_sb(GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
c8c2227e 533
d9bea114 534 if (GET_LMASK64(arg2) <= 1)
0ae43045 535 do_sb(GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
c8c2227e 536
d9bea114 537 if (GET_LMASK64(arg2) <= 0)
0ae43045 538 do_sb(GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
c8c2227e
TS		 539}
540
d9bea114 541void helper_sdr(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e 542{
0ae43045 543 do_sb(arg2, (uint8_t)arg1, mem_idx);
c8c2227e 544
d9bea114 545 if (GET_LMASK64(arg2) >= 1)
0ae43045 546 do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
c8c2227e 547
d9bea114 548 if (GET_LMASK64(arg2) >= 2)
0ae43045 549 do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
c8c2227e 550
d9bea114 551 if (GET_LMASK64(arg2) >= 3)
0ae43045 552 do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
c8c2227e 553
d9bea114 554 if (GET_LMASK64(arg2) >= 4)
0ae43045 555 do_sb(GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
c8c2227e 556
d9bea114 557 if (GET_LMASK64(arg2) >= 5)
0ae43045 558 do_sb(GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
c8c2227e 559
d9bea114 560 if (GET_LMASK64(arg2) >= 6)
0ae43045 561 do_sb(GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
c8c2227e 562
d9bea114 563 if (GET_LMASK64(arg2) == 7)
0ae43045 564 do_sb(GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
c8c2227e
TS		 565}
566#endif /* TARGET_MIPS64 */
567
0eaef5aa 568#ifndef CONFIG_USER_ONLY
6af0bf9c 569/* CP0 helpers */
c01fccd2 570target_ulong helper_mfc0_mvpcontrol (void)
f1aa6320 571{
be24bb4f 572 return env->mvp->CP0_MVPControl;
f1aa6320
TS		 573}
574
c01fccd2 575target_ulong helper_mfc0_mvpconf0 (void)
f1aa6320 576{
be24bb4f 577 return env->mvp->CP0_MVPConf0;
f1aa6320
TS		 578}
579
c01fccd2 580target_ulong helper_mfc0_mvpconf1 (void)
f1aa6320 581{
be24bb4f 582 return env->mvp->CP0_MVPConf1;
f1aa6320
TS		 583}
584
c01fccd2 585target_ulong helper_mfc0_random (void)
6af0bf9c 586{
be24bb4f 587 return (int32_t)cpu_mips_get_random(env);
873eb012 588}
6af0bf9c 589
c01fccd2 590target_ulong helper_mfc0_tcstatus (void)
f1aa6320 591{
b5dc7732 592 return env->active_tc.CP0_TCStatus;
f1aa6320
TS		 593}
594
c01fccd2 595target_ulong helper_mftc0_tcstatus(void)
f1aa6320
TS		 596{
597 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
598
b5dc7732
TS		 599 if (other_tc == env->current_tc)
600 return env->active_tc.CP0_TCStatus;
601 else
602 return env->tcs[other_tc].CP0_TCStatus;
f1aa6320
TS		 603}
604
c01fccd2 605target_ulong helper_mfc0_tcbind (void)
f1aa6320 606{
b5dc7732 607 return env->active_tc.CP0_TCBind;
f1aa6320
TS		 608}
609
c01fccd2 610target_ulong helper_mftc0_tcbind(void)
f1aa6320
TS		 611{
612 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
613
b5dc7732
TS		 614 if (other_tc == env->current_tc)
615 return env->active_tc.CP0_TCBind;
616 else
617 return env->tcs[other_tc].CP0_TCBind;
f1aa6320
TS		 618}
619
c01fccd2 620target_ulong helper_mfc0_tcrestart (void)
f1aa6320 621{
b5dc7732 622 return env->active_tc.PC;
f1aa6320
TS		 623}
624
c01fccd2 625target_ulong helper_mftc0_tcrestart(void)
f1aa6320
TS		 626{
627 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
628
b5dc7732
TS		 629 if (other_tc == env->current_tc)
630 return env->active_tc.PC;
631 else
632 return env->tcs[other_tc].PC;
f1aa6320
TS		 633}
634
c01fccd2 635target_ulong helper_mfc0_tchalt (void)
f1aa6320 636{
b5dc7732 637 return env->active_tc.CP0_TCHalt;
f1aa6320
TS		 638}
639
c01fccd2 640target_ulong helper_mftc0_tchalt(void)
f1aa6320
TS		 641{
642 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
643
b5dc7732
TS		 644 if (other_tc == env->current_tc)
645 return env->active_tc.CP0_TCHalt;
646 else
647 return env->tcs[other_tc].CP0_TCHalt;
f1aa6320
TS		 648}
649
c01fccd2 650target_ulong helper_mfc0_tccontext (void)
f1aa6320 651{
b5dc7732 652 return env->active_tc.CP0_TCContext;
f1aa6320
TS		 653}
654
c01fccd2 655target_ulong helper_mftc0_tccontext(void)
f1aa6320
TS		 656{
657 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
658
b5dc7732
TS		 659 if (other_tc == env->current_tc)
660 return env->active_tc.CP0_TCContext;
661 else
662 return env->tcs[other_tc].CP0_TCContext;
f1aa6320
TS		 663}
664
c01fccd2 665target_ulong helper_mfc0_tcschedule (void)
f1aa6320 666{
b5dc7732 667 return env->active_tc.CP0_TCSchedule;
f1aa6320
TS		 668}
669
c01fccd2 670target_ulong helper_mftc0_tcschedule(void)
f1aa6320
TS		 671{
672 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
673
b5dc7732
TS		 674 if (other_tc == env->current_tc)
675 return env->active_tc.CP0_TCSchedule;
676 else
677 return env->tcs[other_tc].CP0_TCSchedule;
f1aa6320
TS		 678}
679
c01fccd2 680target_ulong helper_mfc0_tcschefback (void)
f1aa6320 681{
b5dc7732 682 return env->active_tc.CP0_TCScheFBack;
f1aa6320
TS		 683}
684
c01fccd2 685target_ulong helper_mftc0_tcschefback(void)
f1aa6320
TS		 686{
687 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
688
b5dc7732
TS		 689 if (other_tc == env->current_tc)
690 return env->active_tc.CP0_TCScheFBack;
691 else
692 return env->tcs[other_tc].CP0_TCScheFBack;
f1aa6320
TS		 693}
694
c01fccd2 695target_ulong helper_mfc0_count (void)
873eb012 696{
be24bb4f 697 return (int32_t)cpu_mips_get_count(env);
6af0bf9c
FB		 698}
699
c01fccd2 700target_ulong helper_mftc0_entryhi(void)
f1aa6320
TS		 701{
702 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
b5dc7732 703 int32_t tcstatus;
f1aa6320 704
b5dc7732
TS		 705 if (other_tc == env->current_tc)
706 tcstatus = env->active_tc.CP0_TCStatus;
707 else
708 tcstatus = env->tcs[other_tc].CP0_TCStatus;
709
710 return (env->CP0_EntryHi & ~0xff) | (tcstatus & 0xff);
f1aa6320
TS		 711}
712
c01fccd2 713target_ulong helper_mftc0_status(void)
f1aa6320
TS		 714{
715 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1a3fd9c3 716 target_ulong t0;
b5dc7732
TS		 717 int32_t tcstatus;
718
719 if (other_tc == env->current_tc)
720 tcstatus = env->active_tc.CP0_TCStatus;
721 else
722 tcstatus = env->tcs[other_tc].CP0_TCStatus;
f1aa6320 723
be24bb4f
TS		 724 t0 = env->CP0_Status & ~0xf1000018;
725 t0 |= tcstatus & (0xf << CP0TCSt_TCU0);
726 t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
727 t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
728
729 return t0;
f1aa6320
TS		 730}
731
c01fccd2 732target_ulong helper_mfc0_lladdr (void)
f1aa6320 733{
2a6e32dd 734 return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
f1aa6320
TS		 735}
736
c01fccd2 737target_ulong helper_mfc0_watchlo (uint32_t sel)
f1aa6320 738{
be24bb4f 739 return (int32_t)env->CP0_WatchLo[sel];
f1aa6320
TS		 740}
741
c01fccd2 742target_ulong helper_mfc0_watchhi (uint32_t sel)
f1aa6320 743{
be24bb4f 744 return env->CP0_WatchHi[sel];
f1aa6320
TS		 745}
746
c01fccd2 747target_ulong helper_mfc0_debug (void)
f1aa6320 748{
1a3fd9c3 749 target_ulong t0 = env->CP0_Debug;
f1aa6320 750 if (env->hflags & MIPS_HFLAG_DM)
be24bb4f
TS		 751 t0 |= 1 << CP0DB_DM;
752
753 return t0;
f1aa6320
TS		 754}
755
c01fccd2 756target_ulong helper_mftc0_debug(void)
f1aa6320
TS		 757{
758 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
b5dc7732
TS		 759 int32_t tcstatus;
760
761 if (other_tc == env->current_tc)
762 tcstatus = env->active_tc.CP0_Debug_tcstatus;
763 else
764 tcstatus = env->tcs[other_tc].CP0_Debug_tcstatus;
f1aa6320
TS		 765
766 /* XXX: Might be wrong, check with EJTAG spec. */
be24bb4f 767 return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
b5dc7732 768 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
f1aa6320
TS		 769}
770
771#if defined(TARGET_MIPS64)
c01fccd2 772target_ulong helper_dmfc0_tcrestart (void)
f1aa6320 773{
b5dc7732 774 return env->active_tc.PC;
f1aa6320
TS		 775}
776
c01fccd2 777target_ulong helper_dmfc0_tchalt (void)
f1aa6320 778{
b5dc7732 779 return env->active_tc.CP0_TCHalt;
f1aa6320
TS		 780}
781
c01fccd2 782target_ulong helper_dmfc0_tccontext (void)
f1aa6320 783{
b5dc7732 784 return env->active_tc.CP0_TCContext;
f1aa6320
TS		 785}
786
c01fccd2 787target_ulong helper_dmfc0_tcschedule (void)
f1aa6320 788{
b5dc7732 789 return env->active_tc.CP0_TCSchedule;
f1aa6320
TS		 790}
791
c01fccd2 792target_ulong helper_dmfc0_tcschefback (void)
f1aa6320 793{
b5dc7732 794 return env->active_tc.CP0_TCScheFBack;
f1aa6320
TS		 795}
796
c01fccd2 797target_ulong helper_dmfc0_lladdr (void)
f1aa6320 798{
2a6e32dd 799 return env->lladdr >> env->CP0_LLAddr_shift;
f1aa6320
TS		 800}
801
c01fccd2 802target_ulong helper_dmfc0_watchlo (uint32_t sel)
f1aa6320 803{
be24bb4f 804 return env->CP0_WatchLo[sel];
f1aa6320
TS		 805}
806#endif /* TARGET_MIPS64 */
807
d9bea114 808void helper_mtc0_index (target_ulong arg1)
f1aa6320
TS		 809{
810 int num = 1;
811 unsigned int tmp = env->tlb->nb_tlb;
812
813 do {
814 tmp >>= 1;
815 num <<= 1;
816 } while (tmp);
d9bea114 817 env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
f1aa6320
TS		 818}
819
d9bea114 820void helper_mtc0_mvpcontrol (target_ulong arg1)
f1aa6320
TS		 821{
822 uint32_t mask = 0;
823 uint32_t newval;
824
825 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
826 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
827 (1 << CP0MVPCo_EVP);
828 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
829 mask |= (1 << CP0MVPCo_STLB);
d9bea114 830 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
f1aa6320
TS		 831
832 // TODO: Enable/disable shared TLB, enable/disable VPEs.
833
834 env->mvp->CP0_MVPControl = newval;
835}
836
d9bea114 837void helper_mtc0_vpecontrol (target_ulong arg1)
f1aa6320
TS		 838{
839 uint32_t mask;
840 uint32_t newval;
841
842 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
843 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
d9bea114 844 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
f1aa6320
TS		 845
846 /* Yield scheduler intercept not implemented. */
847 /* Gating storage scheduler intercept not implemented. */
848
849 // TODO: Enable/disable TCs.
850
851 env->CP0_VPEControl = newval;
852}
853
d9bea114 854void helper_mtc0_vpeconf0 (target_ulong arg1)
f1aa6320
TS		 855{
856 uint32_t mask = 0;
857 uint32_t newval;
858
859 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
860 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
861 mask |= (0xff << CP0VPEC0_XTC);
862 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
863 }
d9bea114 864 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
f1aa6320
TS		 865
866 // TODO: TC exclusive handling due to ERL/EXL.
867
868 env->CP0_VPEConf0 = newval;
869}
870
d9bea114 871void helper_mtc0_vpeconf1 (target_ulong arg1)
f1aa6320
TS		 872{
873 uint32_t mask = 0;
874 uint32_t newval;
875
876 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
877 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
878 (0xff << CP0VPEC1_NCP1);
d9bea114 879 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
f1aa6320
TS		 880
881 /* UDI not implemented. */
882 /* CP2 not implemented. */
883
884 // TODO: Handle FPU (CP1) binding.
885
886 env->CP0_VPEConf1 = newval;
887}
888
d9bea114 889void helper_mtc0_yqmask (target_ulong arg1)
f1aa6320
TS		 890{
891 /* Yield qualifier inputs not implemented. */
892 env->CP0_YQMask = 0x00000000;
893}
894
d9bea114 895void helper_mtc0_vpeopt (target_ulong arg1)
f1aa6320 896{
d9bea114 897 env->CP0_VPEOpt = arg1 & 0x0000ffff;
f1aa6320
TS		 898}
899
d9bea114 900void helper_mtc0_entrylo0 (target_ulong arg1)
f1aa6320
TS		 901{
902 /* Large physaddr (PABITS) not implemented */
903 /* 1k pages not implemented */
d9bea114 904 env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
f1aa6320
TS		 905}
906
d9bea114 907void helper_mtc0_tcstatus (target_ulong arg1)
f1aa6320
TS		 908{
909 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
910 uint32_t newval;
911
d9bea114 912 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
f1aa6320
TS		 913
914 // TODO: Sync with CP0_Status.
915
b5dc7732 916 env->active_tc.CP0_TCStatus = newval;
f1aa6320
TS		 917}
918
d9bea114 919void helper_mttc0_tcstatus (target_ulong arg1)
f1aa6320
TS		 920{
921 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
922
923 // TODO: Sync with CP0_Status.
924
b5dc7732 925 if (other_tc == env->current_tc)
d9bea114 926 env->active_tc.CP0_TCStatus = arg1;
b5dc7732 927 else
d9bea114 928 env->tcs[other_tc].CP0_TCStatus = arg1;
f1aa6320
TS		 929}
930
d9bea114 931void helper_mtc0_tcbind (target_ulong arg1)
f1aa6320
TS		 932{
933 uint32_t mask = (1 << CP0TCBd_TBE);
934 uint32_t newval;
935
936 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
937 mask |= (1 << CP0TCBd_CurVPE);
d9bea114 938 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
b5dc7732 939 env->active_tc.CP0_TCBind = newval;
f1aa6320
TS		 940}
941
d9bea114 942void helper_mttc0_tcbind (target_ulong arg1)
f1aa6320
TS		 943{
944 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
945 uint32_t mask = (1 << CP0TCBd_TBE);
946 uint32_t newval;
947
948 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
949 mask |= (1 << CP0TCBd_CurVPE);
b5dc7732 950 if (other_tc == env->current_tc) {
d9bea114 951 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
b5dc7732
TS		 952 env->active_tc.CP0_TCBind = newval;
953 } else {
d9bea114 954 newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
b5dc7732
TS		 955 env->tcs[other_tc].CP0_TCBind = newval;
956 }
f1aa6320
TS		 957}
958
d9bea114 959void helper_mtc0_tcrestart (target_ulong arg1)
f1aa6320 960{
d9bea114 961 env->active_tc.PC = arg1;
b5dc7732 962 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
5499b6ff 963 env->lladdr = 0ULL;
f1aa6320
TS		 964 /* MIPS16 not implemented. */
965}
966
d9bea114 967void helper_mttc0_tcrestart (target_ulong arg1)
f1aa6320
TS		 968{
969 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
970
b5dc7732 971 if (other_tc == env->current_tc) {
d9bea114 972 env->active_tc.PC = arg1;
b5dc7732 973 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
5499b6ff 974 env->lladdr = 0ULL;
b5dc7732
TS		 975 /* MIPS16 not implemented. */
976 } else {
d9bea114 977 env->tcs[other_tc].PC = arg1;
b5dc7732 978 env->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
5499b6ff 979 env->lladdr = 0ULL;
b5dc7732
TS		 980 /* MIPS16 not implemented. */
981 }
f1aa6320
TS		 982}
983
d9bea114 984void helper_mtc0_tchalt (target_ulong arg1)
f1aa6320 985{
d9bea114 986 env->active_tc.CP0_TCHalt = arg1 & 0x1;
f1aa6320
TS		 987
988 // TODO: Halt TC / Restart (if allocated+active) TC.
989}
990
d9bea114 991void helper_mttc0_tchalt (target_ulong arg1)
f1aa6320
TS		 992{
993 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
994
995 // TODO: Halt TC / Restart (if allocated+active) TC.
996
b5dc7732 997 if (other_tc == env->current_tc)
d9bea114 998 env->active_tc.CP0_TCHalt = arg1;
b5dc7732 999 else
d9bea114 1000 env->tcs[other_tc].CP0_TCHalt = arg1;
f1aa6320
TS		 1001}
1002
d9bea114 1003void helper_mtc0_tccontext (target_ulong arg1)
f1aa6320 1004{
d9bea114 1005 env->active_tc.CP0_TCContext = arg1;
f1aa6320
TS		 1006}
1007
d9bea114 1008void helper_mttc0_tccontext (target_ulong arg1)
f1aa6320
TS		 1009{
1010 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1011
b5dc7732 1012 if (other_tc == env->current_tc)
d9bea114 1013 env->active_tc.CP0_TCContext = arg1;
b5dc7732 1014 else
d9bea114 1015 env->tcs[other_tc].CP0_TCContext = arg1;
f1aa6320
TS		 1016}
1017
d9bea114 1018void helper_mtc0_tcschedule (target_ulong arg1)
f1aa6320 1019{
d9bea114 1020 env->active_tc.CP0_TCSchedule = arg1;
f1aa6320
TS		 1021}
1022
d9bea114 1023void helper_mttc0_tcschedule (target_ulong arg1)
f1aa6320
TS		 1024{
1025 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1026
b5dc7732 1027 if (other_tc == env->current_tc)
d9bea114 1028 env->active_tc.CP0_TCSchedule = arg1;
b5dc7732 1029 else
d9bea114 1030 env->tcs[other_tc].CP0_TCSchedule = arg1;
f1aa6320
TS		 1031}
1032
d9bea114 1033void helper_mtc0_tcschefback (target_ulong arg1)
f1aa6320 1034{
d9bea114 1035 env->active_tc.CP0_TCScheFBack = arg1;
f1aa6320
TS		 1036}
1037
d9bea114 1038void helper_mttc0_tcschefback (target_ulong arg1)
f1aa6320
TS		 1039{
1040 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1041
b5dc7732 1042 if (other_tc == env->current_tc)
d9bea114 1043 env->active_tc.CP0_TCScheFBack = arg1;
b5dc7732 1044 else
d9bea114 1045 env->tcs[other_tc].CP0_TCScheFBack = arg1;
f1aa6320
TS		 1046}
1047
d9bea114 1048void helper_mtc0_entrylo1 (target_ulong arg1)
f1aa6320
TS		 1049{
1050 /* Large physaddr (PABITS) not implemented */
1051 /* 1k pages not implemented */
d9bea114 1052 env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
f1aa6320
TS		 1053}
1054
d9bea114 1055void helper_mtc0_context (target_ulong arg1)
f1aa6320 1056{
d9bea114 1057 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
f1aa6320
TS		 1058}
1059
d9bea114 1060void helper_mtc0_pagemask (target_ulong arg1)
f1aa6320
TS		 1061{
1062 /* 1k pages not implemented */
d9bea114 1063 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
f1aa6320
TS		 1064}
1065
d9bea114 1066void helper_mtc0_pagegrain (target_ulong arg1)
f1aa6320
TS		 1067{
1068 /* SmartMIPS not implemented */
1069 /* Large physaddr (PABITS) not implemented */
1070 /* 1k pages not implemented */
1071 env->CP0_PageGrain = 0;
1072}
1073
d9bea114 1074void helper_mtc0_wired (target_ulong arg1)
f1aa6320 1075{
d9bea114 1076 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
f1aa6320
TS		 1077}
1078
d9bea114 1079void helper_mtc0_srsconf0 (target_ulong arg1)
f1aa6320 1080{
d9bea114 1081 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
f1aa6320
TS		 1082}
1083
d9bea114 1084void helper_mtc0_srsconf1 (target_ulong arg1)
f1aa6320 1085{
d9bea114 1086 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
f1aa6320
TS		 1087}
1088
d9bea114 1089void helper_mtc0_srsconf2 (target_ulong arg1)
f1aa6320 1090{
d9bea114 1091 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
f1aa6320
TS		 1092}
1093
d9bea114 1094void helper_mtc0_srsconf3 (target_ulong arg1)
f1aa6320 1095{
d9bea114 1096 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
f1aa6320
TS		 1097}
1098
d9bea114 1099void helper_mtc0_srsconf4 (target_ulong arg1)
f1aa6320 1100{
d9bea114 1101 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
f1aa6320
TS		 1102}
1103
d9bea114 1104void helper_mtc0_hwrena (target_ulong arg1)
f1aa6320 1105{
d9bea114 1106 env->CP0_HWREna = arg1 & 0x0000000F;
f1aa6320
TS		 1107}
1108
d9bea114 1109void helper_mtc0_count (target_ulong arg1)
f1aa6320 1110{
d9bea114 1111 cpu_mips_store_count(env, arg1);
f1aa6320
TS		 1112}
1113
d9bea114 1114void helper_mtc0_entryhi (target_ulong arg1)
f1aa6320
TS		 1115{
1116 target_ulong old, val;
1117
1118 /* 1k pages not implemented */
d9bea114 1119 val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
f1aa6320
TS		 1120#if defined(TARGET_MIPS64)
1121 val &= env->SEGMask;
1122#endif
1123 old = env->CP0_EntryHi;
1124 env->CP0_EntryHi = val;
1125 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
b5dc7732
TS		 1126 uint32_t tcst = env->active_tc.CP0_TCStatus & ~0xff;
1127 env->active_tc.CP0_TCStatus = tcst | (val & 0xff);
f1aa6320
TS		 1128 }
1129 /* If the ASID changes, flush qemu's TLB. */
1130 if ((old & 0xFF) != (val & 0xFF))
1131 cpu_mips_tlb_flush(env, 1);
1132}
1133
d9bea114 1134void helper_mttc0_entryhi(target_ulong arg1)
f1aa6320
TS		 1135{
1136 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
b5dc7732 1137 int32_t tcstatus;
f1aa6320 1138
d9bea114 1139 env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (arg1 & ~0xff);
b5dc7732 1140 if (other_tc == env->current_tc) {
d9bea114 1141 tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (arg1 & 0xff);
b5dc7732
TS		 1142 env->active_tc.CP0_TCStatus = tcstatus;
1143 } else {
d9bea114 1144 tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (arg1 & 0xff);
b5dc7732
TS		 1145 env->tcs[other_tc].CP0_TCStatus = tcstatus;
1146 }
f1aa6320
TS		 1147}
1148
d9bea114 1149void helper_mtc0_compare (target_ulong arg1)
f1aa6320 1150{
d9bea114 1151 cpu_mips_store_compare(env, arg1);
f1aa6320
TS		 1152}
1153
d9bea114 1154void helper_mtc0_status (target_ulong arg1)
f1aa6320
TS		 1155{
1156 uint32_t val, old;
1157 uint32_t mask = env->CP0_Status_rw_bitmask;
1158
d9bea114 1159 val = arg1 & mask;
f1aa6320
TS		 1160 old = env->CP0_Status;
1161 env->CP0_Status = (env->CP0_Status & ~mask) | val;
1162 compute_hflags(env);
c01fccd2
AJ		 1163 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1164 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1165 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1166 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1167 env->CP0_Cause);
1168 switch (env->hflags & MIPS_HFLAG_KSU) {
1169 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1170 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1171 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1172 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
31e3104f 1173 }
c01fccd2 1174 }
f1aa6320
TS		 1175 cpu_mips_update_irq(env);
1176}
1177
d9bea114 1178void helper_mttc0_status(target_ulong arg1)
f1aa6320
TS		 1179{
1180 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
b5dc7732 1181 int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus;
f1aa6320 1182
d9bea114
AJ		 1183 env->CP0_Status = arg1 & ~0xf1000018;
1184 tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (arg1 & (0xf << CP0St_CU0));
1185 tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((arg1 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
1186 tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((arg1 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
b5dc7732
TS		 1187 if (other_tc == env->current_tc)
1188 env->active_tc.CP0_TCStatus = tcstatus;
1189 else
1190 env->tcs[other_tc].CP0_TCStatus = tcstatus;
f1aa6320
TS		 1191}
1192
d9bea114 1193void helper_mtc0_intctl (target_ulong arg1)
f1aa6320
TS		 1194{
1195 /* vectored interrupts not implemented, no performance counters. */
d9bea114 1196 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (arg1 & 0x000002e0);
f1aa6320
TS		 1197}
1198
d9bea114 1199void helper_mtc0_srsctl (target_ulong arg1)
f1aa6320
TS		 1200{
1201 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
d9bea114 1202 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
f1aa6320
TS		 1203}
1204
d9bea114 1205void helper_mtc0_cause (target_ulong arg1)
f1aa6320
TS		 1206{
1207 uint32_t mask = 0x00C00300;
1208 uint32_t old = env->CP0_Cause;
1209
1210 if (env->insn_flags & ISA_MIPS32R2)
1211 mask |= 1 << CP0Ca_DC;
1212
d9bea114 1213 env->CP0_Cause = (env->CP0_Cause & ~mask) | (arg1 & mask);
f1aa6320
TS		 1214
1215 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
1216 if (env->CP0_Cause & (1 << CP0Ca_DC))
1217 cpu_mips_stop_count(env);
1218 else
1219 cpu_mips_start_count(env);
1220 }
1221
1222 /* Handle the software interrupt as an hardware one, as they
1223 are very similar */
d9bea114 1224 if (arg1 & CP0Ca_IP_mask) {
f1aa6320
TS		 1225 cpu_mips_update_irq(env);
1226 }
1227}
1228
d9bea114 1229void helper_mtc0_ebase (target_ulong arg1)
f1aa6320
TS		 1230{
1231 /* vectored interrupts not implemented */
1232 /* Multi-CPU not implemented */
d9bea114 1233 env->CP0_EBase = 0x80000000 | (arg1 & 0x3FFFF000);
f1aa6320
TS		 1234}
1235
d9bea114 1236void helper_mtc0_config0 (target_ulong arg1)
f1aa6320 1237{
d9bea114 1238 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
f1aa6320
TS		 1239}
1240
d9bea114 1241void helper_mtc0_config2 (target_ulong arg1)
f1aa6320
TS		 1242{
1243 /* tertiary/secondary caches not implemented */
1244 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1245}
1246
2a6e32dd
AJ		 1247void helper_mtc0_lladdr (target_ulong arg1)
1248{
1249 target_long mask = env->CP0_LLAddr_rw_bitmask;
1250 arg1 = arg1 << env->CP0_LLAddr_shift;
1251 env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1252}
1253
d9bea114 1254void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel)
f1aa6320
TS		 1255{
1256 /* Watch exceptions for instructions, data loads, data stores
1257 not implemented. */
d9bea114 1258 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
f1aa6320
TS		 1259}
1260
d9bea114 1261void helper_mtc0_watchhi (target_ulong arg1, uint32_t sel)
f1aa6320 1262{
d9bea114
AJ		 1263 env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1264 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
f1aa6320
TS		 1265}
1266
d9bea114 1267void helper_mtc0_xcontext (target_ulong arg1)
f1aa6320
TS		 1268{
1269 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
d9bea114 1270 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
f1aa6320
TS		 1271}
1272
d9bea114 1273void helper_mtc0_framemask (target_ulong arg1)
f1aa6320 1274{
d9bea114 1275 env->CP0_Framemask = arg1; /* XXX */
f1aa6320
TS		 1276}
1277
d9bea114 1278void helper_mtc0_debug (target_ulong arg1)
f1aa6320 1279{
d9bea114
AJ		 1280 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1281 if (arg1 & (1 << CP0DB_DM))
f1aa6320
TS		 1282 env->hflags |= MIPS_HFLAG_DM;
1283 else
1284 env->hflags &= ~MIPS_HFLAG_DM;
1285}
1286
d9bea114 1287void helper_mttc0_debug(target_ulong arg1)
f1aa6320
TS		 1288{
1289 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
d9bea114 1290 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
f1aa6320
TS		 1291
1292 /* XXX: Might be wrong, check with EJTAG spec. */
b5dc7732
TS		 1293 if (other_tc == env->current_tc)
1294 env->active_tc.CP0_Debug_tcstatus = val;
1295 else
1296 env->tcs[other_tc].CP0_Debug_tcstatus = val;
f1aa6320 1297 env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
d9bea114 1298 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
f1aa6320
TS		 1299}
1300
d9bea114 1301void helper_mtc0_performance0 (target_ulong arg1)
f1aa6320 1302{
d9bea114 1303 env->CP0_Performance0 = arg1 & 0x000007ff;
f1aa6320
TS		 1304}
1305
d9bea114 1306void helper_mtc0_taglo (target_ulong arg1)
f1aa6320 1307{
d9bea114 1308 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
f1aa6320
TS		 1309}
1310
d9bea114 1311void helper_mtc0_datalo (target_ulong arg1)
f1aa6320 1312{
d9bea114 1313 env->CP0_DataLo = arg1; /* XXX */
f1aa6320
TS		 1314}
1315
d9bea114 1316void helper_mtc0_taghi (target_ulong arg1)
f1aa6320 1317{
d9bea114 1318 env->CP0_TagHi = arg1; /* XXX */
f1aa6320
TS		 1319}
1320
d9bea114 1321void helper_mtc0_datahi (target_ulong arg1)
f1aa6320 1322{
d9bea114 1323 env->CP0_DataHi = arg1; /* XXX */
f1aa6320
TS		 1324}
1325
f1aa6320 1326/* MIPS MT functions */
c01fccd2 1327target_ulong helper_mftgpr(uint32_t sel)
f1aa6320
TS		 1328{
1329 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1330
b5dc7732
TS		 1331 if (other_tc == env->current_tc)
1332 return env->active_tc.gpr[sel];
1333 else
1334 return env->tcs[other_tc].gpr[sel];
f1aa6320
TS		 1335}
1336
c01fccd2 1337target_ulong helper_mftlo(uint32_t sel)
f1aa6320
TS		 1338{
1339 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1340
b5dc7732
TS		 1341 if (other_tc == env->current_tc)
1342 return env->active_tc.LO[sel];
1343 else
1344 return env->tcs[other_tc].LO[sel];
f1aa6320
TS		 1345}
1346
c01fccd2 1347target_ulong helper_mfthi(uint32_t sel)
f1aa6320
TS		 1348{
1349 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1350
b5dc7732
TS		 1351 if (other_tc == env->current_tc)
1352 return env->active_tc.HI[sel];
1353 else
1354 return env->tcs[other_tc].HI[sel];
f1aa6320
TS		 1355}
1356
c01fccd2 1357target_ulong helper_mftacx(uint32_t sel)
f1aa6320
TS		 1358{
1359 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1360
b5dc7732
TS		 1361 if (other_tc == env->current_tc)
1362 return env->active_tc.ACX[sel];
1363 else
1364 return env->tcs[other_tc].ACX[sel];
f1aa6320
TS		 1365}
1366
c01fccd2 1367target_ulong helper_mftdsp(void)
f1aa6320
TS		 1368{
1369 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1370
b5dc7732
TS		 1371 if (other_tc == env->current_tc)
1372 return env->active_tc.DSPControl;
1373 else
1374 return env->tcs[other_tc].DSPControl;
f1aa6320 1375}
6af0bf9c 1376
d9bea114 1377void helper_mttgpr(target_ulong arg1, uint32_t sel)
f1aa6320
TS		 1378{
1379 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1380
b5dc7732 1381 if (other_tc == env->current_tc)
d9bea114 1382 env->active_tc.gpr[sel] = arg1;
b5dc7732 1383 else
d9bea114 1384 env->tcs[other_tc].gpr[sel] = arg1;
f1aa6320
TS		 1385}
1386
d9bea114 1387void helper_mttlo(target_ulong arg1, uint32_t sel)
f1aa6320
TS		 1388{
1389 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1390
b5dc7732 1391 if (other_tc == env->current_tc)
d9bea114 1392 env->active_tc.LO[sel] = arg1;
b5dc7732 1393 else
d9bea114 1394 env->tcs[other_tc].LO[sel] = arg1;
f1aa6320
TS		 1395}
1396
d9bea114 1397void helper_mtthi(target_ulong arg1, uint32_t sel)
f1aa6320
TS		 1398{
1399 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1400
b5dc7732 1401 if (other_tc == env->current_tc)
d9bea114 1402 env->active_tc.HI[sel] = arg1;
b5dc7732 1403 else
d9bea114 1404 env->tcs[other_tc].HI[sel] = arg1;
f1aa6320
TS		 1405}
1406
d9bea114 1407void helper_mttacx(target_ulong arg1, uint32_t sel)
f1aa6320
TS		 1408{
1409 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1410
b5dc7732 1411 if (other_tc == env->current_tc)
d9bea114 1412 env->active_tc.ACX[sel] = arg1;
b5dc7732 1413 else
d9bea114 1414 env->tcs[other_tc].ACX[sel] = arg1;
f1aa6320
TS		 1415}
1416
d9bea114 1417void helper_mttdsp(target_ulong arg1)
f1aa6320
TS		 1418{
1419 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1420
b5dc7732 1421 if (other_tc == env->current_tc)
d9bea114 1422 env->active_tc.DSPControl = arg1;
b5dc7732 1423 else
d9bea114 1424 env->tcs[other_tc].DSPControl = arg1;
f1aa6320
TS		 1425}
1426
1427/* MIPS MT functions */
d9bea114 1428target_ulong helper_dmt(target_ulong arg1)
f1aa6320
TS		 1429{
1430 // TODO
d9bea114
AJ		 1431 arg1 = 0;
1432 // rt = arg1
be24bb4f 1433
d9bea114 1434 return arg1;
f1aa6320
TS		 1435}
1436
d9bea114 1437target_ulong helper_emt(target_ulong arg1)
f1aa6320
TS		 1438{
1439 // TODO
d9bea114
AJ		 1440 arg1 = 0;
1441 // rt = arg1
be24bb4f 1442
d9bea114 1443 return arg1;
f1aa6320
TS		 1444}
1445
d9bea114 1446target_ulong helper_dvpe(target_ulong arg1)
f1aa6320
TS		 1447{
1448 // TODO
d9bea114
AJ		 1449 arg1 = 0;
1450 // rt = arg1
be24bb4f 1451
d9bea114 1452 return arg1;
f1aa6320
TS		 1453}
1454
d9bea114 1455target_ulong helper_evpe(target_ulong arg1)
f1aa6320
TS		 1456{
1457 // TODO
d9bea114
AJ		 1458 arg1 = 0;
1459 // rt = arg1
be24bb4f 1460
d9bea114 1461 return arg1;
f1aa6320 1462}
f9480ffc 1463#endif /* !CONFIG_USER_ONLY */
f1aa6320 1464
d9bea114 1465void helper_fork(target_ulong arg1, target_ulong arg2)
f1aa6320 1466{
d9bea114
AJ		 1467 // arg1 = rt, arg2 = rs
1468 arg1 = 0;
f1aa6320
TS		 1469 // TODO: store to TC register
1470}
1471
d9bea114 1472target_ulong helper_yield(target_ulong arg1)
f1aa6320 1473{
d9bea114 1474 if (arg1 < 0) {
f1aa6320 1475 /* No scheduling policy implemented. */
d9bea114 1476 if (arg1 != -2) {
f1aa6320 1477 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
b5dc7732 1478 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
f1aa6320
TS		 1479 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1480 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
c01fccd2 1481 helper_raise_exception(EXCP_THREAD);
f1aa6320
TS		 1482 }
1483 }
d9bea114 1484 } else if (arg1 == 0) {
6958549d 1485 if (0 /* TODO: TC underflow */) {
f1aa6320 1486 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
c01fccd2 1487 helper_raise_exception(EXCP_THREAD);
f1aa6320
TS		 1488 } else {
1489 // TODO: Deallocate TC
1490 }
d9bea114 1491 } else if (arg1 > 0) {
f1aa6320
TS		 1492 /* Yield qualifier inputs not implemented. */
1493 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1494 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
c01fccd2 1495 helper_raise_exception(EXCP_THREAD);
f1aa6320 1496 }
be24bb4f 1497 return env->CP0_YQMask;
f1aa6320
TS		 1498}
1499
f1aa6320 1500#ifndef CONFIG_USER_ONLY
6af0bf9c 1501/* TLB management */
814b9a47
TS		 1502void cpu_mips_tlb_flush (CPUState *env, int flush_global)
1503{
1504 /* Flush qemu's TLB and discard all shadowed entries. */
1505 tlb_flush (env, flush_global);
ead9360e 1506 env->tlb->tlb_in_use = env->tlb->nb_tlb;
814b9a47
TS		 1507}
1508
29929e34 1509static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
814b9a47
TS		 1510{
1511 /* Discard entries from env->tlb[first] onwards. */
ead9360e
TS		 1512 while (env->tlb->tlb_in_use > first) {
1513 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
814b9a47
TS		 1514 }
1515}
1516
29929e34 1517static void r4k_fill_tlb (int idx)
6af0bf9c 1518{
c227f099 1519 r4k_tlb_t *tlb;
6af0bf9c
FB		 1520
1521 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
ead9360e 1522 tlb = &env->tlb->mmu.r4k.tlb[idx];
f2e9ebef 1523 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
d26bc211 1524#if defined(TARGET_MIPS64)
e034e2c3 1525 tlb->VPN &= env->SEGMask;
100ce988 1526#endif
98c1b82b 1527 tlb->ASID = env->CP0_EntryHi & 0xFF;
3b1c8be4 1528 tlb->PageMask = env->CP0_PageMask;
6af0bf9c 1529 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
98c1b82b
PB		 1530 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1531 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1532 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
6af0bf9c 1533 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
98c1b82b
PB		 1534 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1535 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1536 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
6af0bf9c
FB		 1537 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1538}
1539
c01fccd2 1540void r4k_helper_tlbwi (void)
6af0bf9c 1541{
bbc0d79c
AJ		 1542 int idx;
1543
1544 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1545
814b9a47
TS		 1546 /* Discard cached TLB entries. We could avoid doing this if the
1547 tlbwi is just upgrading access permissions on the current entry;
1548 that might be a further win. */
ead9360e 1549 r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
814b9a47 1550
bbc0d79c
AJ		 1551 r4k_invalidate_tlb(env, idx, 0);
1552 r4k_fill_tlb(idx);
6af0bf9c
FB		 1553}
1554
c01fccd2 1555void r4k_helper_tlbwr (void)
6af0bf9c
FB		 1556{
1557 int r = cpu_mips_get_random(env);
1558
29929e34
TS		 1559 r4k_invalidate_tlb(env, r, 1);
1560 r4k_fill_tlb(r);
6af0bf9c
FB		 1561}
1562
c01fccd2 1563void r4k_helper_tlbp (void)
6af0bf9c 1564{
c227f099 1565 r4k_tlb_t *tlb;
f2e9ebef 1566 target_ulong mask;
6af0bf9c 1567 target_ulong tag;
f2e9ebef 1568 target_ulong VPN;
6af0bf9c
FB		 1569 uint8_t ASID;
1570 int i;
1571
3d9fb9fe 1572 ASID = env->CP0_EntryHi & 0xFF;
ead9360e
TS		 1573 for (i = 0; i < env->tlb->nb_tlb; i++) {
1574 tlb = &env->tlb->mmu.r4k.tlb[i];
f2e9ebef
TS		 1575 /* 1k pages are not supported. */
1576 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1577 tag = env->CP0_EntryHi & ~mask;
1578 VPN = tlb->VPN & ~mask;
6af0bf9c 1579 /* Check ASID, virtual page number & size */
f2e9ebef 1580 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
6af0bf9c 1581 /* TLB match */
9c2149c8 1582 env->CP0_Index = i;
6af0bf9c
FB		 1583 break;
1584 }
1585 }
ead9360e 1586 if (i == env->tlb->nb_tlb) {
814b9a47 1587 /* No match. Discard any shadow entries, if any of them match. */
ead9360e 1588 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
6958549d
AJ		 1589 tlb = &env->tlb->mmu.r4k.tlb[i];
1590 /* 1k pages are not supported. */
1591 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1592 tag = env->CP0_EntryHi & ~mask;
1593 VPN = tlb->VPN & ~mask;
1594 /* Check ASID, virtual page number & size */
1595 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
29929e34 1596 r4k_mips_tlb_flush_extra (env, i);
6958549d
AJ		 1597 break;
1598 }
1599 }
814b9a47 1600
9c2149c8 1601 env->CP0_Index |= 0x80000000;
6af0bf9c
FB		 1602 }
1603}
1604
c01fccd2 1605void r4k_helper_tlbr (void)
6af0bf9c 1606{
c227f099 1607 r4k_tlb_t *tlb;
09c56b84 1608 uint8_t ASID;
bbc0d79c 1609 int idx;
6af0bf9c 1610
09c56b84 1611 ASID = env->CP0_EntryHi & 0xFF;
bbc0d79c
AJ		 1612 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1613 tlb = &env->tlb->mmu.r4k.tlb[idx];
4ad40f36
FB		 1614
1615 /* If this will change the current ASID, flush qemu's TLB. */
814b9a47
TS		 1616 if (ASID != tlb->ASID)
1617 cpu_mips_tlb_flush (env, 1);
1618
ead9360e 1619 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
4ad40f36 1620
6af0bf9c 1621 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
3b1c8be4 1622 env->CP0_PageMask = tlb->PageMask;
7495fd0f
TS		 1623 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1624 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1625 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1626 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
6af0bf9c 1627}
6af0bf9c 1628
c01fccd2 1629void helper_tlbwi(void)
a7812ae4 1630{
c01fccd2 1631 env->tlb->helper_tlbwi();
a7812ae4
PB		 1632}
1633
c01fccd2 1634void helper_tlbwr(void)
a7812ae4 1635{
c01fccd2 1636 env->tlb->helper_tlbwr();
a7812ae4
PB		 1637}
1638
c01fccd2 1639void helper_tlbp(void)
a7812ae4 1640{
c01fccd2 1641 env->tlb->helper_tlbp();
a7812ae4
PB		 1642}
1643
c01fccd2 1644void helper_tlbr(void)
a7812ae4 1645{
c01fccd2 1646 env->tlb->helper_tlbr();
a7812ae4
PB		 1647}
1648
2b0233ab 1649/* Specials */
c01fccd2 1650target_ulong helper_di (void)
2b0233ab 1651{
2796188e
TS		 1652 target_ulong t0 = env->CP0_Status;
1653
be24bb4f 1654 env->CP0_Status = t0 & ~(1 << CP0St_IE);
2b0233ab 1655 cpu_mips_update_irq(env);
be24bb4f
TS		 1656
1657 return t0;
2b0233ab
TS		 1658}
1659
c01fccd2 1660target_ulong helper_ei (void)
2b0233ab 1661{
2796188e
TS		 1662 target_ulong t0 = env->CP0_Status;
1663
be24bb4f 1664 env->CP0_Status = t0 | (1 << CP0St_IE);
2b0233ab 1665 cpu_mips_update_irq(env);
be24bb4f
TS		 1666
1667 return t0;
2b0233ab
TS		 1668}
1669
cd5158ea 1670static void debug_pre_eret (void)
6af0bf9c 1671{
8fec2b8c 1672 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
93fcfe39
AL		 1673 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1674 env->active_tc.PC, env->CP0_EPC);
1675 if (env->CP0_Status & (1 << CP0St_ERL))
1676 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1677 if (env->hflags & MIPS_HFLAG_DM)
1678 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1679 qemu_log("\n");
1680 }
f41c52f1
TS		 1681}
1682
cd5158ea 1683static void debug_post_eret (void)
f41c52f1 1684{
8fec2b8c 1685 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
93fcfe39
AL		 1686 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1687 env->active_tc.PC, env->CP0_EPC);
1688 if (env->CP0_Status & (1 << CP0St_ERL))
1689 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1690 if (env->hflags & MIPS_HFLAG_DM)
1691 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1692 switch (env->hflags & MIPS_HFLAG_KSU) {
1693 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1694 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1695 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1696 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1697 }
623a930e 1698 }
6af0bf9c
FB		 1699}
1700
32188a03
NF		 1701static void set_pc (target_ulong error_pc)
1702{
1703 env->active_tc.PC = error_pc & ~(target_ulong)1;
1704 if (error_pc & 1) {
1705 env->hflags |= MIPS_HFLAG_M16;
1706 } else {
1707 env->hflags &= ~(MIPS_HFLAG_M16);
1708 }
1709}
1710
c01fccd2 1711void helper_eret (void)
2b0233ab 1712{
93fcfe39 1713 debug_pre_eret();
2b0233ab 1714 if (env->CP0_Status & (1 << CP0St_ERL)) {
32188a03 1715 set_pc(env->CP0_ErrorEPC);
2b0233ab
TS		 1716 env->CP0_Status &= ~(1 << CP0St_ERL);
1717 } else {
32188a03 1718 set_pc(env->CP0_EPC);
2b0233ab
TS		 1719 env->CP0_Status &= ~(1 << CP0St_EXL);
1720 }
1721 compute_hflags(env);
93fcfe39 1722 debug_post_eret();
5499b6ff 1723 env->lladdr = 1;
2b0233ab
TS		 1724}
1725
c01fccd2 1726void helper_deret (void)
2b0233ab 1727{
93fcfe39 1728 debug_pre_eret();
32188a03
NF		 1729 set_pc(env->CP0_DEPC);
1730
2b0233ab
TS		 1731 env->hflags &= MIPS_HFLAG_DM;
1732 compute_hflags(env);
93fcfe39 1733 debug_post_eret();
5499b6ff 1734 env->lladdr = 1;
2b0233ab 1735}
0eaef5aa 1736#endif /* !CONFIG_USER_ONLY */
2b0233ab 1737
c01fccd2 1738target_ulong helper_rdhwr_cpunum(void)
2b0233ab
TS		 1739{
1740 if ((env->hflags & MIPS_HFLAG_CP0) ||
1741 (env->CP0_HWREna & (1 << 0)))
2796188e 1742 return env->CP0_EBase & 0x3ff;
2b0233ab 1743 else
c01fccd2 1744 helper_raise_exception(EXCP_RI);
be24bb4f 1745
2796188e 1746 return 0;
2b0233ab
TS		 1747}
1748
c01fccd2 1749target_ulong helper_rdhwr_synci_step(void)
2b0233ab
TS		 1750{
1751 if ((env->hflags & MIPS_HFLAG_CP0) ||
1752 (env->CP0_HWREna & (1 << 1)))
2796188e 1753 return env->SYNCI_Step;
2b0233ab 1754 else
c01fccd2 1755 helper_raise_exception(EXCP_RI);
be24bb4f 1756
2796188e 1757 return 0;
2b0233ab
TS		 1758}
1759
c01fccd2 1760target_ulong helper_rdhwr_cc(void)
2b0233ab
TS		 1761{
1762 if ((env->hflags & MIPS_HFLAG_CP0) ||
1763 (env->CP0_HWREna & (1 << 2)))
2796188e 1764 return env->CP0_Count;
2b0233ab 1765 else
c01fccd2 1766 helper_raise_exception(EXCP_RI);
be24bb4f 1767
2796188e 1768 return 0;
2b0233ab
TS		 1769}
1770
c01fccd2 1771target_ulong helper_rdhwr_ccres(void)
2b0233ab
TS		 1772{
1773 if ((env->hflags & MIPS_HFLAG_CP0) ||
1774 (env->CP0_HWREna & (1 << 3)))
2796188e 1775 return env->CCRes;
2b0233ab 1776 else
c01fccd2 1777 helper_raise_exception(EXCP_RI);
be24bb4f 1778
2796188e 1779 return 0;
2b0233ab
TS		 1780}
1781
c01fccd2 1782void helper_pmon (int function)
6af0bf9c
FB		 1783{
1784 function /= 2;
1785 switch (function) {
1786 case 2: /* TODO: char inbyte(int waitflag); */
b5dc7732
TS		 1787 if (env->active_tc.gpr[4] == 0)
1788 env->active_tc.gpr[2] = -1;
6af0bf9c
FB		 1789 /* Fall through */
1790 case 11: /* TODO: char inbyte (void); */
b5dc7732 1791 env->active_tc.gpr[2] = -1;
6af0bf9c
FB		 1792 break;
1793 case 3:
1794 case 12:
b5dc7732 1795 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
6af0bf9c
FB		 1796 break;
1797 case 17:
1798 break;
1799 case 158:
1800 {
b5dc7732 1801 unsigned char *fmt = (void *)(unsigned long)env->active_tc.gpr[4];
6af0bf9c
FB		 1802 printf("%s", fmt);
1803 }
1804 break;
1805 }
1806}
e37e863f 1807
c01fccd2 1808void helper_wait (void)
08ba7963
TS		 1809{
1810 env->halted = 1;
c01fccd2 1811 helper_raise_exception(EXCP_HLT);
08ba7963
TS		 1812}
1813
5fafdf24 1814#if !defined(CONFIG_USER_ONLY)
e37e863f 1815
4ad40f36
FB		 1816static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
1817
e37e863f 1818#define MMUSUFFIX _mmu
4ad40f36 1819#define ALIGNED_ONLY
e37e863f
FB		 1820
1821#define SHIFT 0
1822#include "softmmu_template.h"
1823
1824#define SHIFT 1
1825#include "softmmu_template.h"
1826
1827#define SHIFT 2
1828#include "softmmu_template.h"
1829
1830#define SHIFT 3
1831#include "softmmu_template.h"
1832
4ad40f36
FB		 1833static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
1834{
1835 env->CP0_BadVAddr = addr;
1836 do_restore_state (retaddr);
c01fccd2 1837 helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
4ad40f36
FB		 1838}
1839
6ebbf390 1840void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
e37e863f
FB		 1841{
1842 TranslationBlock *tb;
1843 CPUState *saved_env;
1844 unsigned long pc;
1845 int ret;
1846
1847 /* XXX: hack to restore env in all cases, even if not called from
1848 generated code */
1849 saved_env = env;
1850 env = cpu_single_env;
6ebbf390 1851 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
e37e863f
FB		 1852 if (ret) {
1853 if (retaddr) {
1854 /* now we have a real cpu fault */
1855 pc = (unsigned long)retaddr;
1856 tb = tb_find_pc(pc);
1857 if (tb) {
1858 /* the PC is inside the translated code. It means that we have
1859 a virtual CPU fault */
1860 cpu_restore_state(tb, env, pc, NULL);
1861 }
1862 }
c01fccd2 1863 helper_raise_exception_err(env->exception_index, env->error_code);
e37e863f
FB		 1864 }
1865 env = saved_env;
1866}
1867
c227f099 1868void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
e18231a3 1869 int unused, int size)
647de6ca
TS		 1870{
1871 if (is_exec)
c01fccd2 1872 helper_raise_exception(EXCP_IBE);
647de6ca 1873 else
c01fccd2 1874 helper_raise_exception(EXCP_DBE);
647de6ca 1875}
f1aa6320 1876#endif /* !CONFIG_USER_ONLY */
fd4a04eb
TS		 1877
1878/* Complex FPU operations which may need stack space. */
1879
f090c9d4
PB		 1880#define FLOAT_ONE32 make_float32(0x3f8 << 20)
1881#define FLOAT_ONE64 make_float64(0x3ffULL << 52)
1882#define FLOAT_TWO32 make_float32(1 << 30)
1883#define FLOAT_TWO64 make_float64(1ULL << 62)
54454097
TS		 1884#define FLOAT_QNAN32 0x7fbfffff
1885#define FLOAT_QNAN64 0x7ff7ffffffffffffULL
1886#define FLOAT_SNAN32 0x7fffffff
1887#define FLOAT_SNAN64 0x7fffffffffffffffULL
8dfdb87c 1888
fd4a04eb 1889/* convert MIPS rounding mode in FCR31 to IEEE library */
6f4fc367 1890static unsigned int ieee_rm[] = {
fd4a04eb
TS		 1891 float_round_nearest_even,
1892 float_round_to_zero,
1893 float_round_up,
1894 float_round_down
1895};
1896
1897#define RESTORE_ROUNDING_MODE \
f01be154 1898 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
fd4a04eb 1899
41e0c701
AJ		 1900#define RESTORE_FLUSH_MODE \
1901 set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status);
1902
c01fccd2 1903target_ulong helper_cfc1 (uint32_t reg)
fd4a04eb 1904{
d9bea114 1905 target_ulong arg1;
6c5c1e20 1906
ead9360e
TS		 1907 switch (reg) {
1908 case 0:
d9bea114 1909 arg1 = (int32_t)env->active_fpu.fcr0;
ead9360e
TS		 1910 break;
1911 case 25:
d9bea114 1912 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
ead9360e
TS		 1913 break;
1914 case 26:
d9bea114 1915 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
ead9360e
TS		 1916 break;
1917 case 28:
d9bea114 1918 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
ead9360e
TS		 1919 break;
1920 default:
d9bea114 1921 arg1 = (int32_t)env->active_fpu.fcr31;
ead9360e
TS		 1922 break;
1923 }
be24bb4f 1924
d9bea114 1925 return arg1;
ead9360e
TS		 1926}
1927
d9bea114 1928void helper_ctc1 (target_ulong arg1, uint32_t reg)
ead9360e
TS		 1929{
1930 switch(reg) {
fd4a04eb 1931 case 25:
d9bea114 1932 if (arg1 & 0xffffff00)
fd4a04eb 1933 return;
d9bea114
AJ		 1934 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
1935 ((arg1 & 0x1) << 23);
fd4a04eb
TS		 1936 break;
1937 case 26:
d9bea114 1938 if (arg1 & 0x007c0000)
fd4a04eb 1939 return;
d9bea114 1940 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
fd4a04eb
TS		 1941 break;
1942 case 28:
d9bea114 1943 if (arg1 & 0x007c0000)
fd4a04eb 1944 return;
d9bea114
AJ		 1945 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
1946 ((arg1 & 0x4) << 22);
fd4a04eb
TS		 1947 break;
1948 case 31:
d9bea114 1949 if (arg1 & 0x007c0000)
fd4a04eb 1950 return;
d9bea114 1951 env->active_fpu.fcr31 = arg1;
fd4a04eb
TS		 1952 break;
1953 default:
1954 return;
1955 }
1956 /* set rounding mode */
1957 RESTORE_ROUNDING_MODE;
41e0c701
AJ		 1958 /* set flush-to-zero mode */
1959 RESTORE_FLUSH_MODE;
f01be154
TS		 1960 set_float_exception_flags(0, &env->active_fpu.fp_status);
1961 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
c01fccd2 1962 helper_raise_exception(EXCP_FPE);
fd4a04eb
TS		 1963}
1964
c904ef0e 1965static inline char ieee_ex_to_mips(char xcpt)
fd4a04eb
TS		 1966{
1967 return (xcpt & float_flag_inexact) >> 5 |
1968 (xcpt & float_flag_underflow) >> 3 |
1969 (xcpt & float_flag_overflow) >> 1 |
1970 (xcpt & float_flag_divbyzero) << 1 |
1971 (xcpt & float_flag_invalid) << 4;
1972}
1973
c904ef0e 1974static inline char mips_ex_to_ieee(char xcpt)
fd4a04eb
TS		 1975{
1976 return (xcpt & FP_INEXACT) << 5 |
1977 (xcpt & FP_UNDERFLOW) << 3 |
1978 (xcpt & FP_OVERFLOW) << 1 |
1979 (xcpt & FP_DIV0) >> 1 |
1980 (xcpt & FP_INVALID) >> 4;
1981}
1982
c904ef0e 1983static inline void update_fcr31(void)
fd4a04eb 1984{
f01be154 1985 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
fd4a04eb 1986
f01be154
TS		 1987 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
1988 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp)
c01fccd2 1989 helper_raise_exception(EXCP_FPE);
fd4a04eb 1990 else
f01be154 1991 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
fd4a04eb
TS		 1992}
1993
a16336e4
TS		 1994/* Float support.
1995 Single precition routines have a "s" suffix, double precision a
1996 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
1997 paired single lower "pl", paired single upper "pu". */
1998
a16336e4 1999/* unary operations, modifying fp status */
c01fccd2 2000uint64_t helper_float_sqrt_d(uint64_t fdt0)
b6d96bed 2001{
f01be154 2002 return float64_sqrt(fdt0, &env->active_fpu.fp_status);
b6d96bed
TS		 2003}
2004
c01fccd2 2005uint32_t helper_float_sqrt_s(uint32_t fst0)
b6d96bed 2006{
f01be154 2007 return float32_sqrt(fst0, &env->active_fpu.fp_status);
b6d96bed 2008}
a16336e4 2009
c01fccd2 2010uint64_t helper_float_cvtd_s(uint32_t fst0)
fd4a04eb 2011{
b6d96bed
TS		 2012 uint64_t fdt2;
2013
f01be154
TS		 2014 set_float_exception_flags(0, &env->active_fpu.fp_status);
2015 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
fd4a04eb 2016 update_fcr31();
b6d96bed 2017 return fdt2;
fd4a04eb 2018}
b6d96bed 2019
c01fccd2 2020uint64_t helper_float_cvtd_w(uint32_t wt0)
fd4a04eb 2021{
b6d96bed
TS		 2022 uint64_t fdt2;
2023
f01be154
TS		 2024 set_float_exception_flags(0, &env->active_fpu.fp_status);
2025 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
fd4a04eb 2026 update_fcr31();
b6d96bed 2027 return fdt2;
fd4a04eb 2028}
b6d96bed 2029
c01fccd2 2030uint64_t helper_float_cvtd_l(uint64_t dt0)
fd4a04eb 2031{
b6d96bed
TS		 2032 uint64_t fdt2;
2033
f01be154
TS		 2034 set_float_exception_flags(0, &env->active_fpu.fp_status);
2035 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
fd4a04eb 2036 update_fcr31();
b6d96bed 2037 return fdt2;
fd4a04eb 2038}
b6d96bed 2039
c01fccd2 2040uint64_t helper_float_cvtl_d(uint64_t fdt0)
fd4a04eb 2041{
b6d96bed
TS		 2042 uint64_t dt2;
2043
f01be154
TS		 2044 set_float_exception_flags(0, &env->active_fpu.fp_status);
2045 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2046 update_fcr31();
f01be154 2047 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2048 dt2 = FLOAT_SNAN64;
2049 return dt2;
fd4a04eb 2050}
b6d96bed 2051
c01fccd2 2052uint64_t helper_float_cvtl_s(uint32_t fst0)
fd4a04eb 2053{
b6d96bed
TS		 2054 uint64_t dt2;
2055
f01be154
TS		 2056 set_float_exception_flags(0, &env->active_fpu.fp_status);
2057 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
fd4a04eb 2058 update_fcr31();
f01be154 2059 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2060 dt2 = FLOAT_SNAN64;
2061 return dt2;
fd4a04eb
TS		 2062}
2063
c01fccd2 2064uint64_t helper_float_cvtps_pw(uint64_t dt0)
fd4a04eb 2065{
b6d96bed
TS		 2066 uint32_t fst2;
2067 uint32_t fsth2;
2068
f01be154
TS		 2069 set_float_exception_flags(0, &env->active_fpu.fp_status);
2070 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2071 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
fd4a04eb 2072 update_fcr31();
b6d96bed 2073 return ((uint64_t)fsth2 << 32) | fst2;
fd4a04eb 2074}
b6d96bed 2075
c01fccd2 2076uint64_t helper_float_cvtpw_ps(uint64_t fdt0)
fd4a04eb 2077{
b6d96bed
TS		 2078 uint32_t wt2;
2079 uint32_t wth2;
2080
f01be154
TS		 2081 set_float_exception_flags(0, &env->active_fpu.fp_status);
2082 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2083 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
fd4a04eb 2084 update_fcr31();
f01be154 2085 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) {
b6d96bed
TS		 2086 wt2 = FLOAT_SNAN32;
2087 wth2 = FLOAT_SNAN32;
2088 }
2089 return ((uint64_t)wth2 << 32) | wt2;
fd4a04eb 2090}
b6d96bed 2091
c01fccd2 2092uint32_t helper_float_cvts_d(uint64_t fdt0)
fd4a04eb 2093{
b6d96bed
TS		 2094 uint32_t fst2;
2095
f01be154
TS		 2096 set_float_exception_flags(0, &env->active_fpu.fp_status);
2097 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2098 update_fcr31();
b6d96bed 2099 return fst2;
fd4a04eb 2100}
b6d96bed 2101
c01fccd2 2102uint32_t helper_float_cvts_w(uint32_t wt0)
fd4a04eb 2103{
b6d96bed
TS		 2104 uint32_t fst2;
2105
f01be154
TS		 2106 set_float_exception_flags(0, &env->active_fpu.fp_status);
2107 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
fd4a04eb 2108 update_fcr31();
b6d96bed 2109 return fst2;
fd4a04eb 2110}
b6d96bed 2111
c01fccd2 2112uint32_t helper_float_cvts_l(uint64_t dt0)
fd4a04eb 2113{
b6d96bed
TS		 2114 uint32_t fst2;
2115
f01be154
TS		 2116 set_float_exception_flags(0, &env->active_fpu.fp_status);
2117 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
fd4a04eb 2118 update_fcr31();
b6d96bed 2119 return fst2;
fd4a04eb 2120}
b6d96bed 2121
c01fccd2 2122uint32_t helper_float_cvts_pl(uint32_t wt0)
fd4a04eb 2123{
b6d96bed
TS		 2124 uint32_t wt2;
2125
f01be154 2126 set_float_exception_flags(0, &env->active_fpu.fp_status);
b6d96bed 2127 wt2 = wt0;
fd4a04eb 2128 update_fcr31();
b6d96bed 2129 return wt2;
fd4a04eb 2130}
b6d96bed 2131
c01fccd2 2132uint32_t helper_float_cvts_pu(uint32_t wth0)
fd4a04eb 2133{
b6d96bed
TS		 2134 uint32_t wt2;
2135
f01be154 2136 set_float_exception_flags(0, &env->active_fpu.fp_status);
b6d96bed 2137 wt2 = wth0;
fd4a04eb 2138 update_fcr31();
b6d96bed 2139 return wt2;
fd4a04eb 2140}
b6d96bed 2141
c01fccd2 2142uint32_t helper_float_cvtw_s(uint32_t fst0)
fd4a04eb 2143{
b6d96bed
TS		 2144 uint32_t wt2;
2145
f01be154
TS		 2146 set_float_exception_flags(0, &env->active_fpu.fp_status);
2147 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
fd4a04eb 2148 update_fcr31();
f01be154 2149 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2150 wt2 = FLOAT_SNAN32;
2151 return wt2;
fd4a04eb 2152}
b6d96bed 2153
c01fccd2 2154uint32_t helper_float_cvtw_d(uint64_t fdt0)
fd4a04eb 2155{
b6d96bed
TS		 2156 uint32_t wt2;
2157
f01be154
TS		 2158 set_float_exception_flags(0, &env->active_fpu.fp_status);
2159 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2160 update_fcr31();
f01be154 2161 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2162 wt2 = FLOAT_SNAN32;
2163 return wt2;
fd4a04eb
TS		 2164}
2165
c01fccd2 2166uint64_t helper_float_roundl_d(uint64_t fdt0)
fd4a04eb 2167{
b6d96bed
TS		 2168 uint64_t dt2;
2169
f01be154
TS		 2170 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2171 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2172 RESTORE_ROUNDING_MODE;
2173 update_fcr31();
f01be154 2174 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2175 dt2 = FLOAT_SNAN64;
2176 return dt2;
fd4a04eb 2177}
b6d96bed 2178
c01fccd2 2179uint64_t helper_float_roundl_s(uint32_t fst0)
fd4a04eb 2180{
b6d96bed
TS		 2181 uint64_t dt2;
2182
f01be154
TS		 2183 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2184 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2185 RESTORE_ROUNDING_MODE;
2186 update_fcr31();
f01be154 2187 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2188 dt2 = FLOAT_SNAN64;
2189 return dt2;
fd4a04eb 2190}
b6d96bed 2191
c01fccd2 2192uint32_t helper_float_roundw_d(uint64_t fdt0)
fd4a04eb 2193{
b6d96bed
TS		 2194 uint32_t wt2;
2195
f01be154
TS		 2196 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2197 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2198 RESTORE_ROUNDING_MODE;
2199 update_fcr31();
f01be154 2200 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2201 wt2 = FLOAT_SNAN32;
2202 return wt2;
fd4a04eb 2203}
b6d96bed 2204
c01fccd2 2205uint32_t helper_float_roundw_s(uint32_t fst0)
fd4a04eb 2206{
b6d96bed
TS		 2207 uint32_t wt2;
2208
f01be154
TS		 2209 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2210 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2211 RESTORE_ROUNDING_MODE;
2212 update_fcr31();
f01be154 2213 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2214 wt2 = FLOAT_SNAN32;
2215 return wt2;
fd4a04eb
TS		 2216}
2217
c01fccd2 2218uint64_t helper_float_truncl_d(uint64_t fdt0)
fd4a04eb 2219{
b6d96bed
TS		 2220 uint64_t dt2;
2221
f01be154 2222 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2223 update_fcr31();
f01be154 2224 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2225 dt2 = FLOAT_SNAN64;
2226 return dt2;
fd4a04eb 2227}
b6d96bed 2228
c01fccd2 2229uint64_t helper_float_truncl_s(uint32_t fst0)
fd4a04eb 2230{
b6d96bed
TS		 2231 uint64_t dt2;
2232
f01be154 2233 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
fd4a04eb 2234 update_fcr31();
f01be154 2235 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2236 dt2 = FLOAT_SNAN64;
2237 return dt2;
fd4a04eb 2238}
b6d96bed 2239
c01fccd2 2240uint32_t helper_float_truncw_d(uint64_t fdt0)
fd4a04eb 2241{
b6d96bed
TS		 2242 uint32_t wt2;
2243
f01be154 2244 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2245 update_fcr31();
f01be154 2246 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2247 wt2 = FLOAT_SNAN32;
2248 return wt2;
fd4a04eb 2249}
b6d96bed 2250
c01fccd2 2251uint32_t helper_float_truncw_s(uint32_t fst0)
fd4a04eb 2252{
b6d96bed
TS		 2253 uint32_t wt2;
2254
f01be154 2255 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
fd4a04eb 2256 update_fcr31();
f01be154 2257 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2258 wt2 = FLOAT_SNAN32;
2259 return wt2;
fd4a04eb
TS		 2260}
2261
c01fccd2 2262uint64_t helper_float_ceill_d(uint64_t fdt0)
fd4a04eb 2263{
b6d96bed
TS		 2264 uint64_t dt2;
2265
f01be154
TS		 2266 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2267 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2268 RESTORE_ROUNDING_MODE;
2269 update_fcr31();
f01be154 2270 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2271 dt2 = FLOAT_SNAN64;
2272 return dt2;
fd4a04eb 2273}
b6d96bed 2274
c01fccd2 2275uint64_t helper_float_ceill_s(uint32_t fst0)
fd4a04eb 2276{
b6d96bed
TS		 2277 uint64_t dt2;
2278
f01be154
TS		 2279 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2280 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2281 RESTORE_ROUNDING_MODE;
2282 update_fcr31();
f01be154 2283 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2284 dt2 = FLOAT_SNAN64;
2285 return dt2;
fd4a04eb 2286}
b6d96bed 2287
c01fccd2 2288uint32_t helper_float_ceilw_d(uint64_t fdt0)
fd4a04eb 2289{
b6d96bed
TS		 2290 uint32_t wt2;
2291
f01be154
TS		 2292 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2293 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2294 RESTORE_ROUNDING_MODE;
2295 update_fcr31();
f01be154 2296 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2297 wt2 = FLOAT_SNAN32;
2298 return wt2;
fd4a04eb 2299}
b6d96bed 2300
c01fccd2 2301uint32_t helper_float_ceilw_s(uint32_t fst0)
fd4a04eb 2302{
b6d96bed
TS		 2303 uint32_t wt2;
2304
f01be154
TS		 2305 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2306 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2307 RESTORE_ROUNDING_MODE;
2308 update_fcr31();
f01be154 2309 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2310 wt2 = FLOAT_SNAN32;
2311 return wt2;
fd4a04eb
TS		 2312}
2313
c01fccd2 2314uint64_t helper_float_floorl_d(uint64_t fdt0)
fd4a04eb 2315{
b6d96bed
TS		 2316 uint64_t dt2;
2317
f01be154
TS		 2318 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2319 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2320 RESTORE_ROUNDING_MODE;
2321 update_fcr31();
f01be154 2322 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2323 dt2 = FLOAT_SNAN64;
2324 return dt2;
fd4a04eb 2325}
b6d96bed 2326
c01fccd2 2327uint64_t helper_float_floorl_s(uint32_t fst0)
fd4a04eb 2328{
b6d96bed
TS		 2329 uint64_t dt2;
2330
f01be154
TS		 2331 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2332 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2333 RESTORE_ROUNDING_MODE;
2334 update_fcr31();
f01be154 2335 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2336 dt2 = FLOAT_SNAN64;
2337 return dt2;
fd4a04eb 2338}
b6d96bed 2339
c01fccd2 2340uint32_t helper_float_floorw_d(uint64_t fdt0)
fd4a04eb 2341{
b6d96bed
TS		 2342 uint32_t wt2;
2343
f01be154
TS		 2344 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2345 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2346 RESTORE_ROUNDING_MODE;
2347 update_fcr31();
f01be154 2348 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2349 wt2 = FLOAT_SNAN32;
2350 return wt2;
fd4a04eb 2351}
b6d96bed 2352
c01fccd2 2353uint32_t helper_float_floorw_s(uint32_t fst0)
fd4a04eb 2354{
b6d96bed
TS		 2355 uint32_t wt2;
2356
f01be154
TS		 2357 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2358 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2359 RESTORE_ROUNDING_MODE;
2360 update_fcr31();
f01be154 2361 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2362 wt2 = FLOAT_SNAN32;
2363 return wt2;
fd4a04eb
TS		 2364}
2365
a16336e4 2366/* unary operations, not modifying fp status */
b6d96bed 2367#define FLOAT_UNOP(name) \
c01fccd2 2368uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
b6d96bed
TS		 2369{ \
2370 return float64_ ## name(fdt0); \
2371} \
c01fccd2 2372uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
b6d96bed
TS		 2373{ \
2374 return float32_ ## name(fst0); \
2375} \
c01fccd2 2376uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
b6d96bed
TS		 2377{ \
2378 uint32_t wt0; \
2379 uint32_t wth0; \
2380 \
2381 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
2382 wth0 = float32_ ## name(fdt0 >> 32); \
2383 return ((uint64_t)wth0 << 32) | wt0; \
a16336e4
TS		 2384}
2385FLOAT_UNOP(abs)
2386FLOAT_UNOP(chs)
2387#undef FLOAT_UNOP
2388
8dfdb87c 2389/* MIPS specific unary operations */
c01fccd2 2390uint64_t helper_float_recip_d(uint64_t fdt0)
8dfdb87c 2391{
b6d96bed
TS		 2392 uint64_t fdt2;
2393
f01be154
TS		 2394 set_float_exception_flags(0, &env->active_fpu.fp_status);
2395 fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
8dfdb87c 2396 update_fcr31();
b6d96bed 2397 return fdt2;
8dfdb87c 2398}
b6d96bed 2399
c01fccd2 2400uint32_t helper_float_recip_s(uint32_t fst0)
8dfdb87c 2401{
b6d96bed
TS		 2402 uint32_t fst2;
2403
f01be154
TS		 2404 set_float_exception_flags(0, &env->active_fpu.fp_status);
2405 fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
8dfdb87c 2406 update_fcr31();
b6d96bed 2407 return fst2;
57fa1fb3 2408}
57fa1fb3 2409
c01fccd2 2410uint64_t helper_float_rsqrt_d(uint64_t fdt0)
8dfdb87c 2411{
b6d96bed
TS		 2412 uint64_t fdt2;
2413
f01be154
TS		 2414 set_float_exception_flags(0, &env->active_fpu.fp_status);
2415 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2416 fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
8dfdb87c 2417 update_fcr31();
b6d96bed 2418 return fdt2;
8dfdb87c 2419}
b6d96bed 2420
c01fccd2 2421uint32_t helper_float_rsqrt_s(uint32_t fst0)
8dfdb87c 2422{
b6d96bed
TS		 2423 uint32_t fst2;
2424
f01be154
TS		 2425 set_float_exception_flags(0, &env->active_fpu.fp_status);
2426 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2427 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
8dfdb87c 2428 update_fcr31();
b6d96bed 2429 return fst2;
8dfdb87c
TS		 2430}
2431
c01fccd2 2432uint64_t helper_float_recip1_d(uint64_t fdt0)
8dfdb87c 2433{
b6d96bed
TS		 2434 uint64_t fdt2;
2435
f01be154
TS		 2436 set_float_exception_flags(0, &env->active_fpu.fp_status);
2437 fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
8dfdb87c 2438 update_fcr31();
b6d96bed 2439 return fdt2;
8dfdb87c 2440}
b6d96bed 2441
c01fccd2 2442uint32_t helper_float_recip1_s(uint32_t fst0)
8dfdb87c 2443{
b6d96bed
TS		 2444 uint32_t fst2;
2445
f01be154
TS		 2446 set_float_exception_flags(0, &env->active_fpu.fp_status);
2447 fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
8dfdb87c 2448 update_fcr31();
b6d96bed 2449 return fst2;
8dfdb87c 2450}
b6d96bed 2451
c01fccd2 2452uint64_t helper_float_recip1_ps(uint64_t fdt0)
8dfdb87c 2453{
b6d96bed
TS		 2454 uint32_t fst2;
2455 uint32_t fsth2;
2456
f01be154
TS		 2457 set_float_exception_flags(0, &env->active_fpu.fp_status);
2458 fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2459 fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status);
8dfdb87c 2460 update_fcr31();
b6d96bed 2461 return ((uint64_t)fsth2 << 32) | fst2;
8dfdb87c
TS		 2462}
2463
c01fccd2 2464uint64_t helper_float_rsqrt1_d(uint64_t fdt0)
8dfdb87c 2465{
b6d96bed
TS		 2466 uint64_t fdt2;
2467
f01be154
TS		 2468 set_float_exception_flags(0, &env->active_fpu.fp_status);
2469 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2470 fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
8dfdb87c 2471 update_fcr31();
b6d96bed 2472 return fdt2;
8dfdb87c 2473}
b6d96bed 2474
c01fccd2 2475uint32_t helper_float_rsqrt1_s(uint32_t fst0)
8dfdb87c 2476{
b6d96bed
TS		 2477 uint32_t fst2;
2478
f01be154
TS		 2479 set_float_exception_flags(0, &env->active_fpu.fp_status);
2480 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2481 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
8dfdb87c 2482 update_fcr31();
b6d96bed 2483 return fst2;
8dfdb87c 2484}
b6d96bed 2485
c01fccd2 2486uint64_t helper_float_rsqrt1_ps(uint64_t fdt0)
8dfdb87c 2487{
b6d96bed
TS		 2488 uint32_t fst2;
2489 uint32_t fsth2;
2490
f01be154
TS		 2491 set_float_exception_flags(0, &env->active_fpu.fp_status);
2492 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2493 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2494 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2495 fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status);
8dfdb87c 2496 update_fcr31();
b6d96bed 2497 return ((uint64_t)fsth2 << 32) | fst2;
57fa1fb3 2498}
57fa1fb3 2499
c01fccd2 2500#define FLOAT_OP(name, p) void helper_float_##name##_##p(void)
b6d96bed 2501
fd4a04eb 2502/* binary operations */
b6d96bed 2503#define FLOAT_BINOP(name) \
c01fccd2 2504uint64_t helper_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \
b6d96bed
TS		 2505{ \
2506 uint64_t dt2; \
2507 \
f01be154
TS		 2508 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2509 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
ead9360e 2510 update_fcr31(); \
f01be154 2511 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
b6d96bed
TS		 2512 dt2 = FLOAT_QNAN64; \
2513 return dt2; \
2514} \
2515 \
c01fccd2 2516uint32_t helper_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \
b6d96bed
TS		 2517{ \
2518 uint32_t wt2; \
2519 \
f01be154
TS		 2520 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2521 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
ead9360e 2522 update_fcr31(); \
f01be154 2523 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
b6d96bed
TS		 2524 wt2 = FLOAT_QNAN32; \
2525 return wt2; \
2526} \
2527 \
c01fccd2 2528uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \
b6d96bed
TS		 2529{ \
2530 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2531 uint32_t fsth0 = fdt0 >> 32; \
2532 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2533 uint32_t fsth1 = fdt1 >> 32; \
2534 uint32_t wt2; \
2535 uint32_t wth2; \
2536 \
f01be154
TS		 2537 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2538 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2539 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
b6d96bed 2540 update_fcr31(); \
f01be154 2541 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \
b6d96bed
TS		 2542 wt2 = FLOAT_QNAN32; \
2543 wth2 = FLOAT_QNAN32; \
2544 } \
2545 return ((uint64_t)wth2 << 32) | wt2; \
fd4a04eb 2546}
b6d96bed 2547
fd4a04eb
TS		 2548FLOAT_BINOP(add)
2549FLOAT_BINOP(sub)
2550FLOAT_BINOP(mul)
2551FLOAT_BINOP(div)
2552#undef FLOAT_BINOP
2553
a16336e4 2554/* ternary operations */
b6d96bed 2555#define FLOAT_TERNOP(name1, name2) \
c01fccd2 2556uint64_t helper_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
b6d96bed
TS		 2557 uint64_t fdt2) \
2558{ \
f01be154
TS		 2559 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2560 return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2561} \
2562 \
c01fccd2 2563uint32_t helper_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
b6d96bed
TS		 2564 uint32_t fst2) \
2565{ \
f01be154
TS		 2566 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2567 return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2568} \
2569 \
c01fccd2 2570uint64_t helper_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \
b6d96bed
TS		 2571 uint64_t fdt2) \
2572{ \
2573 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2574 uint32_t fsth0 = fdt0 >> 32; \
2575 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2576 uint32_t fsth1 = fdt1 >> 32; \
2577 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2578 uint32_t fsth2 = fdt2 >> 32; \
2579 \
f01be154
TS		 2580 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2581 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
2582 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2583 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
b6d96bed 2584 return ((uint64_t)fsth2 << 32) | fst2; \
a16336e4 2585}
b6d96bed 2586
a16336e4
TS		 2587FLOAT_TERNOP(mul, add)
2588FLOAT_TERNOP(mul, sub)
2589#undef FLOAT_TERNOP
2590
2591/* negated ternary operations */
b6d96bed 2592#define FLOAT_NTERNOP(name1, name2) \
c01fccd2 2593uint64_t helper_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
b6d96bed
TS		 2594 uint64_t fdt2) \
2595{ \
f01be154
TS		 2596 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2597 fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2598 return float64_chs(fdt2); \
2599} \
2600 \
c01fccd2 2601uint32_t helper_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
b6d96bed
TS		 2602 uint32_t fst2) \
2603{ \
f01be154
TS		 2604 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2605 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2606 return float32_chs(fst2); \
2607} \
2608 \
c01fccd2 2609uint64_t helper_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\
b6d96bed
TS		 2610 uint64_t fdt2) \
2611{ \
2612 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2613 uint32_t fsth0 = fdt0 >> 32; \
2614 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2615 uint32_t fsth1 = fdt1 >> 32; \
2616 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2617 uint32_t fsth2 = fdt2 >> 32; \
2618 \
f01be154
TS		 2619 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2620 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
2621 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2622 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2623 fst2 = float32_chs(fst2); \
2624 fsth2 = float32_chs(fsth2); \
2625 return ((uint64_t)fsth2 << 32) | fst2; \
a16336e4 2626}
b6d96bed 2627
a16336e4
TS		 2628FLOAT_NTERNOP(mul, add)
2629FLOAT_NTERNOP(mul, sub)
2630#undef FLOAT_NTERNOP
2631
8dfdb87c 2632/* MIPS specific binary operations */
c01fccd2 2633uint64_t helper_float_recip2_d(uint64_t fdt0, uint64_t fdt2)
8dfdb87c 2634{
f01be154
TS		 2635 set_float_exception_flags(0, &env->active_fpu.fp_status);
2636 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2637 fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status));
8dfdb87c 2638 update_fcr31();
b6d96bed 2639 return fdt2;
8dfdb87c 2640}
b6d96bed 2641
c01fccd2 2642uint32_t helper_float_recip2_s(uint32_t fst0, uint32_t fst2)
8dfdb87c 2643{
f01be154
TS		 2644 set_float_exception_flags(0, &env->active_fpu.fp_status);
2645 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2646 fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
8dfdb87c 2647 update_fcr31();
b6d96bed 2648 return fst2;
8dfdb87c 2649}
b6d96bed 2650
c01fccd2 2651uint64_t helper_float_recip2_ps(uint64_t fdt0, uint64_t fdt2)
8dfdb87c 2652{
b6d96bed
TS		 2653 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2654 uint32_t fsth0 = fdt0 >> 32;
2655 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2656 uint32_t fsth2 = fdt2 >> 32;
2657
f01be154
TS		 2658 set_float_exception_flags(0, &env->active_fpu.fp_status);
2659 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2660 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2661 fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
2662 fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status));
8dfdb87c 2663 update_fcr31();
b6d96bed 2664 return ((uint64_t)fsth2 << 32) | fst2;
8dfdb87c
TS		 2665}
2666
c01fccd2 2667uint64_t helper_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2)
8dfdb87c 2668{
f01be154
TS		 2669 set_float_exception_flags(0, &env->active_fpu.fp_status);
2670 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2671 fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status);
2672 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
8dfdb87c 2673 update_fcr31();
b6d96bed 2674 return fdt2;
8dfdb87c 2675}
b6d96bed 2676
c01fccd2 2677uint32_t helper_float_rsqrt2_s(uint32_t fst0, uint32_t fst2)
8dfdb87c 2678{
f01be154
TS		 2679 set_float_exception_flags(0, &env->active_fpu.fp_status);
2680 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2681 fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
2682 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
8dfdb87c 2683 update_fcr31();
b6d96bed 2684 return fst2;
8dfdb87c 2685}
b6d96bed 2686
c01fccd2 2687uint64_t helper_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2)
8dfdb87c 2688{
b6d96bed
TS		 2689 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2690 uint32_t fsth0 = fdt0 >> 32;
2691 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2692 uint32_t fsth2 = fdt2 >> 32;
2693
f01be154
TS		 2694 set_float_exception_flags(0, &env->active_fpu.fp_status);
2695 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2696 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2697 fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
2698 fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status);
2699 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2700 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
8dfdb87c 2701 update_fcr31();
b6d96bed 2702 return ((uint64_t)fsth2 << 32) | fst2;
57fa1fb3 2703}
57fa1fb3 2704
c01fccd2 2705uint64_t helper_float_addr_ps(uint64_t fdt0, uint64_t fdt1)
fd4a04eb 2706{
b6d96bed
TS		 2707 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2708 uint32_t fsth0 = fdt0 >> 32;
2709 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2710 uint32_t fsth1 = fdt1 >> 32;
2711 uint32_t fst2;
2712 uint32_t fsth2;
2713
f01be154
TS		 2714 set_float_exception_flags(0, &env->active_fpu.fp_status);
2715 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
2716 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
fd4a04eb 2717 update_fcr31();
b6d96bed 2718 return ((uint64_t)fsth2 << 32) | fst2;
fd4a04eb
TS		 2719}
2720
c01fccd2 2721uint64_t helper_float_mulr_ps(uint64_t fdt0, uint64_t fdt1)
57fa1fb3 2722{
b6d96bed
TS		 2723 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2724 uint32_t fsth0 = fdt0 >> 32;
2725 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2726 uint32_t fsth1 = fdt1 >> 32;
2727 uint32_t fst2;
2728 uint32_t fsth2;
2729
f01be154
TS		 2730 set_float_exception_flags(0, &env->active_fpu.fp_status);
2731 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
2732 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
57fa1fb3 2733 update_fcr31();
b6d96bed 2734 return ((uint64_t)fsth2 << 32) | fst2;
57fa1fb3
TS		 2735}
2736
8dfdb87c 2737/* compare operations */
b6d96bed 2738#define FOP_COND_D(op, cond) \
c01fccd2 2739void helper_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
b6d96bed
TS		 2740{ \
2741 int c = cond; \
2742 update_fcr31(); \
2743 if (c) \
f01be154 2744 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2745 else \
f01be154 2746 CLEAR_FP_COND(cc, env->active_fpu); \
b6d96bed 2747} \
c01fccd2 2748void helper_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
b6d96bed
TS		 2749{ \
2750 int c; \
2751 fdt0 = float64_abs(fdt0); \
2752 fdt1 = float64_abs(fdt1); \
2753 c = cond; \
2754 update_fcr31(); \
2755 if (c) \
f01be154 2756 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2757 else \
f01be154 2758 CLEAR_FP_COND(cc, env->active_fpu); \
fd4a04eb
TS		 2759}
2760
cd5158ea 2761static int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
fd4a04eb
TS		 2762{
2763 if (float64_is_signaling_nan(a) ||
2764 float64_is_signaling_nan(b) ||
2765 (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
2766 float_raise(float_flag_invalid, status);
2767 return 1;
2768 } else if (float64_is_nan(a) || float64_is_nan(b)) {
2769 return 1;
2770 } else {
2771 return 0;
2772 }
2773}
2774
2775/* NOTE: the comma operator will make "cond" to eval to false,
2776 * but float*_is_unordered() is still called. */
f01be154
TS		 2777FOP_COND_D(f, (float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status), 0))
2778FOP_COND_D(un, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status))
2779FOP_COND_D(eq, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2780FOP_COND_D(ueq, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2781FOP_COND_D(olt, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2782FOP_COND_D(ult, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2783FOP_COND_D(ole, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2784FOP_COND_D(ule, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
fd4a04eb
TS		 2785/* NOTE: the comma operator will make "cond" to eval to false,
2786 * but float*_is_unordered() is still called. */
f01be154
TS		 2787FOP_COND_D(sf, (float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status), 0))
2788FOP_COND_D(ngle,float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status))
2789FOP_COND_D(seq, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2790FOP_COND_D(ngl, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2791FOP_COND_D(lt, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2792FOP_COND_D(nge, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2793FOP_COND_D(le, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2794FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
b6d96bed
TS		 2795
2796#define FOP_COND_S(op, cond) \
c01fccd2 2797void helper_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
b6d96bed
TS		 2798{ \
2799 int c = cond; \
2800 update_fcr31(); \
2801 if (c) \
f01be154 2802 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2803 else \
f01be154 2804 CLEAR_FP_COND(cc, env->active_fpu); \
b6d96bed 2805} \
c01fccd2 2806void helper_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
b6d96bed
TS		 2807{ \
2808 int c; \
2809 fst0 = float32_abs(fst0); \
2810 fst1 = float32_abs(fst1); \
2811 c = cond; \
2812 update_fcr31(); \
2813 if (c) \
f01be154 2814 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2815 else \
f01be154 2816 CLEAR_FP_COND(cc, env->active_fpu); \
fd4a04eb
TS		 2817}
2818
cd5158ea 2819static flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
fd4a04eb 2820{
fd4a04eb
TS		 2821 if (float32_is_signaling_nan(a) ||
2822 float32_is_signaling_nan(b) ||
2823 (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
2824 float_raise(float_flag_invalid, status);
2825 return 1;
2826 } else if (float32_is_nan(a) || float32_is_nan(b)) {
2827 return 1;
2828 } else {
2829 return 0;
2830 }
2831}
2832
2833/* NOTE: the comma operator will make "cond" to eval to false,
2834 * but float*_is_unordered() is still called. */
f01be154
TS		 2835FOP_COND_S(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0))
2836FOP_COND_S(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status))
2837FOP_COND_S(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2838FOP_COND_S(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2839FOP_COND_S(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2840FOP_COND_S(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2841FOP_COND_S(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
2842FOP_COND_S(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
fd4a04eb
TS		 2843/* NOTE: the comma operator will make "cond" to eval to false,
2844 * but float*_is_unordered() is still called. */
f01be154
TS		 2845FOP_COND_S(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0))
2846FOP_COND_S(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status))
2847FOP_COND_S(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2848FOP_COND_S(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2849FOP_COND_S(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2850FOP_COND_S(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2851FOP_COND_S(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
2852FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
b6d96bed
TS		 2853
2854#define FOP_COND_PS(op, condl, condh) \
c01fccd2 2855void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
b6d96bed
TS		 2856{ \
2857 uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
2858 uint32_t fsth0 = float32_abs(fdt0 >> 32); \
2859 uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
2860 uint32_t fsth1 = float32_abs(fdt1 >> 32); \
2861 int cl = condl; \
2862 int ch = condh; \
2863 \
2864 update_fcr31(); \
2865 if (cl) \
f01be154 2866 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2867 else \
f01be154 2868 CLEAR_FP_COND(cc, env->active_fpu); \
b6d96bed 2869 if (ch) \
f01be154 2870 SET_FP_COND(cc + 1, env->active_fpu); \
b6d96bed 2871 else \
f01be154 2872 CLEAR_FP_COND(cc + 1, env->active_fpu); \
b6d96bed 2873} \
c01fccd2 2874void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
b6d96bed
TS		 2875{ \
2876 uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
2877 uint32_t fsth0 = float32_abs(fdt0 >> 32); \
2878 uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
2879 uint32_t fsth1 = float32_abs(fdt1 >> 32); \
2880 int cl = condl; \
2881 int ch = condh; \
2882 \
2883 update_fcr31(); \
2884 if (cl) \
f01be154 2885 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2886 else \
f01be154 2887 CLEAR_FP_COND(cc, env->active_fpu); \
b6d96bed 2888 if (ch) \
f01be154 2889 SET_FP_COND(cc + 1, env->active_fpu); \
b6d96bed 2890 else \
f01be154 2891 CLEAR_FP_COND(cc + 1, env->active_fpu); \
fd4a04eb
TS		 2892}
2893
2894/* NOTE: the comma operator will make "cond" to eval to false,
2895 * but float*_is_unordered() is still called. */
f01be154
TS		 2896FOP_COND_PS(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0),
2897 (float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status), 0))
2898FOP_COND_PS(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status),
2899 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status))
2900FOP_COND_PS(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2901 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2902FOP_COND_PS(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2903 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2904FOP_COND_PS(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2905 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2906FOP_COND_PS(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2907 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2908FOP_COND_PS(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status),
2909 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
2910FOP_COND_PS(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
2911 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
fd4a04eb
TS		 2912/* NOTE: the comma operator will make "cond" to eval to false,
2913 * but float*_is_unordered() is still called. */
f01be154
TS		 2914FOP_COND_PS(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0),
2915 (float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status), 0))
2916FOP_COND_PS(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status),
2917 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status))
2918FOP_COND_PS(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2919 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2920FOP_COND_PS(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2921 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2922FOP_COND_PS(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2923 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2924FOP_COND_PS(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2925 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2926FOP_COND_PS(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status),
2927 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
2928FOP_COND_PS(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
2929 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
Qemu copy for testing