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roms: remove option rom packing logic
[qemu.git] / target-mips / op_helper.c
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6af0bf9c
FB		 1/*
2 * MIPS emulation helpers for qemu.
5fafdf24 3 *
6af0bf9c
FB		 4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
6af0bf9c 18 */
2d0e944d 19#include <stdlib.h>
6af0bf9c
FB		 20#include "exec.h"
21
05f778c8
TS		 22#include "host-utils.h"
23
a7812ae4 24#include "helper.h"
6af0bf9c
FB		 25/*****************************************************************************/
26/* Exceptions processing helpers */
6af0bf9c 27
c01fccd2 28void helper_raise_exception_err (uint32_t exception, int error_code)
6af0bf9c
FB		 29{
30#if 1
93fcfe39
AL		 31 if (exception < 0x100)
32 qemu_log("%s: %d %d\n", __func__, exception, error_code);
6af0bf9c
FB		 33#endif
34 env->exception_index = exception;
35 env->error_code = error_code;
6af0bf9c
FB		 36 cpu_loop_exit();
37}
38
c01fccd2 39void helper_raise_exception (uint32_t exception)
6af0bf9c 40{
c01fccd2 41 helper_raise_exception_err(exception, 0);
6af0bf9c
FB		 42}
43
c01fccd2 44void helper_interrupt_restart (void)
48d38ca5
TS		 45{
46 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
47 !(env->CP0_Status & (1 << CP0St_ERL)) &&
48 !(env->hflags & MIPS_HFLAG_DM) &&
49 (env->CP0_Status & (1 << CP0St_IE)) &&
50 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
51 env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
c01fccd2 52 helper_raise_exception(EXCP_EXT_INTERRUPT);
48d38ca5
TS		 53 }
54}
55
f9480ffc
TS		 56#if !defined(CONFIG_USER_ONLY)
57static void do_restore_state (void *pc_ptr)
4ad40f36 58{
a607922c
FB		 59 TranslationBlock *tb;
60 unsigned long pc = (unsigned long) pc_ptr;
61
62 tb = tb_find_pc (pc);
63 if (tb) {
64 cpu_restore_state (tb, env, pc, NULL);
65 }
4ad40f36 66}
f9480ffc 67#endif
4ad40f36 68
0ae43045
AJ		 69#if defined(CONFIG_USER_ONLY)
70#define HELPER_LD(name, insn, type) \
71static inline type do_##name(target_ulong addr, int mem_idx) \
72{ \
73 return (type) insn##_raw(addr); \
74}
75#else
76#define HELPER_LD(name, insn, type) \
77static inline type do_##name(target_ulong addr, int mem_idx) \
78{ \
79 switch (mem_idx) \
80 { \
81 case 0: return (type) insn##_kernel(addr); break; \
82 case 1: return (type) insn##_super(addr); break; \
83 default: \
84 case 2: return (type) insn##_user(addr); break; \
85 } \
86}
87#endif
88HELPER_LD(lbu, ldub, uint8_t)
89HELPER_LD(lw, ldl, int32_t)
90#ifdef TARGET_MIPS64
91HELPER_LD(ld, ldq, int64_t)
92#endif
93#undef HELPER_LD
94
95#if defined(CONFIG_USER_ONLY)
96#define HELPER_ST(name, insn, type) \
97static inline void do_##name(target_ulong addr, type val, int mem_idx) \
98{ \
99 insn##_raw(addr, val); \
100}
101#else
102#define HELPER_ST(name, insn, type) \
103static inline void do_##name(target_ulong addr, type val, int mem_idx) \
104{ \
105 switch (mem_idx) \
106 { \
107 case 0: insn##_kernel(addr, val); break; \
108 case 1: insn##_super(addr, val); break; \
109 default: \
110 case 2: insn##_user(addr, val); break; \
111 } \
112}
113#endif
114HELPER_ST(sb, stb, uint8_t)
115HELPER_ST(sw, stl, uint32_t)
116#ifdef TARGET_MIPS64
117HELPER_ST(sd, stq, uint64_t)
118#endif
119#undef HELPER_ST
120
d9bea114 121target_ulong helper_clo (target_ulong arg1)
30898801 122{
d9bea114 123 return clo32(arg1);
30898801
TS		 124}
125
d9bea114 126target_ulong helper_clz (target_ulong arg1)
30898801 127{
d9bea114 128 return clz32(arg1);
30898801
TS		 129}
130
d26bc211 131#if defined(TARGET_MIPS64)
d9bea114 132target_ulong helper_dclo (target_ulong arg1)
05f778c8 133{
d9bea114 134 return clo64(arg1);
05f778c8
TS		 135}
136
d9bea114 137target_ulong helper_dclz (target_ulong arg1)
05f778c8 138{
d9bea114 139 return clz64(arg1);
05f778c8 140}
d26bc211 141#endif /* TARGET_MIPS64 */
c570fd16 142
6af0bf9c 143/* 64 bits arithmetic for 32 bits hosts */
c904ef0e 144static inline uint64_t get_HILO (void)
6af0bf9c 145{
b5dc7732 146 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
6af0bf9c
FB		 147}
148
c904ef0e 149static inline void set_HILO (uint64_t HILO)
6af0bf9c 150{
b5dc7732
TS		 151 env->active_tc.LO[0] = (int32_t)HILO;
152 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
6af0bf9c
FB		 153}
154
d9bea114 155static inline void set_HIT0_LO (target_ulong arg1, uint64_t HILO)
e9c71dd1 156{
b5dc7732 157 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
d9bea114 158 arg1 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
e9c71dd1
TS		 159}
160
d9bea114 161static inline void set_HI_LOT0 (target_ulong arg1, uint64_t HILO)
e9c71dd1 162{
d9bea114 163 arg1 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
b5dc7732 164 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
e9c71dd1
TS		 165}
166
e9c71dd1 167/* Multiplication variants of the vr54xx. */
d9bea114 168target_ulong helper_muls (target_ulong arg1, target_ulong arg2)
e9c71dd1 169{
d9bea114 170 set_HI_LOT0(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 171
d9bea114 172 return arg1;
e9c71dd1
TS		 173}
174
d9bea114 175target_ulong helper_mulsu (target_ulong arg1, target_ulong arg2)
e9c71dd1 176{
d9bea114 177 set_HI_LOT0(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 178
d9bea114 179 return arg1;
e9c71dd1
TS		 180}
181
d9bea114 182target_ulong helper_macc (target_ulong arg1, target_ulong arg2)
e9c71dd1 183{
d9bea114 184 set_HI_LOT0(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 185
d9bea114 186 return arg1;
e9c71dd1
TS		 187}
188
d9bea114 189target_ulong helper_macchi (target_ulong arg1, target_ulong arg2)
e9c71dd1 190{
d9bea114 191 set_HIT0_LO(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 192
d9bea114 193 return arg1;
e9c71dd1
TS		 194}
195
d9bea114 196target_ulong helper_maccu (target_ulong arg1, target_ulong arg2)
e9c71dd1 197{
d9bea114 198 set_HI_LOT0(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 199
d9bea114 200 return arg1;
e9c71dd1
TS		 201}
202
d9bea114 203target_ulong helper_macchiu (target_ulong arg1, target_ulong arg2)
e9c71dd1 204{
d9bea114 205 set_HIT0_LO(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 206
d9bea114 207 return arg1;
e9c71dd1
TS		 208}
209
d9bea114 210target_ulong helper_msac (target_ulong arg1, target_ulong arg2)
e9c71dd1 211{
d9bea114 212 set_HI_LOT0(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 213
d9bea114 214 return arg1;
e9c71dd1
TS		 215}
216
d9bea114 217target_ulong helper_msachi (target_ulong arg1, target_ulong arg2)
e9c71dd1 218{
d9bea114 219 set_HIT0_LO(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 220
d9bea114 221 return arg1;
e9c71dd1
TS		 222}
223
d9bea114 224target_ulong helper_msacu (target_ulong arg1, target_ulong arg2)
e9c71dd1 225{
d9bea114 226 set_HI_LOT0(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 227
d9bea114 228 return arg1;
e9c71dd1
TS		 229}
230
d9bea114 231target_ulong helper_msachiu (target_ulong arg1, target_ulong arg2)
e9c71dd1 232{
d9bea114 233 set_HIT0_LO(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 234
d9bea114 235 return arg1;
e9c71dd1
TS		 236}
237
d9bea114 238target_ulong helper_mulhi (target_ulong arg1, target_ulong arg2)
e9c71dd1 239{
d9bea114 240 set_HIT0_LO(arg1, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
be24bb4f 241
d9bea114 242 return arg1;
e9c71dd1
TS		 243}
244
d9bea114 245target_ulong helper_mulhiu (target_ulong arg1, target_ulong arg2)
e9c71dd1 246{
d9bea114 247 set_HIT0_LO(arg1, (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
be24bb4f 248
d9bea114 249 return arg1;
e9c71dd1
TS		 250}
251
d9bea114 252target_ulong helper_mulshi (target_ulong arg1, target_ulong arg2)
e9c71dd1 253{
d9bea114 254 set_HIT0_LO(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 255
d9bea114 256 return arg1;
e9c71dd1
TS		 257}
258
d9bea114 259target_ulong helper_mulshiu (target_ulong arg1, target_ulong arg2)
e9c71dd1 260{
d9bea114 261 set_HIT0_LO(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 262
d9bea114 263 return arg1;
e9c71dd1 264}
6af0bf9c 265
214c465f 266#ifdef TARGET_MIPS64
d9bea114 267void helper_dmult (target_ulong arg1, target_ulong arg2)
214c465f 268{
d9bea114 269 muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
214c465f
TS		 270}
271
d9bea114 272void helper_dmultu (target_ulong arg1, target_ulong arg2)
214c465f 273{
d9bea114 274 mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
214c465f
TS		 275}
276#endif
277
e7139c44
AJ		 278#ifndef CONFIG_USER_ONLY
279#define HELPER_LD_ATOMIC(name, insn) \
280target_ulong helper_##name(target_ulong arg, int mem_idx) \
281{ \
282 env->lladdr = do_translate_address(env, arg, 0); \
283 env->llval = do_##insn(arg, mem_idx); \
284 return env->llval; \
285}
286HELPER_LD_ATOMIC(ll, lw)
287#ifdef TARGET_MIPS64
288HELPER_LD_ATOMIC(lld, ld)
289#endif
290#undef HELPER_LD_ATOMIC
291
292#define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
293target_ulong helper_##name(target_ulong arg1, target_ulong arg2, int mem_idx) \
294{ \
295 target_long tmp; \
296 \
297 if (arg2 & almask) { \
298 env->CP0_BadVAddr = arg2; \
299 helper_raise_exception(EXCP_AdES); \
300 } \
301 if (do_translate_address(env, arg2, 1) == env->lladdr) { \
302 tmp = do_##ld_insn(arg2, mem_idx); \
303 if (tmp == env->llval) { \
304 do_##st_insn(arg2, arg1, mem_idx); \
305 return 1; \
306 } \
307 } \
308 return 0; \
309}
310HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
311#ifdef TARGET_MIPS64
312HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
313#endif
314#undef HELPER_ST_ATOMIC
315#endif
316
c8c2227e
TS		 317#ifdef TARGET_WORDS_BIGENDIAN
318#define GET_LMASK(v) ((v) & 3)
319#define GET_OFFSET(addr, offset) (addr + (offset))
320#else
321#define GET_LMASK(v) (((v) & 3) ^ 3)
322#define GET_OFFSET(addr, offset) (addr - (offset))
323#endif
324
d9bea114 325target_ulong helper_lwl(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e
TS		 326{
327 target_ulong tmp;
328
0ae43045 329 tmp = do_lbu(arg2, mem_idx);
d9bea114 330 arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
c8c2227e 331
d9bea114 332 if (GET_LMASK(arg2) <= 2) {
0ae43045 333 tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx);
d9bea114 334 arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
c8c2227e
TS		 335 }
336
d9bea114 337 if (GET_LMASK(arg2) <= 1) {
0ae43045 338 tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx);
d9bea114 339 arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
c8c2227e
TS		 340 }
341
d9bea114 342 if (GET_LMASK(arg2) == 0) {
0ae43045 343 tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx);
d9bea114 344 arg1 = (arg1 & 0xFFFFFF00) | tmp;
c8c2227e 345 }
d9bea114 346 return (int32_t)arg1;
c8c2227e
TS		 347}
348
d9bea114 349target_ulong helper_lwr(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e
TS		 350{
351 target_ulong tmp;
352
0ae43045 353 tmp = do_lbu(arg2, mem_idx);
d9bea114 354 arg1 = (arg1 & 0xFFFFFF00) | tmp;
c8c2227e 355
d9bea114 356 if (GET_LMASK(arg2) >= 1) {
0ae43045 357 tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx);
d9bea114 358 arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
c8c2227e
TS		 359 }
360
d9bea114 361 if (GET_LMASK(arg2) >= 2) {
0ae43045 362 tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx);
d9bea114 363 arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
c8c2227e
TS		 364 }
365
d9bea114 366 if (GET_LMASK(arg2) == 3) {
0ae43045 367 tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx);
d9bea114 368 arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
c8c2227e 369 }
d9bea114 370 return (int32_t)arg1;
c8c2227e
TS		 371}
372
d9bea114 373void helper_swl(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e 374{
0ae43045 375 do_sb(arg2, (uint8_t)(arg1 >> 24), mem_idx);
c8c2227e 376
d9bea114 377 if (GET_LMASK(arg2) <= 2)
0ae43045 378 do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
c8c2227e 379
d9bea114 380 if (GET_LMASK(arg2) <= 1)
0ae43045 381 do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
c8c2227e 382
d9bea114 383 if (GET_LMASK(arg2) == 0)
0ae43045 384 do_sb(GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
c8c2227e
TS		 385}
386
d9bea114 387void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e 388{
0ae43045 389 do_sb(arg2, (uint8_t)arg1, mem_idx);
c8c2227e 390
d9bea114 391 if (GET_LMASK(arg2) >= 1)
0ae43045 392 do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
c8c2227e 393
d9bea114 394 if (GET_LMASK(arg2) >= 2)
0ae43045 395 do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
c8c2227e 396
d9bea114 397 if (GET_LMASK(arg2) == 3)
0ae43045 398 do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
c8c2227e
TS		 399}
400
401#if defined(TARGET_MIPS64)
402/* "half" load and stores. We must do the memory access inline,
403 or fault handling won't work. */
404
405#ifdef TARGET_WORDS_BIGENDIAN
406#define GET_LMASK64(v) ((v) & 7)
407#else
408#define GET_LMASK64(v) (((v) & 7) ^ 7)
409#endif
410
d9bea114 411target_ulong helper_ldl(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e
TS		 412{
413 uint64_t tmp;
414
0ae43045 415 tmp = do_lbu(arg2, mem_idx);
d9bea114 416 arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
c8c2227e 417
d9bea114 418 if (GET_LMASK64(arg2) <= 6) {
0ae43045 419 tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx);
d9bea114 420 arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
c8c2227e
TS		 421 }
422
d9bea114 423 if (GET_LMASK64(arg2) <= 5) {
0ae43045 424 tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx);
d9bea114 425 arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
c8c2227e
TS		 426 }
427
d9bea114 428 if (GET_LMASK64(arg2) <= 4) {
0ae43045 429 tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx);
d9bea114 430 arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
c8c2227e
TS		 431 }
432
d9bea114 433 if (GET_LMASK64(arg2) <= 3) {
0ae43045 434 tmp = do_lbu(GET_OFFSET(arg2, 4), mem_idx);
d9bea114 435 arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
c8c2227e
TS		 436 }
437
d9bea114 438 if (GET_LMASK64(arg2) <= 2) {
0ae43045 439 tmp = do_lbu(GET_OFFSET(arg2, 5), mem_idx);
d9bea114 440 arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
c8c2227e
TS		 441 }
442
d9bea114 443 if (GET_LMASK64(arg2) <= 1) {
0ae43045 444 tmp = do_lbu(GET_OFFSET(arg2, 6), mem_idx);
d9bea114 445 arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
c8c2227e
TS		 446 }
447
d9bea114 448 if (GET_LMASK64(arg2) == 0) {
0ae43045 449 tmp = do_lbu(GET_OFFSET(arg2, 7), mem_idx);
d9bea114 450 arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
c8c2227e 451 }
be24bb4f 452
d9bea114 453 return arg1;
c8c2227e
TS		 454}
455
d9bea114 456target_ulong helper_ldr(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e
TS		 457{
458 uint64_t tmp;
459
0ae43045 460 tmp = do_lbu(arg2, mem_idx);
d9bea114 461 arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
c8c2227e 462
d9bea114 463 if (GET_LMASK64(arg2) >= 1) {
0ae43045 464 tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx);
d9bea114 465 arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
c8c2227e
TS		 466 }
467
d9bea114 468 if (GET_LMASK64(arg2) >= 2) {
0ae43045 469 tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx);
d9bea114 470 arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
c8c2227e
TS		 471 }
472
d9bea114 473 if (GET_LMASK64(arg2) >= 3) {
0ae43045 474 tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx);
d9bea114 475 arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
c8c2227e
TS		 476 }
477
d9bea114 478 if (GET_LMASK64(arg2) >= 4) {
0ae43045 479 tmp = do_lbu(GET_OFFSET(arg2, -4), mem_idx);
d9bea114 480 arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
c8c2227e
TS		 481 }
482
d9bea114 483 if (GET_LMASK64(arg2) >= 5) {
0ae43045 484 tmp = do_lbu(GET_OFFSET(arg2, -5), mem_idx);
d9bea114 485 arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
c8c2227e
TS		 486 }
487
d9bea114 488 if (GET_LMASK64(arg2) >= 6) {
0ae43045 489 tmp = do_lbu(GET_OFFSET(arg2, -6), mem_idx);
d9bea114 490 arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
c8c2227e
TS		 491 }
492
d9bea114 493 if (GET_LMASK64(arg2) == 7) {
0ae43045 494 tmp = do_lbu(GET_OFFSET(arg2, -7), mem_idx);
d9bea114 495 arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
c8c2227e 496 }
be24bb4f 497
d9bea114 498 return arg1;
c8c2227e
TS		 499}
500
d9bea114 501void helper_sdl(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e 502{
0ae43045 503 do_sb(arg2, (uint8_t)(arg1 >> 56), mem_idx);
c8c2227e 504
d9bea114 505 if (GET_LMASK64(arg2) <= 6)
0ae43045 506 do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
c8c2227e 507
d9bea114 508 if (GET_LMASK64(arg2) <= 5)
0ae43045 509 do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
c8c2227e 510
d9bea114 511 if (GET_LMASK64(arg2) <= 4)
0ae43045 512 do_sb(GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
c8c2227e 513
d9bea114 514 if (GET_LMASK64(arg2) <= 3)
0ae43045 515 do_sb(GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
c8c2227e 516
d9bea114 517 if (GET_LMASK64(arg2) <= 2)
0ae43045 518 do_sb(GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
c8c2227e 519
d9bea114 520 if (GET_LMASK64(arg2) <= 1)
0ae43045 521 do_sb(GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
c8c2227e 522
d9bea114 523 if (GET_LMASK64(arg2) <= 0)
0ae43045 524 do_sb(GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
c8c2227e
TS		 525}
526
d9bea114 527void helper_sdr(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e 528{
0ae43045 529 do_sb(arg2, (uint8_t)arg1, mem_idx);
c8c2227e 530
d9bea114 531 if (GET_LMASK64(arg2) >= 1)
0ae43045 532 do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
c8c2227e 533
d9bea114 534 if (GET_LMASK64(arg2) >= 2)
0ae43045 535 do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
c8c2227e 536
d9bea114 537 if (GET_LMASK64(arg2) >= 3)
0ae43045 538 do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
c8c2227e 539
d9bea114 540 if (GET_LMASK64(arg2) >= 4)
0ae43045 541 do_sb(GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
c8c2227e 542
d9bea114 543 if (GET_LMASK64(arg2) >= 5)
0ae43045 544 do_sb(GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
c8c2227e 545
d9bea114 546 if (GET_LMASK64(arg2) >= 6)
0ae43045 547 do_sb(GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
c8c2227e 548
d9bea114 549 if (GET_LMASK64(arg2) == 7)
0ae43045 550 do_sb(GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
c8c2227e
TS		 551}
552#endif /* TARGET_MIPS64 */
553
0eaef5aa 554#ifndef CONFIG_USER_ONLY
6af0bf9c 555/* CP0 helpers */
c01fccd2 556target_ulong helper_mfc0_mvpcontrol (void)
f1aa6320 557{
be24bb4f 558 return env->mvp->CP0_MVPControl;
f1aa6320
TS		 559}
560
c01fccd2 561target_ulong helper_mfc0_mvpconf0 (void)
f1aa6320 562{
be24bb4f 563 return env->mvp->CP0_MVPConf0;
f1aa6320
TS		 564}
565
c01fccd2 566target_ulong helper_mfc0_mvpconf1 (void)
f1aa6320 567{
be24bb4f 568 return env->mvp->CP0_MVPConf1;
f1aa6320
TS		 569}
570
c01fccd2 571target_ulong helper_mfc0_random (void)
6af0bf9c 572{
be24bb4f 573 return (int32_t)cpu_mips_get_random(env);
873eb012 574}
6af0bf9c 575
c01fccd2 576target_ulong helper_mfc0_tcstatus (void)
f1aa6320 577{
b5dc7732 578 return env->active_tc.CP0_TCStatus;
f1aa6320
TS		 579}
580
c01fccd2 581target_ulong helper_mftc0_tcstatus(void)
f1aa6320
TS		 582{
583 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
584
b5dc7732
TS		 585 if (other_tc == env->current_tc)
586 return env->active_tc.CP0_TCStatus;
587 else
588 return env->tcs[other_tc].CP0_TCStatus;
f1aa6320
TS		 589}
590
c01fccd2 591target_ulong helper_mfc0_tcbind (void)
f1aa6320 592{
b5dc7732 593 return env->active_tc.CP0_TCBind;
f1aa6320
TS		 594}
595
c01fccd2 596target_ulong helper_mftc0_tcbind(void)
f1aa6320
TS		 597{
598 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
599
b5dc7732
TS		 600 if (other_tc == env->current_tc)
601 return env->active_tc.CP0_TCBind;
602 else
603 return env->tcs[other_tc].CP0_TCBind;
f1aa6320
TS		 604}
605
c01fccd2 606target_ulong helper_mfc0_tcrestart (void)
f1aa6320 607{
b5dc7732 608 return env->active_tc.PC;
f1aa6320
TS		 609}
610
c01fccd2 611target_ulong helper_mftc0_tcrestart(void)
f1aa6320
TS		 612{
613 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
614
b5dc7732
TS		 615 if (other_tc == env->current_tc)
616 return env->active_tc.PC;
617 else
618 return env->tcs[other_tc].PC;
f1aa6320
TS		 619}
620
c01fccd2 621target_ulong helper_mfc0_tchalt (void)
f1aa6320 622{
b5dc7732 623 return env->active_tc.CP0_TCHalt;
f1aa6320
TS		 624}
625
c01fccd2 626target_ulong helper_mftc0_tchalt(void)
f1aa6320
TS		 627{
628 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
629
b5dc7732
TS		 630 if (other_tc == env->current_tc)
631 return env->active_tc.CP0_TCHalt;
632 else
633 return env->tcs[other_tc].CP0_TCHalt;
f1aa6320
TS		 634}
635
c01fccd2 636target_ulong helper_mfc0_tccontext (void)
f1aa6320 637{
b5dc7732 638 return env->active_tc.CP0_TCContext;
f1aa6320
TS		 639}
640
c01fccd2 641target_ulong helper_mftc0_tccontext(void)
f1aa6320
TS		 642{
643 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
644
b5dc7732
TS		 645 if (other_tc == env->current_tc)
646 return env->active_tc.CP0_TCContext;
647 else
648 return env->tcs[other_tc].CP0_TCContext;
f1aa6320
TS		 649}
650
c01fccd2 651target_ulong helper_mfc0_tcschedule (void)
f1aa6320 652{
b5dc7732 653 return env->active_tc.CP0_TCSchedule;
f1aa6320
TS		 654}
655
c01fccd2 656target_ulong helper_mftc0_tcschedule(void)
f1aa6320
TS		 657{
658 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
659
b5dc7732
TS		 660 if (other_tc == env->current_tc)
661 return env->active_tc.CP0_TCSchedule;
662 else
663 return env->tcs[other_tc].CP0_TCSchedule;
f1aa6320
TS		 664}
665
c01fccd2 666target_ulong helper_mfc0_tcschefback (void)
f1aa6320 667{
b5dc7732 668 return env->active_tc.CP0_TCScheFBack;
f1aa6320
TS		 669}
670
c01fccd2 671target_ulong helper_mftc0_tcschefback(void)
f1aa6320
TS		 672{
673 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
674
b5dc7732
TS		 675 if (other_tc == env->current_tc)
676 return env->active_tc.CP0_TCScheFBack;
677 else
678 return env->tcs[other_tc].CP0_TCScheFBack;
f1aa6320
TS		 679}
680
c01fccd2 681target_ulong helper_mfc0_count (void)
873eb012 682{
be24bb4f 683 return (int32_t)cpu_mips_get_count(env);
6af0bf9c
FB		 684}
685
c01fccd2 686target_ulong helper_mftc0_entryhi(void)
f1aa6320
TS		 687{
688 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
b5dc7732 689 int32_t tcstatus;
f1aa6320 690
b5dc7732
TS		 691 if (other_tc == env->current_tc)
692 tcstatus = env->active_tc.CP0_TCStatus;
693 else
694 tcstatus = env->tcs[other_tc].CP0_TCStatus;
695
696 return (env->CP0_EntryHi & ~0xff) | (tcstatus & 0xff);
f1aa6320
TS		 697}
698
c01fccd2 699target_ulong helper_mftc0_status(void)
f1aa6320
TS		 700{
701 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1a3fd9c3 702 target_ulong t0;
b5dc7732
TS		 703 int32_t tcstatus;
704
705 if (other_tc == env->current_tc)
706 tcstatus = env->active_tc.CP0_TCStatus;
707 else
708 tcstatus = env->tcs[other_tc].CP0_TCStatus;
f1aa6320 709
be24bb4f
TS		 710 t0 = env->CP0_Status & ~0xf1000018;
711 t0 |= tcstatus & (0xf << CP0TCSt_TCU0);
712 t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
713 t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
714
715 return t0;
f1aa6320
TS		 716}
717
c01fccd2 718target_ulong helper_mfc0_lladdr (void)
f1aa6320 719{
2a6e32dd 720 return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
f1aa6320
TS		 721}
722
c01fccd2 723target_ulong helper_mfc0_watchlo (uint32_t sel)
f1aa6320 724{
be24bb4f 725 return (int32_t)env->CP0_WatchLo[sel];
f1aa6320
TS		 726}
727
c01fccd2 728target_ulong helper_mfc0_watchhi (uint32_t sel)
f1aa6320 729{
be24bb4f 730 return env->CP0_WatchHi[sel];
f1aa6320
TS		 731}
732
c01fccd2 733target_ulong helper_mfc0_debug (void)
f1aa6320 734{
1a3fd9c3 735 target_ulong t0 = env->CP0_Debug;
f1aa6320 736 if (env->hflags & MIPS_HFLAG_DM)
be24bb4f
TS		 737 t0 |= 1 << CP0DB_DM;
738
739 return t0;
f1aa6320
TS		 740}
741
c01fccd2 742target_ulong helper_mftc0_debug(void)
f1aa6320
TS		 743{
744 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
b5dc7732
TS		 745 int32_t tcstatus;
746
747 if (other_tc == env->current_tc)
748 tcstatus = env->active_tc.CP0_Debug_tcstatus;
749 else
750 tcstatus = env->tcs[other_tc].CP0_Debug_tcstatus;
f1aa6320
TS		 751
752 /* XXX: Might be wrong, check with EJTAG spec. */
be24bb4f 753 return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
b5dc7732 754 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
f1aa6320
TS		 755}
756
757#if defined(TARGET_MIPS64)
c01fccd2 758target_ulong helper_dmfc0_tcrestart (void)
f1aa6320 759{
b5dc7732 760 return env->active_tc.PC;
f1aa6320
TS		 761}
762
c01fccd2 763target_ulong helper_dmfc0_tchalt (void)
f1aa6320 764{
b5dc7732 765 return env->active_tc.CP0_TCHalt;
f1aa6320
TS		 766}
767
c01fccd2 768target_ulong helper_dmfc0_tccontext (void)
f1aa6320 769{
b5dc7732 770 return env->active_tc.CP0_TCContext;
f1aa6320
TS		 771}
772
c01fccd2 773target_ulong helper_dmfc0_tcschedule (void)
f1aa6320 774{
b5dc7732 775 return env->active_tc.CP0_TCSchedule;
f1aa6320
TS		 776}
777
c01fccd2 778target_ulong helper_dmfc0_tcschefback (void)
f1aa6320 779{
b5dc7732 780 return env->active_tc.CP0_TCScheFBack;
f1aa6320
TS		 781}
782
c01fccd2 783target_ulong helper_dmfc0_lladdr (void)
f1aa6320 784{
2a6e32dd 785 return env->lladdr >> env->CP0_LLAddr_shift;
f1aa6320
TS		 786}
787
c01fccd2 788target_ulong helper_dmfc0_watchlo (uint32_t sel)
f1aa6320 789{
be24bb4f 790 return env->CP0_WatchLo[sel];
f1aa6320
TS		 791}
792#endif /* TARGET_MIPS64 */
793
d9bea114 794void helper_mtc0_index (target_ulong arg1)
f1aa6320
TS		 795{
796 int num = 1;
797 unsigned int tmp = env->tlb->nb_tlb;
798
799 do {
800 tmp >>= 1;
801 num <<= 1;
802 } while (tmp);
d9bea114 803 env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
f1aa6320
TS		 804}
805
d9bea114 806void helper_mtc0_mvpcontrol (target_ulong arg1)
f1aa6320
TS		 807{
808 uint32_t mask = 0;
809 uint32_t newval;
810
811 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
812 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
813 (1 << CP0MVPCo_EVP);
814 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
815 mask |= (1 << CP0MVPCo_STLB);
d9bea114 816 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
f1aa6320
TS		 817
818 // TODO: Enable/disable shared TLB, enable/disable VPEs.
819
820 env->mvp->CP0_MVPControl = newval;
821}
822
d9bea114 823void helper_mtc0_vpecontrol (target_ulong arg1)
f1aa6320
TS		 824{
825 uint32_t mask;
826 uint32_t newval;
827
828 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
829 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
d9bea114 830 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
f1aa6320
TS		 831
832 /* Yield scheduler intercept not implemented. */
833 /* Gating storage scheduler intercept not implemented. */
834
835 // TODO: Enable/disable TCs.
836
837 env->CP0_VPEControl = newval;
838}
839
d9bea114 840void helper_mtc0_vpeconf0 (target_ulong arg1)
f1aa6320
TS		 841{
842 uint32_t mask = 0;
843 uint32_t newval;
844
845 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
846 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
847 mask |= (0xff << CP0VPEC0_XTC);
848 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
849 }
d9bea114 850 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
f1aa6320
TS		 851
852 // TODO: TC exclusive handling due to ERL/EXL.
853
854 env->CP0_VPEConf0 = newval;
855}
856
d9bea114 857void helper_mtc0_vpeconf1 (target_ulong arg1)
f1aa6320
TS		 858{
859 uint32_t mask = 0;
860 uint32_t newval;
861
862 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
863 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
864 (0xff << CP0VPEC1_NCP1);
d9bea114 865 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
f1aa6320
TS		 866
867 /* UDI not implemented. */
868 /* CP2 not implemented. */
869
870 // TODO: Handle FPU (CP1) binding.
871
872 env->CP0_VPEConf1 = newval;
873}
874
d9bea114 875void helper_mtc0_yqmask (target_ulong arg1)
f1aa6320
TS		 876{
877 /* Yield qualifier inputs not implemented. */
878 env->CP0_YQMask = 0x00000000;
879}
880
d9bea114 881void helper_mtc0_vpeopt (target_ulong arg1)
f1aa6320 882{
d9bea114 883 env->CP0_VPEOpt = arg1 & 0x0000ffff;
f1aa6320
TS		 884}
885
d9bea114 886void helper_mtc0_entrylo0 (target_ulong arg1)
f1aa6320
TS		 887{
888 /* Large physaddr (PABITS) not implemented */
889 /* 1k pages not implemented */
d9bea114 890 env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
f1aa6320
TS		 891}
892
d9bea114 893void helper_mtc0_tcstatus (target_ulong arg1)
f1aa6320
TS		 894{
895 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
896 uint32_t newval;
897
d9bea114 898 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
f1aa6320
TS		 899
900 // TODO: Sync with CP0_Status.
901
b5dc7732 902 env->active_tc.CP0_TCStatus = newval;
f1aa6320
TS		 903}
904
d9bea114 905void helper_mttc0_tcstatus (target_ulong arg1)
f1aa6320
TS		 906{
907 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
908
909 // TODO: Sync with CP0_Status.
910
b5dc7732 911 if (other_tc == env->current_tc)
d9bea114 912 env->active_tc.CP0_TCStatus = arg1;
b5dc7732 913 else
d9bea114 914 env->tcs[other_tc].CP0_TCStatus = arg1;
f1aa6320
TS		 915}
916
d9bea114 917void helper_mtc0_tcbind (target_ulong arg1)
f1aa6320
TS		 918{
919 uint32_t mask = (1 << CP0TCBd_TBE);
920 uint32_t newval;
921
922 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
923 mask |= (1 << CP0TCBd_CurVPE);
d9bea114 924 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
b5dc7732 925 env->active_tc.CP0_TCBind = newval;
f1aa6320
TS		 926}
927
d9bea114 928void helper_mttc0_tcbind (target_ulong arg1)
f1aa6320
TS		 929{
930 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
931 uint32_t mask = (1 << CP0TCBd_TBE);
932 uint32_t newval;
933
934 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
935 mask |= (1 << CP0TCBd_CurVPE);
b5dc7732 936 if (other_tc == env->current_tc) {
d9bea114 937 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
b5dc7732
TS		 938 env->active_tc.CP0_TCBind = newval;
939 } else {
d9bea114 940 newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
b5dc7732
TS		 941 env->tcs[other_tc].CP0_TCBind = newval;
942 }
f1aa6320
TS		 943}
944
d9bea114 945void helper_mtc0_tcrestart (target_ulong arg1)
f1aa6320 946{
d9bea114 947 env->active_tc.PC = arg1;
b5dc7732 948 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
5499b6ff 949 env->lladdr = 0ULL;
f1aa6320
TS		 950 /* MIPS16 not implemented. */
951}
952
d9bea114 953void helper_mttc0_tcrestart (target_ulong arg1)
f1aa6320
TS		 954{
955 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
956
b5dc7732 957 if (other_tc == env->current_tc) {
d9bea114 958 env->active_tc.PC = arg1;
b5dc7732 959 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
5499b6ff 960 env->lladdr = 0ULL;
b5dc7732
TS		 961 /* MIPS16 not implemented. */
962 } else {
d9bea114 963 env->tcs[other_tc].PC = arg1;
b5dc7732 964 env->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
5499b6ff 965 env->lladdr = 0ULL;
b5dc7732
TS		 966 /* MIPS16 not implemented. */
967 }
f1aa6320
TS		 968}
969
d9bea114 970void helper_mtc0_tchalt (target_ulong arg1)
f1aa6320 971{
d9bea114 972 env->active_tc.CP0_TCHalt = arg1 & 0x1;
f1aa6320
TS		 973
974 // TODO: Halt TC / Restart (if allocated+active) TC.
975}
976
d9bea114 977void helper_mttc0_tchalt (target_ulong arg1)
f1aa6320
TS		 978{
979 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
980
981 // TODO: Halt TC / Restart (if allocated+active) TC.
982
b5dc7732 983 if (other_tc == env->current_tc)
d9bea114 984 env->active_tc.CP0_TCHalt = arg1;
b5dc7732 985 else
d9bea114 986 env->tcs[other_tc].CP0_TCHalt = arg1;
f1aa6320
TS		 987}
988
d9bea114 989void helper_mtc0_tccontext (target_ulong arg1)
f1aa6320 990{
d9bea114 991 env->active_tc.CP0_TCContext = arg1;
f1aa6320
TS		 992}
993
d9bea114 994void helper_mttc0_tccontext (target_ulong arg1)
f1aa6320
TS		 995{
996 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
997
b5dc7732 998 if (other_tc == env->current_tc)
d9bea114 999 env->active_tc.CP0_TCContext = arg1;
b5dc7732 1000 else
d9bea114 1001 env->tcs[other_tc].CP0_TCContext = arg1;
f1aa6320
TS		 1002}
1003
d9bea114 1004void helper_mtc0_tcschedule (target_ulong arg1)
f1aa6320 1005{
d9bea114 1006 env->active_tc.CP0_TCSchedule = arg1;
f1aa6320
TS		 1007}
1008
d9bea114 1009void helper_mttc0_tcschedule (target_ulong arg1)
f1aa6320
TS		 1010{
1011 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1012
b5dc7732 1013 if (other_tc == env->current_tc)
d9bea114 1014 env->active_tc.CP0_TCSchedule = arg1;
b5dc7732 1015 else
d9bea114 1016 env->tcs[other_tc].CP0_TCSchedule = arg1;
f1aa6320
TS		 1017}
1018
d9bea114 1019void helper_mtc0_tcschefback (target_ulong arg1)
f1aa6320 1020{
d9bea114 1021 env->active_tc.CP0_TCScheFBack = arg1;
f1aa6320
TS		 1022}
1023
d9bea114 1024void helper_mttc0_tcschefback (target_ulong arg1)
f1aa6320
TS		 1025{
1026 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1027
b5dc7732 1028 if (other_tc == env->current_tc)
d9bea114 1029 env->active_tc.CP0_TCScheFBack = arg1;
b5dc7732 1030 else
d9bea114 1031 env->tcs[other_tc].CP0_TCScheFBack = arg1;
f1aa6320
TS		 1032}
1033
d9bea114 1034void helper_mtc0_entrylo1 (target_ulong arg1)
f1aa6320
TS		 1035{
1036 /* Large physaddr (PABITS) not implemented */
1037 /* 1k pages not implemented */
d9bea114 1038 env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
f1aa6320
TS		 1039}
1040
d9bea114 1041void helper_mtc0_context (target_ulong arg1)
f1aa6320 1042{
d9bea114 1043 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
f1aa6320
TS		 1044}
1045
d9bea114 1046void helper_mtc0_pagemask (target_ulong arg1)
f1aa6320
TS		 1047{
1048 /* 1k pages not implemented */
d9bea114 1049 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
f1aa6320
TS		 1050}
1051
d9bea114 1052void helper_mtc0_pagegrain (target_ulong arg1)
f1aa6320
TS		 1053{
1054 /* SmartMIPS not implemented */
1055 /* Large physaddr (PABITS) not implemented */
1056 /* 1k pages not implemented */
1057 env->CP0_PageGrain = 0;
1058}
1059
d9bea114 1060void helper_mtc0_wired (target_ulong arg1)
f1aa6320 1061{
d9bea114 1062 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
f1aa6320
TS		 1063}
1064
d9bea114 1065void helper_mtc0_srsconf0 (target_ulong arg1)
f1aa6320 1066{
d9bea114 1067 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
f1aa6320
TS		 1068}
1069
d9bea114 1070void helper_mtc0_srsconf1 (target_ulong arg1)
f1aa6320 1071{
d9bea114 1072 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
f1aa6320
TS		 1073}
1074
d9bea114 1075void helper_mtc0_srsconf2 (target_ulong arg1)
f1aa6320 1076{
d9bea114 1077 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
f1aa6320
TS		 1078}
1079
d9bea114 1080void helper_mtc0_srsconf3 (target_ulong arg1)
f1aa6320 1081{
d9bea114 1082 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
f1aa6320
TS		 1083}
1084
d9bea114 1085void helper_mtc0_srsconf4 (target_ulong arg1)
f1aa6320 1086{
d9bea114 1087 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
f1aa6320
TS		 1088}
1089
d9bea114 1090void helper_mtc0_hwrena (target_ulong arg1)
f1aa6320 1091{
d9bea114 1092 env->CP0_HWREna = arg1 & 0x0000000F;
f1aa6320
TS		 1093}
1094
d9bea114 1095void helper_mtc0_count (target_ulong arg1)
f1aa6320 1096{
d9bea114 1097 cpu_mips_store_count(env, arg1);
f1aa6320
TS		 1098}
1099
d9bea114 1100void helper_mtc0_entryhi (target_ulong arg1)
f1aa6320
TS		 1101{
1102 target_ulong old, val;
1103
1104 /* 1k pages not implemented */
d9bea114 1105 val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
f1aa6320
TS		 1106#if defined(TARGET_MIPS64)
1107 val &= env->SEGMask;
1108#endif
1109 old = env->CP0_EntryHi;
1110 env->CP0_EntryHi = val;
1111 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
b5dc7732
TS		 1112 uint32_t tcst = env->active_tc.CP0_TCStatus & ~0xff;
1113 env->active_tc.CP0_TCStatus = tcst | (val & 0xff);
f1aa6320
TS		 1114 }
1115 /* If the ASID changes, flush qemu's TLB. */
1116 if ((old & 0xFF) != (val & 0xFF))
1117 cpu_mips_tlb_flush(env, 1);
1118}
1119
d9bea114 1120void helper_mttc0_entryhi(target_ulong arg1)
f1aa6320
TS		 1121{
1122 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
b5dc7732 1123 int32_t tcstatus;
f1aa6320 1124
d9bea114 1125 env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (arg1 & ~0xff);
b5dc7732 1126 if (other_tc == env->current_tc) {
d9bea114 1127 tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (arg1 & 0xff);
b5dc7732
TS		 1128 env->active_tc.CP0_TCStatus = tcstatus;
1129 } else {
d9bea114 1130 tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (arg1 & 0xff);
b5dc7732
TS		 1131 env->tcs[other_tc].CP0_TCStatus = tcstatus;
1132 }
f1aa6320
TS		 1133}
1134
d9bea114 1135void helper_mtc0_compare (target_ulong arg1)
f1aa6320 1136{
d9bea114 1137 cpu_mips_store_compare(env, arg1);
f1aa6320
TS		 1138}
1139
d9bea114 1140void helper_mtc0_status (target_ulong arg1)
f1aa6320
TS		 1141{
1142 uint32_t val, old;
1143 uint32_t mask = env->CP0_Status_rw_bitmask;
1144
d9bea114 1145 val = arg1 & mask;
f1aa6320
TS		 1146 old = env->CP0_Status;
1147 env->CP0_Status = (env->CP0_Status & ~mask) | val;
1148 compute_hflags(env);
c01fccd2
AJ		 1149 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1150 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1151 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1152 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1153 env->CP0_Cause);
1154 switch (env->hflags & MIPS_HFLAG_KSU) {
1155 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1156 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1157 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1158 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
31e3104f 1159 }
c01fccd2 1160 }
f1aa6320
TS		 1161 cpu_mips_update_irq(env);
1162}
1163
d9bea114 1164void helper_mttc0_status(target_ulong arg1)
f1aa6320
TS		 1165{
1166 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
b5dc7732 1167 int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus;
f1aa6320 1168
d9bea114
AJ		 1169 env->CP0_Status = arg1 & ~0xf1000018;
1170 tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (arg1 & (0xf << CP0St_CU0));
1171 tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((arg1 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
1172 tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((arg1 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
b5dc7732
TS		 1173 if (other_tc == env->current_tc)
1174 env->active_tc.CP0_TCStatus = tcstatus;
1175 else
1176 env->tcs[other_tc].CP0_TCStatus = tcstatus;
f1aa6320
TS		 1177}
1178
d9bea114 1179void helper_mtc0_intctl (target_ulong arg1)
f1aa6320
TS		 1180{
1181 /* vectored interrupts not implemented, no performance counters. */
d9bea114 1182 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (arg1 & 0x000002e0);
f1aa6320
TS		 1183}
1184
d9bea114 1185void helper_mtc0_srsctl (target_ulong arg1)
f1aa6320
TS		 1186{
1187 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
d9bea114 1188 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
f1aa6320
TS		 1189}
1190
d9bea114 1191void helper_mtc0_cause (target_ulong arg1)
f1aa6320
TS		 1192{
1193 uint32_t mask = 0x00C00300;
1194 uint32_t old = env->CP0_Cause;
1195
1196 if (env->insn_flags & ISA_MIPS32R2)
1197 mask |= 1 << CP0Ca_DC;
1198
d9bea114 1199 env->CP0_Cause = (env->CP0_Cause & ~mask) | (arg1 & mask);
f1aa6320
TS		 1200
1201 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
1202 if (env->CP0_Cause & (1 << CP0Ca_DC))
1203 cpu_mips_stop_count(env);
1204 else
1205 cpu_mips_start_count(env);
1206 }
1207
1208 /* Handle the software interrupt as an hardware one, as they
1209 are very similar */
d9bea114 1210 if (arg1 & CP0Ca_IP_mask) {
f1aa6320
TS		 1211 cpu_mips_update_irq(env);
1212 }
1213}
1214
d9bea114 1215void helper_mtc0_ebase (target_ulong arg1)
f1aa6320
TS		 1216{
1217 /* vectored interrupts not implemented */
1218 /* Multi-CPU not implemented */
d9bea114 1219 env->CP0_EBase = 0x80000000 | (arg1 & 0x3FFFF000);
f1aa6320
TS		 1220}
1221
d9bea114 1222void helper_mtc0_config0 (target_ulong arg1)
f1aa6320 1223{
d9bea114 1224 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
f1aa6320
TS		 1225}
1226
d9bea114 1227void helper_mtc0_config2 (target_ulong arg1)
f1aa6320
TS		 1228{
1229 /* tertiary/secondary caches not implemented */
1230 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1231}
1232
2a6e32dd
AJ		 1233void helper_mtc0_lladdr (target_ulong arg1)
1234{
1235 target_long mask = env->CP0_LLAddr_rw_bitmask;
1236 arg1 = arg1 << env->CP0_LLAddr_shift;
1237 env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1238}
1239
d9bea114 1240void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel)
f1aa6320
TS		 1241{
1242 /* Watch exceptions for instructions, data loads, data stores
1243 not implemented. */
d9bea114 1244 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
f1aa6320
TS		 1245}
1246
d9bea114 1247void helper_mtc0_watchhi (target_ulong arg1, uint32_t sel)
f1aa6320 1248{
d9bea114
AJ		 1249 env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1250 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
f1aa6320
TS		 1251}
1252
d9bea114 1253void helper_mtc0_xcontext (target_ulong arg1)
f1aa6320
TS		 1254{
1255 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
d9bea114 1256 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
f1aa6320
TS		 1257}
1258
d9bea114 1259void helper_mtc0_framemask (target_ulong arg1)
f1aa6320 1260{
d9bea114 1261 env->CP0_Framemask = arg1; /* XXX */
f1aa6320
TS		 1262}
1263
d9bea114 1264void helper_mtc0_debug (target_ulong arg1)
f1aa6320 1265{
d9bea114
AJ		 1266 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1267 if (arg1 & (1 << CP0DB_DM))
f1aa6320
TS		 1268 env->hflags |= MIPS_HFLAG_DM;
1269 else
1270 env->hflags &= ~MIPS_HFLAG_DM;
1271}
1272
d9bea114 1273void helper_mttc0_debug(target_ulong arg1)
f1aa6320
TS		 1274{
1275 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
d9bea114 1276 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
f1aa6320
TS		 1277
1278 /* XXX: Might be wrong, check with EJTAG spec. */
b5dc7732
TS		 1279 if (other_tc == env->current_tc)
1280 env->active_tc.CP0_Debug_tcstatus = val;
1281 else
1282 env->tcs[other_tc].CP0_Debug_tcstatus = val;
f1aa6320 1283 env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
d9bea114 1284 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
f1aa6320
TS		 1285}
1286
d9bea114 1287void helper_mtc0_performance0 (target_ulong arg1)
f1aa6320 1288{
d9bea114 1289 env->CP0_Performance0 = arg1 & 0x000007ff;
f1aa6320
TS		 1290}
1291
d9bea114 1292void helper_mtc0_taglo (target_ulong arg1)
f1aa6320 1293{
d9bea114 1294 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
f1aa6320
TS		 1295}
1296
d9bea114 1297void helper_mtc0_datalo (target_ulong arg1)
f1aa6320 1298{
d9bea114 1299 env->CP0_DataLo = arg1; /* XXX */
f1aa6320
TS		 1300}
1301
d9bea114 1302void helper_mtc0_taghi (target_ulong arg1)
f1aa6320 1303{
d9bea114 1304 env->CP0_TagHi = arg1; /* XXX */
f1aa6320
TS		 1305}
1306
d9bea114 1307void helper_mtc0_datahi (target_ulong arg1)
f1aa6320 1308{
d9bea114 1309 env->CP0_DataHi = arg1; /* XXX */
f1aa6320
TS		 1310}
1311
f1aa6320 1312/* MIPS MT functions */
c01fccd2 1313target_ulong helper_mftgpr(uint32_t sel)
f1aa6320
TS		 1314{
1315 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1316
b5dc7732
TS		 1317 if (other_tc == env->current_tc)
1318 return env->active_tc.gpr[sel];
1319 else
1320 return env->tcs[other_tc].gpr[sel];
f1aa6320
TS		 1321}
1322
c01fccd2 1323target_ulong helper_mftlo(uint32_t sel)
f1aa6320
TS		 1324{
1325 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1326
b5dc7732
TS		 1327 if (other_tc == env->current_tc)
1328 return env->active_tc.LO[sel];
1329 else
1330 return env->tcs[other_tc].LO[sel];
f1aa6320
TS		 1331}
1332
c01fccd2 1333target_ulong helper_mfthi(uint32_t sel)
f1aa6320
TS		 1334{
1335 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1336
b5dc7732
TS		 1337 if (other_tc == env->current_tc)
1338 return env->active_tc.HI[sel];
1339 else
1340 return env->tcs[other_tc].HI[sel];
f1aa6320
TS		 1341}
1342
c01fccd2 1343target_ulong helper_mftacx(uint32_t sel)
f1aa6320
TS		 1344{
1345 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1346
b5dc7732
TS		 1347 if (other_tc == env->current_tc)
1348 return env->active_tc.ACX[sel];
1349 else
1350 return env->tcs[other_tc].ACX[sel];
f1aa6320
TS		 1351}
1352
c01fccd2 1353target_ulong helper_mftdsp(void)
f1aa6320
TS		 1354{
1355 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1356
b5dc7732
TS		 1357 if (other_tc == env->current_tc)
1358 return env->active_tc.DSPControl;
1359 else
1360 return env->tcs[other_tc].DSPControl;
f1aa6320 1361}
6af0bf9c 1362
d9bea114 1363void helper_mttgpr(target_ulong arg1, uint32_t sel)
f1aa6320
TS		 1364{
1365 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1366
b5dc7732 1367 if (other_tc == env->current_tc)
d9bea114 1368 env->active_tc.gpr[sel] = arg1;
b5dc7732 1369 else
d9bea114 1370 env->tcs[other_tc].gpr[sel] = arg1;
f1aa6320
TS		 1371}
1372
d9bea114 1373void helper_mttlo(target_ulong arg1, uint32_t sel)
f1aa6320
TS		 1374{
1375 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1376
b5dc7732 1377 if (other_tc == env->current_tc)
d9bea114 1378 env->active_tc.LO[sel] = arg1;
b5dc7732 1379 else
d9bea114 1380 env->tcs[other_tc].LO[sel] = arg1;
f1aa6320
TS		 1381}
1382
d9bea114 1383void helper_mtthi(target_ulong arg1, uint32_t sel)
f1aa6320
TS		 1384{
1385 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1386
b5dc7732 1387 if (other_tc == env->current_tc)
d9bea114 1388 env->active_tc.HI[sel] = arg1;
b5dc7732 1389 else
d9bea114 1390 env->tcs[other_tc].HI[sel] = arg1;
f1aa6320
TS		 1391}
1392
d9bea114 1393void helper_mttacx(target_ulong arg1, uint32_t sel)
f1aa6320
TS		 1394{
1395 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1396
b5dc7732 1397 if (other_tc == env->current_tc)
d9bea114 1398 env->active_tc.ACX[sel] = arg1;
b5dc7732 1399 else
d9bea114 1400 env->tcs[other_tc].ACX[sel] = arg1;
f1aa6320
TS		 1401}
1402
d9bea114 1403void helper_mttdsp(target_ulong arg1)
f1aa6320
TS		 1404{
1405 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1406
b5dc7732 1407 if (other_tc == env->current_tc)
d9bea114 1408 env->active_tc.DSPControl = arg1;
b5dc7732 1409 else
d9bea114 1410 env->tcs[other_tc].DSPControl = arg1;
f1aa6320
TS		 1411}
1412
1413/* MIPS MT functions */
d9bea114 1414target_ulong helper_dmt(target_ulong arg1)
f1aa6320
TS		 1415{
1416 // TODO
d9bea114
AJ		 1417 arg1 = 0;
1418 // rt = arg1
be24bb4f 1419
d9bea114 1420 return arg1;
f1aa6320
TS		 1421}
1422
d9bea114 1423target_ulong helper_emt(target_ulong arg1)
f1aa6320
TS		 1424{
1425 // TODO
d9bea114
AJ		 1426 arg1 = 0;
1427 // rt = arg1
be24bb4f 1428
d9bea114 1429 return arg1;
f1aa6320
TS		 1430}
1431
d9bea114 1432target_ulong helper_dvpe(target_ulong arg1)
f1aa6320
TS		 1433{
1434 // TODO
d9bea114
AJ		 1435 arg1 = 0;
1436 // rt = arg1
be24bb4f 1437
d9bea114 1438 return arg1;
f1aa6320
TS		 1439}
1440
d9bea114 1441target_ulong helper_evpe(target_ulong arg1)
f1aa6320
TS		 1442{
1443 // TODO
d9bea114
AJ		 1444 arg1 = 0;
1445 // rt = arg1
be24bb4f 1446
d9bea114 1447 return arg1;
f1aa6320 1448}
f9480ffc 1449#endif /* !CONFIG_USER_ONLY */
f1aa6320 1450
d9bea114 1451void helper_fork(target_ulong arg1, target_ulong arg2)
f1aa6320 1452{
d9bea114
AJ		 1453 // arg1 = rt, arg2 = rs
1454 arg1 = 0;
f1aa6320
TS		 1455 // TODO: store to TC register
1456}
1457
d9bea114 1458target_ulong helper_yield(target_ulong arg1)
f1aa6320 1459{
d9bea114 1460 if (arg1 < 0) {
f1aa6320 1461 /* No scheduling policy implemented. */
d9bea114 1462 if (arg1 != -2) {
f1aa6320 1463 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
b5dc7732 1464 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
f1aa6320
TS		 1465 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1466 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
c01fccd2 1467 helper_raise_exception(EXCP_THREAD);
f1aa6320
TS		 1468 }
1469 }
d9bea114 1470 } else if (arg1 == 0) {
6958549d 1471 if (0 /* TODO: TC underflow */) {
f1aa6320 1472 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
c01fccd2 1473 helper_raise_exception(EXCP_THREAD);
f1aa6320
TS		 1474 } else {
1475 // TODO: Deallocate TC
1476 }
d9bea114 1477 } else if (arg1 > 0) {
f1aa6320
TS		 1478 /* Yield qualifier inputs not implemented. */
1479 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1480 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
c01fccd2 1481 helper_raise_exception(EXCP_THREAD);
f1aa6320 1482 }
be24bb4f 1483 return env->CP0_YQMask;
f1aa6320
TS		 1484}
1485
f1aa6320 1486#ifndef CONFIG_USER_ONLY
6af0bf9c 1487/* TLB management */
814b9a47
TS		 1488void cpu_mips_tlb_flush (CPUState *env, int flush_global)
1489{
1490 /* Flush qemu's TLB and discard all shadowed entries. */
1491 tlb_flush (env, flush_global);
ead9360e 1492 env->tlb->tlb_in_use = env->tlb->nb_tlb;
814b9a47
TS		 1493}
1494
29929e34 1495static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
814b9a47
TS		 1496{
1497 /* Discard entries from env->tlb[first] onwards. */
ead9360e
TS		 1498 while (env->tlb->tlb_in_use > first) {
1499 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
814b9a47
TS		 1500 }
1501}
1502
29929e34 1503static void r4k_fill_tlb (int idx)
6af0bf9c 1504{
c227f099 1505 r4k_tlb_t *tlb;
6af0bf9c
FB		 1506
1507 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
ead9360e 1508 tlb = &env->tlb->mmu.r4k.tlb[idx];
f2e9ebef 1509 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
d26bc211 1510#if defined(TARGET_MIPS64)
e034e2c3 1511 tlb->VPN &= env->SEGMask;
100ce988 1512#endif
98c1b82b 1513 tlb->ASID = env->CP0_EntryHi & 0xFF;
3b1c8be4 1514 tlb->PageMask = env->CP0_PageMask;
6af0bf9c 1515 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
98c1b82b
PB		 1516 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1517 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1518 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
6af0bf9c 1519 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
98c1b82b
PB		 1520 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1521 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1522 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
6af0bf9c
FB		 1523 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1524}
1525
c01fccd2 1526void r4k_helper_tlbwi (void)
6af0bf9c 1527{
bbc0d79c
AJ		 1528 int idx;
1529
1530 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1531
814b9a47
TS		 1532 /* Discard cached TLB entries. We could avoid doing this if the
1533 tlbwi is just upgrading access permissions on the current entry;
1534 that might be a further win. */
ead9360e 1535 r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
814b9a47 1536
bbc0d79c
AJ		 1537 r4k_invalidate_tlb(env, idx, 0);
1538 r4k_fill_tlb(idx);
6af0bf9c
FB		 1539}
1540
c01fccd2 1541void r4k_helper_tlbwr (void)
6af0bf9c
FB		 1542{
1543 int r = cpu_mips_get_random(env);
1544
29929e34
TS		 1545 r4k_invalidate_tlb(env, r, 1);
1546 r4k_fill_tlb(r);
6af0bf9c
FB		 1547}
1548
c01fccd2 1549void r4k_helper_tlbp (void)
6af0bf9c 1550{
c227f099 1551 r4k_tlb_t *tlb;
f2e9ebef 1552 target_ulong mask;
6af0bf9c 1553 target_ulong tag;
f2e9ebef 1554 target_ulong VPN;
6af0bf9c
FB		 1555 uint8_t ASID;
1556 int i;
1557
3d9fb9fe 1558 ASID = env->CP0_EntryHi & 0xFF;
ead9360e
TS		 1559 for (i = 0; i < env->tlb->nb_tlb; i++) {
1560 tlb = &env->tlb->mmu.r4k.tlb[i];
f2e9ebef
TS		 1561 /* 1k pages are not supported. */
1562 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1563 tag = env->CP0_EntryHi & ~mask;
1564 VPN = tlb->VPN & ~mask;
6af0bf9c 1565 /* Check ASID, virtual page number & size */
f2e9ebef 1566 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
6af0bf9c 1567 /* TLB match */
9c2149c8 1568 env->CP0_Index = i;
6af0bf9c
FB		 1569 break;
1570 }
1571 }
ead9360e 1572 if (i == env->tlb->nb_tlb) {
814b9a47 1573 /* No match. Discard any shadow entries, if any of them match. */
ead9360e 1574 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
6958549d
AJ		 1575 tlb = &env->tlb->mmu.r4k.tlb[i];
1576 /* 1k pages are not supported. */
1577 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1578 tag = env->CP0_EntryHi & ~mask;
1579 VPN = tlb->VPN & ~mask;
1580 /* Check ASID, virtual page number & size */
1581 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
29929e34 1582 r4k_mips_tlb_flush_extra (env, i);
6958549d
AJ		 1583 break;
1584 }
1585 }
814b9a47 1586
9c2149c8 1587 env->CP0_Index |= 0x80000000;
6af0bf9c
FB		 1588 }
1589}
1590
c01fccd2 1591void r4k_helper_tlbr (void)
6af0bf9c 1592{
c227f099 1593 r4k_tlb_t *tlb;
09c56b84 1594 uint8_t ASID;
bbc0d79c 1595 int idx;
6af0bf9c 1596
09c56b84 1597 ASID = env->CP0_EntryHi & 0xFF;
bbc0d79c
AJ		 1598 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1599 tlb = &env->tlb->mmu.r4k.tlb[idx];
4ad40f36
FB		 1600
1601 /* If this will change the current ASID, flush qemu's TLB. */
814b9a47
TS		 1602 if (ASID != tlb->ASID)
1603 cpu_mips_tlb_flush (env, 1);
1604
ead9360e 1605 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
4ad40f36 1606
6af0bf9c 1607 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
3b1c8be4 1608 env->CP0_PageMask = tlb->PageMask;
7495fd0f
TS		 1609 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1610 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1611 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1612 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
6af0bf9c 1613}
6af0bf9c 1614
c01fccd2 1615void helper_tlbwi(void)
a7812ae4 1616{
c01fccd2 1617 env->tlb->helper_tlbwi();
a7812ae4
PB		 1618}
1619
c01fccd2 1620void helper_tlbwr(void)
a7812ae4 1621{
c01fccd2 1622 env->tlb->helper_tlbwr();
a7812ae4
PB		 1623}
1624
c01fccd2 1625void helper_tlbp(void)
a7812ae4 1626{
c01fccd2 1627 env->tlb->helper_tlbp();
a7812ae4
PB		 1628}
1629
c01fccd2 1630void helper_tlbr(void)
a7812ae4 1631{
c01fccd2 1632 env->tlb->helper_tlbr();
a7812ae4
PB		 1633}
1634
2b0233ab 1635/* Specials */
c01fccd2 1636target_ulong helper_di (void)
2b0233ab 1637{
2796188e
TS		 1638 target_ulong t0 = env->CP0_Status;
1639
be24bb4f 1640 env->CP0_Status = t0 & ~(1 << CP0St_IE);
2b0233ab 1641 cpu_mips_update_irq(env);
be24bb4f
TS		 1642
1643 return t0;
2b0233ab
TS		 1644}
1645
c01fccd2 1646target_ulong helper_ei (void)
2b0233ab 1647{
2796188e
TS		 1648 target_ulong t0 = env->CP0_Status;
1649
be24bb4f 1650 env->CP0_Status = t0 | (1 << CP0St_IE);
2b0233ab 1651 cpu_mips_update_irq(env);
be24bb4f
TS		 1652
1653 return t0;
2b0233ab
TS		 1654}
1655
cd5158ea 1656static void debug_pre_eret (void)
6af0bf9c 1657{
8fec2b8c 1658 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
93fcfe39
AL		 1659 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1660 env->active_tc.PC, env->CP0_EPC);
1661 if (env->CP0_Status & (1 << CP0St_ERL))
1662 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1663 if (env->hflags & MIPS_HFLAG_DM)
1664 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1665 qemu_log("\n");
1666 }
f41c52f1
TS		 1667}
1668
cd5158ea 1669static void debug_post_eret (void)
f41c52f1 1670{
8fec2b8c 1671 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
93fcfe39
AL		 1672 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1673 env->active_tc.PC, env->CP0_EPC);
1674 if (env->CP0_Status & (1 << CP0St_ERL))
1675 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1676 if (env->hflags & MIPS_HFLAG_DM)
1677 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1678 switch (env->hflags & MIPS_HFLAG_KSU) {
1679 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1680 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1681 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1682 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1683 }
623a930e 1684 }
6af0bf9c
FB		 1685}
1686
c01fccd2 1687void helper_eret (void)
2b0233ab 1688{
93fcfe39 1689 debug_pre_eret();
2b0233ab 1690 if (env->CP0_Status & (1 << CP0St_ERL)) {
b5dc7732 1691 env->active_tc.PC = env->CP0_ErrorEPC;
2b0233ab
TS		 1692 env->CP0_Status &= ~(1 << CP0St_ERL);
1693 } else {
b5dc7732 1694 env->active_tc.PC = env->CP0_EPC;
2b0233ab
TS		 1695 env->CP0_Status &= ~(1 << CP0St_EXL);
1696 }
1697 compute_hflags(env);
93fcfe39 1698 debug_post_eret();
5499b6ff 1699 env->lladdr = 1;
2b0233ab
TS		 1700}
1701
c01fccd2 1702void helper_deret (void)
2b0233ab 1703{
93fcfe39 1704 debug_pre_eret();
b5dc7732 1705 env->active_tc.PC = env->CP0_DEPC;
2b0233ab
TS		 1706 env->hflags &= MIPS_HFLAG_DM;
1707 compute_hflags(env);
93fcfe39 1708 debug_post_eret();
5499b6ff 1709 env->lladdr = 1;
2b0233ab 1710}
0eaef5aa 1711#endif /* !CONFIG_USER_ONLY */
2b0233ab 1712
c01fccd2 1713target_ulong helper_rdhwr_cpunum(void)
2b0233ab
TS		 1714{
1715 if ((env->hflags & MIPS_HFLAG_CP0) ||
1716 (env->CP0_HWREna & (1 << 0)))
2796188e 1717 return env->CP0_EBase & 0x3ff;
2b0233ab 1718 else
c01fccd2 1719 helper_raise_exception(EXCP_RI);
be24bb4f 1720
2796188e 1721 return 0;
2b0233ab
TS		 1722}
1723
c01fccd2 1724target_ulong helper_rdhwr_synci_step(void)
2b0233ab
TS		 1725{
1726 if ((env->hflags & MIPS_HFLAG_CP0) ||
1727 (env->CP0_HWREna & (1 << 1)))
2796188e 1728 return env->SYNCI_Step;
2b0233ab 1729 else
c01fccd2 1730 helper_raise_exception(EXCP_RI);
be24bb4f 1731
2796188e 1732 return 0;
2b0233ab
TS		 1733}
1734
c01fccd2 1735target_ulong helper_rdhwr_cc(void)
2b0233ab
TS		 1736{
1737 if ((env->hflags & MIPS_HFLAG_CP0) ||
1738 (env->CP0_HWREna & (1 << 2)))
2796188e 1739 return env->CP0_Count;
2b0233ab 1740 else
c01fccd2 1741 helper_raise_exception(EXCP_RI);
be24bb4f 1742
2796188e 1743 return 0;
2b0233ab
TS		 1744}
1745
c01fccd2 1746target_ulong helper_rdhwr_ccres(void)
2b0233ab
TS		 1747{
1748 if ((env->hflags & MIPS_HFLAG_CP0) ||
1749 (env->CP0_HWREna & (1 << 3)))
2796188e 1750 return env->CCRes;
2b0233ab 1751 else
c01fccd2 1752 helper_raise_exception(EXCP_RI);
be24bb4f 1753
2796188e 1754 return 0;
2b0233ab
TS		 1755}
1756
c01fccd2 1757void helper_pmon (int function)
6af0bf9c
FB		 1758{
1759 function /= 2;
1760 switch (function) {
1761 case 2: /* TODO: char inbyte(int waitflag); */
b5dc7732
TS		 1762 if (env->active_tc.gpr[4] == 0)
1763 env->active_tc.gpr[2] = -1;
6af0bf9c
FB		 1764 /* Fall through */
1765 case 11: /* TODO: char inbyte (void); */
b5dc7732 1766 env->active_tc.gpr[2] = -1;
6af0bf9c
FB		 1767 break;
1768 case 3:
1769 case 12:
b5dc7732 1770 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
6af0bf9c
FB		 1771 break;
1772 case 17:
1773 break;
1774 case 158:
1775 {
b5dc7732 1776 unsigned char *fmt = (void *)(unsigned long)env->active_tc.gpr[4];
6af0bf9c
FB		 1777 printf("%s", fmt);
1778 }
1779 break;
1780 }
1781}
e37e863f 1782
c01fccd2 1783void helper_wait (void)
08ba7963
TS		 1784{
1785 env->halted = 1;
c01fccd2 1786 helper_raise_exception(EXCP_HLT);
08ba7963
TS		 1787}
1788
5fafdf24 1789#if !defined(CONFIG_USER_ONLY)
e37e863f 1790
4ad40f36
FB		 1791static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
1792
e37e863f 1793#define MMUSUFFIX _mmu
4ad40f36 1794#define ALIGNED_ONLY
e37e863f
FB		 1795
1796#define SHIFT 0
1797#include "softmmu_template.h"
1798
1799#define SHIFT 1
1800#include "softmmu_template.h"
1801
1802#define SHIFT 2
1803#include "softmmu_template.h"
1804
1805#define SHIFT 3
1806#include "softmmu_template.h"
1807
4ad40f36
FB		 1808static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
1809{
1810 env->CP0_BadVAddr = addr;
1811 do_restore_state (retaddr);
c01fccd2 1812 helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
4ad40f36
FB		 1813}
1814
6ebbf390 1815void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
e37e863f
FB		 1816{
1817 TranslationBlock *tb;
1818 CPUState *saved_env;
1819 unsigned long pc;
1820 int ret;
1821
1822 /* XXX: hack to restore env in all cases, even if not called from
1823 generated code */
1824 saved_env = env;
1825 env = cpu_single_env;
6ebbf390 1826 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
e37e863f
FB		 1827 if (ret) {
1828 if (retaddr) {
1829 /* now we have a real cpu fault */
1830 pc = (unsigned long)retaddr;
1831 tb = tb_find_pc(pc);
1832 if (tb) {
1833 /* the PC is inside the translated code. It means that we have
1834 a virtual CPU fault */
1835 cpu_restore_state(tb, env, pc, NULL);
1836 }
1837 }
c01fccd2 1838 helper_raise_exception_err(env->exception_index, env->error_code);
e37e863f
FB		 1839 }
1840 env = saved_env;
1841}
1842
c227f099 1843void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
e18231a3 1844 int unused, int size)
647de6ca
TS		 1845{
1846 if (is_exec)
c01fccd2 1847 helper_raise_exception(EXCP_IBE);
647de6ca 1848 else
c01fccd2 1849 helper_raise_exception(EXCP_DBE);
647de6ca 1850}
f1aa6320 1851#endif /* !CONFIG_USER_ONLY */
fd4a04eb
TS		 1852
1853/* Complex FPU operations which may need stack space. */
1854
f090c9d4
PB		 1855#define FLOAT_ONE32 make_float32(0x3f8 << 20)
1856#define FLOAT_ONE64 make_float64(0x3ffULL << 52)
1857#define FLOAT_TWO32 make_float32(1 << 30)
1858#define FLOAT_TWO64 make_float64(1ULL << 62)
54454097
TS		 1859#define FLOAT_QNAN32 0x7fbfffff
1860#define FLOAT_QNAN64 0x7ff7ffffffffffffULL
1861#define FLOAT_SNAN32 0x7fffffff
1862#define FLOAT_SNAN64 0x7fffffffffffffffULL
8dfdb87c 1863
fd4a04eb 1864/* convert MIPS rounding mode in FCR31 to IEEE library */
6f4fc367 1865static unsigned int ieee_rm[] = {
fd4a04eb
TS		 1866 float_round_nearest_even,
1867 float_round_to_zero,
1868 float_round_up,
1869 float_round_down
1870};
1871
1872#define RESTORE_ROUNDING_MODE \
f01be154 1873 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
fd4a04eb 1874
41e0c701
AJ		 1875#define RESTORE_FLUSH_MODE \
1876 set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status);
1877
c01fccd2 1878target_ulong helper_cfc1 (uint32_t reg)
fd4a04eb 1879{
d9bea114 1880 target_ulong arg1;
6c5c1e20 1881
ead9360e
TS		 1882 switch (reg) {
1883 case 0:
d9bea114 1884 arg1 = (int32_t)env->active_fpu.fcr0;
ead9360e
TS		 1885 break;
1886 case 25:
d9bea114 1887 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
ead9360e
TS		 1888 break;
1889 case 26:
d9bea114 1890 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
ead9360e
TS		 1891 break;
1892 case 28:
d9bea114 1893 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
ead9360e
TS		 1894 break;
1895 default:
d9bea114 1896 arg1 = (int32_t)env->active_fpu.fcr31;
ead9360e
TS		 1897 break;
1898 }
be24bb4f 1899
d9bea114 1900 return arg1;
ead9360e
TS		 1901}
1902
d9bea114 1903void helper_ctc1 (target_ulong arg1, uint32_t reg)
ead9360e
TS		 1904{
1905 switch(reg) {
fd4a04eb 1906 case 25:
d9bea114 1907 if (arg1 & 0xffffff00)
fd4a04eb 1908 return;
d9bea114
AJ		 1909 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
1910 ((arg1 & 0x1) << 23);
fd4a04eb
TS		 1911 break;
1912 case 26:
d9bea114 1913 if (arg1 & 0x007c0000)
fd4a04eb 1914 return;
d9bea114 1915 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
fd4a04eb
TS		 1916 break;
1917 case 28:
d9bea114 1918 if (arg1 & 0x007c0000)
fd4a04eb 1919 return;
d9bea114
AJ		 1920 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
1921 ((arg1 & 0x4) << 22);
fd4a04eb
TS		 1922 break;
1923 case 31:
d9bea114 1924 if (arg1 & 0x007c0000)
fd4a04eb 1925 return;
d9bea114 1926 env->active_fpu.fcr31 = arg1;
fd4a04eb
TS		 1927 break;
1928 default:
1929 return;
1930 }
1931 /* set rounding mode */
1932 RESTORE_ROUNDING_MODE;
41e0c701
AJ		 1933 /* set flush-to-zero mode */
1934 RESTORE_FLUSH_MODE;
f01be154
TS		 1935 set_float_exception_flags(0, &env->active_fpu.fp_status);
1936 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
c01fccd2 1937 helper_raise_exception(EXCP_FPE);
fd4a04eb
TS		 1938}
1939
c904ef0e 1940static inline char ieee_ex_to_mips(char xcpt)
fd4a04eb
TS		 1941{
1942 return (xcpt & float_flag_inexact) >> 5 |
1943 (xcpt & float_flag_underflow) >> 3 |
1944 (xcpt & float_flag_overflow) >> 1 |
1945 (xcpt & float_flag_divbyzero) << 1 |
1946 (xcpt & float_flag_invalid) << 4;
1947}
1948
c904ef0e 1949static inline char mips_ex_to_ieee(char xcpt)
fd4a04eb
TS		 1950{
1951 return (xcpt & FP_INEXACT) << 5 |
1952 (xcpt & FP_UNDERFLOW) << 3 |
1953 (xcpt & FP_OVERFLOW) << 1 |
1954 (xcpt & FP_DIV0) >> 1 |
1955 (xcpt & FP_INVALID) >> 4;
1956}
1957
c904ef0e 1958static inline void update_fcr31(void)
fd4a04eb 1959{
f01be154 1960 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
fd4a04eb 1961
f01be154
TS		 1962 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
1963 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp)
c01fccd2 1964 helper_raise_exception(EXCP_FPE);
fd4a04eb 1965 else
f01be154 1966 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
fd4a04eb
TS		 1967}
1968
a16336e4
TS		 1969/* Float support.
1970 Single precition routines have a "s" suffix, double precision a
1971 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
1972 paired single lower "pl", paired single upper "pu". */
1973
a16336e4 1974/* unary operations, modifying fp status */
c01fccd2 1975uint64_t helper_float_sqrt_d(uint64_t fdt0)
b6d96bed 1976{
f01be154 1977 return float64_sqrt(fdt0, &env->active_fpu.fp_status);
b6d96bed
TS		 1978}
1979
c01fccd2 1980uint32_t helper_float_sqrt_s(uint32_t fst0)
b6d96bed 1981{
f01be154 1982 return float32_sqrt(fst0, &env->active_fpu.fp_status);
b6d96bed 1983}
a16336e4 1984
c01fccd2 1985uint64_t helper_float_cvtd_s(uint32_t fst0)
fd4a04eb 1986{
b6d96bed
TS		 1987 uint64_t fdt2;
1988
f01be154
TS		 1989 set_float_exception_flags(0, &env->active_fpu.fp_status);
1990 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
fd4a04eb 1991 update_fcr31();
b6d96bed 1992 return fdt2;
fd4a04eb 1993}
b6d96bed 1994
c01fccd2 1995uint64_t helper_float_cvtd_w(uint32_t wt0)
fd4a04eb 1996{
b6d96bed
TS		 1997 uint64_t fdt2;
1998
f01be154
TS		 1999 set_float_exception_flags(0, &env->active_fpu.fp_status);
2000 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
fd4a04eb 2001 update_fcr31();
b6d96bed 2002 return fdt2;
fd4a04eb 2003}
b6d96bed 2004
c01fccd2 2005uint64_t helper_float_cvtd_l(uint64_t dt0)
fd4a04eb 2006{
b6d96bed
TS		 2007 uint64_t fdt2;
2008
f01be154
TS		 2009 set_float_exception_flags(0, &env->active_fpu.fp_status);
2010 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
fd4a04eb 2011 update_fcr31();
b6d96bed 2012 return fdt2;
fd4a04eb 2013}
b6d96bed 2014
c01fccd2 2015uint64_t helper_float_cvtl_d(uint64_t fdt0)
fd4a04eb 2016{
b6d96bed
TS		 2017 uint64_t dt2;
2018
f01be154
TS		 2019 set_float_exception_flags(0, &env->active_fpu.fp_status);
2020 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2021 update_fcr31();
f01be154 2022 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2023 dt2 = FLOAT_SNAN64;
2024 return dt2;
fd4a04eb 2025}
b6d96bed 2026
c01fccd2 2027uint64_t helper_float_cvtl_s(uint32_t fst0)
fd4a04eb 2028{
b6d96bed
TS		 2029 uint64_t dt2;
2030
f01be154
TS		 2031 set_float_exception_flags(0, &env->active_fpu.fp_status);
2032 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
fd4a04eb 2033 update_fcr31();
f01be154 2034 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2035 dt2 = FLOAT_SNAN64;
2036 return dt2;
fd4a04eb
TS		 2037}
2038
c01fccd2 2039uint64_t helper_float_cvtps_pw(uint64_t dt0)
fd4a04eb 2040{
b6d96bed
TS		 2041 uint32_t fst2;
2042 uint32_t fsth2;
2043
f01be154
TS		 2044 set_float_exception_flags(0, &env->active_fpu.fp_status);
2045 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2046 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
fd4a04eb 2047 update_fcr31();
b6d96bed 2048 return ((uint64_t)fsth2 << 32) | fst2;
fd4a04eb 2049}
b6d96bed 2050
c01fccd2 2051uint64_t helper_float_cvtpw_ps(uint64_t fdt0)
fd4a04eb 2052{
b6d96bed
TS		 2053 uint32_t wt2;
2054 uint32_t wth2;
2055
f01be154
TS		 2056 set_float_exception_flags(0, &env->active_fpu.fp_status);
2057 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2058 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
fd4a04eb 2059 update_fcr31();
f01be154 2060 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) {
b6d96bed
TS		 2061 wt2 = FLOAT_SNAN32;
2062 wth2 = FLOAT_SNAN32;
2063 }
2064 return ((uint64_t)wth2 << 32) | wt2;
fd4a04eb 2065}
b6d96bed 2066
c01fccd2 2067uint32_t helper_float_cvts_d(uint64_t fdt0)
fd4a04eb 2068{
b6d96bed
TS		 2069 uint32_t fst2;
2070
f01be154
TS		 2071 set_float_exception_flags(0, &env->active_fpu.fp_status);
2072 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2073 update_fcr31();
b6d96bed 2074 return fst2;
fd4a04eb 2075}
b6d96bed 2076
c01fccd2 2077uint32_t helper_float_cvts_w(uint32_t wt0)
fd4a04eb 2078{
b6d96bed
TS		 2079 uint32_t fst2;
2080
f01be154
TS		 2081 set_float_exception_flags(0, &env->active_fpu.fp_status);
2082 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
fd4a04eb 2083 update_fcr31();
b6d96bed 2084 return fst2;
fd4a04eb 2085}
b6d96bed 2086
c01fccd2 2087uint32_t helper_float_cvts_l(uint64_t dt0)
fd4a04eb 2088{
b6d96bed
TS		 2089 uint32_t fst2;
2090
f01be154
TS		 2091 set_float_exception_flags(0, &env->active_fpu.fp_status);
2092 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
fd4a04eb 2093 update_fcr31();
b6d96bed 2094 return fst2;
fd4a04eb 2095}
b6d96bed 2096
c01fccd2 2097uint32_t helper_float_cvts_pl(uint32_t wt0)
fd4a04eb 2098{
b6d96bed
TS		 2099 uint32_t wt2;
2100
f01be154 2101 set_float_exception_flags(0, &env->active_fpu.fp_status);
b6d96bed 2102 wt2 = wt0;
fd4a04eb 2103 update_fcr31();
b6d96bed 2104 return wt2;
fd4a04eb 2105}
b6d96bed 2106
c01fccd2 2107uint32_t helper_float_cvts_pu(uint32_t wth0)
fd4a04eb 2108{
b6d96bed
TS		 2109 uint32_t wt2;
2110
f01be154 2111 set_float_exception_flags(0, &env->active_fpu.fp_status);
b6d96bed 2112 wt2 = wth0;
fd4a04eb 2113 update_fcr31();
b6d96bed 2114 return wt2;
fd4a04eb 2115}
b6d96bed 2116
c01fccd2 2117uint32_t helper_float_cvtw_s(uint32_t fst0)
fd4a04eb 2118{
b6d96bed
TS		 2119 uint32_t wt2;
2120
f01be154
TS		 2121 set_float_exception_flags(0, &env->active_fpu.fp_status);
2122 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
fd4a04eb 2123 update_fcr31();
f01be154 2124 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2125 wt2 = FLOAT_SNAN32;
2126 return wt2;
fd4a04eb 2127}
b6d96bed 2128
c01fccd2 2129uint32_t helper_float_cvtw_d(uint64_t fdt0)
fd4a04eb 2130{
b6d96bed
TS		 2131 uint32_t wt2;
2132
f01be154
TS		 2133 set_float_exception_flags(0, &env->active_fpu.fp_status);
2134 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2135 update_fcr31();
f01be154 2136 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2137 wt2 = FLOAT_SNAN32;
2138 return wt2;
fd4a04eb
TS		 2139}
2140
c01fccd2 2141uint64_t helper_float_roundl_d(uint64_t fdt0)
fd4a04eb 2142{
b6d96bed
TS		 2143 uint64_t dt2;
2144
f01be154
TS		 2145 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2146 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2147 RESTORE_ROUNDING_MODE;
2148 update_fcr31();
f01be154 2149 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2150 dt2 = FLOAT_SNAN64;
2151 return dt2;
fd4a04eb 2152}
b6d96bed 2153
c01fccd2 2154uint64_t helper_float_roundl_s(uint32_t fst0)
fd4a04eb 2155{
b6d96bed
TS		 2156 uint64_t dt2;
2157
f01be154
TS		 2158 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2159 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2160 RESTORE_ROUNDING_MODE;
2161 update_fcr31();
f01be154 2162 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2163 dt2 = FLOAT_SNAN64;
2164 return dt2;
fd4a04eb 2165}
b6d96bed 2166
c01fccd2 2167uint32_t helper_float_roundw_d(uint64_t fdt0)
fd4a04eb 2168{
b6d96bed
TS		 2169 uint32_t wt2;
2170
f01be154
TS		 2171 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2172 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2173 RESTORE_ROUNDING_MODE;
2174 update_fcr31();
f01be154 2175 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2176 wt2 = FLOAT_SNAN32;
2177 return wt2;
fd4a04eb 2178}
b6d96bed 2179
c01fccd2 2180uint32_t helper_float_roundw_s(uint32_t fst0)
fd4a04eb 2181{
b6d96bed
TS		 2182 uint32_t wt2;
2183
f01be154
TS		 2184 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2185 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2186 RESTORE_ROUNDING_MODE;
2187 update_fcr31();
f01be154 2188 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2189 wt2 = FLOAT_SNAN32;
2190 return wt2;
fd4a04eb
TS		 2191}
2192
c01fccd2 2193uint64_t helper_float_truncl_d(uint64_t fdt0)
fd4a04eb 2194{
b6d96bed
TS		 2195 uint64_t dt2;
2196
f01be154 2197 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2198 update_fcr31();
f01be154 2199 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2200 dt2 = FLOAT_SNAN64;
2201 return dt2;
fd4a04eb 2202}
b6d96bed 2203
c01fccd2 2204uint64_t helper_float_truncl_s(uint32_t fst0)
fd4a04eb 2205{
b6d96bed
TS		 2206 uint64_t dt2;
2207
f01be154 2208 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
fd4a04eb 2209 update_fcr31();
f01be154 2210 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2211 dt2 = FLOAT_SNAN64;
2212 return dt2;
fd4a04eb 2213}
b6d96bed 2214
c01fccd2 2215uint32_t helper_float_truncw_d(uint64_t fdt0)
fd4a04eb 2216{
b6d96bed
TS		 2217 uint32_t wt2;
2218
f01be154 2219 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2220 update_fcr31();
f01be154 2221 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2222 wt2 = FLOAT_SNAN32;
2223 return wt2;
fd4a04eb 2224}
b6d96bed 2225
c01fccd2 2226uint32_t helper_float_truncw_s(uint32_t fst0)
fd4a04eb 2227{
b6d96bed
TS		 2228 uint32_t wt2;
2229
f01be154 2230 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
fd4a04eb 2231 update_fcr31();
f01be154 2232 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2233 wt2 = FLOAT_SNAN32;
2234 return wt2;
fd4a04eb
TS		 2235}
2236
c01fccd2 2237uint64_t helper_float_ceill_d(uint64_t fdt0)
fd4a04eb 2238{
b6d96bed
TS		 2239 uint64_t dt2;
2240
f01be154
TS		 2241 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2242 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2243 RESTORE_ROUNDING_MODE;
2244 update_fcr31();
f01be154 2245 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2246 dt2 = FLOAT_SNAN64;
2247 return dt2;
fd4a04eb 2248}
b6d96bed 2249
c01fccd2 2250uint64_t helper_float_ceill_s(uint32_t fst0)
fd4a04eb 2251{
b6d96bed
TS		 2252 uint64_t dt2;
2253
f01be154
TS		 2254 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2255 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2256 RESTORE_ROUNDING_MODE;
2257 update_fcr31();
f01be154 2258 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2259 dt2 = FLOAT_SNAN64;
2260 return dt2;
fd4a04eb 2261}
b6d96bed 2262
c01fccd2 2263uint32_t helper_float_ceilw_d(uint64_t fdt0)
fd4a04eb 2264{
b6d96bed
TS		 2265 uint32_t wt2;
2266
f01be154
TS		 2267 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2268 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2269 RESTORE_ROUNDING_MODE;
2270 update_fcr31();
f01be154 2271 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2272 wt2 = FLOAT_SNAN32;
2273 return wt2;
fd4a04eb 2274}
b6d96bed 2275
c01fccd2 2276uint32_t helper_float_ceilw_s(uint32_t fst0)
fd4a04eb 2277{
b6d96bed
TS		 2278 uint32_t wt2;
2279
f01be154
TS		 2280 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2281 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2282 RESTORE_ROUNDING_MODE;
2283 update_fcr31();
f01be154 2284 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2285 wt2 = FLOAT_SNAN32;
2286 return wt2;
fd4a04eb
TS		 2287}
2288
c01fccd2 2289uint64_t helper_float_floorl_d(uint64_t fdt0)
fd4a04eb 2290{
b6d96bed
TS		 2291 uint64_t dt2;
2292
f01be154
TS		 2293 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2294 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2295 RESTORE_ROUNDING_MODE;
2296 update_fcr31();
f01be154 2297 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2298 dt2 = FLOAT_SNAN64;
2299 return dt2;
fd4a04eb 2300}
b6d96bed 2301
c01fccd2 2302uint64_t helper_float_floorl_s(uint32_t fst0)
fd4a04eb 2303{
b6d96bed
TS		 2304 uint64_t dt2;
2305
f01be154
TS		 2306 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2307 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2308 RESTORE_ROUNDING_MODE;
2309 update_fcr31();
f01be154 2310 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2311 dt2 = FLOAT_SNAN64;
2312 return dt2;
fd4a04eb 2313}
b6d96bed 2314
c01fccd2 2315uint32_t helper_float_floorw_d(uint64_t fdt0)
fd4a04eb 2316{
b6d96bed
TS		 2317 uint32_t wt2;
2318
f01be154
TS		 2319 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2320 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2321 RESTORE_ROUNDING_MODE;
2322 update_fcr31();
f01be154 2323 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2324 wt2 = FLOAT_SNAN32;
2325 return wt2;
fd4a04eb 2326}
b6d96bed 2327
c01fccd2 2328uint32_t helper_float_floorw_s(uint32_t fst0)
fd4a04eb 2329{
b6d96bed
TS		 2330 uint32_t wt2;
2331
f01be154
TS		 2332 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2333 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2334 RESTORE_ROUNDING_MODE;
2335 update_fcr31();
f01be154 2336 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2337 wt2 = FLOAT_SNAN32;
2338 return wt2;
fd4a04eb
TS		 2339}
2340
a16336e4 2341/* unary operations, not modifying fp status */
b6d96bed 2342#define FLOAT_UNOP(name) \
c01fccd2 2343uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
b6d96bed
TS		 2344{ \
2345 return float64_ ## name(fdt0); \
2346} \
c01fccd2 2347uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
b6d96bed
TS		 2348{ \
2349 return float32_ ## name(fst0); \
2350} \
c01fccd2 2351uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
b6d96bed
TS		 2352{ \
2353 uint32_t wt0; \
2354 uint32_t wth0; \
2355 \
2356 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
2357 wth0 = float32_ ## name(fdt0 >> 32); \
2358 return ((uint64_t)wth0 << 32) | wt0; \
a16336e4
TS		 2359}
2360FLOAT_UNOP(abs)
2361FLOAT_UNOP(chs)
2362#undef FLOAT_UNOP
2363
8dfdb87c 2364/* MIPS specific unary operations */
c01fccd2 2365uint64_t helper_float_recip_d(uint64_t fdt0)
8dfdb87c 2366{
b6d96bed
TS		 2367 uint64_t fdt2;
2368
f01be154
TS		 2369 set_float_exception_flags(0, &env->active_fpu.fp_status);
2370 fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
8dfdb87c 2371 update_fcr31();
b6d96bed 2372 return fdt2;
8dfdb87c 2373}
b6d96bed 2374
c01fccd2 2375uint32_t helper_float_recip_s(uint32_t fst0)
8dfdb87c 2376{
b6d96bed
TS		 2377 uint32_t fst2;
2378
f01be154
TS		 2379 set_float_exception_flags(0, &env->active_fpu.fp_status);
2380 fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
8dfdb87c 2381 update_fcr31();
b6d96bed 2382 return fst2;
57fa1fb3 2383}
57fa1fb3 2384
c01fccd2 2385uint64_t helper_float_rsqrt_d(uint64_t fdt0)
8dfdb87c 2386{
b6d96bed
TS		 2387 uint64_t fdt2;
2388
f01be154
TS		 2389 set_float_exception_flags(0, &env->active_fpu.fp_status);
2390 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2391 fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
8dfdb87c 2392 update_fcr31();
b6d96bed 2393 return fdt2;
8dfdb87c 2394}
b6d96bed 2395
c01fccd2 2396uint32_t helper_float_rsqrt_s(uint32_t fst0)
8dfdb87c 2397{
b6d96bed
TS		 2398 uint32_t fst2;
2399
f01be154
TS		 2400 set_float_exception_flags(0, &env->active_fpu.fp_status);
2401 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2402 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
8dfdb87c 2403 update_fcr31();
b6d96bed 2404 return fst2;
8dfdb87c
TS		 2405}
2406
c01fccd2 2407uint64_t helper_float_recip1_d(uint64_t fdt0)
8dfdb87c 2408{
b6d96bed
TS		 2409 uint64_t fdt2;
2410
f01be154
TS		 2411 set_float_exception_flags(0, &env->active_fpu.fp_status);
2412 fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
8dfdb87c 2413 update_fcr31();
b6d96bed 2414 return fdt2;
8dfdb87c 2415}
b6d96bed 2416
c01fccd2 2417uint32_t helper_float_recip1_s(uint32_t fst0)
8dfdb87c 2418{
b6d96bed
TS		 2419 uint32_t fst2;
2420
f01be154
TS		 2421 set_float_exception_flags(0, &env->active_fpu.fp_status);
2422 fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
8dfdb87c 2423 update_fcr31();
b6d96bed 2424 return fst2;
8dfdb87c 2425}
b6d96bed 2426
c01fccd2 2427uint64_t helper_float_recip1_ps(uint64_t fdt0)
8dfdb87c 2428{
b6d96bed
TS		 2429 uint32_t fst2;
2430 uint32_t fsth2;
2431
f01be154
TS		 2432 set_float_exception_flags(0, &env->active_fpu.fp_status);
2433 fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2434 fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status);
8dfdb87c 2435 update_fcr31();
b6d96bed 2436 return ((uint64_t)fsth2 << 32) | fst2;
8dfdb87c
TS		 2437}
2438
c01fccd2 2439uint64_t helper_float_rsqrt1_d(uint64_t fdt0)
8dfdb87c 2440{
b6d96bed
TS		 2441 uint64_t fdt2;
2442
f01be154
TS		 2443 set_float_exception_flags(0, &env->active_fpu.fp_status);
2444 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2445 fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
8dfdb87c 2446 update_fcr31();
b6d96bed 2447 return fdt2;
8dfdb87c 2448}
b6d96bed 2449
c01fccd2 2450uint32_t helper_float_rsqrt1_s(uint32_t fst0)
8dfdb87c 2451{
b6d96bed
TS		 2452 uint32_t fst2;
2453
f01be154
TS		 2454 set_float_exception_flags(0, &env->active_fpu.fp_status);
2455 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2456 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
8dfdb87c 2457 update_fcr31();
b6d96bed 2458 return fst2;
8dfdb87c 2459}
b6d96bed 2460
c01fccd2 2461uint64_t helper_float_rsqrt1_ps(uint64_t fdt0)
8dfdb87c 2462{
b6d96bed
TS		 2463 uint32_t fst2;
2464 uint32_t fsth2;
2465
f01be154
TS		 2466 set_float_exception_flags(0, &env->active_fpu.fp_status);
2467 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2468 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2469 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2470 fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status);
8dfdb87c 2471 update_fcr31();
b6d96bed 2472 return ((uint64_t)fsth2 << 32) | fst2;
57fa1fb3 2473}
57fa1fb3 2474
c01fccd2 2475#define FLOAT_OP(name, p) void helper_float_##name##_##p(void)
b6d96bed 2476
fd4a04eb 2477/* binary operations */
b6d96bed 2478#define FLOAT_BINOP(name) \
c01fccd2 2479uint64_t helper_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \
b6d96bed
TS		 2480{ \
2481 uint64_t dt2; \
2482 \
f01be154
TS		 2483 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2484 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
ead9360e 2485 update_fcr31(); \
f01be154 2486 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
b6d96bed
TS		 2487 dt2 = FLOAT_QNAN64; \
2488 return dt2; \
2489} \
2490 \
c01fccd2 2491uint32_t helper_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \
b6d96bed
TS		 2492{ \
2493 uint32_t wt2; \
2494 \
f01be154
TS		 2495 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2496 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
ead9360e 2497 update_fcr31(); \
f01be154 2498 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
b6d96bed
TS		 2499 wt2 = FLOAT_QNAN32; \
2500 return wt2; \
2501} \
2502 \
c01fccd2 2503uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \
b6d96bed
TS		 2504{ \
2505 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2506 uint32_t fsth0 = fdt0 >> 32; \
2507 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2508 uint32_t fsth1 = fdt1 >> 32; \
2509 uint32_t wt2; \
2510 uint32_t wth2; \
2511 \
f01be154
TS		 2512 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2513 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2514 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
b6d96bed 2515 update_fcr31(); \
f01be154 2516 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \
b6d96bed
TS		 2517 wt2 = FLOAT_QNAN32; \
2518 wth2 = FLOAT_QNAN32; \
2519 } \
2520 return ((uint64_t)wth2 << 32) | wt2; \
fd4a04eb 2521}
b6d96bed 2522
fd4a04eb
TS		 2523FLOAT_BINOP(add)
2524FLOAT_BINOP(sub)
2525FLOAT_BINOP(mul)
2526FLOAT_BINOP(div)
2527#undef FLOAT_BINOP
2528
a16336e4 2529/* ternary operations */
b6d96bed 2530#define FLOAT_TERNOP(name1, name2) \
c01fccd2 2531uint64_t helper_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
b6d96bed
TS		 2532 uint64_t fdt2) \
2533{ \
f01be154
TS		 2534 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2535 return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2536} \
2537 \
c01fccd2 2538uint32_t helper_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
b6d96bed
TS		 2539 uint32_t fst2) \
2540{ \
f01be154
TS		 2541 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2542 return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2543} \
2544 \
c01fccd2 2545uint64_t helper_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \
b6d96bed
TS		 2546 uint64_t fdt2) \
2547{ \
2548 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2549 uint32_t fsth0 = fdt0 >> 32; \
2550 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2551 uint32_t fsth1 = fdt1 >> 32; \
2552 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2553 uint32_t fsth2 = fdt2 >> 32; \
2554 \
f01be154
TS		 2555 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2556 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
2557 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2558 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
b6d96bed 2559 return ((uint64_t)fsth2 << 32) | fst2; \
a16336e4 2560}
b6d96bed 2561
a16336e4
TS		 2562FLOAT_TERNOP(mul, add)
2563FLOAT_TERNOP(mul, sub)
2564#undef FLOAT_TERNOP
2565
2566/* negated ternary operations */
b6d96bed 2567#define FLOAT_NTERNOP(name1, name2) \
c01fccd2 2568uint64_t helper_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
b6d96bed
TS		 2569 uint64_t fdt2) \
2570{ \
f01be154
TS		 2571 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2572 fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2573 return float64_chs(fdt2); \
2574} \
2575 \
c01fccd2 2576uint32_t helper_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
b6d96bed
TS		 2577 uint32_t fst2) \
2578{ \
f01be154
TS		 2579 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2580 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2581 return float32_chs(fst2); \
2582} \
2583 \
c01fccd2 2584uint64_t helper_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\
b6d96bed
TS		 2585 uint64_t fdt2) \
2586{ \
2587 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2588 uint32_t fsth0 = fdt0 >> 32; \
2589 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2590 uint32_t fsth1 = fdt1 >> 32; \
2591 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2592 uint32_t fsth2 = fdt2 >> 32; \
2593 \
f01be154
TS		 2594 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2595 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
2596 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2597 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2598 fst2 = float32_chs(fst2); \
2599 fsth2 = float32_chs(fsth2); \
2600 return ((uint64_t)fsth2 << 32) | fst2; \
a16336e4 2601}
b6d96bed 2602
a16336e4
TS		 2603FLOAT_NTERNOP(mul, add)
2604FLOAT_NTERNOP(mul, sub)
2605#undef FLOAT_NTERNOP
2606
8dfdb87c 2607/* MIPS specific binary operations */
c01fccd2 2608uint64_t helper_float_recip2_d(uint64_t fdt0, uint64_t fdt2)
8dfdb87c 2609{
f01be154
TS		 2610 set_float_exception_flags(0, &env->active_fpu.fp_status);
2611 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2612 fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status));
8dfdb87c 2613 update_fcr31();
b6d96bed 2614 return fdt2;
8dfdb87c 2615}
b6d96bed 2616
c01fccd2 2617uint32_t helper_float_recip2_s(uint32_t fst0, uint32_t fst2)
8dfdb87c 2618{
f01be154
TS		 2619 set_float_exception_flags(0, &env->active_fpu.fp_status);
2620 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2621 fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
8dfdb87c 2622 update_fcr31();
b6d96bed 2623 return fst2;
8dfdb87c 2624}
b6d96bed 2625
c01fccd2 2626uint64_t helper_float_recip2_ps(uint64_t fdt0, uint64_t fdt2)
8dfdb87c 2627{
b6d96bed
TS		 2628 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2629 uint32_t fsth0 = fdt0 >> 32;
2630 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2631 uint32_t fsth2 = fdt2 >> 32;
2632
f01be154
TS		 2633 set_float_exception_flags(0, &env->active_fpu.fp_status);
2634 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2635 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2636 fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
2637 fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status));
8dfdb87c 2638 update_fcr31();
b6d96bed 2639 return ((uint64_t)fsth2 << 32) | fst2;
8dfdb87c
TS		 2640}
2641
c01fccd2 2642uint64_t helper_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2)
8dfdb87c 2643{
f01be154
TS		 2644 set_float_exception_flags(0, &env->active_fpu.fp_status);
2645 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2646 fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status);
2647 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
8dfdb87c 2648 update_fcr31();
b6d96bed 2649 return fdt2;
8dfdb87c 2650}
b6d96bed 2651
c01fccd2 2652uint32_t helper_float_rsqrt2_s(uint32_t fst0, uint32_t fst2)
8dfdb87c 2653{
f01be154
TS		 2654 set_float_exception_flags(0, &env->active_fpu.fp_status);
2655 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2656 fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
2657 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
8dfdb87c 2658 update_fcr31();
b6d96bed 2659 return fst2;
8dfdb87c 2660}
b6d96bed 2661
c01fccd2 2662uint64_t helper_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2)
8dfdb87c 2663{
b6d96bed
TS		 2664 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2665 uint32_t fsth0 = fdt0 >> 32;
2666 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2667 uint32_t fsth2 = fdt2 >> 32;
2668
f01be154
TS		 2669 set_float_exception_flags(0, &env->active_fpu.fp_status);
2670 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2671 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2672 fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
2673 fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status);
2674 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2675 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
8dfdb87c 2676 update_fcr31();
b6d96bed 2677 return ((uint64_t)fsth2 << 32) | fst2;
57fa1fb3 2678}
57fa1fb3 2679
c01fccd2 2680uint64_t helper_float_addr_ps(uint64_t fdt0, uint64_t fdt1)
fd4a04eb 2681{
b6d96bed
TS		 2682 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2683 uint32_t fsth0 = fdt0 >> 32;
2684 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2685 uint32_t fsth1 = fdt1 >> 32;
2686 uint32_t fst2;
2687 uint32_t fsth2;
2688
f01be154
TS		 2689 set_float_exception_flags(0, &env->active_fpu.fp_status);
2690 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
2691 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
fd4a04eb 2692 update_fcr31();
b6d96bed 2693 return ((uint64_t)fsth2 << 32) | fst2;
fd4a04eb
TS		 2694}
2695
c01fccd2 2696uint64_t helper_float_mulr_ps(uint64_t fdt0, uint64_t fdt1)
57fa1fb3 2697{
b6d96bed
TS		 2698 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2699 uint32_t fsth0 = fdt0 >> 32;
2700 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2701 uint32_t fsth1 = fdt1 >> 32;
2702 uint32_t fst2;
2703 uint32_t fsth2;
2704
f01be154
TS		 2705 set_float_exception_flags(0, &env->active_fpu.fp_status);
2706 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
2707 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
57fa1fb3 2708 update_fcr31();
b6d96bed 2709 return ((uint64_t)fsth2 << 32) | fst2;
57fa1fb3
TS		 2710}
2711
8dfdb87c 2712/* compare operations */
b6d96bed 2713#define FOP_COND_D(op, cond) \
c01fccd2 2714void helper_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
b6d96bed
TS		 2715{ \
2716 int c = cond; \
2717 update_fcr31(); \
2718 if (c) \
f01be154 2719 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2720 else \
f01be154 2721 CLEAR_FP_COND(cc, env->active_fpu); \
b6d96bed 2722} \
c01fccd2 2723void helper_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
b6d96bed
TS		 2724{ \
2725 int c; \
2726 fdt0 = float64_abs(fdt0); \
2727 fdt1 = float64_abs(fdt1); \
2728 c = cond; \
2729 update_fcr31(); \
2730 if (c) \
f01be154 2731 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2732 else \
f01be154 2733 CLEAR_FP_COND(cc, env->active_fpu); \
fd4a04eb
TS		 2734}
2735
cd5158ea 2736static int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
fd4a04eb
TS		 2737{
2738 if (float64_is_signaling_nan(a) ||
2739 float64_is_signaling_nan(b) ||
2740 (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
2741 float_raise(float_flag_invalid, status);
2742 return 1;
2743 } else if (float64_is_nan(a) || float64_is_nan(b)) {
2744 return 1;
2745 } else {
2746 return 0;
2747 }
2748}
2749
2750/* NOTE: the comma operator will make "cond" to eval to false,
2751 * but float*_is_unordered() is still called. */
f01be154
TS		 2752FOP_COND_D(f, (float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status), 0))
2753FOP_COND_D(un, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status))
2754FOP_COND_D(eq, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2755FOP_COND_D(ueq, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2756FOP_COND_D(olt, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2757FOP_COND_D(ult, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2758FOP_COND_D(ole, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2759FOP_COND_D(ule, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
fd4a04eb
TS		 2760/* NOTE: the comma operator will make "cond" to eval to false,
2761 * but float*_is_unordered() is still called. */
f01be154
TS		 2762FOP_COND_D(sf, (float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status), 0))
2763FOP_COND_D(ngle,float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status))
2764FOP_COND_D(seq, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2765FOP_COND_D(ngl, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2766FOP_COND_D(lt, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2767FOP_COND_D(nge, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2768FOP_COND_D(le, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2769FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
b6d96bed
TS		 2770
2771#define FOP_COND_S(op, cond) \
c01fccd2 2772void helper_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
b6d96bed
TS		 2773{ \
2774 int c = cond; \
2775 update_fcr31(); \
2776 if (c) \
f01be154 2777 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2778 else \
f01be154 2779 CLEAR_FP_COND(cc, env->active_fpu); \
b6d96bed 2780} \
c01fccd2 2781void helper_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
b6d96bed
TS		 2782{ \
2783 int c; \
2784 fst0 = float32_abs(fst0); \
2785 fst1 = float32_abs(fst1); \
2786 c = cond; \
2787 update_fcr31(); \
2788 if (c) \
f01be154 2789 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2790 else \
f01be154 2791 CLEAR_FP_COND(cc, env->active_fpu); \
fd4a04eb
TS		 2792}
2793
cd5158ea 2794static flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
fd4a04eb 2795{
fd4a04eb
TS		 2796 if (float32_is_signaling_nan(a) ||
2797 float32_is_signaling_nan(b) ||
2798 (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
2799 float_raise(float_flag_invalid, status);
2800 return 1;
2801 } else if (float32_is_nan(a) || float32_is_nan(b)) {
2802 return 1;
2803 } else {
2804 return 0;
2805 }
2806}
2807
2808/* NOTE: the comma operator will make "cond" to eval to false,
2809 * but float*_is_unordered() is still called. */
f01be154
TS		 2810FOP_COND_S(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0))
2811FOP_COND_S(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status))
2812FOP_COND_S(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2813FOP_COND_S(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2814FOP_COND_S(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2815FOP_COND_S(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2816FOP_COND_S(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
2817FOP_COND_S(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
fd4a04eb
TS		 2818/* NOTE: the comma operator will make "cond" to eval to false,
2819 * but float*_is_unordered() is still called. */
f01be154
TS		 2820FOP_COND_S(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0))
2821FOP_COND_S(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status))
2822FOP_COND_S(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2823FOP_COND_S(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2824FOP_COND_S(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2825FOP_COND_S(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2826FOP_COND_S(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
2827FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
b6d96bed
TS		 2828
2829#define FOP_COND_PS(op, condl, condh) \
c01fccd2 2830void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
b6d96bed
TS		 2831{ \
2832 uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
2833 uint32_t fsth0 = float32_abs(fdt0 >> 32); \
2834 uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
2835 uint32_t fsth1 = float32_abs(fdt1 >> 32); \
2836 int cl = condl; \
2837 int ch = condh; \
2838 \
2839 update_fcr31(); \
2840 if (cl) \
f01be154 2841 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2842 else \
f01be154 2843 CLEAR_FP_COND(cc, env->active_fpu); \
b6d96bed 2844 if (ch) \
f01be154 2845 SET_FP_COND(cc + 1, env->active_fpu); \
b6d96bed 2846 else \
f01be154 2847 CLEAR_FP_COND(cc + 1, env->active_fpu); \
b6d96bed 2848} \
c01fccd2 2849void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
b6d96bed
TS		 2850{ \
2851 uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
2852 uint32_t fsth0 = float32_abs(fdt0 >> 32); \
2853 uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
2854 uint32_t fsth1 = float32_abs(fdt1 >> 32); \
2855 int cl = condl; \
2856 int ch = condh; \
2857 \
2858 update_fcr31(); \
2859 if (cl) \
f01be154 2860 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2861 else \
f01be154 2862 CLEAR_FP_COND(cc, env->active_fpu); \
b6d96bed 2863 if (ch) \
f01be154 2864 SET_FP_COND(cc + 1, env->active_fpu); \
b6d96bed 2865 else \
f01be154 2866 CLEAR_FP_COND(cc + 1, env->active_fpu); \
fd4a04eb
TS		 2867}
2868
2869/* NOTE: the comma operator will make "cond" to eval to false,
2870 * but float*_is_unordered() is still called. */
f01be154
TS		 2871FOP_COND_PS(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0),
2872 (float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status), 0))
2873FOP_COND_PS(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status),
2874 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status))
2875FOP_COND_PS(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2876 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2877FOP_COND_PS(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2878 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2879FOP_COND_PS(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2880 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2881FOP_COND_PS(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2882 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2883FOP_COND_PS(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status),
2884 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
2885FOP_COND_PS(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
2886 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
fd4a04eb
TS		 2887/* NOTE: the comma operator will make "cond" to eval to false,
2888 * but float*_is_unordered() is still called. */
f01be154
TS		 2889FOP_COND_PS(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0),
2890 (float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status), 0))
2891FOP_COND_PS(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status),
2892 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status))
2893FOP_COND_PS(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2894 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2895FOP_COND_PS(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2896 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2897FOP_COND_PS(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2898 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2899FOP_COND_PS(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2900 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2901FOP_COND_PS(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status),
2902 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
2903FOP_COND_PS(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
2904 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
Qemu copy for testing