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make qemu_thread_create block all signals
[qemu.git] / target-mips / op_helper.c
CommitLineData
6af0bf9c
FB		 1/*
2 * MIPS emulation helpers for qemu.
5fafdf24 3 *
6af0bf9c
FB		 4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
6af0bf9c 18 */
2d0e944d 19#include <stdlib.h>
6af0bf9c
FB		 20#include "exec.h"
21
05f778c8
TS		 22#include "host-utils.h"
23
a7812ae4 24#include "helper.h"
6af0bf9c
FB		 25/*****************************************************************************/
26/* Exceptions processing helpers */
6af0bf9c 27
c01fccd2 28void helper_raise_exception_err (uint32_t exception, int error_code)
6af0bf9c
FB		 29{
30#if 1
93fcfe39
AL		 31 if (exception < 0x100)
32 qemu_log("%s: %d %d\n", __func__, exception, error_code);
6af0bf9c
FB		 33#endif
34 env->exception_index = exception;
35 env->error_code = error_code;
6af0bf9c
FB		 36 cpu_loop_exit();
37}
38
c01fccd2 39void helper_raise_exception (uint32_t exception)
6af0bf9c 40{
c01fccd2 41 helper_raise_exception_err(exception, 0);
6af0bf9c
FB		 42}
43
c01fccd2 44void helper_interrupt_restart (void)
48d38ca5
TS		 45{
46 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
47 !(env->CP0_Status & (1 << CP0St_ERL)) &&
48 !(env->hflags & MIPS_HFLAG_DM) &&
49 (env->CP0_Status & (1 << CP0St_IE)) &&
50 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
51 env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
c01fccd2 52 helper_raise_exception(EXCP_EXT_INTERRUPT);
48d38ca5
TS		 53 }
54}
55
f9480ffc
TS		 56#if !defined(CONFIG_USER_ONLY)
57static void do_restore_state (void *pc_ptr)
4ad40f36 58{
a607922c
FB		 59 TranslationBlock *tb;
60 unsigned long pc = (unsigned long) pc_ptr;
61
62 tb = tb_find_pc (pc);
63 if (tb) {
64 cpu_restore_state (tb, env, pc, NULL);
65 }
4ad40f36 66}
f9480ffc 67#endif
4ad40f36 68
0ae43045
AJ		 69#if defined(CONFIG_USER_ONLY)
70#define HELPER_LD(name, insn, type) \
71static inline type do_##name(target_ulong addr, int mem_idx) \
72{ \
73 return (type) insn##_raw(addr); \
74}
75#else
76#define HELPER_LD(name, insn, type) \
77static inline type do_##name(target_ulong addr, int mem_idx) \
78{ \
79 switch (mem_idx) \
80 { \
81 case 0: return (type) insn##_kernel(addr); break; \
82 case 1: return (type) insn##_super(addr); break; \
83 default: \
84 case 2: return (type) insn##_user(addr); break; \
85 } \
86}
87#endif
88HELPER_LD(lbu, ldub, uint8_t)
89HELPER_LD(lw, ldl, int32_t)
90#ifdef TARGET_MIPS64
91HELPER_LD(ld, ldq, int64_t)
92#endif
93#undef HELPER_LD
94
95#if defined(CONFIG_USER_ONLY)
96#define HELPER_ST(name, insn, type) \
97static inline void do_##name(target_ulong addr, type val, int mem_idx) \
98{ \
99 insn##_raw(addr, val); \
100}
101#else
102#define HELPER_ST(name, insn, type) \
103static inline void do_##name(target_ulong addr, type val, int mem_idx) \
104{ \
105 switch (mem_idx) \
106 { \
107 case 0: insn##_kernel(addr, val); break; \
108 case 1: insn##_super(addr, val); break; \
109 default: \
110 case 2: insn##_user(addr, val); break; \
111 } \
112}
113#endif
114HELPER_ST(sb, stb, uint8_t)
115HELPER_ST(sw, stl, uint32_t)
116#ifdef TARGET_MIPS64
117HELPER_ST(sd, stq, uint64_t)
118#endif
119#undef HELPER_ST
120
d9bea114 121target_ulong helper_clo (target_ulong arg1)
30898801 122{
d9bea114 123 return clo32(arg1);
30898801
TS		 124}
125
d9bea114 126target_ulong helper_clz (target_ulong arg1)
30898801 127{
d9bea114 128 return clz32(arg1);
30898801
TS		 129}
130
d26bc211 131#if defined(TARGET_MIPS64)
d9bea114 132target_ulong helper_dclo (target_ulong arg1)
05f778c8 133{
d9bea114 134 return clo64(arg1);
05f778c8
TS		 135}
136
d9bea114 137target_ulong helper_dclz (target_ulong arg1)
05f778c8 138{
d9bea114 139 return clz64(arg1);
05f778c8 140}
d26bc211 141#endif /* TARGET_MIPS64 */
c570fd16 142
6af0bf9c 143/* 64 bits arithmetic for 32 bits hosts */
c904ef0e 144static inline uint64_t get_HILO (void)
6af0bf9c 145{
b5dc7732 146 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
6af0bf9c
FB		 147}
148
c904ef0e 149static inline void set_HILO (uint64_t HILO)
6af0bf9c 150{
b5dc7732
TS		 151 env->active_tc.LO[0] = (int32_t)HILO;
152 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
6af0bf9c
FB		 153}
154
d9bea114 155static inline void set_HIT0_LO (target_ulong arg1, uint64_t HILO)
e9c71dd1 156{
b5dc7732 157 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
d9bea114 158 arg1 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
e9c71dd1
TS		 159}
160
d9bea114 161static inline void set_HI_LOT0 (target_ulong arg1, uint64_t HILO)
e9c71dd1 162{
d9bea114 163 arg1 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
b5dc7732 164 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
e9c71dd1
TS		 165}
166
e9c71dd1 167/* Multiplication variants of the vr54xx. */
d9bea114 168target_ulong helper_muls (target_ulong arg1, target_ulong arg2)
e9c71dd1 169{
d9bea114 170 set_HI_LOT0(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 171
d9bea114 172 return arg1;
e9c71dd1
TS		 173}
174
d9bea114 175target_ulong helper_mulsu (target_ulong arg1, target_ulong arg2)
e9c71dd1 176{
d9bea114 177 set_HI_LOT0(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 178
d9bea114 179 return arg1;
e9c71dd1
TS		 180}
181
d9bea114 182target_ulong helper_macc (target_ulong arg1, target_ulong arg2)
e9c71dd1 183{
d9bea114 184 set_HI_LOT0(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 185
d9bea114 186 return arg1;
e9c71dd1
TS		 187}
188
d9bea114 189target_ulong helper_macchi (target_ulong arg1, target_ulong arg2)
e9c71dd1 190{
d9bea114 191 set_HIT0_LO(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 192
d9bea114 193 return arg1;
e9c71dd1
TS		 194}
195
d9bea114 196target_ulong helper_maccu (target_ulong arg1, target_ulong arg2)
e9c71dd1 197{
d9bea114 198 set_HI_LOT0(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 199
d9bea114 200 return arg1;
e9c71dd1
TS		 201}
202
d9bea114 203target_ulong helper_macchiu (target_ulong arg1, target_ulong arg2)
e9c71dd1 204{
d9bea114 205 set_HIT0_LO(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 206
d9bea114 207 return arg1;
e9c71dd1
TS		 208}
209
d9bea114 210target_ulong helper_msac (target_ulong arg1, target_ulong arg2)
e9c71dd1 211{
d9bea114 212 set_HI_LOT0(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 213
d9bea114 214 return arg1;
e9c71dd1
TS		 215}
216
d9bea114 217target_ulong helper_msachi (target_ulong arg1, target_ulong arg2)
e9c71dd1 218{
d9bea114 219 set_HIT0_LO(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 220
d9bea114 221 return arg1;
e9c71dd1
TS		 222}
223
d9bea114 224target_ulong helper_msacu (target_ulong arg1, target_ulong arg2)
e9c71dd1 225{
d9bea114 226 set_HI_LOT0(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 227
d9bea114 228 return arg1;
e9c71dd1
TS		 229}
230
d9bea114 231target_ulong helper_msachiu (target_ulong arg1, target_ulong arg2)
e9c71dd1 232{
d9bea114 233 set_HIT0_LO(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 234
d9bea114 235 return arg1;
e9c71dd1
TS		 236}
237
d9bea114 238target_ulong helper_mulhi (target_ulong arg1, target_ulong arg2)
e9c71dd1 239{
d9bea114 240 set_HIT0_LO(arg1, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
be24bb4f 241
d9bea114 242 return arg1;
e9c71dd1
TS		 243}
244
d9bea114 245target_ulong helper_mulhiu (target_ulong arg1, target_ulong arg2)
e9c71dd1 246{
d9bea114 247 set_HIT0_LO(arg1, (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
be24bb4f 248
d9bea114 249 return arg1;
e9c71dd1
TS		 250}
251
d9bea114 252target_ulong helper_mulshi (target_ulong arg1, target_ulong arg2)
e9c71dd1 253{
d9bea114 254 set_HIT0_LO(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 255
d9bea114 256 return arg1;
e9c71dd1
TS		 257}
258
d9bea114 259target_ulong helper_mulshiu (target_ulong arg1, target_ulong arg2)
e9c71dd1 260{
d9bea114 261 set_HIT0_LO(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 262
d9bea114 263 return arg1;
e9c71dd1 264}
6af0bf9c 265
214c465f 266#ifdef TARGET_MIPS64
d9bea114 267void helper_dmult (target_ulong arg1, target_ulong arg2)
214c465f 268{
d9bea114 269 muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
214c465f
TS		 270}
271
d9bea114 272void helper_dmultu (target_ulong arg1, target_ulong arg2)
214c465f 273{
d9bea114 274 mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
214c465f
TS		 275}
276#endif
277
e7139c44 278#ifndef CONFIG_USER_ONLY
c36bbb28
AJ		 279
280static inline target_phys_addr_t do_translate_address(target_ulong address, int rw)
281{
282 target_phys_addr_t lladdr;
283
284 lladdr = cpu_mips_translate_address(env, address, rw);
285
286 if (lladdr == -1LL) {
287 cpu_loop_exit();
288 } else {
289 return lladdr;
290 }
291}
292
e7139c44
AJ		 293#define HELPER_LD_ATOMIC(name, insn) \
294target_ulong helper_##name(target_ulong arg, int mem_idx) \
295{ \
c36bbb28 296 env->lladdr = do_translate_address(arg, 0); \
e7139c44
AJ		 297 env->llval = do_##insn(arg, mem_idx); \
298 return env->llval; \
299}
300HELPER_LD_ATOMIC(ll, lw)
301#ifdef TARGET_MIPS64
302HELPER_LD_ATOMIC(lld, ld)
303#endif
304#undef HELPER_LD_ATOMIC
305
306#define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
307target_ulong helper_##name(target_ulong arg1, target_ulong arg2, int mem_idx) \
308{ \
309 target_long tmp; \
310 \
311 if (arg2 & almask) { \
312 env->CP0_BadVAddr = arg2; \
313 helper_raise_exception(EXCP_AdES); \
314 } \
c36bbb28 315 if (do_translate_address(arg2, 1) == env->lladdr) { \
e7139c44
AJ		 316 tmp = do_##ld_insn(arg2, mem_idx); \
317 if (tmp == env->llval) { \
318 do_##st_insn(arg2, arg1, mem_idx); \
319 return 1; \
320 } \
321 } \
322 return 0; \
323}
324HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
325#ifdef TARGET_MIPS64
326HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
327#endif
328#undef HELPER_ST_ATOMIC
329#endif
330
c8c2227e
TS		 331#ifdef TARGET_WORDS_BIGENDIAN
332#define GET_LMASK(v) ((v) & 3)
333#define GET_OFFSET(addr, offset) (addr + (offset))
334#else
335#define GET_LMASK(v) (((v) & 3) ^ 3)
336#define GET_OFFSET(addr, offset) (addr - (offset))
337#endif
338
d9bea114 339target_ulong helper_lwl(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e
TS		 340{
341 target_ulong tmp;
342
0ae43045 343 tmp = do_lbu(arg2, mem_idx);
d9bea114 344 arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
c8c2227e 345
d9bea114 346 if (GET_LMASK(arg2) <= 2) {
0ae43045 347 tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx);
d9bea114 348 arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
c8c2227e
TS		 349 }
350
d9bea114 351 if (GET_LMASK(arg2) <= 1) {
0ae43045 352 tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx);
d9bea114 353 arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
c8c2227e
TS		 354 }
355
d9bea114 356 if (GET_LMASK(arg2) == 0) {
0ae43045 357 tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx);
d9bea114 358 arg1 = (arg1 & 0xFFFFFF00) | tmp;
c8c2227e 359 }
d9bea114 360 return (int32_t)arg1;
c8c2227e
TS		 361}
362
d9bea114 363target_ulong helper_lwr(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e
TS		 364{
365 target_ulong tmp;
366
0ae43045 367 tmp = do_lbu(arg2, mem_idx);
d9bea114 368 arg1 = (arg1 & 0xFFFFFF00) | tmp;
c8c2227e 369
d9bea114 370 if (GET_LMASK(arg2) >= 1) {
0ae43045 371 tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx);
d9bea114 372 arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
c8c2227e
TS		 373 }
374
d9bea114 375 if (GET_LMASK(arg2) >= 2) {
0ae43045 376 tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx);
d9bea114 377 arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
c8c2227e
TS		 378 }
379
d9bea114 380 if (GET_LMASK(arg2) == 3) {
0ae43045 381 tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx);
d9bea114 382 arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
c8c2227e 383 }
d9bea114 384 return (int32_t)arg1;
c8c2227e
TS		 385}
386
d9bea114 387void helper_swl(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e 388{
0ae43045 389 do_sb(arg2, (uint8_t)(arg1 >> 24), mem_idx);
c8c2227e 390
d9bea114 391 if (GET_LMASK(arg2) <= 2)
0ae43045 392 do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
c8c2227e 393
d9bea114 394 if (GET_LMASK(arg2) <= 1)
0ae43045 395 do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
c8c2227e 396
d9bea114 397 if (GET_LMASK(arg2) == 0)
0ae43045 398 do_sb(GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
c8c2227e
TS		 399}
400
d9bea114 401void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e 402{
0ae43045 403 do_sb(arg2, (uint8_t)arg1, mem_idx);
c8c2227e 404
d9bea114 405 if (GET_LMASK(arg2) >= 1)
0ae43045 406 do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
c8c2227e 407
d9bea114 408 if (GET_LMASK(arg2) >= 2)
0ae43045 409 do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
c8c2227e 410
d9bea114 411 if (GET_LMASK(arg2) == 3)
0ae43045 412 do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
c8c2227e
TS		 413}
414
415#if defined(TARGET_MIPS64)
416/* "half" load and stores. We must do the memory access inline,
417 or fault handling won't work. */
418
419#ifdef TARGET_WORDS_BIGENDIAN
420#define GET_LMASK64(v) ((v) & 7)
421#else
422#define GET_LMASK64(v) (((v) & 7) ^ 7)
423#endif
424
d9bea114 425target_ulong helper_ldl(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e
TS		 426{
427 uint64_t tmp;
428
0ae43045 429 tmp = do_lbu(arg2, mem_idx);
d9bea114 430 arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
c8c2227e 431
d9bea114 432 if (GET_LMASK64(arg2) <= 6) {
0ae43045 433 tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx);
d9bea114 434 arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
c8c2227e
TS		 435 }
436
d9bea114 437 if (GET_LMASK64(arg2) <= 5) {
0ae43045 438 tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx);
d9bea114 439 arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
c8c2227e
TS		 440 }
441
d9bea114 442 if (GET_LMASK64(arg2) <= 4) {
0ae43045 443 tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx);
d9bea114 444 arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
c8c2227e
TS		 445 }
446
d9bea114 447 if (GET_LMASK64(arg2) <= 3) {
0ae43045 448 tmp = do_lbu(GET_OFFSET(arg2, 4), mem_idx);
d9bea114 449 arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
c8c2227e
TS		 450 }
451
d9bea114 452 if (GET_LMASK64(arg2) <= 2) {
0ae43045 453 tmp = do_lbu(GET_OFFSET(arg2, 5), mem_idx);
d9bea114 454 arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
c8c2227e
TS		 455 }
456
d9bea114 457 if (GET_LMASK64(arg2) <= 1) {
0ae43045 458 tmp = do_lbu(GET_OFFSET(arg2, 6), mem_idx);
d9bea114 459 arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
c8c2227e
TS		 460 }
461
d9bea114 462 if (GET_LMASK64(arg2) == 0) {
0ae43045 463 tmp = do_lbu(GET_OFFSET(arg2, 7), mem_idx);
d9bea114 464 arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
c8c2227e 465 }
be24bb4f 466
d9bea114 467 return arg1;
c8c2227e
TS		 468}
469
d9bea114 470target_ulong helper_ldr(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e
TS		 471{
472 uint64_t tmp;
473
0ae43045 474 tmp = do_lbu(arg2, mem_idx);
d9bea114 475 arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
c8c2227e 476
d9bea114 477 if (GET_LMASK64(arg2) >= 1) {
0ae43045 478 tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx);
d9bea114 479 arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
c8c2227e
TS		 480 }
481
d9bea114 482 if (GET_LMASK64(arg2) >= 2) {
0ae43045 483 tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx);
d9bea114 484 arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
c8c2227e
TS		 485 }
486
d9bea114 487 if (GET_LMASK64(arg2) >= 3) {
0ae43045 488 tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx);
d9bea114 489 arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
c8c2227e
TS		 490 }
491
d9bea114 492 if (GET_LMASK64(arg2) >= 4) {
0ae43045 493 tmp = do_lbu(GET_OFFSET(arg2, -4), mem_idx);
d9bea114 494 arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
c8c2227e
TS		 495 }
496
d9bea114 497 if (GET_LMASK64(arg2) >= 5) {
0ae43045 498 tmp = do_lbu(GET_OFFSET(arg2, -5), mem_idx);
d9bea114 499 arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
c8c2227e
TS		 500 }
501
d9bea114 502 if (GET_LMASK64(arg2) >= 6) {
0ae43045 503 tmp = do_lbu(GET_OFFSET(arg2, -6), mem_idx);
d9bea114 504 arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
c8c2227e
TS		 505 }
506
d9bea114 507 if (GET_LMASK64(arg2) == 7) {
0ae43045 508 tmp = do_lbu(GET_OFFSET(arg2, -7), mem_idx);
d9bea114 509 arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
c8c2227e 510 }
be24bb4f 511
d9bea114 512 return arg1;
c8c2227e
TS		 513}
514
d9bea114 515void helper_sdl(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e 516{
0ae43045 517 do_sb(arg2, (uint8_t)(arg1 >> 56), mem_idx);
c8c2227e 518
d9bea114 519 if (GET_LMASK64(arg2) <= 6)
0ae43045 520 do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
c8c2227e 521
d9bea114 522 if (GET_LMASK64(arg2) <= 5)
0ae43045 523 do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
c8c2227e 524
d9bea114 525 if (GET_LMASK64(arg2) <= 4)
0ae43045 526 do_sb(GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
c8c2227e 527
d9bea114 528 if (GET_LMASK64(arg2) <= 3)
0ae43045 529 do_sb(GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
c8c2227e 530
d9bea114 531 if (GET_LMASK64(arg2) <= 2)
0ae43045 532 do_sb(GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
c8c2227e 533
d9bea114 534 if (GET_LMASK64(arg2) <= 1)
0ae43045 535 do_sb(GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
c8c2227e 536
d9bea114 537 if (GET_LMASK64(arg2) <= 0)
0ae43045 538 do_sb(GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
c8c2227e
TS		 539}
540
d9bea114 541void helper_sdr(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e 542{
0ae43045 543 do_sb(arg2, (uint8_t)arg1, mem_idx);
c8c2227e 544
d9bea114 545 if (GET_LMASK64(arg2) >= 1)
0ae43045 546 do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
c8c2227e 547
d9bea114 548 if (GET_LMASK64(arg2) >= 2)
0ae43045 549 do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
c8c2227e 550
d9bea114 551 if (GET_LMASK64(arg2) >= 3)
0ae43045 552 do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
c8c2227e 553
d9bea114 554 if (GET_LMASK64(arg2) >= 4)
0ae43045 555 do_sb(GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
c8c2227e 556
d9bea114 557 if (GET_LMASK64(arg2) >= 5)
0ae43045 558 do_sb(GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
c8c2227e 559
d9bea114 560 if (GET_LMASK64(arg2) >= 6)
0ae43045 561 do_sb(GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
c8c2227e 562
d9bea114 563 if (GET_LMASK64(arg2) == 7)
0ae43045 564 do_sb(GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
c8c2227e
TS		 565}
566#endif /* TARGET_MIPS64 */
567
3c824109
NF		 568static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
569
570void helper_lwm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
571{
572 target_ulong base_reglist = reglist & 0xf;
573 target_ulong do_r31 = reglist & 0x10;
574#ifdef CONFIG_USER_ONLY
575#undef ldfun
576#define ldfun ldl_raw
577#else
578 uint32_t (*ldfun)(target_ulong);
579
580 switch (mem_idx)
581 {
582 case 0: ldfun = ldl_kernel; break;
583 case 1: ldfun = ldl_super; break;
584 default:
585 case 2: ldfun = ldl_user; break;
586 }
587#endif
588
589 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
590 target_ulong i;
591
592 for (i = 0; i < base_reglist; i++) {
593 env->active_tc.gpr[multiple_regs[i]] = (target_long) ldfun(addr);
594 addr += 4;
595 }
596 }
597
598 if (do_r31) {
599 env->active_tc.gpr[31] = (target_long) ldfun(addr);
600 }
601}
602
603void helper_swm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
604{
605 target_ulong base_reglist = reglist & 0xf;
606 target_ulong do_r31 = reglist & 0x10;
607#ifdef CONFIG_USER_ONLY
608#undef stfun
609#define stfun stl_raw
610#else
611 void (*stfun)(target_ulong, uint32_t);
612
613 switch (mem_idx)
614 {
615 case 0: stfun = stl_kernel; break;
616 case 1: stfun = stl_super; break;
617 default:
618 case 2: stfun = stl_user; break;
619 }
620#endif
621
622 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
623 target_ulong i;
624
625 for (i = 0; i < base_reglist; i++) {
626 stfun(addr, env->active_tc.gpr[multiple_regs[i]]);
627 addr += 4;
628 }
629 }
630
631 if (do_r31) {
632 stfun(addr, env->active_tc.gpr[31]);
633 }
634}
635
636#if defined(TARGET_MIPS64)
637void helper_ldm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
638{
639 target_ulong base_reglist = reglist & 0xf;
640 target_ulong do_r31 = reglist & 0x10;
641#ifdef CONFIG_USER_ONLY
642#undef ldfun
643#define ldfun ldq_raw
644#else
645 uint64_t (*ldfun)(target_ulong);
646
647 switch (mem_idx)
648 {
649 case 0: ldfun = ldq_kernel; break;
650 case 1: ldfun = ldq_super; break;
651 default:
652 case 2: ldfun = ldq_user; break;
653 }
654#endif
655
656 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
657 target_ulong i;
658
659 for (i = 0; i < base_reglist; i++) {
660 env->active_tc.gpr[multiple_regs[i]] = ldfun(addr);
661 addr += 8;
662 }
663 }
664
665 if (do_r31) {
666 env->active_tc.gpr[31] = ldfun(addr);
667 }
668}
669
670void helper_sdm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
671{
672 target_ulong base_reglist = reglist & 0xf;
673 target_ulong do_r31 = reglist & 0x10;
674#ifdef CONFIG_USER_ONLY
675#undef stfun
676#define stfun stq_raw
677#else
678 void (*stfun)(target_ulong, uint64_t);
679
680 switch (mem_idx)
681 {
682 case 0: stfun = stq_kernel; break;
683 case 1: stfun = stq_super; break;
684 default:
685 case 2: stfun = stq_user; break;
686 }
687#endif
688
689 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
690 target_ulong i;
691
692 for (i = 0; i < base_reglist; i++) {
693 stfun(addr, env->active_tc.gpr[multiple_regs[i]]);
694 addr += 8;
695 }
696 }
697
698 if (do_r31) {
699 stfun(addr, env->active_tc.gpr[31]);
700 }
701}
702#endif
703
0eaef5aa 704#ifndef CONFIG_USER_ONLY
6af0bf9c 705/* CP0 helpers */
c01fccd2 706target_ulong helper_mfc0_mvpcontrol (void)
f1aa6320 707{
be24bb4f 708 return env->mvp->CP0_MVPControl;
f1aa6320
TS		 709}
710
c01fccd2 711target_ulong helper_mfc0_mvpconf0 (void)
f1aa6320 712{
be24bb4f 713 return env->mvp->CP0_MVPConf0;
f1aa6320
TS		 714}
715
c01fccd2 716target_ulong helper_mfc0_mvpconf1 (void)
f1aa6320 717{
be24bb4f 718 return env->mvp->CP0_MVPConf1;
f1aa6320
TS		 719}
720
c01fccd2 721target_ulong helper_mfc0_random (void)
6af0bf9c 722{
be24bb4f 723 return (int32_t)cpu_mips_get_random(env);
873eb012 724}
6af0bf9c 725
c01fccd2 726target_ulong helper_mfc0_tcstatus (void)
f1aa6320 727{
b5dc7732 728 return env->active_tc.CP0_TCStatus;
f1aa6320
TS		 729}
730
c01fccd2 731target_ulong helper_mftc0_tcstatus(void)
f1aa6320
TS		 732{
733 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
734
b5dc7732
TS		 735 if (other_tc == env->current_tc)
736 return env->active_tc.CP0_TCStatus;
737 else
738 return env->tcs[other_tc].CP0_TCStatus;
f1aa6320
TS		 739}
740
c01fccd2 741target_ulong helper_mfc0_tcbind (void)
f1aa6320 742{
b5dc7732 743 return env->active_tc.CP0_TCBind;
f1aa6320
TS		 744}
745
c01fccd2 746target_ulong helper_mftc0_tcbind(void)
f1aa6320
TS		 747{
748 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
749
b5dc7732
TS		 750 if (other_tc == env->current_tc)
751 return env->active_tc.CP0_TCBind;
752 else
753 return env->tcs[other_tc].CP0_TCBind;
f1aa6320
TS		 754}
755
c01fccd2 756target_ulong helper_mfc0_tcrestart (void)
f1aa6320 757{
b5dc7732 758 return env->active_tc.PC;
f1aa6320
TS		 759}
760
c01fccd2 761target_ulong helper_mftc0_tcrestart(void)
f1aa6320
TS		 762{
763 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
764
b5dc7732
TS		 765 if (other_tc == env->current_tc)
766 return env->active_tc.PC;
767 else
768 return env->tcs[other_tc].PC;
f1aa6320
TS		 769}
770
c01fccd2 771target_ulong helper_mfc0_tchalt (void)
f1aa6320 772{
b5dc7732 773 return env->active_tc.CP0_TCHalt;
f1aa6320
TS		 774}
775
c01fccd2 776target_ulong helper_mftc0_tchalt(void)
f1aa6320
TS		 777{
778 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
779
b5dc7732
TS		 780 if (other_tc == env->current_tc)
781 return env->active_tc.CP0_TCHalt;
782 else
783 return env->tcs[other_tc].CP0_TCHalt;
f1aa6320
TS		 784}
785
c01fccd2 786target_ulong helper_mfc0_tccontext (void)
f1aa6320 787{
b5dc7732 788 return env->active_tc.CP0_TCContext;
f1aa6320
TS		 789}
790
c01fccd2 791target_ulong helper_mftc0_tccontext(void)
f1aa6320
TS		 792{
793 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
794
b5dc7732
TS		 795 if (other_tc == env->current_tc)
796 return env->active_tc.CP0_TCContext;
797 else
798 return env->tcs[other_tc].CP0_TCContext;
f1aa6320
TS		 799}
800
c01fccd2 801target_ulong helper_mfc0_tcschedule (void)
f1aa6320 802{
b5dc7732 803 return env->active_tc.CP0_TCSchedule;
f1aa6320
TS		 804}
805
c01fccd2 806target_ulong helper_mftc0_tcschedule(void)
f1aa6320
TS		 807{
808 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
809
b5dc7732
TS		 810 if (other_tc == env->current_tc)
811 return env->active_tc.CP0_TCSchedule;
812 else
813 return env->tcs[other_tc].CP0_TCSchedule;
f1aa6320
TS		 814}
815
c01fccd2 816target_ulong helper_mfc0_tcschefback (void)
f1aa6320 817{
b5dc7732 818 return env->active_tc.CP0_TCScheFBack;
f1aa6320
TS		 819}
820
c01fccd2 821target_ulong helper_mftc0_tcschefback(void)
f1aa6320
TS		 822{
823 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
824
b5dc7732
TS		 825 if (other_tc == env->current_tc)
826 return env->active_tc.CP0_TCScheFBack;
827 else
828 return env->tcs[other_tc].CP0_TCScheFBack;
f1aa6320
TS		 829}
830
c01fccd2 831target_ulong helper_mfc0_count (void)
873eb012 832{
be24bb4f 833 return (int32_t)cpu_mips_get_count(env);
6af0bf9c
FB		 834}
835
c01fccd2 836target_ulong helper_mftc0_entryhi(void)
f1aa6320
TS		 837{
838 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
b5dc7732 839 int32_t tcstatus;
f1aa6320 840
b5dc7732
TS		 841 if (other_tc == env->current_tc)
842 tcstatus = env->active_tc.CP0_TCStatus;
843 else
844 tcstatus = env->tcs[other_tc].CP0_TCStatus;
845
846 return (env->CP0_EntryHi & ~0xff) | (tcstatus & 0xff);
f1aa6320
TS		 847}
848
c01fccd2 849target_ulong helper_mftc0_status(void)
f1aa6320
TS		 850{
851 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1a3fd9c3 852 target_ulong t0;
b5dc7732
TS		 853 int32_t tcstatus;
854
855 if (other_tc == env->current_tc)
856 tcstatus = env->active_tc.CP0_TCStatus;
857 else
858 tcstatus = env->tcs[other_tc].CP0_TCStatus;
f1aa6320 859
be24bb4f
TS		 860 t0 = env->CP0_Status & ~0xf1000018;
861 t0 |= tcstatus & (0xf << CP0TCSt_TCU0);
862 t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
863 t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
864
865 return t0;
f1aa6320
TS		 866}
867
c01fccd2 868target_ulong helper_mfc0_lladdr (void)
f1aa6320 869{
2a6e32dd 870 return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
f1aa6320
TS		 871}
872
c01fccd2 873target_ulong helper_mfc0_watchlo (uint32_t sel)
f1aa6320 874{
be24bb4f 875 return (int32_t)env->CP0_WatchLo[sel];
f1aa6320
TS		 876}
877
c01fccd2 878target_ulong helper_mfc0_watchhi (uint32_t sel)
f1aa6320 879{
be24bb4f 880 return env->CP0_WatchHi[sel];
f1aa6320
TS		 881}
882
c01fccd2 883target_ulong helper_mfc0_debug (void)
f1aa6320 884{
1a3fd9c3 885 target_ulong t0 = env->CP0_Debug;
f1aa6320 886 if (env->hflags & MIPS_HFLAG_DM)
be24bb4f
TS		 887 t0 |= 1 << CP0DB_DM;
888
889 return t0;
f1aa6320
TS		 890}
891
c01fccd2 892target_ulong helper_mftc0_debug(void)
f1aa6320
TS		 893{
894 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
b5dc7732
TS		 895 int32_t tcstatus;
896
897 if (other_tc == env->current_tc)
898 tcstatus = env->active_tc.CP0_Debug_tcstatus;
899 else
900 tcstatus = env->tcs[other_tc].CP0_Debug_tcstatus;
f1aa6320
TS		 901
902 /* XXX: Might be wrong, check with EJTAG spec. */
be24bb4f 903 return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
b5dc7732 904 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
f1aa6320
TS		 905}
906
907#if defined(TARGET_MIPS64)
c01fccd2 908target_ulong helper_dmfc0_tcrestart (void)
f1aa6320 909{
b5dc7732 910 return env->active_tc.PC;
f1aa6320
TS		 911}
912
c01fccd2 913target_ulong helper_dmfc0_tchalt (void)
f1aa6320 914{
b5dc7732 915 return env->active_tc.CP0_TCHalt;
f1aa6320
TS		 916}
917
c01fccd2 918target_ulong helper_dmfc0_tccontext (void)
f1aa6320 919{
b5dc7732 920 return env->active_tc.CP0_TCContext;
f1aa6320
TS		 921}
922
c01fccd2 923target_ulong helper_dmfc0_tcschedule (void)
f1aa6320 924{
b5dc7732 925 return env->active_tc.CP0_TCSchedule;
f1aa6320
TS		 926}
927
c01fccd2 928target_ulong helper_dmfc0_tcschefback (void)
f1aa6320 929{
b5dc7732 930 return env->active_tc.CP0_TCScheFBack;
f1aa6320
TS		 931}
932
c01fccd2 933target_ulong helper_dmfc0_lladdr (void)
f1aa6320 934{
2a6e32dd 935 return env->lladdr >> env->CP0_LLAddr_shift;
f1aa6320
TS		 936}
937
c01fccd2 938target_ulong helper_dmfc0_watchlo (uint32_t sel)
f1aa6320 939{
be24bb4f 940 return env->CP0_WatchLo[sel];
f1aa6320
TS		 941}
942#endif /* TARGET_MIPS64 */
943
d9bea114 944void helper_mtc0_index (target_ulong arg1)
f1aa6320
TS		 945{
946 int num = 1;
947 unsigned int tmp = env->tlb->nb_tlb;
948
949 do {
950 tmp >>= 1;
951 num <<= 1;
952 } while (tmp);
d9bea114 953 env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
f1aa6320
TS		 954}
955
d9bea114 956void helper_mtc0_mvpcontrol (target_ulong arg1)
f1aa6320
TS		 957{
958 uint32_t mask = 0;
959 uint32_t newval;
960
961 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
962 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
963 (1 << CP0MVPCo_EVP);
964 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
965 mask |= (1 << CP0MVPCo_STLB);
d9bea114 966 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
f1aa6320
TS		 967
968 // TODO: Enable/disable shared TLB, enable/disable VPEs.
969
970 env->mvp->CP0_MVPControl = newval;
971}
972
d9bea114 973void helper_mtc0_vpecontrol (target_ulong arg1)
f1aa6320
TS		 974{
975 uint32_t mask;
976 uint32_t newval;
977
978 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
979 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
d9bea114 980 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
f1aa6320
TS		 981
982 /* Yield scheduler intercept not implemented. */
983 /* Gating storage scheduler intercept not implemented. */
984
985 // TODO: Enable/disable TCs.
986
987 env->CP0_VPEControl = newval;
988}
989
d9bea114 990void helper_mtc0_vpeconf0 (target_ulong arg1)
f1aa6320
TS		 991{
992 uint32_t mask = 0;
993 uint32_t newval;
994
995 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
996 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
997 mask |= (0xff << CP0VPEC0_XTC);
998 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
999 }
d9bea114 1000 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
f1aa6320
TS		 1001
1002 // TODO: TC exclusive handling due to ERL/EXL.
1003
1004 env->CP0_VPEConf0 = newval;
1005}
1006
d9bea114 1007void helper_mtc0_vpeconf1 (target_ulong arg1)
f1aa6320
TS		 1008{
1009 uint32_t mask = 0;
1010 uint32_t newval;
1011
1012 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1013 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1014 (0xff << CP0VPEC1_NCP1);
d9bea114 1015 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
f1aa6320
TS		 1016
1017 /* UDI not implemented. */
1018 /* CP2 not implemented. */
1019
1020 // TODO: Handle FPU (CP1) binding.
1021
1022 env->CP0_VPEConf1 = newval;
1023}
1024
d9bea114 1025void helper_mtc0_yqmask (target_ulong arg1)
f1aa6320
TS		 1026{
1027 /* Yield qualifier inputs not implemented. */
1028 env->CP0_YQMask = 0x00000000;
1029}
1030
d9bea114 1031void helper_mtc0_vpeopt (target_ulong arg1)
f1aa6320 1032{
d9bea114 1033 env->CP0_VPEOpt = arg1 & 0x0000ffff;
f1aa6320
TS		 1034}
1035
d9bea114 1036void helper_mtc0_entrylo0 (target_ulong arg1)
f1aa6320
TS		 1037{
1038 /* Large physaddr (PABITS) not implemented */
1039 /* 1k pages not implemented */
d9bea114 1040 env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
f1aa6320
TS		 1041}
1042
d9bea114 1043void helper_mtc0_tcstatus (target_ulong arg1)
f1aa6320
TS		 1044{
1045 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1046 uint32_t newval;
1047
d9bea114 1048 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
f1aa6320
TS		 1049
1050 // TODO: Sync with CP0_Status.
1051
b5dc7732 1052 env->active_tc.CP0_TCStatus = newval;
f1aa6320
TS		 1053}
1054
d9bea114 1055void helper_mttc0_tcstatus (target_ulong arg1)
f1aa6320
TS		 1056{
1057 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1058
1059 // TODO: Sync with CP0_Status.
1060
b5dc7732 1061 if (other_tc == env->current_tc)
d9bea114 1062 env->active_tc.CP0_TCStatus = arg1;
b5dc7732 1063 else
d9bea114 1064 env->tcs[other_tc].CP0_TCStatus = arg1;
f1aa6320
TS		 1065}
1066
d9bea114 1067void helper_mtc0_tcbind (target_ulong arg1)
f1aa6320
TS		 1068{
1069 uint32_t mask = (1 << CP0TCBd_TBE);
1070 uint32_t newval;
1071
1072 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1073 mask |= (1 << CP0TCBd_CurVPE);
d9bea114 1074 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
b5dc7732 1075 env->active_tc.CP0_TCBind = newval;
f1aa6320
TS		 1076}
1077
d9bea114 1078void helper_mttc0_tcbind (target_ulong arg1)
f1aa6320
TS		 1079{
1080 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1081 uint32_t mask = (1 << CP0TCBd_TBE);
1082 uint32_t newval;
1083
1084 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1085 mask |= (1 << CP0TCBd_CurVPE);
b5dc7732 1086 if (other_tc == env->current_tc) {
d9bea114 1087 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
b5dc7732
TS		 1088 env->active_tc.CP0_TCBind = newval;
1089 } else {
d9bea114 1090 newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
b5dc7732
TS		 1091 env->tcs[other_tc].CP0_TCBind = newval;
1092 }
f1aa6320
TS		 1093}
1094
d9bea114 1095void helper_mtc0_tcrestart (target_ulong arg1)
f1aa6320 1096{
d9bea114 1097 env->active_tc.PC = arg1;
b5dc7732 1098 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
5499b6ff 1099 env->lladdr = 0ULL;
f1aa6320
TS		 1100 /* MIPS16 not implemented. */
1101}
1102
d9bea114 1103void helper_mttc0_tcrestart (target_ulong arg1)
f1aa6320
TS		 1104{
1105 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1106
b5dc7732 1107 if (other_tc == env->current_tc) {
d9bea114 1108 env->active_tc.PC = arg1;
b5dc7732 1109 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
5499b6ff 1110 env->lladdr = 0ULL;
b5dc7732
TS		 1111 /* MIPS16 not implemented. */
1112 } else {
d9bea114 1113 env->tcs[other_tc].PC = arg1;
b5dc7732 1114 env->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
5499b6ff 1115 env->lladdr = 0ULL;
b5dc7732
TS		 1116 /* MIPS16 not implemented. */
1117 }
f1aa6320
TS		 1118}
1119
d9bea114 1120void helper_mtc0_tchalt (target_ulong arg1)
f1aa6320 1121{
d9bea114 1122 env->active_tc.CP0_TCHalt = arg1 & 0x1;
f1aa6320
TS		 1123
1124 // TODO: Halt TC / Restart (if allocated+active) TC.
1125}
1126
d9bea114 1127void helper_mttc0_tchalt (target_ulong arg1)
f1aa6320
TS		 1128{
1129 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1130
1131 // TODO: Halt TC / Restart (if allocated+active) TC.
1132
b5dc7732 1133 if (other_tc == env->current_tc)
d9bea114 1134 env->active_tc.CP0_TCHalt = arg1;
b5dc7732 1135 else
d9bea114 1136 env->tcs[other_tc].CP0_TCHalt = arg1;
f1aa6320
TS		 1137}
1138
d9bea114 1139void helper_mtc0_tccontext (target_ulong arg1)
f1aa6320 1140{
d9bea114 1141 env->active_tc.CP0_TCContext = arg1;
f1aa6320
TS		 1142}
1143
d9bea114 1144void helper_mttc0_tccontext (target_ulong arg1)
f1aa6320
TS		 1145{
1146 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1147
b5dc7732 1148 if (other_tc == env->current_tc)
d9bea114 1149 env->active_tc.CP0_TCContext = arg1;
b5dc7732 1150 else
d9bea114 1151 env->tcs[other_tc].CP0_TCContext = arg1;
f1aa6320
TS		 1152}
1153
d9bea114 1154void helper_mtc0_tcschedule (target_ulong arg1)
f1aa6320 1155{
d9bea114 1156 env->active_tc.CP0_TCSchedule = arg1;
f1aa6320
TS		 1157}
1158
d9bea114 1159void helper_mttc0_tcschedule (target_ulong arg1)
f1aa6320
TS		 1160{
1161 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1162
b5dc7732 1163 if (other_tc == env->current_tc)
d9bea114 1164 env->active_tc.CP0_TCSchedule = arg1;
b5dc7732 1165 else
d9bea114 1166 env->tcs[other_tc].CP0_TCSchedule = arg1;
f1aa6320
TS		 1167}
1168
d9bea114 1169void helper_mtc0_tcschefback (target_ulong arg1)
f1aa6320 1170{
d9bea114 1171 env->active_tc.CP0_TCScheFBack = arg1;
f1aa6320
TS		 1172}
1173
d9bea114 1174void helper_mttc0_tcschefback (target_ulong arg1)
f1aa6320
TS		 1175{
1176 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1177
b5dc7732 1178 if (other_tc == env->current_tc)
d9bea114 1179 env->active_tc.CP0_TCScheFBack = arg1;
b5dc7732 1180 else
d9bea114 1181 env->tcs[other_tc].CP0_TCScheFBack = arg1;
f1aa6320
TS		 1182}
1183
d9bea114 1184void helper_mtc0_entrylo1 (target_ulong arg1)
f1aa6320
TS		 1185{
1186 /* Large physaddr (PABITS) not implemented */
1187 /* 1k pages not implemented */
d9bea114 1188 env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
f1aa6320
TS		 1189}
1190
d9bea114 1191void helper_mtc0_context (target_ulong arg1)
f1aa6320 1192{
d9bea114 1193 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
f1aa6320
TS		 1194}
1195
d9bea114 1196void helper_mtc0_pagemask (target_ulong arg1)
f1aa6320
TS		 1197{
1198 /* 1k pages not implemented */
d9bea114 1199 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
f1aa6320
TS		 1200}
1201
d9bea114 1202void helper_mtc0_pagegrain (target_ulong arg1)
f1aa6320
TS		 1203{
1204 /* SmartMIPS not implemented */
1205 /* Large physaddr (PABITS) not implemented */
1206 /* 1k pages not implemented */
1207 env->CP0_PageGrain = 0;
1208}
1209
d9bea114 1210void helper_mtc0_wired (target_ulong arg1)
f1aa6320 1211{
d9bea114 1212 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
f1aa6320
TS		 1213}
1214
d9bea114 1215void helper_mtc0_srsconf0 (target_ulong arg1)
f1aa6320 1216{
d9bea114 1217 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
f1aa6320
TS		 1218}
1219
d9bea114 1220void helper_mtc0_srsconf1 (target_ulong arg1)
f1aa6320 1221{
d9bea114 1222 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
f1aa6320
TS		 1223}
1224
d9bea114 1225void helper_mtc0_srsconf2 (target_ulong arg1)
f1aa6320 1226{
d9bea114 1227 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
f1aa6320
TS		 1228}
1229
d9bea114 1230void helper_mtc0_srsconf3 (target_ulong arg1)
f1aa6320 1231{
d9bea114 1232 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
f1aa6320
TS		 1233}
1234
d9bea114 1235void helper_mtc0_srsconf4 (target_ulong arg1)
f1aa6320 1236{
d9bea114 1237 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
f1aa6320
TS		 1238}
1239
d9bea114 1240void helper_mtc0_hwrena (target_ulong arg1)
f1aa6320 1241{
d9bea114 1242 env->CP0_HWREna = arg1 & 0x0000000F;
f1aa6320
TS		 1243}
1244
d9bea114 1245void helper_mtc0_count (target_ulong arg1)
f1aa6320 1246{
d9bea114 1247 cpu_mips_store_count(env, arg1);
f1aa6320
TS		 1248}
1249
d9bea114 1250void helper_mtc0_entryhi (target_ulong arg1)
f1aa6320
TS		 1251{
1252 target_ulong old, val;
1253
1254 /* 1k pages not implemented */
d9bea114 1255 val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
f1aa6320
TS		 1256#if defined(TARGET_MIPS64)
1257 val &= env->SEGMask;
1258#endif
1259 old = env->CP0_EntryHi;
1260 env->CP0_EntryHi = val;
1261 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
b5dc7732
TS		 1262 uint32_t tcst = env->active_tc.CP0_TCStatus & ~0xff;
1263 env->active_tc.CP0_TCStatus = tcst | (val & 0xff);
f1aa6320
TS		 1264 }
1265 /* If the ASID changes, flush qemu's TLB. */
1266 if ((old & 0xFF) != (val & 0xFF))
1267 cpu_mips_tlb_flush(env, 1);
1268}
1269
d9bea114 1270void helper_mttc0_entryhi(target_ulong arg1)
f1aa6320
TS		 1271{
1272 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
b5dc7732 1273 int32_t tcstatus;
f1aa6320 1274
d9bea114 1275 env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (arg1 & ~0xff);
b5dc7732 1276 if (other_tc == env->current_tc) {
d9bea114 1277 tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (arg1 & 0xff);
b5dc7732
TS		 1278 env->active_tc.CP0_TCStatus = tcstatus;
1279 } else {
d9bea114 1280 tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (arg1 & 0xff);
b5dc7732
TS		 1281 env->tcs[other_tc].CP0_TCStatus = tcstatus;
1282 }
f1aa6320
TS		 1283}
1284
d9bea114 1285void helper_mtc0_compare (target_ulong arg1)
f1aa6320 1286{
d9bea114 1287 cpu_mips_store_compare(env, arg1);
f1aa6320
TS		 1288}
1289
d9bea114 1290void helper_mtc0_status (target_ulong arg1)
f1aa6320
TS		 1291{
1292 uint32_t val, old;
1293 uint32_t mask = env->CP0_Status_rw_bitmask;
1294
d9bea114 1295 val = arg1 & mask;
f1aa6320
TS		 1296 old = env->CP0_Status;
1297 env->CP0_Status = (env->CP0_Status & ~mask) | val;
1298 compute_hflags(env);
c01fccd2
AJ		 1299 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1300 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1301 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1302 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1303 env->CP0_Cause);
1304 switch (env->hflags & MIPS_HFLAG_KSU) {
1305 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1306 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1307 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1308 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
31e3104f 1309 }
c01fccd2 1310 }
f1aa6320
TS		 1311 cpu_mips_update_irq(env);
1312}
1313
d9bea114 1314void helper_mttc0_status(target_ulong arg1)
f1aa6320
TS		 1315{
1316 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
b5dc7732 1317 int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus;
f1aa6320 1318
d9bea114
AJ		 1319 env->CP0_Status = arg1 & ~0xf1000018;
1320 tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (arg1 & (0xf << CP0St_CU0));
1321 tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((arg1 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
1322 tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((arg1 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
b5dc7732
TS		 1323 if (other_tc == env->current_tc)
1324 env->active_tc.CP0_TCStatus = tcstatus;
1325 else
1326 env->tcs[other_tc].CP0_TCStatus = tcstatus;
f1aa6320
TS		 1327}
1328
d9bea114 1329void helper_mtc0_intctl (target_ulong arg1)
f1aa6320
TS		 1330{
1331 /* vectored interrupts not implemented, no performance counters. */
d9bea114 1332 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (arg1 & 0x000002e0);
f1aa6320
TS		 1333}
1334
d9bea114 1335void helper_mtc0_srsctl (target_ulong arg1)
f1aa6320
TS		 1336{
1337 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
d9bea114 1338 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
f1aa6320
TS		 1339}
1340
d9bea114 1341void helper_mtc0_cause (target_ulong arg1)
f1aa6320
TS		 1342{
1343 uint32_t mask = 0x00C00300;
1344 uint32_t old = env->CP0_Cause;
1345
1346 if (env->insn_flags & ISA_MIPS32R2)
1347 mask |= 1 << CP0Ca_DC;
1348
d9bea114 1349 env->CP0_Cause = (env->CP0_Cause & ~mask) | (arg1 & mask);
f1aa6320
TS		 1350
1351 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
1352 if (env->CP0_Cause & (1 << CP0Ca_DC))
1353 cpu_mips_stop_count(env);
1354 else
1355 cpu_mips_start_count(env);
1356 }
1357
1358 /* Handle the software interrupt as an hardware one, as they
1359 are very similar */
d9bea114 1360 if (arg1 & CP0Ca_IP_mask) {
f1aa6320
TS		 1361 cpu_mips_update_irq(env);
1362 }
1363}
1364
d9bea114 1365void helper_mtc0_ebase (target_ulong arg1)
f1aa6320
TS		 1366{
1367 /* vectored interrupts not implemented */
1368 /* Multi-CPU not implemented */
d9bea114 1369 env->CP0_EBase = 0x80000000 | (arg1 & 0x3FFFF000);
f1aa6320
TS		 1370}
1371
d9bea114 1372void helper_mtc0_config0 (target_ulong arg1)
f1aa6320 1373{
d9bea114 1374 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
f1aa6320
TS		 1375}
1376
d9bea114 1377void helper_mtc0_config2 (target_ulong arg1)
f1aa6320
TS		 1378{
1379 /* tertiary/secondary caches not implemented */
1380 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1381}
1382
2a6e32dd
AJ		 1383void helper_mtc0_lladdr (target_ulong arg1)
1384{
1385 target_long mask = env->CP0_LLAddr_rw_bitmask;
1386 arg1 = arg1 << env->CP0_LLAddr_shift;
1387 env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1388}
1389
d9bea114 1390void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel)
f1aa6320
TS		 1391{
1392 /* Watch exceptions for instructions, data loads, data stores
1393 not implemented. */
d9bea114 1394 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
f1aa6320
TS		 1395}
1396
d9bea114 1397void helper_mtc0_watchhi (target_ulong arg1, uint32_t sel)
f1aa6320 1398{
d9bea114
AJ		 1399 env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1400 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
f1aa6320
TS		 1401}
1402
d9bea114 1403void helper_mtc0_xcontext (target_ulong arg1)
f1aa6320
TS		 1404{
1405 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
d9bea114 1406 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
f1aa6320
TS		 1407}
1408
d9bea114 1409void helper_mtc0_framemask (target_ulong arg1)
f1aa6320 1410{
d9bea114 1411 env->CP0_Framemask = arg1; /* XXX */
f1aa6320
TS		 1412}
1413
d9bea114 1414void helper_mtc0_debug (target_ulong arg1)
f1aa6320 1415{
d9bea114
AJ		 1416 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1417 if (arg1 & (1 << CP0DB_DM))
f1aa6320
TS		 1418 env->hflags |= MIPS_HFLAG_DM;
1419 else
1420 env->hflags &= ~MIPS_HFLAG_DM;
1421}
1422
d9bea114 1423void helper_mttc0_debug(target_ulong arg1)
f1aa6320
TS		 1424{
1425 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
d9bea114 1426 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
f1aa6320
TS		 1427
1428 /* XXX: Might be wrong, check with EJTAG spec. */
b5dc7732
TS		 1429 if (other_tc == env->current_tc)
1430 env->active_tc.CP0_Debug_tcstatus = val;
1431 else
1432 env->tcs[other_tc].CP0_Debug_tcstatus = val;
f1aa6320 1433 env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
d9bea114 1434 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
f1aa6320
TS		 1435}
1436
d9bea114 1437void helper_mtc0_performance0 (target_ulong arg1)
f1aa6320 1438{
d9bea114 1439 env->CP0_Performance0 = arg1 & 0x000007ff;
f1aa6320
TS		 1440}
1441
d9bea114 1442void helper_mtc0_taglo (target_ulong arg1)
f1aa6320 1443{
d9bea114 1444 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
f1aa6320
TS		 1445}
1446
d9bea114 1447void helper_mtc0_datalo (target_ulong arg1)
f1aa6320 1448{
d9bea114 1449 env->CP0_DataLo = arg1; /* XXX */
f1aa6320
TS		 1450}
1451
d9bea114 1452void helper_mtc0_taghi (target_ulong arg1)
f1aa6320 1453{
d9bea114 1454 env->CP0_TagHi = arg1; /* XXX */
f1aa6320
TS		 1455}
1456
d9bea114 1457void helper_mtc0_datahi (target_ulong arg1)
f1aa6320 1458{
d9bea114 1459 env->CP0_DataHi = arg1; /* XXX */
f1aa6320
TS		 1460}
1461
f1aa6320 1462/* MIPS MT functions */
c01fccd2 1463target_ulong helper_mftgpr(uint32_t sel)
f1aa6320
TS		 1464{
1465 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1466
b5dc7732
TS		 1467 if (other_tc == env->current_tc)
1468 return env->active_tc.gpr[sel];
1469 else
1470 return env->tcs[other_tc].gpr[sel];
f1aa6320
TS		 1471}
1472
c01fccd2 1473target_ulong helper_mftlo(uint32_t sel)
f1aa6320
TS		 1474{
1475 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1476
b5dc7732
TS		 1477 if (other_tc == env->current_tc)
1478 return env->active_tc.LO[sel];
1479 else
1480 return env->tcs[other_tc].LO[sel];
f1aa6320
TS		 1481}
1482
c01fccd2 1483target_ulong helper_mfthi(uint32_t sel)
f1aa6320
TS		 1484{
1485 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1486
b5dc7732
TS		 1487 if (other_tc == env->current_tc)
1488 return env->active_tc.HI[sel];
1489 else
1490 return env->tcs[other_tc].HI[sel];
f1aa6320
TS		 1491}
1492
c01fccd2 1493target_ulong helper_mftacx(uint32_t sel)
f1aa6320
TS		 1494{
1495 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1496
b5dc7732
TS		 1497 if (other_tc == env->current_tc)
1498 return env->active_tc.ACX[sel];
1499 else
1500 return env->tcs[other_tc].ACX[sel];
f1aa6320
TS		 1501}
1502
c01fccd2 1503target_ulong helper_mftdsp(void)
f1aa6320
TS		 1504{
1505 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1506
b5dc7732
TS		 1507 if (other_tc == env->current_tc)
1508 return env->active_tc.DSPControl;
1509 else
1510 return env->tcs[other_tc].DSPControl;
f1aa6320 1511}
6af0bf9c 1512
d9bea114 1513void helper_mttgpr(target_ulong arg1, uint32_t sel)
f1aa6320
TS		 1514{
1515 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1516
b5dc7732 1517 if (other_tc == env->current_tc)
d9bea114 1518 env->active_tc.gpr[sel] = arg1;
b5dc7732 1519 else
d9bea114 1520 env->tcs[other_tc].gpr[sel] = arg1;
f1aa6320
TS		 1521}
1522
d9bea114 1523void helper_mttlo(target_ulong arg1, uint32_t sel)
f1aa6320
TS		 1524{
1525 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1526
b5dc7732 1527 if (other_tc == env->current_tc)
d9bea114 1528 env->active_tc.LO[sel] = arg1;
b5dc7732 1529 else
d9bea114 1530 env->tcs[other_tc].LO[sel] = arg1;
f1aa6320
TS		 1531}
1532
d9bea114 1533void helper_mtthi(target_ulong arg1, uint32_t sel)
f1aa6320
TS		 1534{
1535 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1536
b5dc7732 1537 if (other_tc == env->current_tc)
d9bea114 1538 env->active_tc.HI[sel] = arg1;
b5dc7732 1539 else
d9bea114 1540 env->tcs[other_tc].HI[sel] = arg1;
f1aa6320
TS		 1541}
1542
d9bea114 1543void helper_mttacx(target_ulong arg1, uint32_t sel)
f1aa6320
TS		 1544{
1545 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1546
b5dc7732 1547 if (other_tc == env->current_tc)
d9bea114 1548 env->active_tc.ACX[sel] = arg1;
b5dc7732 1549 else
d9bea114 1550 env->tcs[other_tc].ACX[sel] = arg1;
f1aa6320
TS		 1551}
1552
d9bea114 1553void helper_mttdsp(target_ulong arg1)
f1aa6320
TS		 1554{
1555 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1556
b5dc7732 1557 if (other_tc == env->current_tc)
d9bea114 1558 env->active_tc.DSPControl = arg1;
b5dc7732 1559 else
d9bea114 1560 env->tcs[other_tc].DSPControl = arg1;
f1aa6320
TS		 1561}
1562
1563/* MIPS MT functions */
d9bea114 1564target_ulong helper_dmt(target_ulong arg1)
f1aa6320
TS		 1565{
1566 // TODO
d9bea114
AJ		 1567 arg1 = 0;
1568 // rt = arg1
be24bb4f 1569
d9bea114 1570 return arg1;
f1aa6320
TS		 1571}
1572
d9bea114 1573target_ulong helper_emt(target_ulong arg1)
f1aa6320
TS		 1574{
1575 // TODO
d9bea114
AJ		 1576 arg1 = 0;
1577 // rt = arg1
be24bb4f 1578
d9bea114 1579 return arg1;
f1aa6320
TS		 1580}
1581
d9bea114 1582target_ulong helper_dvpe(target_ulong arg1)
f1aa6320
TS		 1583{
1584 // TODO
d9bea114
AJ		 1585 arg1 = 0;
1586 // rt = arg1
be24bb4f 1587
d9bea114 1588 return arg1;
f1aa6320
TS		 1589}
1590
d9bea114 1591target_ulong helper_evpe(target_ulong arg1)
f1aa6320
TS		 1592{
1593 // TODO
d9bea114
AJ		 1594 arg1 = 0;
1595 // rt = arg1
be24bb4f 1596
d9bea114 1597 return arg1;
f1aa6320 1598}
f9480ffc 1599#endif /* !CONFIG_USER_ONLY */
f1aa6320 1600
d9bea114 1601void helper_fork(target_ulong arg1, target_ulong arg2)
f1aa6320 1602{
d9bea114
AJ		 1603 // arg1 = rt, arg2 = rs
1604 arg1 = 0;
f1aa6320
TS		 1605 // TODO: store to TC register
1606}
1607
d9bea114 1608target_ulong helper_yield(target_ulong arg1)
f1aa6320 1609{
d9bea114 1610 if (arg1 < 0) {
f1aa6320 1611 /* No scheduling policy implemented. */
d9bea114 1612 if (arg1 != -2) {
f1aa6320 1613 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
b5dc7732 1614 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
f1aa6320
TS		 1615 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1616 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
c01fccd2 1617 helper_raise_exception(EXCP_THREAD);
f1aa6320
TS		 1618 }
1619 }
d9bea114 1620 } else if (arg1 == 0) {
6958549d 1621 if (0 /* TODO: TC underflow */) {
f1aa6320 1622 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
c01fccd2 1623 helper_raise_exception(EXCP_THREAD);
f1aa6320
TS		 1624 } else {
1625 // TODO: Deallocate TC
1626 }
d9bea114 1627 } else if (arg1 > 0) {
f1aa6320
TS		 1628 /* Yield qualifier inputs not implemented. */
1629 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1630 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
c01fccd2 1631 helper_raise_exception(EXCP_THREAD);
f1aa6320 1632 }
be24bb4f 1633 return env->CP0_YQMask;
f1aa6320
TS		 1634}
1635
f1aa6320 1636#ifndef CONFIG_USER_ONLY
6af0bf9c 1637/* TLB management */
814b9a47
TS		 1638void cpu_mips_tlb_flush (CPUState *env, int flush_global)
1639{
1640 /* Flush qemu's TLB and discard all shadowed entries. */
1641 tlb_flush (env, flush_global);
ead9360e 1642 env->tlb->tlb_in_use = env->tlb->nb_tlb;
814b9a47
TS		 1643}
1644
29929e34 1645static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
814b9a47
TS		 1646{
1647 /* Discard entries from env->tlb[first] onwards. */
ead9360e
TS		 1648 while (env->tlb->tlb_in_use > first) {
1649 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
814b9a47
TS		 1650 }
1651}
1652
29929e34 1653static void r4k_fill_tlb (int idx)
6af0bf9c 1654{
c227f099 1655 r4k_tlb_t *tlb;
6af0bf9c
FB		 1656
1657 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
ead9360e 1658 tlb = &env->tlb->mmu.r4k.tlb[idx];
f2e9ebef 1659 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
d26bc211 1660#if defined(TARGET_MIPS64)
e034e2c3 1661 tlb->VPN &= env->SEGMask;
100ce988 1662#endif
98c1b82b 1663 tlb->ASID = env->CP0_EntryHi & 0xFF;
3b1c8be4 1664 tlb->PageMask = env->CP0_PageMask;
6af0bf9c 1665 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
98c1b82b
PB		 1666 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1667 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1668 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
6af0bf9c 1669 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
98c1b82b
PB		 1670 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1671 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1672 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
6af0bf9c
FB		 1673 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1674}
1675
c01fccd2 1676void r4k_helper_tlbwi (void)
6af0bf9c 1677{
bbc0d79c
AJ		 1678 int idx;
1679
1680 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1681
814b9a47
TS		 1682 /* Discard cached TLB entries. We could avoid doing this if the
1683 tlbwi is just upgrading access permissions on the current entry;
1684 that might be a further win. */
ead9360e 1685 r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
814b9a47 1686
bbc0d79c
AJ		 1687 r4k_invalidate_tlb(env, idx, 0);
1688 r4k_fill_tlb(idx);
6af0bf9c
FB		 1689}
1690
c01fccd2 1691void r4k_helper_tlbwr (void)
6af0bf9c
FB		 1692{
1693 int r = cpu_mips_get_random(env);
1694
29929e34
TS		 1695 r4k_invalidate_tlb(env, r, 1);
1696 r4k_fill_tlb(r);
6af0bf9c
FB		 1697}
1698
c01fccd2 1699void r4k_helper_tlbp (void)
6af0bf9c 1700{
c227f099 1701 r4k_tlb_t *tlb;
f2e9ebef 1702 target_ulong mask;
6af0bf9c 1703 target_ulong tag;
f2e9ebef 1704 target_ulong VPN;
6af0bf9c
FB		 1705 uint8_t ASID;
1706 int i;
1707
3d9fb9fe 1708 ASID = env->CP0_EntryHi & 0xFF;
ead9360e
TS		 1709 for (i = 0; i < env->tlb->nb_tlb; i++) {
1710 tlb = &env->tlb->mmu.r4k.tlb[i];
f2e9ebef
TS		 1711 /* 1k pages are not supported. */
1712 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1713 tag = env->CP0_EntryHi & ~mask;
1714 VPN = tlb->VPN & ~mask;
6af0bf9c 1715 /* Check ASID, virtual page number & size */
f2e9ebef 1716 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
6af0bf9c 1717 /* TLB match */
9c2149c8 1718 env->CP0_Index = i;
6af0bf9c
FB		 1719 break;
1720 }
1721 }
ead9360e 1722 if (i == env->tlb->nb_tlb) {
814b9a47 1723 /* No match. Discard any shadow entries, if any of them match. */
ead9360e 1724 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
6958549d
AJ		 1725 tlb = &env->tlb->mmu.r4k.tlb[i];
1726 /* 1k pages are not supported. */
1727 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1728 tag = env->CP0_EntryHi & ~mask;
1729 VPN = tlb->VPN & ~mask;
1730 /* Check ASID, virtual page number & size */
1731 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
29929e34 1732 r4k_mips_tlb_flush_extra (env, i);
6958549d
AJ		 1733 break;
1734 }
1735 }
814b9a47 1736
9c2149c8 1737 env->CP0_Index |= 0x80000000;
6af0bf9c
FB		 1738 }
1739}
1740
c01fccd2 1741void r4k_helper_tlbr (void)
6af0bf9c 1742{
c227f099 1743 r4k_tlb_t *tlb;
09c56b84 1744 uint8_t ASID;
bbc0d79c 1745 int idx;
6af0bf9c 1746
09c56b84 1747 ASID = env->CP0_EntryHi & 0xFF;
bbc0d79c
AJ		 1748 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1749 tlb = &env->tlb->mmu.r4k.tlb[idx];
4ad40f36
FB		 1750
1751 /* If this will change the current ASID, flush qemu's TLB. */
814b9a47
TS		 1752 if (ASID != tlb->ASID)
1753 cpu_mips_tlb_flush (env, 1);
1754
ead9360e 1755 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
4ad40f36 1756
6af0bf9c 1757 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
3b1c8be4 1758 env->CP0_PageMask = tlb->PageMask;
7495fd0f
TS		 1759 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1760 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1761 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1762 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
6af0bf9c 1763}
6af0bf9c 1764
c01fccd2 1765void helper_tlbwi(void)
a7812ae4 1766{
c01fccd2 1767 env->tlb->helper_tlbwi();
a7812ae4
PB		 1768}
1769
c01fccd2 1770void helper_tlbwr(void)
a7812ae4 1771{
c01fccd2 1772 env->tlb->helper_tlbwr();
a7812ae4
PB		 1773}
1774
c01fccd2 1775void helper_tlbp(void)
a7812ae4 1776{
c01fccd2 1777 env->tlb->helper_tlbp();
a7812ae4
PB		 1778}
1779
c01fccd2 1780void helper_tlbr(void)
a7812ae4 1781{
c01fccd2 1782 env->tlb->helper_tlbr();
a7812ae4
PB		 1783}
1784
2b0233ab 1785/* Specials */
c01fccd2 1786target_ulong helper_di (void)
2b0233ab 1787{
2796188e
TS		 1788 target_ulong t0 = env->CP0_Status;
1789
be24bb4f 1790 env->CP0_Status = t0 & ~(1 << CP0St_IE);
2b0233ab 1791 cpu_mips_update_irq(env);
be24bb4f
TS		 1792
1793 return t0;
2b0233ab
TS		 1794}
1795
c01fccd2 1796target_ulong helper_ei (void)
2b0233ab 1797{
2796188e
TS		 1798 target_ulong t0 = env->CP0_Status;
1799
be24bb4f 1800 env->CP0_Status = t0 | (1 << CP0St_IE);
2b0233ab 1801 cpu_mips_update_irq(env);
be24bb4f
TS		 1802
1803 return t0;
2b0233ab
TS		 1804}
1805
cd5158ea 1806static void debug_pre_eret (void)
6af0bf9c 1807{
8fec2b8c 1808 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
93fcfe39
AL		 1809 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1810 env->active_tc.PC, env->CP0_EPC);
1811 if (env->CP0_Status & (1 << CP0St_ERL))
1812 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1813 if (env->hflags & MIPS_HFLAG_DM)
1814 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1815 qemu_log("\n");
1816 }
f41c52f1
TS		 1817}
1818
cd5158ea 1819static void debug_post_eret (void)
f41c52f1 1820{
8fec2b8c 1821 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
93fcfe39
AL		 1822 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1823 env->active_tc.PC, env->CP0_EPC);
1824 if (env->CP0_Status & (1 << CP0St_ERL))
1825 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1826 if (env->hflags & MIPS_HFLAG_DM)
1827 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1828 switch (env->hflags & MIPS_HFLAG_KSU) {
1829 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1830 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1831 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1832 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1833 }
623a930e 1834 }
6af0bf9c
FB		 1835}
1836
32188a03
NF		 1837static void set_pc (target_ulong error_pc)
1838{
1839 env->active_tc.PC = error_pc & ~(target_ulong)1;
1840 if (error_pc & 1) {
1841 env->hflags |= MIPS_HFLAG_M16;
1842 } else {
1843 env->hflags &= ~(MIPS_HFLAG_M16);
1844 }
1845}
1846
c01fccd2 1847void helper_eret (void)
2b0233ab 1848{
93fcfe39 1849 debug_pre_eret();
2b0233ab 1850 if (env->CP0_Status & (1 << CP0St_ERL)) {
32188a03 1851 set_pc(env->CP0_ErrorEPC);
2b0233ab
TS		 1852 env->CP0_Status &= ~(1 << CP0St_ERL);
1853 } else {
32188a03 1854 set_pc(env->CP0_EPC);
2b0233ab
TS		 1855 env->CP0_Status &= ~(1 << CP0St_EXL);
1856 }
1857 compute_hflags(env);
93fcfe39 1858 debug_post_eret();
5499b6ff 1859 env->lladdr = 1;
2b0233ab
TS		 1860}
1861
c01fccd2 1862void helper_deret (void)
2b0233ab 1863{
93fcfe39 1864 debug_pre_eret();
32188a03
NF		 1865 set_pc(env->CP0_DEPC);
1866
2b0233ab
TS		 1867 env->hflags &= MIPS_HFLAG_DM;
1868 compute_hflags(env);
93fcfe39 1869 debug_post_eret();
5499b6ff 1870 env->lladdr = 1;
2b0233ab 1871}
0eaef5aa 1872#endif /* !CONFIG_USER_ONLY */
2b0233ab 1873
c01fccd2 1874target_ulong helper_rdhwr_cpunum(void)
2b0233ab
TS		 1875{
1876 if ((env->hflags & MIPS_HFLAG_CP0) ||
1877 (env->CP0_HWREna & (1 << 0)))
2796188e 1878 return env->CP0_EBase & 0x3ff;
2b0233ab 1879 else
c01fccd2 1880 helper_raise_exception(EXCP_RI);
be24bb4f 1881
2796188e 1882 return 0;
2b0233ab
TS		 1883}
1884
c01fccd2 1885target_ulong helper_rdhwr_synci_step(void)
2b0233ab
TS		 1886{
1887 if ((env->hflags & MIPS_HFLAG_CP0) ||
1888 (env->CP0_HWREna & (1 << 1)))
2796188e 1889 return env->SYNCI_Step;
2b0233ab 1890 else
c01fccd2 1891 helper_raise_exception(EXCP_RI);
be24bb4f 1892
2796188e 1893 return 0;
2b0233ab
TS		 1894}
1895
c01fccd2 1896target_ulong helper_rdhwr_cc(void)
2b0233ab
TS		 1897{
1898 if ((env->hflags & MIPS_HFLAG_CP0) ||
1899 (env->CP0_HWREna & (1 << 2)))
2796188e 1900 return env->CP0_Count;
2b0233ab 1901 else
c01fccd2 1902 helper_raise_exception(EXCP_RI);
be24bb4f 1903
2796188e 1904 return 0;
2b0233ab
TS		 1905}
1906
c01fccd2 1907target_ulong helper_rdhwr_ccres(void)
2b0233ab
TS		 1908{
1909 if ((env->hflags & MIPS_HFLAG_CP0) ||
1910 (env->CP0_HWREna & (1 << 3)))
2796188e 1911 return env->CCRes;
2b0233ab 1912 else
c01fccd2 1913 helper_raise_exception(EXCP_RI);
be24bb4f 1914
2796188e 1915 return 0;
2b0233ab
TS		 1916}
1917
c01fccd2 1918void helper_pmon (int function)
6af0bf9c
FB		 1919{
1920 function /= 2;
1921 switch (function) {
1922 case 2: /* TODO: char inbyte(int waitflag); */
b5dc7732
TS		 1923 if (env->active_tc.gpr[4] == 0)
1924 env->active_tc.gpr[2] = -1;
6af0bf9c
FB		 1925 /* Fall through */
1926 case 11: /* TODO: char inbyte (void); */
b5dc7732 1927 env->active_tc.gpr[2] = -1;
6af0bf9c
FB		 1928 break;
1929 case 3:
1930 case 12:
b5dc7732 1931 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
6af0bf9c
FB		 1932 break;
1933 case 17:
1934 break;
1935 case 158:
1936 {
b5dc7732 1937 unsigned char *fmt = (void *)(unsigned long)env->active_tc.gpr[4];
6af0bf9c
FB		 1938 printf("%s", fmt);
1939 }
1940 break;
1941 }
1942}
e37e863f 1943
c01fccd2 1944void helper_wait (void)
08ba7963
TS		 1945{
1946 env->halted = 1;
c01fccd2 1947 helper_raise_exception(EXCP_HLT);
08ba7963
TS		 1948}
1949
5fafdf24 1950#if !defined(CONFIG_USER_ONLY)
e37e863f 1951
4ad40f36
FB		 1952static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
1953
e37e863f 1954#define MMUSUFFIX _mmu
4ad40f36 1955#define ALIGNED_ONLY
e37e863f
FB		 1956
1957#define SHIFT 0
1958#include "softmmu_template.h"
1959
1960#define SHIFT 1
1961#include "softmmu_template.h"
1962
1963#define SHIFT 2
1964#include "softmmu_template.h"
1965
1966#define SHIFT 3
1967#include "softmmu_template.h"
1968
4ad40f36
FB		 1969static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
1970{
1971 env->CP0_BadVAddr = addr;
1972 do_restore_state (retaddr);
c01fccd2 1973 helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
4ad40f36
FB		 1974}
1975
6ebbf390 1976void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
e37e863f
FB		 1977{
1978 TranslationBlock *tb;
1979 CPUState *saved_env;
1980 unsigned long pc;
1981 int ret;
1982
1983 /* XXX: hack to restore env in all cases, even if not called from
1984 generated code */
1985 saved_env = env;
1986 env = cpu_single_env;
6ebbf390 1987 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
e37e863f
FB		 1988 if (ret) {
1989 if (retaddr) {
1990 /* now we have a real cpu fault */
1991 pc = (unsigned long)retaddr;
1992 tb = tb_find_pc(pc);
1993 if (tb) {
1994 /* the PC is inside the translated code. It means that we have
1995 a virtual CPU fault */
1996 cpu_restore_state(tb, env, pc, NULL);
1997 }
1998 }
c01fccd2 1999 helper_raise_exception_err(env->exception_index, env->error_code);
e37e863f
FB		 2000 }
2001 env = saved_env;
2002}
2003
c227f099 2004void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
e18231a3 2005 int unused, int size)
647de6ca
TS		 2006{
2007 if (is_exec)
c01fccd2 2008 helper_raise_exception(EXCP_IBE);
647de6ca 2009 else
c01fccd2 2010 helper_raise_exception(EXCP_DBE);
647de6ca 2011}
f1aa6320 2012#endif /* !CONFIG_USER_ONLY */
fd4a04eb
TS		 2013
2014/* Complex FPU operations which may need stack space. */
2015
f090c9d4
PB		 2016#define FLOAT_ONE32 make_float32(0x3f8 << 20)
2017#define FLOAT_ONE64 make_float64(0x3ffULL << 52)
2018#define FLOAT_TWO32 make_float32(1 << 30)
2019#define FLOAT_TWO64 make_float64(1ULL << 62)
54454097
TS		 2020#define FLOAT_QNAN32 0x7fbfffff
2021#define FLOAT_QNAN64 0x7ff7ffffffffffffULL
2022#define FLOAT_SNAN32 0x7fffffff
2023#define FLOAT_SNAN64 0x7fffffffffffffffULL
8dfdb87c 2024
fd4a04eb 2025/* convert MIPS rounding mode in FCR31 to IEEE library */
6f4fc367 2026static unsigned int ieee_rm[] = {
fd4a04eb
TS		 2027 float_round_nearest_even,
2028 float_round_to_zero,
2029 float_round_up,
2030 float_round_down
2031};
2032
2033#define RESTORE_ROUNDING_MODE \
f01be154 2034 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
fd4a04eb 2035
41e0c701
AJ		 2036#define RESTORE_FLUSH_MODE \
2037 set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status);
2038
c01fccd2 2039target_ulong helper_cfc1 (uint32_t reg)
fd4a04eb 2040{
d9bea114 2041 target_ulong arg1;
6c5c1e20 2042
ead9360e
TS		 2043 switch (reg) {
2044 case 0:
d9bea114 2045 arg1 = (int32_t)env->active_fpu.fcr0;
ead9360e
TS		 2046 break;
2047 case 25:
d9bea114 2048 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
ead9360e
TS		 2049 break;
2050 case 26:
d9bea114 2051 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
ead9360e
TS		 2052 break;
2053 case 28:
d9bea114 2054 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
ead9360e
TS		 2055 break;
2056 default:
d9bea114 2057 arg1 = (int32_t)env->active_fpu.fcr31;
ead9360e
TS		 2058 break;
2059 }
be24bb4f 2060
d9bea114 2061 return arg1;
ead9360e
TS		 2062}
2063
d9bea114 2064void helper_ctc1 (target_ulong arg1, uint32_t reg)
ead9360e
TS		 2065{
2066 switch(reg) {
fd4a04eb 2067 case 25:
d9bea114 2068 if (arg1 & 0xffffff00)
fd4a04eb 2069 return;
d9bea114
AJ		 2070 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2071 ((arg1 & 0x1) << 23);
fd4a04eb
TS		 2072 break;
2073 case 26:
d9bea114 2074 if (arg1 & 0x007c0000)
fd4a04eb 2075 return;
d9bea114 2076 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
fd4a04eb
TS		 2077 break;
2078 case 28:
d9bea114 2079 if (arg1 & 0x007c0000)
fd4a04eb 2080 return;
d9bea114
AJ		 2081 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2082 ((arg1 & 0x4) << 22);
fd4a04eb
TS		 2083 break;
2084 case 31:
d9bea114 2085 if (arg1 & 0x007c0000)
fd4a04eb 2086 return;
d9bea114 2087 env->active_fpu.fcr31 = arg1;
fd4a04eb
TS		 2088 break;
2089 default:
2090 return;
2091 }
2092 /* set rounding mode */
2093 RESTORE_ROUNDING_MODE;
41e0c701
AJ		 2094 /* set flush-to-zero mode */
2095 RESTORE_FLUSH_MODE;
f01be154
TS		 2096 set_float_exception_flags(0, &env->active_fpu.fp_status);
2097 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
c01fccd2 2098 helper_raise_exception(EXCP_FPE);
fd4a04eb
TS		 2099}
2100
c904ef0e 2101static inline char ieee_ex_to_mips(char xcpt)
fd4a04eb
TS		 2102{
2103 return (xcpt & float_flag_inexact) >> 5 |
2104 (xcpt & float_flag_underflow) >> 3 |
2105 (xcpt & float_flag_overflow) >> 1 |
2106 (xcpt & float_flag_divbyzero) << 1 |
2107 (xcpt & float_flag_invalid) << 4;
2108}
2109
c904ef0e 2110static inline char mips_ex_to_ieee(char xcpt)
fd4a04eb
TS		 2111{
2112 return (xcpt & FP_INEXACT) << 5 |
2113 (xcpt & FP_UNDERFLOW) << 3 |
2114 (xcpt & FP_OVERFLOW) << 1 |
2115 (xcpt & FP_DIV0) >> 1 |
2116 (xcpt & FP_INVALID) >> 4;
2117}
2118
c904ef0e 2119static inline void update_fcr31(void)
fd4a04eb 2120{
f01be154 2121 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
fd4a04eb 2122
f01be154
TS		 2123 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2124 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp)
c01fccd2 2125 helper_raise_exception(EXCP_FPE);
fd4a04eb 2126 else
f01be154 2127 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
fd4a04eb
TS		 2128}
2129
a16336e4
TS		 2130/* Float support.
2131 Single precition routines have a "s" suffix, double precision a
2132 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2133 paired single lower "pl", paired single upper "pu". */
2134
a16336e4 2135/* unary operations, modifying fp status */
c01fccd2 2136uint64_t helper_float_sqrt_d(uint64_t fdt0)
b6d96bed 2137{
f01be154 2138 return float64_sqrt(fdt0, &env->active_fpu.fp_status);
b6d96bed
TS		 2139}
2140
c01fccd2 2141uint32_t helper_float_sqrt_s(uint32_t fst0)
b6d96bed 2142{
f01be154 2143 return float32_sqrt(fst0, &env->active_fpu.fp_status);
b6d96bed 2144}
a16336e4 2145
c01fccd2 2146uint64_t helper_float_cvtd_s(uint32_t fst0)
fd4a04eb 2147{
b6d96bed
TS		 2148 uint64_t fdt2;
2149
f01be154
TS		 2150 set_float_exception_flags(0, &env->active_fpu.fp_status);
2151 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
fd4a04eb 2152 update_fcr31();
b6d96bed 2153 return fdt2;
fd4a04eb 2154}
b6d96bed 2155
c01fccd2 2156uint64_t helper_float_cvtd_w(uint32_t wt0)
fd4a04eb 2157{
b6d96bed
TS		 2158 uint64_t fdt2;
2159
f01be154
TS		 2160 set_float_exception_flags(0, &env->active_fpu.fp_status);
2161 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
fd4a04eb 2162 update_fcr31();
b6d96bed 2163 return fdt2;
fd4a04eb 2164}
b6d96bed 2165
c01fccd2 2166uint64_t helper_float_cvtd_l(uint64_t dt0)
fd4a04eb 2167{
b6d96bed
TS		 2168 uint64_t fdt2;
2169
f01be154
TS		 2170 set_float_exception_flags(0, &env->active_fpu.fp_status);
2171 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
fd4a04eb 2172 update_fcr31();
b6d96bed 2173 return fdt2;
fd4a04eb 2174}
b6d96bed 2175
c01fccd2 2176uint64_t helper_float_cvtl_d(uint64_t fdt0)
fd4a04eb 2177{
b6d96bed
TS		 2178 uint64_t dt2;
2179
f01be154
TS		 2180 set_float_exception_flags(0, &env->active_fpu.fp_status);
2181 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2182 update_fcr31();
f01be154 2183 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2184 dt2 = FLOAT_SNAN64;
2185 return dt2;
fd4a04eb 2186}
b6d96bed 2187
c01fccd2 2188uint64_t helper_float_cvtl_s(uint32_t fst0)
fd4a04eb 2189{
b6d96bed
TS		 2190 uint64_t dt2;
2191
f01be154
TS		 2192 set_float_exception_flags(0, &env->active_fpu.fp_status);
2193 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
fd4a04eb 2194 update_fcr31();
f01be154 2195 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2196 dt2 = FLOAT_SNAN64;
2197 return dt2;
fd4a04eb
TS		 2198}
2199
c01fccd2 2200uint64_t helper_float_cvtps_pw(uint64_t dt0)
fd4a04eb 2201{
b6d96bed
TS		 2202 uint32_t fst2;
2203 uint32_t fsth2;
2204
f01be154
TS		 2205 set_float_exception_flags(0, &env->active_fpu.fp_status);
2206 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2207 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
fd4a04eb 2208 update_fcr31();
b6d96bed 2209 return ((uint64_t)fsth2 << 32) | fst2;
fd4a04eb 2210}
b6d96bed 2211
c01fccd2 2212uint64_t helper_float_cvtpw_ps(uint64_t fdt0)
fd4a04eb 2213{
b6d96bed
TS		 2214 uint32_t wt2;
2215 uint32_t wth2;
2216
f01be154
TS		 2217 set_float_exception_flags(0, &env->active_fpu.fp_status);
2218 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2219 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
fd4a04eb 2220 update_fcr31();
f01be154 2221 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) {
b6d96bed
TS		 2222 wt2 = FLOAT_SNAN32;
2223 wth2 = FLOAT_SNAN32;
2224 }
2225 return ((uint64_t)wth2 << 32) | wt2;
fd4a04eb 2226}
b6d96bed 2227
c01fccd2 2228uint32_t helper_float_cvts_d(uint64_t fdt0)
fd4a04eb 2229{
b6d96bed
TS		 2230 uint32_t fst2;
2231
f01be154
TS		 2232 set_float_exception_flags(0, &env->active_fpu.fp_status);
2233 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2234 update_fcr31();
b6d96bed 2235 return fst2;
fd4a04eb 2236}
b6d96bed 2237
c01fccd2 2238uint32_t helper_float_cvts_w(uint32_t wt0)
fd4a04eb 2239{
b6d96bed
TS		 2240 uint32_t fst2;
2241
f01be154
TS		 2242 set_float_exception_flags(0, &env->active_fpu.fp_status);
2243 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
fd4a04eb 2244 update_fcr31();
b6d96bed 2245 return fst2;
fd4a04eb 2246}
b6d96bed 2247
c01fccd2 2248uint32_t helper_float_cvts_l(uint64_t dt0)
fd4a04eb 2249{
b6d96bed
TS		 2250 uint32_t fst2;
2251
f01be154
TS		 2252 set_float_exception_flags(0, &env->active_fpu.fp_status);
2253 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
fd4a04eb 2254 update_fcr31();
b6d96bed 2255 return fst2;
fd4a04eb 2256}
b6d96bed 2257
c01fccd2 2258uint32_t helper_float_cvts_pl(uint32_t wt0)
fd4a04eb 2259{
b6d96bed
TS		 2260 uint32_t wt2;
2261
f01be154 2262 set_float_exception_flags(0, &env->active_fpu.fp_status);
b6d96bed 2263 wt2 = wt0;
fd4a04eb 2264 update_fcr31();
b6d96bed 2265 return wt2;
fd4a04eb 2266}
b6d96bed 2267
c01fccd2 2268uint32_t helper_float_cvts_pu(uint32_t wth0)
fd4a04eb 2269{
b6d96bed
TS		 2270 uint32_t wt2;
2271
f01be154 2272 set_float_exception_flags(0, &env->active_fpu.fp_status);
b6d96bed 2273 wt2 = wth0;
fd4a04eb 2274 update_fcr31();
b6d96bed 2275 return wt2;
fd4a04eb 2276}
b6d96bed 2277
c01fccd2 2278uint32_t helper_float_cvtw_s(uint32_t fst0)
fd4a04eb 2279{
b6d96bed
TS		 2280 uint32_t wt2;
2281
f01be154
TS		 2282 set_float_exception_flags(0, &env->active_fpu.fp_status);
2283 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
fd4a04eb 2284 update_fcr31();
f01be154 2285 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2286 wt2 = FLOAT_SNAN32;
2287 return wt2;
fd4a04eb 2288}
b6d96bed 2289
c01fccd2 2290uint32_t helper_float_cvtw_d(uint64_t fdt0)
fd4a04eb 2291{
b6d96bed
TS		 2292 uint32_t wt2;
2293
f01be154
TS		 2294 set_float_exception_flags(0, &env->active_fpu.fp_status);
2295 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2296 update_fcr31();
f01be154 2297 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2298 wt2 = FLOAT_SNAN32;
2299 return wt2;
fd4a04eb
TS		 2300}
2301
c01fccd2 2302uint64_t helper_float_roundl_d(uint64_t fdt0)
fd4a04eb 2303{
b6d96bed
TS		 2304 uint64_t dt2;
2305
f01be154
TS		 2306 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2307 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2308 RESTORE_ROUNDING_MODE;
2309 update_fcr31();
f01be154 2310 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2311 dt2 = FLOAT_SNAN64;
2312 return dt2;
fd4a04eb 2313}
b6d96bed 2314
c01fccd2 2315uint64_t helper_float_roundl_s(uint32_t fst0)
fd4a04eb 2316{
b6d96bed
TS		 2317 uint64_t dt2;
2318
f01be154
TS		 2319 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2320 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2321 RESTORE_ROUNDING_MODE;
2322 update_fcr31();
f01be154 2323 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2324 dt2 = FLOAT_SNAN64;
2325 return dt2;
fd4a04eb 2326}
b6d96bed 2327
c01fccd2 2328uint32_t helper_float_roundw_d(uint64_t fdt0)
fd4a04eb 2329{
b6d96bed
TS		 2330 uint32_t wt2;
2331
f01be154
TS		 2332 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2333 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2334 RESTORE_ROUNDING_MODE;
2335 update_fcr31();
f01be154 2336 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2337 wt2 = FLOAT_SNAN32;
2338 return wt2;
fd4a04eb 2339}
b6d96bed 2340
c01fccd2 2341uint32_t helper_float_roundw_s(uint32_t fst0)
fd4a04eb 2342{
b6d96bed
TS		 2343 uint32_t wt2;
2344
f01be154
TS		 2345 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2346 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2347 RESTORE_ROUNDING_MODE;
2348 update_fcr31();
f01be154 2349 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2350 wt2 = FLOAT_SNAN32;
2351 return wt2;
fd4a04eb
TS		 2352}
2353
c01fccd2 2354uint64_t helper_float_truncl_d(uint64_t fdt0)
fd4a04eb 2355{
b6d96bed
TS		 2356 uint64_t dt2;
2357
f01be154 2358 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2359 update_fcr31();
f01be154 2360 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2361 dt2 = FLOAT_SNAN64;
2362 return dt2;
fd4a04eb 2363}
b6d96bed 2364
c01fccd2 2365uint64_t helper_float_truncl_s(uint32_t fst0)
fd4a04eb 2366{
b6d96bed
TS		 2367 uint64_t dt2;
2368
f01be154 2369 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
fd4a04eb 2370 update_fcr31();
f01be154 2371 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2372 dt2 = FLOAT_SNAN64;
2373 return dt2;
fd4a04eb 2374}
b6d96bed 2375
c01fccd2 2376uint32_t helper_float_truncw_d(uint64_t fdt0)
fd4a04eb 2377{
b6d96bed
TS		 2378 uint32_t wt2;
2379
f01be154 2380 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2381 update_fcr31();
f01be154 2382 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2383 wt2 = FLOAT_SNAN32;
2384 return wt2;
fd4a04eb 2385}
b6d96bed 2386
c01fccd2 2387uint32_t helper_float_truncw_s(uint32_t fst0)
fd4a04eb 2388{
b6d96bed
TS		 2389 uint32_t wt2;
2390
f01be154 2391 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
fd4a04eb 2392 update_fcr31();
f01be154 2393 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2394 wt2 = FLOAT_SNAN32;
2395 return wt2;
fd4a04eb
TS		 2396}
2397
c01fccd2 2398uint64_t helper_float_ceill_d(uint64_t fdt0)
fd4a04eb 2399{
b6d96bed
TS		 2400 uint64_t dt2;
2401
f01be154
TS		 2402 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2403 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2404 RESTORE_ROUNDING_MODE;
2405 update_fcr31();
f01be154 2406 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2407 dt2 = FLOAT_SNAN64;
2408 return dt2;
fd4a04eb 2409}
b6d96bed 2410
c01fccd2 2411uint64_t helper_float_ceill_s(uint32_t fst0)
fd4a04eb 2412{
b6d96bed
TS		 2413 uint64_t dt2;
2414
f01be154
TS		 2415 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2416 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2417 RESTORE_ROUNDING_MODE;
2418 update_fcr31();
f01be154 2419 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2420 dt2 = FLOAT_SNAN64;
2421 return dt2;
fd4a04eb 2422}
b6d96bed 2423
c01fccd2 2424uint32_t helper_float_ceilw_d(uint64_t fdt0)
fd4a04eb 2425{
b6d96bed
TS		 2426 uint32_t wt2;
2427
f01be154
TS		 2428 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2429 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2430 RESTORE_ROUNDING_MODE;
2431 update_fcr31();
f01be154 2432 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2433 wt2 = FLOAT_SNAN32;
2434 return wt2;
fd4a04eb 2435}
b6d96bed 2436
c01fccd2 2437uint32_t helper_float_ceilw_s(uint32_t fst0)
fd4a04eb 2438{
b6d96bed
TS		 2439 uint32_t wt2;
2440
f01be154
TS		 2441 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2442 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2443 RESTORE_ROUNDING_MODE;
2444 update_fcr31();
f01be154 2445 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2446 wt2 = FLOAT_SNAN32;
2447 return wt2;
fd4a04eb
TS		 2448}
2449
c01fccd2 2450uint64_t helper_float_floorl_d(uint64_t fdt0)
fd4a04eb 2451{
b6d96bed
TS		 2452 uint64_t dt2;
2453
f01be154
TS		 2454 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2455 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2456 RESTORE_ROUNDING_MODE;
2457 update_fcr31();
f01be154 2458 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2459 dt2 = FLOAT_SNAN64;
2460 return dt2;
fd4a04eb 2461}
b6d96bed 2462
c01fccd2 2463uint64_t helper_float_floorl_s(uint32_t fst0)
fd4a04eb 2464{
b6d96bed
TS		 2465 uint64_t dt2;
2466
f01be154
TS		 2467 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2468 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2469 RESTORE_ROUNDING_MODE;
2470 update_fcr31();
f01be154 2471 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2472 dt2 = FLOAT_SNAN64;
2473 return dt2;
fd4a04eb 2474}
b6d96bed 2475
c01fccd2 2476uint32_t helper_float_floorw_d(uint64_t fdt0)
fd4a04eb 2477{
b6d96bed
TS		 2478 uint32_t wt2;
2479
f01be154
TS		 2480 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2481 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2482 RESTORE_ROUNDING_MODE;
2483 update_fcr31();
f01be154 2484 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2485 wt2 = FLOAT_SNAN32;
2486 return wt2;
fd4a04eb 2487}
b6d96bed 2488
c01fccd2 2489uint32_t helper_float_floorw_s(uint32_t fst0)
fd4a04eb 2490{
b6d96bed
TS		 2491 uint32_t wt2;
2492
f01be154
TS		 2493 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2494 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2495 RESTORE_ROUNDING_MODE;
2496 update_fcr31();
f01be154 2497 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2498 wt2 = FLOAT_SNAN32;
2499 return wt2;
fd4a04eb
TS		 2500}
2501
a16336e4 2502/* unary operations, not modifying fp status */
b6d96bed 2503#define FLOAT_UNOP(name) \
c01fccd2 2504uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
b6d96bed
TS		 2505{ \
2506 return float64_ ## name(fdt0); \
2507} \
c01fccd2 2508uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
b6d96bed
TS		 2509{ \
2510 return float32_ ## name(fst0); \
2511} \
c01fccd2 2512uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
b6d96bed
TS		 2513{ \
2514 uint32_t wt0; \
2515 uint32_t wth0; \
2516 \
2517 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
2518 wth0 = float32_ ## name(fdt0 >> 32); \
2519 return ((uint64_t)wth0 << 32) | wt0; \
a16336e4
TS		 2520}
2521FLOAT_UNOP(abs)
2522FLOAT_UNOP(chs)
2523#undef FLOAT_UNOP
2524
8dfdb87c 2525/* MIPS specific unary operations */
c01fccd2 2526uint64_t helper_float_recip_d(uint64_t fdt0)
8dfdb87c 2527{
b6d96bed
TS		 2528 uint64_t fdt2;
2529
f01be154
TS		 2530 set_float_exception_flags(0, &env->active_fpu.fp_status);
2531 fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
8dfdb87c 2532 update_fcr31();
b6d96bed 2533 return fdt2;
8dfdb87c 2534}
b6d96bed 2535
c01fccd2 2536uint32_t helper_float_recip_s(uint32_t fst0)
8dfdb87c 2537{
b6d96bed
TS		 2538 uint32_t fst2;
2539
f01be154
TS		 2540 set_float_exception_flags(0, &env->active_fpu.fp_status);
2541 fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
8dfdb87c 2542 update_fcr31();
b6d96bed 2543 return fst2;
57fa1fb3 2544}
57fa1fb3 2545
c01fccd2 2546uint64_t helper_float_rsqrt_d(uint64_t fdt0)
8dfdb87c 2547{
b6d96bed
TS		 2548 uint64_t fdt2;
2549
f01be154
TS		 2550 set_float_exception_flags(0, &env->active_fpu.fp_status);
2551 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2552 fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
8dfdb87c 2553 update_fcr31();
b6d96bed 2554 return fdt2;
8dfdb87c 2555}
b6d96bed 2556
c01fccd2 2557uint32_t helper_float_rsqrt_s(uint32_t fst0)
8dfdb87c 2558{
b6d96bed
TS		 2559 uint32_t fst2;
2560
f01be154
TS		 2561 set_float_exception_flags(0, &env->active_fpu.fp_status);
2562 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2563 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
8dfdb87c 2564 update_fcr31();
b6d96bed 2565 return fst2;
8dfdb87c
TS		 2566}
2567
c01fccd2 2568uint64_t helper_float_recip1_d(uint64_t fdt0)
8dfdb87c 2569{
b6d96bed
TS		 2570 uint64_t fdt2;
2571
f01be154
TS		 2572 set_float_exception_flags(0, &env->active_fpu.fp_status);
2573 fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
8dfdb87c 2574 update_fcr31();
b6d96bed 2575 return fdt2;
8dfdb87c 2576}
b6d96bed 2577
c01fccd2 2578uint32_t helper_float_recip1_s(uint32_t fst0)
8dfdb87c 2579{
b6d96bed
TS		 2580 uint32_t fst2;
2581
f01be154
TS		 2582 set_float_exception_flags(0, &env->active_fpu.fp_status);
2583 fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
8dfdb87c 2584 update_fcr31();
b6d96bed 2585 return fst2;
8dfdb87c 2586}
b6d96bed 2587
c01fccd2 2588uint64_t helper_float_recip1_ps(uint64_t fdt0)
8dfdb87c 2589{
b6d96bed
TS		 2590 uint32_t fst2;
2591 uint32_t fsth2;
2592
f01be154
TS		 2593 set_float_exception_flags(0, &env->active_fpu.fp_status);
2594 fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2595 fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status);
8dfdb87c 2596 update_fcr31();
b6d96bed 2597 return ((uint64_t)fsth2 << 32) | fst2;
8dfdb87c
TS		 2598}
2599
c01fccd2 2600uint64_t helper_float_rsqrt1_d(uint64_t fdt0)
8dfdb87c 2601{
b6d96bed
TS		 2602 uint64_t fdt2;
2603
f01be154
TS		 2604 set_float_exception_flags(0, &env->active_fpu.fp_status);
2605 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2606 fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
8dfdb87c 2607 update_fcr31();
b6d96bed 2608 return fdt2;
8dfdb87c 2609}
b6d96bed 2610
c01fccd2 2611uint32_t helper_float_rsqrt1_s(uint32_t fst0)
8dfdb87c 2612{
b6d96bed
TS		 2613 uint32_t fst2;
2614
f01be154
TS		 2615 set_float_exception_flags(0, &env->active_fpu.fp_status);
2616 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2617 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
8dfdb87c 2618 update_fcr31();
b6d96bed 2619 return fst2;
8dfdb87c 2620}
b6d96bed 2621
c01fccd2 2622uint64_t helper_float_rsqrt1_ps(uint64_t fdt0)
8dfdb87c 2623{
b6d96bed
TS		 2624 uint32_t fst2;
2625 uint32_t fsth2;
2626
f01be154
TS		 2627 set_float_exception_flags(0, &env->active_fpu.fp_status);
2628 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2629 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2630 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2631 fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status);
8dfdb87c 2632 update_fcr31();
b6d96bed 2633 return ((uint64_t)fsth2 << 32) | fst2;
57fa1fb3 2634}
57fa1fb3 2635
c01fccd2 2636#define FLOAT_OP(name, p) void helper_float_##name##_##p(void)
b6d96bed 2637
fd4a04eb 2638/* binary operations */
b6d96bed 2639#define FLOAT_BINOP(name) \
c01fccd2 2640uint64_t helper_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \
b6d96bed
TS		 2641{ \
2642 uint64_t dt2; \
2643 \
f01be154
TS		 2644 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2645 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
ead9360e 2646 update_fcr31(); \
f01be154 2647 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
b6d96bed
TS		 2648 dt2 = FLOAT_QNAN64; \
2649 return dt2; \
2650} \
2651 \
c01fccd2 2652uint32_t helper_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \
b6d96bed
TS		 2653{ \
2654 uint32_t wt2; \
2655 \
f01be154
TS		 2656 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2657 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
ead9360e 2658 update_fcr31(); \
f01be154 2659 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
b6d96bed
TS		 2660 wt2 = FLOAT_QNAN32; \
2661 return wt2; \
2662} \
2663 \
c01fccd2 2664uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \
b6d96bed
TS		 2665{ \
2666 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2667 uint32_t fsth0 = fdt0 >> 32; \
2668 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2669 uint32_t fsth1 = fdt1 >> 32; \
2670 uint32_t wt2; \
2671 uint32_t wth2; \
2672 \
f01be154
TS		 2673 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2674 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2675 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
b6d96bed 2676 update_fcr31(); \
f01be154 2677 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \
b6d96bed
TS		 2678 wt2 = FLOAT_QNAN32; \
2679 wth2 = FLOAT_QNAN32; \
2680 } \
2681 return ((uint64_t)wth2 << 32) | wt2; \
fd4a04eb 2682}
b6d96bed 2683
fd4a04eb
TS		 2684FLOAT_BINOP(add)
2685FLOAT_BINOP(sub)
2686FLOAT_BINOP(mul)
2687FLOAT_BINOP(div)
2688#undef FLOAT_BINOP
2689
a16336e4 2690/* ternary operations */
b6d96bed 2691#define FLOAT_TERNOP(name1, name2) \
c01fccd2 2692uint64_t helper_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
b6d96bed
TS		 2693 uint64_t fdt2) \
2694{ \
f01be154
TS		 2695 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2696 return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2697} \
2698 \
c01fccd2 2699uint32_t helper_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
b6d96bed
TS		 2700 uint32_t fst2) \
2701{ \
f01be154
TS		 2702 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2703 return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2704} \
2705 \
c01fccd2 2706uint64_t helper_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \
b6d96bed
TS		 2707 uint64_t fdt2) \
2708{ \
2709 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2710 uint32_t fsth0 = fdt0 >> 32; \
2711 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2712 uint32_t fsth1 = fdt1 >> 32; \
2713 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2714 uint32_t fsth2 = fdt2 >> 32; \
2715 \
f01be154
TS		 2716 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2717 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
2718 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2719 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
b6d96bed 2720 return ((uint64_t)fsth2 << 32) | fst2; \
a16336e4 2721}
b6d96bed 2722
a16336e4
TS		 2723FLOAT_TERNOP(mul, add)
2724FLOAT_TERNOP(mul, sub)
2725#undef FLOAT_TERNOP
2726
2727/* negated ternary operations */
b6d96bed 2728#define FLOAT_NTERNOP(name1, name2) \
c01fccd2 2729uint64_t helper_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
b6d96bed
TS		 2730 uint64_t fdt2) \
2731{ \
f01be154
TS		 2732 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2733 fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2734 return float64_chs(fdt2); \
2735} \
2736 \
c01fccd2 2737uint32_t helper_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
b6d96bed
TS		 2738 uint32_t fst2) \
2739{ \
f01be154
TS		 2740 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2741 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2742 return float32_chs(fst2); \
2743} \
2744 \
c01fccd2 2745uint64_t helper_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\
b6d96bed
TS		 2746 uint64_t fdt2) \
2747{ \
2748 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2749 uint32_t fsth0 = fdt0 >> 32; \
2750 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2751 uint32_t fsth1 = fdt1 >> 32; \
2752 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2753 uint32_t fsth2 = fdt2 >> 32; \
2754 \
f01be154
TS		 2755 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2756 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
2757 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2758 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2759 fst2 = float32_chs(fst2); \
2760 fsth2 = float32_chs(fsth2); \
2761 return ((uint64_t)fsth2 << 32) | fst2; \
a16336e4 2762}
b6d96bed 2763
a16336e4
TS		 2764FLOAT_NTERNOP(mul, add)
2765FLOAT_NTERNOP(mul, sub)
2766#undef FLOAT_NTERNOP
2767
8dfdb87c 2768/* MIPS specific binary operations */
c01fccd2 2769uint64_t helper_float_recip2_d(uint64_t fdt0, uint64_t fdt2)
8dfdb87c 2770{
f01be154
TS		 2771 set_float_exception_flags(0, &env->active_fpu.fp_status);
2772 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2773 fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status));
8dfdb87c 2774 update_fcr31();
b6d96bed 2775 return fdt2;
8dfdb87c 2776}
b6d96bed 2777
c01fccd2 2778uint32_t helper_float_recip2_s(uint32_t fst0, uint32_t fst2)
8dfdb87c 2779{
f01be154
TS		 2780 set_float_exception_flags(0, &env->active_fpu.fp_status);
2781 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2782 fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
8dfdb87c 2783 update_fcr31();
b6d96bed 2784 return fst2;
8dfdb87c 2785}
b6d96bed 2786
c01fccd2 2787uint64_t helper_float_recip2_ps(uint64_t fdt0, uint64_t fdt2)
8dfdb87c 2788{
b6d96bed
TS		 2789 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2790 uint32_t fsth0 = fdt0 >> 32;
2791 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2792 uint32_t fsth2 = fdt2 >> 32;
2793
f01be154
TS		 2794 set_float_exception_flags(0, &env->active_fpu.fp_status);
2795 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2796 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2797 fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
2798 fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status));
8dfdb87c 2799 update_fcr31();
b6d96bed 2800 return ((uint64_t)fsth2 << 32) | fst2;
8dfdb87c
TS		 2801}
2802
c01fccd2 2803uint64_t helper_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2)
8dfdb87c 2804{
f01be154
TS		 2805 set_float_exception_flags(0, &env->active_fpu.fp_status);
2806 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2807 fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status);
2808 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
8dfdb87c 2809 update_fcr31();
b6d96bed 2810 return fdt2;
8dfdb87c 2811}
b6d96bed 2812
c01fccd2 2813uint32_t helper_float_rsqrt2_s(uint32_t fst0, uint32_t fst2)
8dfdb87c 2814{
f01be154
TS		 2815 set_float_exception_flags(0, &env->active_fpu.fp_status);
2816 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2817 fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
2818 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
8dfdb87c 2819 update_fcr31();
b6d96bed 2820 return fst2;
8dfdb87c 2821}
b6d96bed 2822
c01fccd2 2823uint64_t helper_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2)
8dfdb87c 2824{
b6d96bed
TS		 2825 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2826 uint32_t fsth0 = fdt0 >> 32;
2827 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2828 uint32_t fsth2 = fdt2 >> 32;
2829
f01be154
TS		 2830 set_float_exception_flags(0, &env->active_fpu.fp_status);
2831 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2832 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2833 fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
2834 fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status);
2835 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2836 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
8dfdb87c 2837 update_fcr31();
b6d96bed 2838 return ((uint64_t)fsth2 << 32) | fst2;
57fa1fb3 2839}
57fa1fb3 2840
c01fccd2 2841uint64_t helper_float_addr_ps(uint64_t fdt0, uint64_t fdt1)
fd4a04eb 2842{
b6d96bed
TS		 2843 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2844 uint32_t fsth0 = fdt0 >> 32;
2845 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2846 uint32_t fsth1 = fdt1 >> 32;
2847 uint32_t fst2;
2848 uint32_t fsth2;
2849
f01be154
TS		 2850 set_float_exception_flags(0, &env->active_fpu.fp_status);
2851 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
2852 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
fd4a04eb 2853 update_fcr31();
b6d96bed 2854 return ((uint64_t)fsth2 << 32) | fst2;
fd4a04eb
TS		 2855}
2856
c01fccd2 2857uint64_t helper_float_mulr_ps(uint64_t fdt0, uint64_t fdt1)
57fa1fb3 2858{
b6d96bed
TS		 2859 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2860 uint32_t fsth0 = fdt0 >> 32;
2861 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2862 uint32_t fsth1 = fdt1 >> 32;
2863 uint32_t fst2;
2864 uint32_t fsth2;
2865
f01be154
TS		 2866 set_float_exception_flags(0, &env->active_fpu.fp_status);
2867 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
2868 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
57fa1fb3 2869 update_fcr31();
b6d96bed 2870 return ((uint64_t)fsth2 << 32) | fst2;
57fa1fb3
TS		 2871}
2872
8dfdb87c 2873/* compare operations */
b6d96bed 2874#define FOP_COND_D(op, cond) \
c01fccd2 2875void helper_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
b6d96bed
TS		 2876{ \
2877 int c = cond; \
2878 update_fcr31(); \
2879 if (c) \
f01be154 2880 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2881 else \
f01be154 2882 CLEAR_FP_COND(cc, env->active_fpu); \
b6d96bed 2883} \
c01fccd2 2884void helper_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
b6d96bed
TS		 2885{ \
2886 int c; \
2887 fdt0 = float64_abs(fdt0); \
2888 fdt1 = float64_abs(fdt1); \
2889 c = cond; \
2890 update_fcr31(); \
2891 if (c) \
f01be154 2892 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2893 else \
f01be154 2894 CLEAR_FP_COND(cc, env->active_fpu); \
fd4a04eb
TS		 2895}
2896
cd5158ea 2897static int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
fd4a04eb
TS		 2898{
2899 if (float64_is_signaling_nan(a) ||
2900 float64_is_signaling_nan(b) ||
2901 (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
2902 float_raise(float_flag_invalid, status);
2903 return 1;
2904 } else if (float64_is_nan(a) || float64_is_nan(b)) {
2905 return 1;
2906 } else {
2907 return 0;
2908 }
2909}
2910
2911/* NOTE: the comma operator will make "cond" to eval to false,
2912 * but float*_is_unordered() is still called. */
f01be154
TS		 2913FOP_COND_D(f, (float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status), 0))
2914FOP_COND_D(un, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status))
2915FOP_COND_D(eq, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2916FOP_COND_D(ueq, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2917FOP_COND_D(olt, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2918FOP_COND_D(ult, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2919FOP_COND_D(ole, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2920FOP_COND_D(ule, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
fd4a04eb
TS		 2921/* NOTE: the comma operator will make "cond" to eval to false,
2922 * but float*_is_unordered() is still called. */
f01be154
TS		 2923FOP_COND_D(sf, (float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status), 0))
2924FOP_COND_D(ngle,float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status))
2925FOP_COND_D(seq, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2926FOP_COND_D(ngl, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2927FOP_COND_D(lt, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2928FOP_COND_D(nge, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2929FOP_COND_D(le, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2930FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
b6d96bed
TS		 2931
2932#define FOP_COND_S(op, cond) \
c01fccd2 2933void helper_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
b6d96bed
TS		 2934{ \
2935 int c = cond; \
2936 update_fcr31(); \
2937 if (c) \
f01be154 2938 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2939 else \
f01be154 2940 CLEAR_FP_COND(cc, env->active_fpu); \
b6d96bed 2941} \
c01fccd2 2942void helper_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
b6d96bed
TS		 2943{ \
2944 int c; \
2945 fst0 = float32_abs(fst0); \
2946 fst1 = float32_abs(fst1); \
2947 c = cond; \
2948 update_fcr31(); \
2949 if (c) \
f01be154 2950 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2951 else \
f01be154 2952 CLEAR_FP_COND(cc, env->active_fpu); \
fd4a04eb
TS		 2953}
2954
cd5158ea 2955static flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
fd4a04eb 2956{
fd4a04eb
TS		 2957 if (float32_is_signaling_nan(a) ||
2958 float32_is_signaling_nan(b) ||
2959 (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
2960 float_raise(float_flag_invalid, status);
2961 return 1;
2962 } else if (float32_is_nan(a) || float32_is_nan(b)) {
2963 return 1;
2964 } else {
2965 return 0;
2966 }
2967}
2968
2969/* NOTE: the comma operator will make "cond" to eval to false,
2970 * but float*_is_unordered() is still called. */
f01be154
TS		 2971FOP_COND_S(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0))
2972FOP_COND_S(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status))
2973FOP_COND_S(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2974FOP_COND_S(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2975FOP_COND_S(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2976FOP_COND_S(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2977FOP_COND_S(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
2978FOP_COND_S(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
fd4a04eb
TS		 2979/* NOTE: the comma operator will make "cond" to eval to false,
2980 * but float*_is_unordered() is still called. */
f01be154
TS		 2981FOP_COND_S(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0))
2982FOP_COND_S(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status))
2983FOP_COND_S(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2984FOP_COND_S(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2985FOP_COND_S(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2986FOP_COND_S(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2987FOP_COND_S(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
2988FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
b6d96bed
TS		 2989
2990#define FOP_COND_PS(op, condl, condh) \
c01fccd2 2991void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
b6d96bed
TS		 2992{ \
2993 uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
2994 uint32_t fsth0 = float32_abs(fdt0 >> 32); \
2995 uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
2996 uint32_t fsth1 = float32_abs(fdt1 >> 32); \
2997 int cl = condl; \
2998 int ch = condh; \
2999 \
3000 update_fcr31(); \
3001 if (cl) \
f01be154 3002 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 3003 else \
f01be154 3004 CLEAR_FP_COND(cc, env->active_fpu); \
b6d96bed 3005 if (ch) \
f01be154 3006 SET_FP_COND(cc + 1, env->active_fpu); \
b6d96bed 3007 else \
f01be154 3008 CLEAR_FP_COND(cc + 1, env->active_fpu); \
b6d96bed 3009} \
c01fccd2 3010void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
b6d96bed
TS		 3011{ \
3012 uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
3013 uint32_t fsth0 = float32_abs(fdt0 >> 32); \
3014 uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
3015 uint32_t fsth1 = float32_abs(fdt1 >> 32); \
3016 int cl = condl; \
3017 int ch = condh; \
3018 \
3019 update_fcr31(); \
3020 if (cl) \
f01be154 3021 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 3022 else \
f01be154 3023 CLEAR_FP_COND(cc, env->active_fpu); \
b6d96bed 3024 if (ch) \
f01be154 3025 SET_FP_COND(cc + 1, env->active_fpu); \
b6d96bed 3026 else \
f01be154 3027 CLEAR_FP_COND(cc + 1, env->active_fpu); \
fd4a04eb
TS		 3028}
3029
3030/* NOTE: the comma operator will make "cond" to eval to false,
3031 * but float*_is_unordered() is still called. */
f01be154
TS		 3032FOP_COND_PS(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0),
3033 (float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status), 0))
3034FOP_COND_PS(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status),
3035 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status))
3036FOP_COND_PS(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3037 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3038FOP_COND_PS(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3039 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3040FOP_COND_PS(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3041 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3042FOP_COND_PS(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3043 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3044FOP_COND_PS(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status),
3045 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3046FOP_COND_PS(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3047 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
fd4a04eb
TS		 3048/* NOTE: the comma operator will make "cond" to eval to false,
3049 * but float*_is_unordered() is still called. */
f01be154
TS		 3050FOP_COND_PS(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0),
3051 (float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status), 0))
3052FOP_COND_PS(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status),
3053 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status))
3054FOP_COND_PS(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3055 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3056FOP_COND_PS(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3057 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3058FOP_COND_PS(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3059 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3060FOP_COND_PS(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3061 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3062FOP_COND_PS(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status),
3063 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3064FOP_COND_PS(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3065 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
Qemu copy for testing