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[qemu.git] / target-mips / op_helper.c
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6af0bf9c
FB		 1/*
2 * MIPS emulation helpers for qemu.
5fafdf24 3 *
6af0bf9c
FB		 4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
2d0e944d 20#include <stdlib.h>
6af0bf9c
FB		 21#include "exec.h"
22
05f778c8
TS		 23#include "host-utils.h"
24
6af0bf9c
FB		 25/*****************************************************************************/
26/* Exceptions processing helpers */
6af0bf9c 27
6af0bf9c
FB		 28void do_raise_exception_err (uint32_t exception, int error_code)
29{
30#if 1
31 if (logfile && exception < 0x100)
32 fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
33#endif
34 env->exception_index = exception;
35 env->error_code = error_code;
36 T0 = 0;
37 cpu_loop_exit();
38}
39
6af0bf9c
FB		 40void do_raise_exception (uint32_t exception)
41{
42 do_raise_exception_err(exception, 0);
43}
44
48d38ca5
TS		 45void do_interrupt_restart (void)
46{
47 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
48 !(env->CP0_Status & (1 << CP0St_ERL)) &&
49 !(env->hflags & MIPS_HFLAG_DM) &&
50 (env->CP0_Status & (1 << CP0St_IE)) &&
51 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
52 env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
53 do_raise_exception(EXCP_EXT_INTERRUPT);
54 }
55}
56
4ad40f36
FB		 57void do_restore_state (void *pc_ptr)
58{
a607922c
FB		 59 TranslationBlock *tb;
60 unsigned long pc = (unsigned long) pc_ptr;
61
62 tb = tb_find_pc (pc);
63 if (tb) {
64 cpu_restore_state (tb, env, pc, NULL);
65 }
4ad40f36
FB		 66}
67
30898801
TS		 68void do_clo (void)
69{
70 T0 = clo32(T0);
71}
72
73void do_clz (void)
74{
75 T0 = clz32(T0);
76}
77
d26bc211 78#if defined(TARGET_MIPS64)
c570fd16
TS		 79#if TARGET_LONG_BITS > HOST_LONG_BITS
80/* Those might call libgcc functions. */
81void do_dsll (void)
82{
83 T0 = T0 << T1;
84}
85
86void do_dsll32 (void)
87{
88 T0 = T0 << (T1 + 32);
89}
90
91void do_dsra (void)
92{
93 T0 = (int64_t)T0 >> T1;
94}
95
96void do_dsra32 (void)
97{
98 T0 = (int64_t)T0 >> (T1 + 32);
99}
100
101void do_dsrl (void)
102{
103 T0 = T0 >> T1;
104}
105
106void do_dsrl32 (void)
107{
108 T0 = T0 >> (T1 + 32);
109}
110
111void do_drotr (void)
112{
113 target_ulong tmp;
114
115 if (T1) {
c6d6dd7c
TS		 116 tmp = T0 << (0x40 - T1);
117 T0 = (T0 >> T1) | tmp;
5a63bcb2 118 }
c570fd16
TS		 119}
120
121void do_drotr32 (void)
122{
123 target_ulong tmp;
124
c6d6dd7c
TS		 125 tmp = T0 << (0x40 - (32 + T1));
126 T0 = (T0 >> (32 + T1)) | tmp;
c570fd16
TS		 127}
128
129void do_dsllv (void)
130{
131 T0 = T1 << (T0 & 0x3F);
132}
133
134void do_dsrav (void)
135{
136 T0 = (int64_t)T1 >> (T0 & 0x3F);
137}
138
139void do_dsrlv (void)
140{
141 T0 = T1 >> (T0 & 0x3F);
142}
143
144void do_drotrv (void)
145{
146 target_ulong tmp;
147
148 T0 &= 0x3F;
149 if (T0) {
c6d6dd7c
TS		 150 tmp = T1 << (0x40 - T0);
151 T0 = (T1 >> T0) | tmp;
c570fd16 152 } else
c6d6dd7c 153 T0 = T1;
c570fd16 154}
05f778c8 155
95af5ce5
TS		 156#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
157
05f778c8
TS		 158void do_dclo (void)
159{
160 T0 = clo64(T0);
161}
162
163void do_dclz (void)
164{
165 T0 = clz64(T0);
166}
167
d26bc211 168#endif /* TARGET_MIPS64 */
c570fd16 169
6af0bf9c 170/* 64 bits arithmetic for 32 bits hosts */
c570fd16 171#if TARGET_LONG_BITS > HOST_LONG_BITS
aa343735 172static always_inline uint64_t get_HILO (void)
6af0bf9c 173{
d0dc7dc3 174 return (env->HI[env->current_tc][0] << 32) | (uint32_t)env->LO[env->current_tc][0];
6af0bf9c
FB		 175}
176
aa343735 177static always_inline void set_HILO (uint64_t HILO)
6af0bf9c 178{
d0dc7dc3
TS		 179 env->LO[env->current_tc][0] = (int32_t)HILO;
180 env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
6af0bf9c
FB		 181}
182
e9c71dd1
TS		 183static always_inline void set_HIT0_LO (uint64_t HILO)
184{
d0dc7dc3
TS		 185 env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);
186 T0 = env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
e9c71dd1
TS		 187}
188
189static always_inline void set_HI_LOT0 (uint64_t HILO)
190{
d0dc7dc3
TS		 191 T0 = env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);
192 env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
e9c71dd1
TS		 193}
194
6af0bf9c
FB		 195void do_mult (void)
196{
4ad40f36 197 set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
6af0bf9c
FB		 198}
199
200void do_multu (void)
201{
c570fd16 202 set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
6af0bf9c
FB		 203}
204
205void do_madd (void)
206{
207 int64_t tmp;
208
4ad40f36 209 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
6af0bf9c
FB		 210 set_HILO((int64_t)get_HILO() + tmp);
211}
212
213void do_maddu (void)
214{
215 uint64_t tmp;
216
c570fd16 217 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
6af0bf9c
FB		 218 set_HILO(get_HILO() + tmp);
219}
220
221void do_msub (void)
222{
223 int64_t tmp;
224
4ad40f36 225 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
6af0bf9c
FB		 226 set_HILO((int64_t)get_HILO() - tmp);
227}
228
229void do_msubu (void)
230{
231 uint64_t tmp;
232
c570fd16 233 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
6af0bf9c
FB		 234 set_HILO(get_HILO() - tmp);
235}
e9c71dd1
TS		 236
237/* Multiplication variants of the vr54xx. */
238void do_muls (void)
239{
240 set_HI_LOT0(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
241}
242
243void do_mulsu (void)
244{
245 set_HI_LOT0(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
246}
247
248void do_macc (void)
249{
250 set_HI_LOT0(((int64_t)get_HILO()) + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
251}
252
253void do_macchi (void)
254{
255 set_HIT0_LO(((int64_t)get_HILO()) + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
256}
257
258void do_maccu (void)
259{
260 set_HI_LOT0(((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
261}
262
263void do_macchiu (void)
264{
265 set_HIT0_LO(((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
266}
267
268void do_msac (void)
269{
270 set_HI_LOT0(((int64_t)get_HILO()) - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
271}
272
273void do_msachi (void)
274{
275 set_HIT0_LO(((int64_t)get_HILO()) - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
276}
277
278void do_msacu (void)
279{
280 set_HI_LOT0(((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
281}
282
283void do_msachiu (void)
284{
285 set_HIT0_LO(((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
286}
287
288void do_mulhi (void)
289{
290 set_HIT0_LO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
291}
292
293void do_mulhiu (void)
294{
295 set_HIT0_LO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
296}
297
298void do_mulshi (void)
299{
300 set_HIT0_LO(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
301}
302
303void do_mulshiu (void)
304{
305 set_HIT0_LO(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
306}
307#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
6af0bf9c 308
f1aa6320 309#ifdef CONFIG_USER_ONLY
873eb012 310void do_mfc0_random (void)
048f6b4d 311{
873eb012 312 cpu_abort(env, "mfc0 random\n");
048f6b4d 313}
873eb012
TS		 314
315void do_mfc0_count (void)
316{
317 cpu_abort(env, "mfc0 count\n");
318}
319
8c0fdd85 320void cpu_mips_store_count(CPUState *env, uint32_t value)
048f6b4d 321{
8c0fdd85
TS		 322 cpu_abort(env, "mtc0 count\n");
323}
324
325void cpu_mips_store_compare(CPUState *env, uint32_t value)
326{
327 cpu_abort(env, "mtc0 compare\n");
328}
329
42532189
TS		 330void cpu_mips_start_count(CPUState *env)
331{
332 cpu_abort(env, "start count\n");
333}
334
335void cpu_mips_stop_count(CPUState *env)
336{
337 cpu_abort(env, "stop count\n");
338}
339
4de9b249
TS		 340void cpu_mips_update_irq(CPUState *env)
341{
342 cpu_abort(env, "mtc0 status / mtc0 cause\n");
343}
344
8c0fdd85
TS		 345void do_mtc0_status_debug(uint32_t old, uint32_t val)
346{
7a387fff 347 cpu_abort(env, "mtc0 status debug\n");
8c0fdd85
TS		 348}
349
7a387fff 350void do_mtc0_status_irqraise_debug (void)
8c0fdd85 351{
7a387fff 352 cpu_abort(env, "mtc0 status irqraise debug\n");
048f6b4d
FB		 353}
354
8c0fdd85
TS		 355void cpu_mips_tlb_flush (CPUState *env, int flush_global)
356{
357 cpu_abort(env, "mips_tlb_flush\n");
358}
359
048f6b4d
FB		 360#else
361
6af0bf9c 362/* CP0 helpers */
f1aa6320
TS		 363void do_mfc0_mvpcontrol (void)
364{
365 T0 = env->mvp->CP0_MVPControl;
366}
367
368void do_mfc0_mvpconf0 (void)
369{
370 T0 = env->mvp->CP0_MVPConf0;
371}
372
373void do_mfc0_mvpconf1 (void)
374{
375 T0 = env->mvp->CP0_MVPConf1;
376}
377
873eb012 378void do_mfc0_random (void)
6af0bf9c 379{
5dc4b744 380 T0 = (int32_t)cpu_mips_get_random(env);
873eb012 381}
6af0bf9c 382
f1aa6320
TS		 383void do_mfc0_tcstatus (void)
384{
385 T0 = env->CP0_TCStatus[env->current_tc];
386}
387
388void do_mftc0_tcstatus(void)
389{
390 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
391
392 T0 = env->CP0_TCStatus[other_tc];
393}
394
395void do_mfc0_tcbind (void)
396{
397 T0 = env->CP0_TCBind[env->current_tc];
398}
399
400void do_mftc0_tcbind(void)
401{
402 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
403
404 T0 = env->CP0_TCBind[other_tc];
405}
406
407void do_mfc0_tcrestart (void)
408{
409 T0 = env->PC[env->current_tc];
410}
411
412void do_mftc0_tcrestart(void)
413{
414 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
415
416 T0 = env->PC[other_tc];
417}
418
419void do_mfc0_tchalt (void)
420{
421 T0 = env->CP0_TCHalt[env->current_tc];
422}
423
424void do_mftc0_tchalt(void)
425{
426 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
427
428 T0 = env->CP0_TCHalt[other_tc];
429}
430
431void do_mfc0_tccontext (void)
432{
433 T0 = env->CP0_TCContext[env->current_tc];
434}
435
436void do_mftc0_tccontext(void)
437{
438 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
439
440 T0 = env->CP0_TCContext[other_tc];
441}
442
443void do_mfc0_tcschedule (void)
444{
445 T0 = env->CP0_TCSchedule[env->current_tc];
446}
447
448void do_mftc0_tcschedule(void)
449{
450 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
451
452 T0 = env->CP0_TCSchedule[other_tc];
453}
454
455void do_mfc0_tcschefback (void)
456{
457 T0 = env->CP0_TCScheFBack[env->current_tc];
458}
459
460void do_mftc0_tcschefback(void)
461{
462 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
463
464 T0 = env->CP0_TCScheFBack[other_tc];
465}
466
873eb012
TS		 467void do_mfc0_count (void)
468{
5dc4b744 469 T0 = (int32_t)cpu_mips_get_count(env);
6af0bf9c
FB		 470}
471
f1aa6320
TS		 472void do_mftc0_entryhi(void)
473{
474 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
475
476 T0 = (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff);
477}
478
479void do_mftc0_status(void)
480{
481 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
482 uint32_t tcstatus = env->CP0_TCStatus[other_tc];
483
484 T0 = env->CP0_Status & ~0xf1000018;
485 T0 |= tcstatus & (0xf << CP0TCSt_TCU0);
486 T0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
487 T0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
488}
489
490void do_mfc0_lladdr (void)
491{
492 T0 = (int32_t)env->CP0_LLAddr >> 4;
493}
494
495void do_mfc0_watchlo (uint32_t sel)
496{
497 T0 = (int32_t)env->CP0_WatchLo[sel];
498}
499
500void do_mfc0_watchhi (uint32_t sel)
501{
502 T0 = env->CP0_WatchHi[sel];
503}
504
505void do_mfc0_debug (void)
506{
507 T0 = env->CP0_Debug;
508 if (env->hflags & MIPS_HFLAG_DM)
509 T0 |= 1 << CP0DB_DM;
510}
511
512void do_mftc0_debug(void)
513{
514 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
515
516 /* XXX: Might be wrong, check with EJTAG spec. */
517 T0 = (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
518 (env->CP0_Debug_tcstatus[other_tc] &
519 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
520}
521
522#if defined(TARGET_MIPS64)
523void do_dmfc0_tcrestart (void)
524{
525 T0 = env->PC[env->current_tc];
526}
527
528void do_dmfc0_tchalt (void)
529{
530 T0 = env->CP0_TCHalt[env->current_tc];
531}
532
533void do_dmfc0_tccontext (void)
534{
535 T0 = env->CP0_TCContext[env->current_tc];
536}
537
538void do_dmfc0_tcschedule (void)
539{
540 T0 = env->CP0_TCSchedule[env->current_tc];
541}
542
543void do_dmfc0_tcschefback (void)
544{
545 T0 = env->CP0_TCScheFBack[env->current_tc];
546}
547
548void do_dmfc0_lladdr (void)
549{
550 T0 = env->CP0_LLAddr >> 4;
551}
552
553void do_dmfc0_watchlo (uint32_t sel)
554{
555 T0 = env->CP0_WatchLo[sel];
556}
557#endif /* TARGET_MIPS64 */
558
559void do_mtc0_index (void)
560{
561 int num = 1;
562 unsigned int tmp = env->tlb->nb_tlb;
563
564 do {
565 tmp >>= 1;
566 num <<= 1;
567 } while (tmp);
568 env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (num - 1));
569}
570
571void do_mtc0_mvpcontrol (void)
572{
573 uint32_t mask = 0;
574 uint32_t newval;
575
576 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
577 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
578 (1 << CP0MVPCo_EVP);
579 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
580 mask |= (1 << CP0MVPCo_STLB);
581 newval = (env->mvp->CP0_MVPControl & ~mask) | (T0 & mask);
582
583 // TODO: Enable/disable shared TLB, enable/disable VPEs.
584
585 env->mvp->CP0_MVPControl = newval;
586}
587
588void do_mtc0_vpecontrol (void)
589{
590 uint32_t mask;
591 uint32_t newval;
592
593 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
594 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
595 newval = (env->CP0_VPEControl & ~mask) | (T0 & mask);
596
597 /* Yield scheduler intercept not implemented. */
598 /* Gating storage scheduler intercept not implemented. */
599
600 // TODO: Enable/disable TCs.
601
602 env->CP0_VPEControl = newval;
603}
604
605void do_mtc0_vpeconf0 (void)
606{
607 uint32_t mask = 0;
608 uint32_t newval;
609
610 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
611 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
612 mask |= (0xff << CP0VPEC0_XTC);
613 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
614 }
615 newval = (env->CP0_VPEConf0 & ~mask) | (T0 & mask);
616
617 // TODO: TC exclusive handling due to ERL/EXL.
618
619 env->CP0_VPEConf0 = newval;
620}
621
622void do_mtc0_vpeconf1 (void)
623{
624 uint32_t mask = 0;
625 uint32_t newval;
626
627 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
628 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
629 (0xff << CP0VPEC1_NCP1);
630 newval = (env->CP0_VPEConf1 & ~mask) | (T0 & mask);
631
632 /* UDI not implemented. */
633 /* CP2 not implemented. */
634
635 // TODO: Handle FPU (CP1) binding.
636
637 env->CP0_VPEConf1 = newval;
638}
639
640void do_mtc0_yqmask (void)
641{
642 /* Yield qualifier inputs not implemented. */
643 env->CP0_YQMask = 0x00000000;
644}
645
646void do_mtc0_vpeopt (void)
647{
648 env->CP0_VPEOpt = T0 & 0x0000ffff;
649}
650
651void do_mtc0_entrylo0 (void)
652{
653 /* Large physaddr (PABITS) not implemented */
654 /* 1k pages not implemented */
655 env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
656}
657
658void do_mtc0_tcstatus (void)
659{
660 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
661 uint32_t newval;
662
663 newval = (env->CP0_TCStatus[env->current_tc] & ~mask) | (T0 & mask);
664
665 // TODO: Sync with CP0_Status.
666
667 env->CP0_TCStatus[env->current_tc] = newval;
668}
669
670void do_mttc0_tcstatus (void)
671{
672 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
673
674 // TODO: Sync with CP0_Status.
675
676 env->CP0_TCStatus[other_tc] = T0;
677}
678
679void do_mtc0_tcbind (void)
680{
681 uint32_t mask = (1 << CP0TCBd_TBE);
682 uint32_t newval;
683
684 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
685 mask |= (1 << CP0TCBd_CurVPE);
686 newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (T0 & mask);
687 env->CP0_TCBind[env->current_tc] = newval;
688}
689
690void do_mttc0_tcbind (void)
691{
692 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
693 uint32_t mask = (1 << CP0TCBd_TBE);
694 uint32_t newval;
695
696 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
697 mask |= (1 << CP0TCBd_CurVPE);
698 newval = (env->CP0_TCBind[other_tc] & ~mask) | (T0 & mask);
699 env->CP0_TCBind[other_tc] = newval;
700}
701
702void do_mtc0_tcrestart (void)
703{
704 env->PC[env->current_tc] = T0;
705 env->CP0_TCStatus[env->current_tc] &= ~(1 << CP0TCSt_TDS);
706 env->CP0_LLAddr = 0ULL;
707 /* MIPS16 not implemented. */
708}
709
710void do_mttc0_tcrestart (void)
711{
712 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
713
714 env->PC[other_tc] = T0;
715 env->CP0_TCStatus[other_tc] &= ~(1 << CP0TCSt_TDS);
716 env->CP0_LLAddr = 0ULL;
717 /* MIPS16 not implemented. */
718}
719
720void do_mtc0_tchalt (void)
721{
722 env->CP0_TCHalt[env->current_tc] = T0 & 0x1;
723
724 // TODO: Halt TC / Restart (if allocated+active) TC.
725}
726
727void do_mttc0_tchalt (void)
728{
729 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
730
731 // TODO: Halt TC / Restart (if allocated+active) TC.
732
733 env->CP0_TCHalt[other_tc] = T0;
734}
735
736void do_mtc0_tccontext (void)
737{
738 env->CP0_TCContext[env->current_tc] = T0;
739}
740
741void do_mttc0_tccontext (void)
742{
743 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
744
745 env->CP0_TCContext[other_tc] = T0;
746}
747
748void do_mtc0_tcschedule (void)
749{
750 env->CP0_TCSchedule[env->current_tc] = T0;
751}
752
753void do_mttc0_tcschedule (void)
754{
755 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
756
757 env->CP0_TCSchedule[other_tc] = T0;
758}
759
760void do_mtc0_tcschefback (void)
761{
762 env->CP0_TCScheFBack[env->current_tc] = T0;
763}
764
765void do_mttc0_tcschefback (void)
766{
767 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
768
769 env->CP0_TCScheFBack[other_tc] = T0;
770}
771
772void do_mtc0_entrylo1 (void)
773{
774 /* Large physaddr (PABITS) not implemented */
775 /* 1k pages not implemented */
776 env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
777}
778
779void do_mtc0_context (void)
780{
781 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
782}
783
784void do_mtc0_pagemask (void)
785{
786 /* 1k pages not implemented */
787 env->CP0_PageMask = T0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
788}
789
790void do_mtc0_pagegrain (void)
791{
792 /* SmartMIPS not implemented */
793 /* Large physaddr (PABITS) not implemented */
794 /* 1k pages not implemented */
795 env->CP0_PageGrain = 0;
796}
797
798void do_mtc0_wired (void)
799{
800 env->CP0_Wired = T0 % env->tlb->nb_tlb;
801}
802
803void do_mtc0_srsconf0 (void)
804{
805 env->CP0_SRSConf0 |= T0 & env->CP0_SRSConf0_rw_bitmask;
806}
807
808void do_mtc0_srsconf1 (void)
809{
810 env->CP0_SRSConf1 |= T0 & env->CP0_SRSConf1_rw_bitmask;
811}
812
813void do_mtc0_srsconf2 (void)
814{
815 env->CP0_SRSConf2 |= T0 & env->CP0_SRSConf2_rw_bitmask;
816}
817
818void do_mtc0_srsconf3 (void)
819{
820 env->CP0_SRSConf3 |= T0 & env->CP0_SRSConf3_rw_bitmask;
821}
822
823void do_mtc0_srsconf4 (void)
824{
825 env->CP0_SRSConf4 |= T0 & env->CP0_SRSConf4_rw_bitmask;
826}
827
828void do_mtc0_hwrena (void)
829{
830 env->CP0_HWREna = T0 & 0x0000000F;
831}
832
833void do_mtc0_count (void)
834{
835 cpu_mips_store_count(env, T0);
836}
837
838void do_mtc0_entryhi (void)
839{
840 target_ulong old, val;
841
842 /* 1k pages not implemented */
843 val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
844#if defined(TARGET_MIPS64)
845 val &= env->SEGMask;
846#endif
847 old = env->CP0_EntryHi;
848 env->CP0_EntryHi = val;
849 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
850 uint32_t tcst = env->CP0_TCStatus[env->current_tc] & ~0xff;
851 env->CP0_TCStatus[env->current_tc] = tcst | (val & 0xff);
852 }
853 /* If the ASID changes, flush qemu's TLB. */
854 if ((old & 0xFF) != (val & 0xFF))
855 cpu_mips_tlb_flush(env, 1);
856}
857
858void do_mttc0_entryhi(void)
859{
860 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
861
862 env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (T0 & ~0xff);
863 env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (T0 & 0xff);
864}
865
866void do_mtc0_compare (void)
867{
868 cpu_mips_store_compare(env, T0);
869}
870
871void do_mtc0_status (void)
872{
873 uint32_t val, old;
874 uint32_t mask = env->CP0_Status_rw_bitmask;
875
876 val = T0 & mask;
877 old = env->CP0_Status;
878 env->CP0_Status = (env->CP0_Status & ~mask) | val;
879 compute_hflags(env);
880 if (loglevel & CPU_LOG_EXEC)
881 do_mtc0_status_debug(old, val);
882 cpu_mips_update_irq(env);
883}
884
885void do_mttc0_status(void)
886{
887 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
888 uint32_t tcstatus = env->CP0_TCStatus[other_tc];
889
890 env->CP0_Status = T0 & ~0xf1000018;
891 tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (T0 & (0xf << CP0St_CU0));
892 tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((T0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
893 tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((T0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
894 env->CP0_TCStatus[other_tc] = tcstatus;
895}
896
897void do_mtc0_intctl (void)
898{
899 /* vectored interrupts not implemented, no performance counters. */
900 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (T0 & 0x000002e0);
901}
902
903void do_mtc0_srsctl (void)
904{
905 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
906 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (T0 & mask);
907}
908
909void do_mtc0_cause (void)
910{
911 uint32_t mask = 0x00C00300;
912 uint32_t old = env->CP0_Cause;
913
914 if (env->insn_flags & ISA_MIPS32R2)
915 mask |= 1 << CP0Ca_DC;
916
917 env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask);
918
919 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
920 if (env->CP0_Cause & (1 << CP0Ca_DC))
921 cpu_mips_stop_count(env);
922 else
923 cpu_mips_start_count(env);
924 }
925
926 /* Handle the software interrupt as an hardware one, as they
927 are very similar */
928 if (T0 & CP0Ca_IP_mask) {
929 cpu_mips_update_irq(env);
930 }
931}
932
933void do_mtc0_ebase (void)
934{
935 /* vectored interrupts not implemented */
936 /* Multi-CPU not implemented */
937 env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
938}
939
940void do_mtc0_config0 (void)
941{
942 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000007);
943}
944
945void do_mtc0_config2 (void)
946{
947 /* tertiary/secondary caches not implemented */
948 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
949}
950
951void do_mtc0_watchlo (uint32_t sel)
952{
953 /* Watch exceptions for instructions, data loads, data stores
954 not implemented. */
955 env->CP0_WatchLo[sel] = (T0 & ~0x7);
956}
957
958void do_mtc0_watchhi (uint32_t sel)
959{
960 env->CP0_WatchHi[sel] = (T0 & 0x40FF0FF8);
961 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & T0 & 0x7);
962}
963
964void do_mtc0_xcontext (void)
965{
966 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
967 env->CP0_XContext = (env->CP0_XContext & mask) | (T0 & ~mask);
968}
969
970void do_mtc0_framemask (void)
971{
972 env->CP0_Framemask = T0; /* XXX */
973}
974
975void do_mtc0_debug (void)
976{
977 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
978 if (T0 & (1 << CP0DB_DM))
979 env->hflags |= MIPS_HFLAG_DM;
980 else
981 env->hflags &= ~MIPS_HFLAG_DM;
982}
983
984void do_mttc0_debug(void)
985{
986 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
987
988 /* XXX: Might be wrong, check with EJTAG spec. */
989 env->CP0_Debug_tcstatus[other_tc] = T0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
990 env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
991 (T0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
992}
993
994void do_mtc0_performance0 (void)
995{
996 env->CP0_Performance0 = T0 & 0x000007ff;
997}
998
999void do_mtc0_taglo (void)
1000{
1001 env->CP0_TagLo = T0 & 0xFFFFFCF6;
1002}
1003
1004void do_mtc0_datalo (void)
1005{
1006 env->CP0_DataLo = T0; /* XXX */
1007}
1008
1009void do_mtc0_taghi (void)
1010{
1011 env->CP0_TagHi = T0; /* XXX */
1012}
1013
1014void do_mtc0_datahi (void)
1015{
1016 env->CP0_DataHi = T0; /* XXX */
1017}
1018
8c0fdd85 1019void do_mtc0_status_debug(uint32_t old, uint32_t val)
6af0bf9c 1020{
f41c52f1
TS		 1021 fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
1022 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1023 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1024 env->CP0_Cause);
623a930e
TS		 1025 switch (env->hflags & MIPS_HFLAG_KSU) {
1026 case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break;
1027 case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break;
1028 case MIPS_HFLAG_KM: fputs("\n", logfile); break;
1029 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1030 }
8c0fdd85
TS		 1031}
1032
1033void do_mtc0_status_irqraise_debug(void)
1034{
1035 fprintf(logfile, "Raise pending IRQs\n");
6af0bf9c 1036}
f1aa6320
TS		 1037#endif /* !CONFIG_USER_ONLY */
1038
1039/* MIPS MT functions */
1040void do_mftgpr(uint32_t sel)
1041{
1042 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1043
1044 T0 = env->gpr[other_tc][sel];
1045}
1046
1047void do_mftlo(uint32_t sel)
1048{
1049 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1050
1051 T0 = env->LO[other_tc][sel];
1052}
1053
1054void do_mfthi(uint32_t sel)
1055{
1056 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1057
1058 T0 = env->HI[other_tc][sel];
1059}
1060
1061void do_mftacx(uint32_t sel)
1062{
1063 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1064
1065 T0 = env->ACX[other_tc][sel];
1066}
1067
1068void do_mftdsp(void)
1069{
1070 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1071
1072 T0 = env->DSPControl[other_tc];
1073}
6af0bf9c 1074
f1aa6320
TS		 1075void do_mttgpr(uint32_t sel)
1076{
1077 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1078
1079 T0 = env->gpr[other_tc][sel];
1080}
1081
1082void do_mttlo(uint32_t sel)
1083{
1084 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1085
1086 T0 = env->LO[other_tc][sel];
1087}
1088
1089void do_mtthi(uint32_t sel)
1090{
1091 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1092
1093 T0 = env->HI[other_tc][sel];
1094}
1095
1096void do_mttacx(uint32_t sel)
1097{
1098 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1099
1100 T0 = env->ACX[other_tc][sel];
1101}
1102
1103void do_mttdsp(void)
1104{
1105 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1106
1107 T0 = env->DSPControl[other_tc];
1108}
1109
1110/* MIPS MT functions */
1111void do_dmt(void)
1112{
1113 // TODO
1114 T0 = 0;
1115 // rt = T0
1116}
1117
1118void do_emt(void)
1119{
1120 // TODO
1121 T0 = 0;
1122 // rt = T0
1123}
1124
1125void do_dvpe(void)
1126{
1127 // TODO
1128 T0 = 0;
1129 // rt = T0
1130}
1131
1132void do_evpe(void)
1133{
1134 // TODO
1135 T0 = 0;
1136 // rt = T0
1137}
1138
1139void do_fork(void)
1140{
1141 // T0 = rt, T1 = rs
1142 T0 = 0;
1143 // TODO: store to TC register
1144}
1145
1146void do_yield(void)
1147{
1148 if (T0 < 0) {
1149 /* No scheduling policy implemented. */
1150 if (T0 != -2) {
1151 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1152 env->CP0_TCStatus[env->current_tc] & (1 << CP0TCSt_DT)) {
1153 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1154 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1155 do_raise_exception(EXCP_THREAD);
1156 }
1157 }
1158 } else if (T0 == 0) {
1159 if (0 /* TODO: TC underflow */) {
1160 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1161 do_raise_exception(EXCP_THREAD);
1162 } else {
1163 // TODO: Deallocate TC
1164 }
1165 } else if (T0 > 0) {
1166 /* Yield qualifier inputs not implemented. */
1167 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1168 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1169 do_raise_exception(EXCP_THREAD);
1170 }
1171 T0 = env->CP0_YQMask;
1172}
1173
1174/* CP1 functions */
6ea83fed
FB		 1175void fpu_handle_exception(void)
1176{
1177#ifdef CONFIG_SOFTFLOAT
ead9360e 1178 int flags = get_float_exception_flags(&env->fpu->fp_status);
6ea83fed
FB		 1179 unsigned int cpuflags = 0, enable, cause = 0;
1180
ead9360e 1181 enable = GET_FP_ENABLE(env->fpu->fcr31);
6ea83fed 1182
3b46e624 1183 /* determine current flags */
6ea83fed
FB		 1184 if (flags & float_flag_invalid) {
1185 cpuflags |= FP_INVALID;
1186 cause |= FP_INVALID & enable;
1187 }
1188 if (flags & float_flag_divbyzero) {
3b46e624 1189 cpuflags |= FP_DIV0;
6ea83fed
FB		 1190 cause |= FP_DIV0 & enable;
1191 }
1192 if (flags & float_flag_overflow) {
3b46e624 1193 cpuflags |= FP_OVERFLOW;
6ea83fed
FB		 1194 cause |= FP_OVERFLOW & enable;
1195 }
1196 if (flags & float_flag_underflow) {
3b46e624 1197 cpuflags |= FP_UNDERFLOW;
6ea83fed
FB		 1198 cause |= FP_UNDERFLOW & enable;
1199 }
1200 if (flags & float_flag_inexact) {
5fafdf24 1201 cpuflags |= FP_INEXACT;
6ea83fed
FB		 1202 cause |= FP_INEXACT & enable;
1203 }
ead9360e
TS		 1204 SET_FP_FLAGS(env->fpu->fcr31, cpuflags);
1205 SET_FP_CAUSE(env->fpu->fcr31, cause);
6ea83fed 1206#else
ead9360e
TS		 1207 SET_FP_FLAGS(env->fpu->fcr31, 0);
1208 SET_FP_CAUSE(env->fpu->fcr31, 0);
6ea83fed
FB		 1209#endif
1210}
6ea83fed 1211
f1aa6320 1212#ifndef CONFIG_USER_ONLY
6af0bf9c 1213/* TLB management */
814b9a47
TS		 1214void cpu_mips_tlb_flush (CPUState *env, int flush_global)
1215{
1216 /* Flush qemu's TLB and discard all shadowed entries. */
1217 tlb_flush (env, flush_global);
ead9360e 1218 env->tlb->tlb_in_use = env->tlb->nb_tlb;
814b9a47
TS		 1219}
1220
29929e34 1221static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
814b9a47
TS		 1222{
1223 /* Discard entries from env->tlb[first] onwards. */
ead9360e
TS		 1224 while (env->tlb->tlb_in_use > first) {
1225 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
814b9a47
TS		 1226 }
1227}
1228
29929e34 1229static void r4k_fill_tlb (int idx)
6af0bf9c 1230{
29929e34 1231 r4k_tlb_t *tlb;
6af0bf9c
FB		 1232
1233 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
ead9360e 1234 tlb = &env->tlb->mmu.r4k.tlb[idx];
f2e9ebef 1235 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
d26bc211 1236#if defined(TARGET_MIPS64)
e034e2c3 1237 tlb->VPN &= env->SEGMask;
100ce988 1238#endif
98c1b82b 1239 tlb->ASID = env->CP0_EntryHi & 0xFF;
3b1c8be4 1240 tlb->PageMask = env->CP0_PageMask;
6af0bf9c 1241 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
98c1b82b
PB		 1242 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1243 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1244 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
6af0bf9c 1245 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
98c1b82b
PB		 1246 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1247 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1248 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
6af0bf9c
FB		 1249 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1250}
1251
29929e34 1252void r4k_do_tlbwi (void)
6af0bf9c 1253{
814b9a47
TS		 1254 /* Discard cached TLB entries. We could avoid doing this if the
1255 tlbwi is just upgrading access permissions on the current entry;
1256 that might be a further win. */
ead9360e 1257 r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
814b9a47 1258
ead9360e
TS		 1259 r4k_invalidate_tlb(env, env->CP0_Index % env->tlb->nb_tlb, 0);
1260 r4k_fill_tlb(env->CP0_Index % env->tlb->nb_tlb);
6af0bf9c
FB		 1261}
1262
29929e34 1263void r4k_do_tlbwr (void)
6af0bf9c
FB		 1264{
1265 int r = cpu_mips_get_random(env);
1266
29929e34
TS		 1267 r4k_invalidate_tlb(env, r, 1);
1268 r4k_fill_tlb(r);
6af0bf9c
FB		 1269}
1270
29929e34 1271void r4k_do_tlbp (void)
6af0bf9c 1272{
29929e34 1273 r4k_tlb_t *tlb;
f2e9ebef 1274 target_ulong mask;
6af0bf9c 1275 target_ulong tag;
f2e9ebef 1276 target_ulong VPN;
6af0bf9c
FB		 1277 uint8_t ASID;
1278 int i;
1279
3d9fb9fe 1280 ASID = env->CP0_EntryHi & 0xFF;
ead9360e
TS		 1281 for (i = 0; i < env->tlb->nb_tlb; i++) {
1282 tlb = &env->tlb->mmu.r4k.tlb[i];
f2e9ebef
TS		 1283 /* 1k pages are not supported. */
1284 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1285 tag = env->CP0_EntryHi & ~mask;
1286 VPN = tlb->VPN & ~mask;
6af0bf9c 1287 /* Check ASID, virtual page number & size */
f2e9ebef 1288 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
6af0bf9c 1289 /* TLB match */
9c2149c8 1290 env->CP0_Index = i;
6af0bf9c
FB		 1291 break;
1292 }
1293 }
ead9360e 1294 if (i == env->tlb->nb_tlb) {
814b9a47 1295 /* No match. Discard any shadow entries, if any of them match. */
ead9360e
TS		 1296 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1297 tlb = &env->tlb->mmu.r4k.tlb[i];
f2e9ebef
TS		 1298 /* 1k pages are not supported. */
1299 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1300 tag = env->CP0_EntryHi & ~mask;
1301 VPN = tlb->VPN & ~mask;
814b9a47 1302 /* Check ASID, virtual page number & size */
f2e9ebef 1303 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
29929e34 1304 r4k_mips_tlb_flush_extra (env, i);
814b9a47
TS		 1305 break;
1306 }
1307 }
1308
9c2149c8 1309 env->CP0_Index |= 0x80000000;
6af0bf9c
FB		 1310 }
1311}
1312
29929e34 1313void r4k_do_tlbr (void)
6af0bf9c 1314{
29929e34 1315 r4k_tlb_t *tlb;
09c56b84 1316 uint8_t ASID;
6af0bf9c 1317
09c56b84 1318 ASID = env->CP0_EntryHi & 0xFF;
ead9360e 1319 tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb];
4ad40f36
FB		 1320
1321 /* If this will change the current ASID, flush qemu's TLB. */
814b9a47
TS		 1322 if (ASID != tlb->ASID)
1323 cpu_mips_tlb_flush (env, 1);
1324
ead9360e 1325 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
4ad40f36 1326
6af0bf9c 1327 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
3b1c8be4 1328 env->CP0_PageMask = tlb->PageMask;
7495fd0f
TS		 1329 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1330 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1331 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1332 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
6af0bf9c 1333}
6af0bf9c 1334
048f6b4d
FB		 1335#endif /* !CONFIG_USER_ONLY */
1336
c570fd16 1337void dump_ldst (const unsigned char *func)
6af0bf9c
FB		 1338{
1339 if (loglevel)
3594c774 1340 fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
6af0bf9c
FB		 1341}
1342
1343void dump_sc (void)
1344{
1345 if (loglevel) {
3594c774 1346 fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
6af0bf9c
FB		 1347 T1, T0, env->CP0_LLAddr);
1348 }
1349}
1350
f41c52f1 1351void debug_pre_eret (void)
6af0bf9c 1352{
f41c52f1 1353 fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
ead9360e 1354 env->PC[env->current_tc], env->CP0_EPC);
f41c52f1
TS		 1355 if (env->CP0_Status & (1 << CP0St_ERL))
1356 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1357 if (env->hflags & MIPS_HFLAG_DM)
1358 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1359 fputs("\n", logfile);
1360}
1361
1362void debug_post_eret (void)
1363{
744e0915 1364 fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
ead9360e 1365 env->PC[env->current_tc], env->CP0_EPC);
f41c52f1
TS		 1366 if (env->CP0_Status & (1 << CP0St_ERL))
1367 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1368 if (env->hflags & MIPS_HFLAG_DM)
1369 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
623a930e
TS		 1370 switch (env->hflags & MIPS_HFLAG_KSU) {
1371 case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break;
1372 case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break;
1373 case MIPS_HFLAG_KM: fputs("\n", logfile); break;
1374 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1375 }
6af0bf9c
FB		 1376}
1377
6af0bf9c
FB		 1378void do_pmon (int function)
1379{
1380 function /= 2;
1381 switch (function) {
1382 case 2: /* TODO: char inbyte(int waitflag); */
d0dc7dc3
TS		 1383 if (env->gpr[env->current_tc][4] == 0)
1384 env->gpr[env->current_tc][2] = -1;
6af0bf9c
FB		 1385 /* Fall through */
1386 case 11: /* TODO: char inbyte (void); */
d0dc7dc3 1387 env->gpr[env->current_tc][2] = -1;
6af0bf9c
FB		 1388 break;
1389 case 3:
1390 case 12:
d0dc7dc3 1391 printf("%c", (char)(env->gpr[env->current_tc][4] & 0xFF));
6af0bf9c
FB		 1392 break;
1393 case 17:
1394 break;
1395 case 158:
1396 {
d0dc7dc3 1397 unsigned char *fmt = (void *)(unsigned long)env->gpr[env->current_tc][4];
6af0bf9c
FB		 1398 printf("%s", fmt);
1399 }
1400 break;
1401 }
1402}
e37e863f 1403
5fafdf24 1404#if !defined(CONFIG_USER_ONLY)
e37e863f 1405
4ad40f36
FB		 1406static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
1407
e37e863f 1408#define MMUSUFFIX _mmu
4ad40f36 1409#define ALIGNED_ONLY
e37e863f
FB		 1410
1411#define SHIFT 0
1412#include "softmmu_template.h"
1413
1414#define SHIFT 1
1415#include "softmmu_template.h"
1416
1417#define SHIFT 2
1418#include "softmmu_template.h"
1419
1420#define SHIFT 3
1421#include "softmmu_template.h"
1422
4ad40f36
FB		 1423static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
1424{
1425 env->CP0_BadVAddr = addr;
1426 do_restore_state (retaddr);
1427 do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
1428}
1429
6ebbf390 1430void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
e37e863f
FB		 1431{
1432 TranslationBlock *tb;
1433 CPUState *saved_env;
1434 unsigned long pc;
1435 int ret;
1436
1437 /* XXX: hack to restore env in all cases, even if not called from
1438 generated code */
1439 saved_env = env;
1440 env = cpu_single_env;
6ebbf390 1441 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
e37e863f
FB		 1442 if (ret) {
1443 if (retaddr) {
1444 /* now we have a real cpu fault */
1445 pc = (unsigned long)retaddr;
1446 tb = tb_find_pc(pc);
1447 if (tb) {
1448 /* the PC is inside the translated code. It means that we have
1449 a virtual CPU fault */
1450 cpu_restore_state(tb, env, pc, NULL);
1451 }
1452 }
1453 do_raise_exception_err(env->exception_index, env->error_code);
1454 }
1455 env = saved_env;
1456}
1457
647de6ca
TS		 1458void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1459 int unused)
1460{
1461 if (is_exec)
1462 do_raise_exception(EXCP_IBE);
1463 else
1464 do_raise_exception(EXCP_DBE);
1465}
f1aa6320 1466#endif /* !CONFIG_USER_ONLY */
fd4a04eb
TS		 1467
1468/* Complex FPU operations which may need stack space. */
1469
f090c9d4
PB		 1470#define FLOAT_ONE32 make_float32(0x3f8 << 20)
1471#define FLOAT_ONE64 make_float64(0x3ffULL << 52)
1472#define FLOAT_TWO32 make_float32(1 << 30)
1473#define FLOAT_TWO64 make_float64(1ULL << 62)
54454097
TS		 1474#define FLOAT_QNAN32 0x7fbfffff
1475#define FLOAT_QNAN64 0x7ff7ffffffffffffULL
1476#define FLOAT_SNAN32 0x7fffffff
1477#define FLOAT_SNAN64 0x7fffffffffffffffULL
8dfdb87c 1478
fd4a04eb
TS		 1479/* convert MIPS rounding mode in FCR31 to IEEE library */
1480unsigned int ieee_rm[] = {
1481 float_round_nearest_even,
1482 float_round_to_zero,
1483 float_round_up,
1484 float_round_down
1485};
1486
1487#define RESTORE_ROUNDING_MODE \
ead9360e 1488 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
fd4a04eb 1489
f1aa6320 1490void do_cfc1 (uint32_t reg)
fd4a04eb 1491{
ead9360e
TS		 1492 switch (reg) {
1493 case 0:
1494 T0 = (int32_t)env->fpu->fcr0;
1495 break;
1496 case 25:
1497 T0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1);
1498 break;
1499 case 26:
1500 T0 = env->fpu->fcr31 & 0x0003f07c;
1501 break;
1502 case 28:
1503 T0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4);
1504 break;
1505 default:
1506 T0 = (int32_t)env->fpu->fcr31;
1507 break;
1508 }
1509}
1510
f1aa6320 1511void do_ctc1 (uint32_t reg)
ead9360e
TS		 1512{
1513 switch(reg) {
fd4a04eb
TS		 1514 case 25:
1515 if (T0 & 0xffffff00)
1516 return;
ead9360e 1517 env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) |
fd4a04eb
TS		 1518 ((T0 & 0x1) << 23);
1519 break;
1520 case 26:
1521 if (T0 & 0x007c0000)
1522 return;
ead9360e 1523 env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c);
fd4a04eb
TS		 1524 break;
1525 case 28:
1526 if (T0 & 0x007c0000)
1527 return;
ead9360e 1528 env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) |
fd4a04eb
TS		 1529 ((T0 & 0x4) << 22);
1530 break;
1531 case 31:
1532 if (T0 & 0x007c0000)
1533 return;
ead9360e 1534 env->fpu->fcr31 = T0;
fd4a04eb
TS		 1535 break;
1536 default:
1537 return;
1538 }
1539 /* set rounding mode */
1540 RESTORE_ROUNDING_MODE;
ead9360e
TS		 1541 set_float_exception_flags(0, &env->fpu->fp_status);
1542 if ((GET_FP_ENABLE(env->fpu->fcr31) | 0x20) & GET_FP_CAUSE(env->fpu->fcr31))
fd4a04eb
TS		 1543 do_raise_exception(EXCP_FPE);
1544}
1545
aa343735 1546static always_inline char ieee_ex_to_mips(char xcpt)
fd4a04eb
TS		 1547{
1548 return (xcpt & float_flag_inexact) >> 5 |
1549 (xcpt & float_flag_underflow) >> 3 |
1550 (xcpt & float_flag_overflow) >> 1 |
1551 (xcpt & float_flag_divbyzero) << 1 |
1552 (xcpt & float_flag_invalid) << 4;
1553}
1554
aa343735 1555static always_inline char mips_ex_to_ieee(char xcpt)
fd4a04eb
TS		 1556{
1557 return (xcpt & FP_INEXACT) << 5 |
1558 (xcpt & FP_UNDERFLOW) << 3 |
1559 (xcpt & FP_OVERFLOW) << 1 |
1560 (xcpt & FP_DIV0) >> 1 |
1561 (xcpt & FP_INVALID) >> 4;
1562}
1563
aa343735 1564static always_inline void update_fcr31(void)
fd4a04eb 1565{
ead9360e 1566 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status));
fd4a04eb 1567
ead9360e
TS		 1568 SET_FP_CAUSE(env->fpu->fcr31, tmp);
1569 if (GET_FP_ENABLE(env->fpu->fcr31) & tmp)
fd4a04eb
TS		 1570 do_raise_exception(EXCP_FPE);
1571 else
ead9360e 1572 UPDATE_FP_FLAGS(env->fpu->fcr31, tmp);
fd4a04eb
TS		 1573}
1574
1575#define FLOAT_OP(name, p) void do_float_##name##_##p(void)
1576
1577FLOAT_OP(cvtd, s)
1578{
ead9360e
TS		 1579 set_float_exception_flags(0, &env->fpu->fp_status);
1580 FDT2 = float32_to_float64(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 1581 update_fcr31();
1582}
1583FLOAT_OP(cvtd, w)
1584{
ead9360e
TS		 1585 set_float_exception_flags(0, &env->fpu->fp_status);
1586 FDT2 = int32_to_float64(WT0, &env->fpu->fp_status);
fd4a04eb
TS		 1587 update_fcr31();
1588}
1589FLOAT_OP(cvtd, l)
1590{
ead9360e
TS		 1591 set_float_exception_flags(0, &env->fpu->fp_status);
1592 FDT2 = int64_to_float64(DT0, &env->fpu->fp_status);
fd4a04eb
TS		 1593 update_fcr31();
1594}
1595FLOAT_OP(cvtl, d)
1596{
ead9360e
TS		 1597 set_float_exception_flags(0, &env->fpu->fp_status);
1598 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
fd4a04eb 1599 update_fcr31();
ead9360e 1600 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 1601 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 1602}
1603FLOAT_OP(cvtl, s)
1604{
ead9360e
TS		 1605 set_float_exception_flags(0, &env->fpu->fp_status);
1606 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
fd4a04eb 1607 update_fcr31();
ead9360e 1608 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 1609 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 1610}
1611
1612FLOAT_OP(cvtps, pw)
1613{
ead9360e
TS		 1614 set_float_exception_flags(0, &env->fpu->fp_status);
1615 FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
1616 FSTH2 = int32_to_float32(WTH0, &env->fpu->fp_status);
fd4a04eb
TS		 1617 update_fcr31();
1618}
1619FLOAT_OP(cvtpw, ps)
1620{
ead9360e
TS		 1621 set_float_exception_flags(0, &env->fpu->fp_status);
1622 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
1623 WTH2 = float32_to_int32(FSTH0, &env->fpu->fp_status);
fd4a04eb 1624 update_fcr31();
ead9360e 1625 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 1626 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 1627}
1628FLOAT_OP(cvts, d)
1629{
ead9360e
TS		 1630 set_float_exception_flags(0, &env->fpu->fp_status);
1631 FST2 = float64_to_float32(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 1632 update_fcr31();
1633}
1634FLOAT_OP(cvts, w)
1635{
ead9360e
TS		 1636 set_float_exception_flags(0, &env->fpu->fp_status);
1637 FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
fd4a04eb
TS		 1638 update_fcr31();
1639}
1640FLOAT_OP(cvts, l)
1641{
ead9360e
TS		 1642 set_float_exception_flags(0, &env->fpu->fp_status);
1643 FST2 = int64_to_float32(DT0, &env->fpu->fp_status);
fd4a04eb
TS		 1644 update_fcr31();
1645}
1646FLOAT_OP(cvts, pl)
1647{
ead9360e 1648 set_float_exception_flags(0, &env->fpu->fp_status);
fd4a04eb
TS		 1649 WT2 = WT0;
1650 update_fcr31();
1651}
1652FLOAT_OP(cvts, pu)
1653{
ead9360e 1654 set_float_exception_flags(0, &env->fpu->fp_status);
fd4a04eb
TS		 1655 WT2 = WTH0;
1656 update_fcr31();
1657}
1658FLOAT_OP(cvtw, s)
1659{
ead9360e
TS		 1660 set_float_exception_flags(0, &env->fpu->fp_status);
1661 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
fd4a04eb 1662 update_fcr31();
ead9360e 1663 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 1664 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 1665}
1666FLOAT_OP(cvtw, d)
1667{
ead9360e
TS		 1668 set_float_exception_flags(0, &env->fpu->fp_status);
1669 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
fd4a04eb 1670 update_fcr31();
ead9360e 1671 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 1672 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 1673}
1674
1675FLOAT_OP(roundl, d)
1676{
ead9360e
TS		 1677 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
1678 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 1679 RESTORE_ROUNDING_MODE;
1680 update_fcr31();
ead9360e 1681 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 1682 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 1683}
1684FLOAT_OP(roundl, s)
1685{
ead9360e
TS		 1686 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
1687 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 1688 RESTORE_ROUNDING_MODE;
1689 update_fcr31();
ead9360e 1690 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 1691 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 1692}
1693FLOAT_OP(roundw, d)
1694{
ead9360e
TS		 1695 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
1696 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 1697 RESTORE_ROUNDING_MODE;
1698 update_fcr31();
ead9360e 1699 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 1700 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 1701}
1702FLOAT_OP(roundw, s)
1703{
ead9360e
TS		 1704 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
1705 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 1706 RESTORE_ROUNDING_MODE;
1707 update_fcr31();
ead9360e 1708 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 1709 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 1710}
1711
1712FLOAT_OP(truncl, d)
1713{
ead9360e 1714 DT2 = float64_to_int64_round_to_zero(FDT0, &env->fpu->fp_status);
fd4a04eb 1715 update_fcr31();
ead9360e 1716 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 1717 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 1718}
1719FLOAT_OP(truncl, s)
1720{
ead9360e 1721 DT2 = float32_to_int64_round_to_zero(FST0, &env->fpu->fp_status);
fd4a04eb 1722 update_fcr31();
ead9360e 1723 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 1724 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 1725}
1726FLOAT_OP(truncw, d)
1727{
ead9360e 1728 WT2 = float64_to_int32_round_to_zero(FDT0, &env->fpu->fp_status);
fd4a04eb 1729 update_fcr31();
ead9360e 1730 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 1731 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 1732}
1733FLOAT_OP(truncw, s)
1734{
ead9360e 1735 WT2 = float32_to_int32_round_to_zero(FST0, &env->fpu->fp_status);
fd4a04eb 1736 update_fcr31();
ead9360e 1737 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 1738 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 1739}
1740
1741FLOAT_OP(ceill, d)
1742{
ead9360e
TS		 1743 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
1744 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 1745 RESTORE_ROUNDING_MODE;
1746 update_fcr31();
ead9360e 1747 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 1748 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 1749}
1750FLOAT_OP(ceill, s)
1751{
ead9360e
TS		 1752 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
1753 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 1754 RESTORE_ROUNDING_MODE;
1755 update_fcr31();
ead9360e 1756 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 1757 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 1758}
1759FLOAT_OP(ceilw, d)
1760{
ead9360e
TS		 1761 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
1762 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 1763 RESTORE_ROUNDING_MODE;
1764 update_fcr31();
ead9360e 1765 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 1766 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 1767}
1768FLOAT_OP(ceilw, s)
1769{
ead9360e
TS		 1770 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
1771 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 1772 RESTORE_ROUNDING_MODE;
1773 update_fcr31();
ead9360e 1774 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 1775 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 1776}
1777
1778FLOAT_OP(floorl, d)
1779{
ead9360e
TS		 1780 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
1781 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 1782 RESTORE_ROUNDING_MODE;
1783 update_fcr31();
ead9360e 1784 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 1785 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 1786}
1787FLOAT_OP(floorl, s)
1788{
ead9360e
TS		 1789 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
1790 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 1791 RESTORE_ROUNDING_MODE;
1792 update_fcr31();
ead9360e 1793 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 1794 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 1795}
1796FLOAT_OP(floorw, d)
1797{
ead9360e
TS		 1798 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
1799 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 1800 RESTORE_ROUNDING_MODE;
1801 update_fcr31();
ead9360e 1802 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 1803 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 1804}
1805FLOAT_OP(floorw, s)
1806{
ead9360e
TS		 1807 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
1808 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 1809 RESTORE_ROUNDING_MODE;
1810 update_fcr31();
ead9360e 1811 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 1812 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 1813}
1814
8dfdb87c
TS		 1815/* MIPS specific unary operations */
1816FLOAT_OP(recip, d)
1817{
ead9360e
TS		 1818 set_float_exception_flags(0, &env->fpu->fp_status);
1819 FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
8dfdb87c
TS		 1820 update_fcr31();
1821}
1822FLOAT_OP(recip, s)
1823{
ead9360e
TS		 1824 set_float_exception_flags(0, &env->fpu->fp_status);
1825 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
8dfdb87c 1826 update_fcr31();
57fa1fb3 1827}
57fa1fb3 1828
8dfdb87c
TS		 1829FLOAT_OP(rsqrt, d)
1830{
ead9360e
TS		 1831 set_float_exception_flags(0, &env->fpu->fp_status);
1832 FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
1833 FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
8dfdb87c
TS		 1834 update_fcr31();
1835}
1836FLOAT_OP(rsqrt, s)
1837{
ead9360e
TS		 1838 set_float_exception_flags(0, &env->fpu->fp_status);
1839 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1840 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
8dfdb87c
TS		 1841 update_fcr31();
1842}
1843
1844FLOAT_OP(recip1, d)
1845{
ead9360e
TS		 1846 set_float_exception_flags(0, &env->fpu->fp_status);
1847 FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
8dfdb87c
TS		 1848 update_fcr31();
1849}
1850FLOAT_OP(recip1, s)
1851{
ead9360e
TS		 1852 set_float_exception_flags(0, &env->fpu->fp_status);
1853 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
8dfdb87c
TS		 1854 update_fcr31();
1855}
1856FLOAT_OP(recip1, ps)
1857{
ead9360e
TS		 1858 set_float_exception_flags(0, &env->fpu->fp_status);
1859 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
1860 FSTH2 = float32_div(FLOAT_ONE32, FSTH0, &env->fpu->fp_status);
8dfdb87c
TS		 1861 update_fcr31();
1862}
1863
1864FLOAT_OP(rsqrt1, d)
1865{
ead9360e
TS		 1866 set_float_exception_flags(0, &env->fpu->fp_status);
1867 FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
1868 FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
8dfdb87c
TS		 1869 update_fcr31();
1870}
1871FLOAT_OP(rsqrt1, s)
1872{
ead9360e
TS		 1873 set_float_exception_flags(0, &env->fpu->fp_status);
1874 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1875 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
8dfdb87c
TS		 1876 update_fcr31();
1877}
1878FLOAT_OP(rsqrt1, ps)
1879{
ead9360e
TS		 1880 set_float_exception_flags(0, &env->fpu->fp_status);
1881 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1882 FSTH2 = float32_sqrt(FSTH0, &env->fpu->fp_status);
1883 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
1884 FSTH2 = float32_div(FLOAT_ONE32, FSTH2, &env->fpu->fp_status);
8dfdb87c 1885 update_fcr31();
57fa1fb3 1886}
57fa1fb3 1887
fd4a04eb
TS		 1888/* binary operations */
1889#define FLOAT_BINOP(name) \
1890FLOAT_OP(name, d) \
1891{ \
ead9360e
TS		 1892 set_float_exception_flags(0, &env->fpu->fp_status); \
1893 FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \
1894 update_fcr31(); \
1895 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
5747c073 1896 DT2 = FLOAT_QNAN64; \
fd4a04eb
TS		 1897} \
1898FLOAT_OP(name, s) \
1899{ \
ead9360e
TS		 1900 set_float_exception_flags(0, &env->fpu->fp_status); \
1901 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
1902 update_fcr31(); \
1903 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
5747c073 1904 WT2 = FLOAT_QNAN32; \
fd4a04eb
TS		 1905} \
1906FLOAT_OP(name, ps) \
1907{ \
ead9360e
TS		 1908 set_float_exception_flags(0, &env->fpu->fp_status); \
1909 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
1910 FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \
fd4a04eb 1911 update_fcr31(); \
ead9360e 1912 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
5747c073
PB		 1913 WT2 = FLOAT_QNAN32; \
1914 WTH2 = FLOAT_QNAN32; \
3a5b360d 1915 } \
fd4a04eb
TS		 1916}
1917FLOAT_BINOP(add)
1918FLOAT_BINOP(sub)
1919FLOAT_BINOP(mul)
1920FLOAT_BINOP(div)
1921#undef FLOAT_BINOP
1922
8dfdb87c
TS		 1923/* MIPS specific binary operations */
1924FLOAT_OP(recip2, d)
1925{
ead9360e
TS		 1926 set_float_exception_flags(0, &env->fpu->fp_status);
1927 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
5747c073 1928 FDT2 = float64_chs(float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status));
8dfdb87c
TS		 1929 update_fcr31();
1930}
1931FLOAT_OP(recip2, s)
1932{
ead9360e
TS		 1933 set_float_exception_flags(0, &env->fpu->fp_status);
1934 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
5747c073 1935 FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
8dfdb87c
TS		 1936 update_fcr31();
1937}
1938FLOAT_OP(recip2, ps)
1939{
ead9360e
TS		 1940 set_float_exception_flags(0, &env->fpu->fp_status);
1941 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1942 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
5747c073
PB		 1943 FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
1944 FSTH2 = float32_chs(float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status));
8dfdb87c
TS		 1945 update_fcr31();
1946}
1947
1948FLOAT_OP(rsqrt2, d)
1949{
ead9360e
TS		 1950 set_float_exception_flags(0, &env->fpu->fp_status);
1951 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
1952 FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status);
5747c073 1953 FDT2 = float64_chs(float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status));
8dfdb87c
TS		 1954 update_fcr31();
1955}
1956FLOAT_OP(rsqrt2, s)
1957{
ead9360e
TS		 1958 set_float_exception_flags(0, &env->fpu->fp_status);
1959 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1960 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
5747c073 1961 FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
8dfdb87c
TS		 1962 update_fcr31();
1963}
1964FLOAT_OP(rsqrt2, ps)
1965{
ead9360e
TS		 1966 set_float_exception_flags(0, &env->fpu->fp_status);
1967 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1968 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
1969 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
1970 FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status);
5747c073
PB		 1971 FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
1972 FSTH2 = float32_chs(float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status));
8dfdb87c 1973 update_fcr31();
57fa1fb3 1974}
57fa1fb3 1975
fd4a04eb
TS		 1976FLOAT_OP(addr, ps)
1977{
ead9360e
TS		 1978 set_float_exception_flags(0, &env->fpu->fp_status);
1979 FST2 = float32_add (FST0, FSTH0, &env->fpu->fp_status);
1980 FSTH2 = float32_add (FST1, FSTH1, &env->fpu->fp_status);
fd4a04eb
TS		 1981 update_fcr31();
1982}
1983
57fa1fb3
TS		 1984FLOAT_OP(mulr, ps)
1985{
ead9360e
TS		 1986 set_float_exception_flags(0, &env->fpu->fp_status);
1987 FST2 = float32_mul (FST0, FSTH0, &env->fpu->fp_status);
1988 FSTH2 = float32_mul (FST1, FSTH1, &env->fpu->fp_status);
57fa1fb3
TS		 1989 update_fcr31();
1990}
1991
8dfdb87c 1992/* compare operations */
fd4a04eb
TS		 1993#define FOP_COND_D(op, cond) \
1994void do_cmp_d_ ## op (long cc) \
1995{ \
1996 int c = cond; \
1997 update_fcr31(); \
1998 if (c) \
ead9360e 1999 SET_FP_COND(cc, env->fpu); \
fd4a04eb 2000 else \
ead9360e 2001 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb
TS		 2002} \
2003void do_cmpabs_d_ ## op (long cc) \
2004{ \
2005 int c; \
6b5435d7
TS		 2006 FDT0 = float64_abs(FDT0); \
2007 FDT1 = float64_abs(FDT1); \
fd4a04eb
TS		 2008 c = cond; \
2009 update_fcr31(); \
2010 if (c) \
ead9360e 2011 SET_FP_COND(cc, env->fpu); \
fd4a04eb 2012 else \
ead9360e 2013 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb
TS		 2014}
2015
2016int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
2017{
2018 if (float64_is_signaling_nan(a) ||
2019 float64_is_signaling_nan(b) ||
2020 (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
2021 float_raise(float_flag_invalid, status);
2022 return 1;
2023 } else if (float64_is_nan(a) || float64_is_nan(b)) {
2024 return 1;
2025 } else {
2026 return 0;
2027 }
2028}
2029
2030/* NOTE: the comma operator will make "cond" to eval to false,
2031 * but float*_is_unordered() is still called. */
ead9360e
TS		 2032FOP_COND_D(f, (float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status), 0))
2033FOP_COND_D(un, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status))
2034FOP_COND_D(eq, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
2035FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
2036FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
2037FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
2038FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
2039FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
fd4a04eb
TS		 2040/* NOTE: the comma operator will make "cond" to eval to false,
2041 * but float*_is_unordered() is still called. */
ead9360e
TS		 2042FOP_COND_D(sf, (float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status), 0))
2043FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status))
2044FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
2045FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
2046FOP_COND_D(lt, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
2047FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
2048FOP_COND_D(le, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
2049FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
fd4a04eb
TS		 2050
2051#define FOP_COND_S(op, cond) \
2052void do_cmp_s_ ## op (long cc) \
2053{ \
2054 int c = cond; \
2055 update_fcr31(); \
2056 if (c) \
ead9360e 2057 SET_FP_COND(cc, env->fpu); \
fd4a04eb 2058 else \
ead9360e 2059 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb
TS		 2060} \
2061void do_cmpabs_s_ ## op (long cc) \
2062{ \
2063 int c; \
5747c073
PB		 2064 FST0 = float32_abs(FST0); \
2065 FST1 = float32_abs(FST1); \
fd4a04eb
TS		 2066 c = cond; \
2067 update_fcr31(); \
2068 if (c) \
ead9360e 2069 SET_FP_COND(cc, env->fpu); \
fd4a04eb 2070 else \
ead9360e 2071 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb
TS		 2072}
2073
2074flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
2075{
fd4a04eb
TS		 2076 if (float32_is_signaling_nan(a) ||
2077 float32_is_signaling_nan(b) ||
2078 (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
2079 float_raise(float_flag_invalid, status);
2080 return 1;
2081 } else if (float32_is_nan(a) || float32_is_nan(b)) {
2082 return 1;
2083 } else {
2084 return 0;
2085 }
2086}
2087
2088/* NOTE: the comma operator will make "cond" to eval to false,
2089 * but float*_is_unordered() is still called. */
ead9360e
TS		 2090FOP_COND_S(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0))
2091FOP_COND_S(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status))
2092FOP_COND_S(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
2093FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
2094FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
2095FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
2096FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
2097FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
fd4a04eb
TS		 2098/* NOTE: the comma operator will make "cond" to eval to false,
2099 * but float*_is_unordered() is still called. */
ead9360e
TS		 2100FOP_COND_S(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0))
2101FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status))
2102FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
2103FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
2104FOP_COND_S(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
2105FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
2106FOP_COND_S(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
2107FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
fd4a04eb
TS		 2108
2109#define FOP_COND_PS(op, condl, condh) \
2110void do_cmp_ps_ ## op (long cc) \
2111{ \
2112 int cl = condl; \
2113 int ch = condh; \
2114 update_fcr31(); \
2115 if (cl) \
ead9360e 2116 SET_FP_COND(cc, env->fpu); \
fd4a04eb 2117 else \
ead9360e 2118 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb 2119 if (ch) \
ead9360e 2120 SET_FP_COND(cc + 1, env->fpu); \
fd4a04eb 2121 else \
ead9360e 2122 CLEAR_FP_COND(cc + 1, env->fpu); \
fd4a04eb
TS		 2123} \
2124void do_cmpabs_ps_ ## op (long cc) \
2125{ \
2126 int cl, ch; \
5747c073
PB		 2127 FST0 = float32_abs(FST0); \
2128 FSTH0 = float32_abs(FSTH0); \
2129 FST1 = float32_abs(FST1); \
2130 FSTH1 = float32_abs(FSTH1); \
fd4a04eb
TS		 2131 cl = condl; \
2132 ch = condh; \
2133 update_fcr31(); \
2134 if (cl) \
ead9360e 2135 SET_FP_COND(cc, env->fpu); \
fd4a04eb 2136 else \
ead9360e 2137 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb 2138 if (ch) \
ead9360e 2139 SET_FP_COND(cc + 1, env->fpu); \
fd4a04eb 2140 else \
ead9360e 2141 CLEAR_FP_COND(cc + 1, env->fpu); \
fd4a04eb
TS		 2142}
2143
2144/* NOTE: the comma operator will make "cond" to eval to false,
2145 * but float*_is_unordered() is still called. */
ead9360e
TS		 2146FOP_COND_PS(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0),
2147 (float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status), 0))
2148FOP_COND_PS(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status),
2149 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status))
2150FOP_COND_PS(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
2151 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
2152FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
2153 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
2154FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
2155 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
2156FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
2157 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
2158FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
2159 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
2160FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
2161 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
fd4a04eb
TS		 2162/* NOTE: the comma operator will make "cond" to eval to false,
2163 * but float*_is_unordered() is still called. */
ead9360e
TS		 2164FOP_COND_PS(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0),
2165 (float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status), 0))
2166FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status),
2167 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status))
2168FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
2169 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
2170FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
2171 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
2172FOP_COND_PS(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
2173 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
2174FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
2175 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
2176FOP_COND_PS(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
2177 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
2178FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
2179 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
Qemu copy for testing