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[qemu.git] / target-mips / op_helper.c
CommitLineData
6af0bf9c
FB		 1/*
2 * MIPS emulation helpers for qemu.
5fafdf24 3 *
6af0bf9c
FB		 4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
2d0e944d 20#include <stdlib.h>
6af0bf9c
FB		 21#include "exec.h"
22
05f778c8
TS		 23#include "host-utils.h"
24
273af660
TS		 25#ifdef __s390__
26# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
27#else
28# define GETPC() (__builtin_return_address(0))
29#endif
4ad40f36 30
6af0bf9c
FB		 31/*****************************************************************************/
32/* Exceptions processing helpers */
6af0bf9c 33
6af0bf9c
FB		 34void do_raise_exception_err (uint32_t exception, int error_code)
35{
36#if 1
37 if (logfile && exception < 0x100)
38 fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
39#endif
40 env->exception_index = exception;
41 env->error_code = error_code;
42 T0 = 0;
43 cpu_loop_exit();
44}
45
6af0bf9c
FB		 46void do_raise_exception (uint32_t exception)
47{
48 do_raise_exception_err(exception, 0);
49}
50
4ad40f36
FB		 51void do_restore_state (void *pc_ptr)
52{
53 TranslationBlock *tb;
54 unsigned long pc = (unsigned long) pc_ptr;
55
56 tb = tb_find_pc (pc);
57 cpu_restore_state (tb, env, pc, NULL);
58}
59
e397ee33 60void do_raise_exception_direct_err (uint32_t exception, int error_code)
4ad40f36
FB		 61{
62 do_restore_state (GETPC ());
e397ee33
TS		 63 do_raise_exception_err (exception, error_code);
64}
65
66void do_raise_exception_direct (uint32_t exception)
67{
68 do_raise_exception_direct_err (exception, 0);
4ad40f36
FB		 69}
70
d26bc211 71#if defined(TARGET_MIPS64)
c570fd16
TS		 72#if TARGET_LONG_BITS > HOST_LONG_BITS
73/* Those might call libgcc functions. */
74void do_dsll (void)
75{
76 T0 = T0 << T1;
77}
78
79void do_dsll32 (void)
80{
81 T0 = T0 << (T1 + 32);
82}
83
84void do_dsra (void)
85{
86 T0 = (int64_t)T0 >> T1;
87}
88
89void do_dsra32 (void)
90{
91 T0 = (int64_t)T0 >> (T1 + 32);
92}
93
94void do_dsrl (void)
95{
96 T0 = T0 >> T1;
97}
98
99void do_dsrl32 (void)
100{
101 T0 = T0 >> (T1 + 32);
102}
103
104void do_drotr (void)
105{
106 target_ulong tmp;
107
108 if (T1) {
c6d6dd7c
TS		 109 tmp = T0 << (0x40 - T1);
110 T0 = (T0 >> T1) | tmp;
5a63bcb2 111 }
c570fd16
TS		 112}
113
114void do_drotr32 (void)
115{
116 target_ulong tmp;
117
c6d6dd7c
TS		 118 tmp = T0 << (0x40 - (32 + T1));
119 T0 = (T0 >> (32 + T1)) | tmp;
c570fd16
TS		 120}
121
122void do_dsllv (void)
123{
124 T0 = T1 << (T0 & 0x3F);
125}
126
127void do_dsrav (void)
128{
129 T0 = (int64_t)T1 >> (T0 & 0x3F);
130}
131
132void do_dsrlv (void)
133{
134 T0 = T1 >> (T0 & 0x3F);
135}
136
137void do_drotrv (void)
138{
139 target_ulong tmp;
140
141 T0 &= 0x3F;
142 if (T0) {
c6d6dd7c
TS		 143 tmp = T1 << (0x40 - T0);
144 T0 = (T1 >> T0) | tmp;
c570fd16 145 } else
c6d6dd7c 146 T0 = T1;
c570fd16 147}
05f778c8
TS		 148
149void do_dclo (void)
150{
151 T0 = clo64(T0);
152}
153
154void do_dclz (void)
155{
156 T0 = clz64(T0);
157}
158
c570fd16 159#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
d26bc211 160#endif /* TARGET_MIPS64 */
c570fd16 161
6af0bf9c 162/* 64 bits arithmetic for 32 bits hosts */
c570fd16 163#if TARGET_LONG_BITS > HOST_LONG_BITS
aa343735 164static always_inline uint64_t get_HILO (void)
6af0bf9c 165{
ead9360e 166 return (env->HI[0][env->current_tc] << 32) | (uint32_t)env->LO[0][env->current_tc];
6af0bf9c
FB		 167}
168
aa343735 169static always_inline void set_HILO (uint64_t HILO)
6af0bf9c 170{
ead9360e
TS		 171 env->LO[0][env->current_tc] = (int32_t)HILO;
172 env->HI[0][env->current_tc] = (int32_t)(HILO >> 32);
6af0bf9c
FB		 173}
174
175void do_mult (void)
176{
4ad40f36 177 set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
6af0bf9c
FB		 178}
179
180void do_multu (void)
181{
c570fd16 182 set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
6af0bf9c
FB		 183}
184
185void do_madd (void)
186{
187 int64_t tmp;
188
4ad40f36 189 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
6af0bf9c
FB		 190 set_HILO((int64_t)get_HILO() + tmp);
191}
192
193void do_maddu (void)
194{
195 uint64_t tmp;
196
c570fd16 197 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
6af0bf9c
FB		 198 set_HILO(get_HILO() + tmp);
199}
200
201void do_msub (void)
202{
203 int64_t tmp;
204
4ad40f36 205 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
6af0bf9c
FB		 206 set_HILO((int64_t)get_HILO() - tmp);
207}
208
209void do_msubu (void)
210{
211 uint64_t tmp;
212
c570fd16 213 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
6af0bf9c
FB		 214 set_HILO(get_HILO() - tmp);
215}
216#endif
217
80c27194
TS		 218#if HOST_LONG_BITS < 64
219void do_div (void)
220{
221 /* 64bit datatypes because we may see overflow/underflow. */
222 if (T1 != 0) {
ead9360e
TS		 223 env->LO[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
224 env->HI[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
80c27194
TS		 225 }
226}
227#endif
228
d26bc211 229#if defined(TARGET_MIPS64)
c570fd16
TS		 230void do_ddiv (void)
231{
232 if (T1 != 0) {
306ab3e8
TS		 233 int64_t arg0 = (int64_t)T0;
234 int64_t arg1 = (int64_t)T1;
235 if (arg0 == ((int64_t)-1 << 63) && arg1 == (int64_t)-1) {
236 env->LO[0][env->current_tc] = arg0;
237 env->HI[0][env->current_tc] = 0;
238 } else {
239 lldiv_t res = lldiv(arg0, arg1);
240 env->LO[0][env->current_tc] = res.quot;
241 env->HI[0][env->current_tc] = res.rem;
242 }
c570fd16
TS		 243 }
244}
245
12a4b2aa 246#if TARGET_LONG_BITS > HOST_LONG_BITS
c570fd16
TS		 247void do_ddivu (void)
248{
249 if (T1 != 0) {
ead9360e
TS		 250 env->LO[0][env->current_tc] = T0 / T1;
251 env->HI[0][env->current_tc] = T0 % T1;
c570fd16
TS		 252 }
253}
254#endif
d26bc211 255#endif /* TARGET_MIPS64 */
c570fd16 256
5fafdf24 257#if defined(CONFIG_USER_ONLY)
873eb012 258void do_mfc0_random (void)
048f6b4d 259{
873eb012 260 cpu_abort(env, "mfc0 random\n");
048f6b4d 261}
873eb012
TS		 262
263void do_mfc0_count (void)
264{
265 cpu_abort(env, "mfc0 count\n");
266}
267
8c0fdd85 268void cpu_mips_store_count(CPUState *env, uint32_t value)
048f6b4d 269{
8c0fdd85
TS		 270 cpu_abort(env, "mtc0 count\n");
271}
272
273void cpu_mips_store_compare(CPUState *env, uint32_t value)
274{
275 cpu_abort(env, "mtc0 compare\n");
276}
277
42532189
TS		 278void cpu_mips_start_count(CPUState *env)
279{
280 cpu_abort(env, "start count\n");
281}
282
283void cpu_mips_stop_count(CPUState *env)
284{
285 cpu_abort(env, "stop count\n");
286}
287
4de9b249
TS		 288void cpu_mips_update_irq(CPUState *env)
289{
290 cpu_abort(env, "mtc0 status / mtc0 cause\n");
291}
292
8c0fdd85
TS		 293void do_mtc0_status_debug(uint32_t old, uint32_t val)
294{
7a387fff 295 cpu_abort(env, "mtc0 status debug\n");
8c0fdd85
TS		 296}
297
7a387fff 298void do_mtc0_status_irqraise_debug (void)
8c0fdd85 299{
7a387fff 300 cpu_abort(env, "mtc0 status irqraise debug\n");
048f6b4d
FB		 301}
302
8c0fdd85
TS		 303void cpu_mips_tlb_flush (CPUState *env, int flush_global)
304{
305 cpu_abort(env, "mips_tlb_flush\n");
306}
307
048f6b4d
FB		 308#else
309
6af0bf9c 310/* CP0 helpers */
873eb012 311void do_mfc0_random (void)
6af0bf9c 312{
5dc4b744 313 T0 = (int32_t)cpu_mips_get_random(env);
873eb012 314}
6af0bf9c 315
873eb012
TS		 316void do_mfc0_count (void)
317{
5dc4b744 318 T0 = (int32_t)cpu_mips_get_count(env);
6af0bf9c
FB		 319}
320
8c0fdd85 321void do_mtc0_status_debug(uint32_t old, uint32_t val)
6af0bf9c 322{
f41c52f1
TS		 323 fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
324 old, old & env->CP0_Cause & CP0Ca_IP_mask,
325 val, val & env->CP0_Cause & CP0Ca_IP_mask,
326 env->CP0_Cause);
623a930e
TS		 327 switch (env->hflags & MIPS_HFLAG_KSU) {
328 case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break;
329 case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break;
330 case MIPS_HFLAG_KM: fputs("\n", logfile); break;
331 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
332 }
8c0fdd85
TS		 333}
334
335void do_mtc0_status_irqraise_debug(void)
336{
337 fprintf(logfile, "Raise pending IRQs\n");
6af0bf9c
FB		 338}
339
6ea83fed
FB		 340void fpu_handle_exception(void)
341{
342#ifdef CONFIG_SOFTFLOAT
ead9360e 343 int flags = get_float_exception_flags(&env->fpu->fp_status);
6ea83fed
FB		 344 unsigned int cpuflags = 0, enable, cause = 0;
345
ead9360e 346 enable = GET_FP_ENABLE(env->fpu->fcr31);
6ea83fed 347
3b46e624 348 /* determine current flags */
6ea83fed
FB		 349 if (flags & float_flag_invalid) {
350 cpuflags |= FP_INVALID;
351 cause |= FP_INVALID & enable;
352 }
353 if (flags & float_flag_divbyzero) {
3b46e624 354 cpuflags |= FP_DIV0;
6ea83fed
FB		 355 cause |= FP_DIV0 & enable;
356 }
357 if (flags & float_flag_overflow) {
3b46e624 358 cpuflags |= FP_OVERFLOW;
6ea83fed
FB		 359 cause |= FP_OVERFLOW & enable;
360 }
361 if (flags & float_flag_underflow) {
3b46e624 362 cpuflags |= FP_UNDERFLOW;
6ea83fed
FB		 363 cause |= FP_UNDERFLOW & enable;
364 }
365 if (flags & float_flag_inexact) {
5fafdf24 366 cpuflags |= FP_INEXACT;
6ea83fed
FB		 367 cause |= FP_INEXACT & enable;
368 }
ead9360e
TS		 369 SET_FP_FLAGS(env->fpu->fcr31, cpuflags);
370 SET_FP_CAUSE(env->fpu->fcr31, cause);
6ea83fed 371#else
ead9360e
TS		 372 SET_FP_FLAGS(env->fpu->fcr31, 0);
373 SET_FP_CAUSE(env->fpu->fcr31, 0);
6ea83fed
FB		 374#endif
375}
6ea83fed 376
6af0bf9c 377/* TLB management */
814b9a47
TS		 378void cpu_mips_tlb_flush (CPUState *env, int flush_global)
379{
380 /* Flush qemu's TLB and discard all shadowed entries. */
381 tlb_flush (env, flush_global);
ead9360e 382 env->tlb->tlb_in_use = env->tlb->nb_tlb;
814b9a47
TS		 383}
384
29929e34 385static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
814b9a47
TS		 386{
387 /* Discard entries from env->tlb[first] onwards. */
ead9360e
TS		 388 while (env->tlb->tlb_in_use > first) {
389 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
814b9a47
TS		 390 }
391}
392
29929e34 393static void r4k_fill_tlb (int idx)
6af0bf9c 394{
29929e34 395 r4k_tlb_t *tlb;
6af0bf9c
FB		 396
397 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
ead9360e 398 tlb = &env->tlb->mmu.r4k.tlb[idx];
f2e9ebef 399 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
d26bc211 400#if defined(TARGET_MIPS64)
e034e2c3 401 tlb->VPN &= env->SEGMask;
100ce988 402#endif
98c1b82b 403 tlb->ASID = env->CP0_EntryHi & 0xFF;
3b1c8be4 404 tlb->PageMask = env->CP0_PageMask;
6af0bf9c 405 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
98c1b82b
PB		 406 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
407 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
408 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
6af0bf9c 409 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
98c1b82b
PB		 410 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
411 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
412 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
6af0bf9c
FB		 413 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
414}
415
29929e34 416void r4k_do_tlbwi (void)
6af0bf9c 417{
814b9a47
TS		 418 /* Discard cached TLB entries. We could avoid doing this if the
419 tlbwi is just upgrading access permissions on the current entry;
420 that might be a further win. */
ead9360e 421 r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
814b9a47 422
ead9360e
TS		 423 r4k_invalidate_tlb(env, env->CP0_Index % env->tlb->nb_tlb, 0);
424 r4k_fill_tlb(env->CP0_Index % env->tlb->nb_tlb);
6af0bf9c
FB		 425}
426
29929e34 427void r4k_do_tlbwr (void)
6af0bf9c
FB		 428{
429 int r = cpu_mips_get_random(env);
430
29929e34
TS		 431 r4k_invalidate_tlb(env, r, 1);
432 r4k_fill_tlb(r);
6af0bf9c
FB		 433}
434
29929e34 435void r4k_do_tlbp (void)
6af0bf9c 436{
29929e34 437 r4k_tlb_t *tlb;
f2e9ebef 438 target_ulong mask;
6af0bf9c 439 target_ulong tag;
f2e9ebef 440 target_ulong VPN;
6af0bf9c
FB		 441 uint8_t ASID;
442 int i;
443
3d9fb9fe 444 ASID = env->CP0_EntryHi & 0xFF;
ead9360e
TS		 445 for (i = 0; i < env->tlb->nb_tlb; i++) {
446 tlb = &env->tlb->mmu.r4k.tlb[i];
f2e9ebef
TS		 447 /* 1k pages are not supported. */
448 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
449 tag = env->CP0_EntryHi & ~mask;
450 VPN = tlb->VPN & ~mask;
6af0bf9c 451 /* Check ASID, virtual page number & size */
f2e9ebef 452 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
6af0bf9c 453 /* TLB match */
9c2149c8 454 env->CP0_Index = i;
6af0bf9c
FB		 455 break;
456 }
457 }
ead9360e 458 if (i == env->tlb->nb_tlb) {
814b9a47 459 /* No match. Discard any shadow entries, if any of them match. */
ead9360e
TS		 460 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
461 tlb = &env->tlb->mmu.r4k.tlb[i];
f2e9ebef
TS		 462 /* 1k pages are not supported. */
463 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
464 tag = env->CP0_EntryHi & ~mask;
465 VPN = tlb->VPN & ~mask;
814b9a47 466 /* Check ASID, virtual page number & size */
f2e9ebef 467 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
29929e34 468 r4k_mips_tlb_flush_extra (env, i);
814b9a47
TS		 469 break;
470 }
471 }
472
9c2149c8 473 env->CP0_Index |= 0x80000000;
6af0bf9c
FB		 474 }
475}
476
29929e34 477void r4k_do_tlbr (void)
6af0bf9c 478{
29929e34 479 r4k_tlb_t *tlb;
09c56b84 480 uint8_t ASID;
6af0bf9c 481
09c56b84 482 ASID = env->CP0_EntryHi & 0xFF;
ead9360e 483 tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb];
4ad40f36
FB		 484
485 /* If this will change the current ASID, flush qemu's TLB. */
814b9a47
TS		 486 if (ASID != tlb->ASID)
487 cpu_mips_tlb_flush (env, 1);
488
ead9360e 489 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
4ad40f36 490
6af0bf9c 491 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
3b1c8be4 492 env->CP0_PageMask = tlb->PageMask;
7495fd0f
TS		 493 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
494 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
495 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
496 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
6af0bf9c 497}
6af0bf9c 498
048f6b4d
FB		 499#endif /* !CONFIG_USER_ONLY */
500
c570fd16 501void dump_ldst (const unsigned char *func)
6af0bf9c
FB		 502{
503 if (loglevel)
3594c774 504 fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
6af0bf9c
FB		 505}
506
507void dump_sc (void)
508{
509 if (loglevel) {
3594c774 510 fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
6af0bf9c
FB		 511 T1, T0, env->CP0_LLAddr);
512 }
513}
514
f41c52f1 515void debug_pre_eret (void)
6af0bf9c 516{
f41c52f1 517 fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
ead9360e 518 env->PC[env->current_tc], env->CP0_EPC);
f41c52f1
TS		 519 if (env->CP0_Status & (1 << CP0St_ERL))
520 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
521 if (env->hflags & MIPS_HFLAG_DM)
522 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
523 fputs("\n", logfile);
524}
525
526void debug_post_eret (void)
527{
744e0915 528 fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
ead9360e 529 env->PC[env->current_tc], env->CP0_EPC);
f41c52f1
TS		 530 if (env->CP0_Status & (1 << CP0St_ERL))
531 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
532 if (env->hflags & MIPS_HFLAG_DM)
533 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
623a930e
TS		 534 switch (env->hflags & MIPS_HFLAG_KSU) {
535 case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break;
536 case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break;
537 case MIPS_HFLAG_KM: fputs("\n", logfile); break;
538 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
539 }
6af0bf9c
FB		 540}
541
6af0bf9c
FB		 542void do_pmon (int function)
543{
544 function /= 2;
545 switch (function) {
546 case 2: /* TODO: char inbyte(int waitflag); */
ead9360e
TS		 547 if (env->gpr[4][env->current_tc] == 0)
548 env->gpr[2][env->current_tc] = -1;
6af0bf9c
FB		 549 /* Fall through */
550 case 11: /* TODO: char inbyte (void); */
ead9360e 551 env->gpr[2][env->current_tc] = -1;
6af0bf9c
FB		 552 break;
553 case 3:
554 case 12:
ead9360e 555 printf("%c", (char)(env->gpr[4][env->current_tc] & 0xFF));
6af0bf9c
FB		 556 break;
557 case 17:
558 break;
559 case 158:
560 {
ead9360e 561 unsigned char *fmt = (void *)(unsigned long)env->gpr[4][env->current_tc];
6af0bf9c
FB		 562 printf("%s", fmt);
563 }
564 break;
565 }
566}
e37e863f 567
5fafdf24 568#if !defined(CONFIG_USER_ONLY)
e37e863f 569
4ad40f36
FB		 570static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
571
e37e863f 572#define MMUSUFFIX _mmu
4ad40f36 573#define ALIGNED_ONLY
e37e863f
FB		 574
575#define SHIFT 0
576#include "softmmu_template.h"
577
578#define SHIFT 1
579#include "softmmu_template.h"
580
581#define SHIFT 2
582#include "softmmu_template.h"
583
584#define SHIFT 3
585#include "softmmu_template.h"
586
4ad40f36
FB		 587static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
588{
589 env->CP0_BadVAddr = addr;
590 do_restore_state (retaddr);
591 do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
592}
593
6ebbf390 594void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
e37e863f
FB		 595{
596 TranslationBlock *tb;
597 CPUState *saved_env;
598 unsigned long pc;
599 int ret;
600
601 /* XXX: hack to restore env in all cases, even if not called from
602 generated code */
603 saved_env = env;
604 env = cpu_single_env;
6ebbf390 605 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
e37e863f
FB		 606 if (ret) {
607 if (retaddr) {
608 /* now we have a real cpu fault */
609 pc = (unsigned long)retaddr;
610 tb = tb_find_pc(pc);
611 if (tb) {
612 /* the PC is inside the translated code. It means that we have
613 a virtual CPU fault */
614 cpu_restore_state(tb, env, pc, NULL);
615 }
616 }
617 do_raise_exception_err(env->exception_index, env->error_code);
618 }
619 env = saved_env;
620}
621
647de6ca
TS		 622void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
623 int unused)
624{
625 if (is_exec)
626 do_raise_exception(EXCP_IBE);
627 else
628 do_raise_exception(EXCP_DBE);
629}
e37e863f 630#endif
fd4a04eb
TS		 631
632/* Complex FPU operations which may need stack space. */
633
f090c9d4
PB		 634#define FLOAT_ONE32 make_float32(0x3f8 << 20)
635#define FLOAT_ONE64 make_float64(0x3ffULL << 52)
636#define FLOAT_TWO32 make_float32(1 << 30)
637#define FLOAT_TWO64 make_float64(1ULL << 62)
54454097
TS		 638#define FLOAT_QNAN32 0x7fbfffff
639#define FLOAT_QNAN64 0x7ff7ffffffffffffULL
640#define FLOAT_SNAN32 0x7fffffff
641#define FLOAT_SNAN64 0x7fffffffffffffffULL
8dfdb87c 642
fd4a04eb
TS		 643/* convert MIPS rounding mode in FCR31 to IEEE library */
644unsigned int ieee_rm[] = {
645 float_round_nearest_even,
646 float_round_to_zero,
647 float_round_up,
648 float_round_down
649};
650
651#define RESTORE_ROUNDING_MODE \
ead9360e 652 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
fd4a04eb 653
ead9360e 654void do_cfc1 (int reg)
fd4a04eb 655{
ead9360e
TS		 656 switch (reg) {
657 case 0:
658 T0 = (int32_t)env->fpu->fcr0;
659 break;
660 case 25:
661 T0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1);
662 break;
663 case 26:
664 T0 = env->fpu->fcr31 & 0x0003f07c;
665 break;
666 case 28:
667 T0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4);
668 break;
669 default:
670 T0 = (int32_t)env->fpu->fcr31;
671 break;
672 }
673}
674
675void do_ctc1 (int reg)
676{
677 switch(reg) {
fd4a04eb
TS		 678 case 25:
679 if (T0 & 0xffffff00)
680 return;
ead9360e 681 env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) |
fd4a04eb
TS		 682 ((T0 & 0x1) << 23);
683 break;
684 case 26:
685 if (T0 & 0x007c0000)
686 return;
ead9360e 687 env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c);
fd4a04eb
TS		 688 break;
689 case 28:
690 if (T0 & 0x007c0000)
691 return;
ead9360e 692 env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) |
fd4a04eb
TS		 693 ((T0 & 0x4) << 22);
694 break;
695 case 31:
696 if (T0 & 0x007c0000)
697 return;
ead9360e 698 env->fpu->fcr31 = T0;
fd4a04eb
TS		 699 break;
700 default:
701 return;
702 }
703 /* set rounding mode */
704 RESTORE_ROUNDING_MODE;
ead9360e
TS		 705 set_float_exception_flags(0, &env->fpu->fp_status);
706 if ((GET_FP_ENABLE(env->fpu->fcr31) | 0x20) & GET_FP_CAUSE(env->fpu->fcr31))
fd4a04eb
TS		 707 do_raise_exception(EXCP_FPE);
708}
709
aa343735 710static always_inline char ieee_ex_to_mips(char xcpt)
fd4a04eb
TS		 711{
712 return (xcpt & float_flag_inexact) >> 5 |
713 (xcpt & float_flag_underflow) >> 3 |
714 (xcpt & float_flag_overflow) >> 1 |
715 (xcpt & float_flag_divbyzero) << 1 |
716 (xcpt & float_flag_invalid) << 4;
717}
718
aa343735 719static always_inline char mips_ex_to_ieee(char xcpt)
fd4a04eb
TS		 720{
721 return (xcpt & FP_INEXACT) << 5 |
722 (xcpt & FP_UNDERFLOW) << 3 |
723 (xcpt & FP_OVERFLOW) << 1 |
724 (xcpt & FP_DIV0) >> 1 |
725 (xcpt & FP_INVALID) >> 4;
726}
727
aa343735 728static always_inline void update_fcr31(void)
fd4a04eb 729{
ead9360e 730 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status));
fd4a04eb 731
ead9360e
TS		 732 SET_FP_CAUSE(env->fpu->fcr31, tmp);
733 if (GET_FP_ENABLE(env->fpu->fcr31) & tmp)
fd4a04eb
TS		 734 do_raise_exception(EXCP_FPE);
735 else
ead9360e 736 UPDATE_FP_FLAGS(env->fpu->fcr31, tmp);
fd4a04eb
TS		 737}
738
739#define FLOAT_OP(name, p) void do_float_##name##_##p(void)
740
741FLOAT_OP(cvtd, s)
742{
ead9360e
TS		 743 set_float_exception_flags(0, &env->fpu->fp_status);
744 FDT2 = float32_to_float64(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 745 update_fcr31();
746}
747FLOAT_OP(cvtd, w)
748{
ead9360e
TS		 749 set_float_exception_flags(0, &env->fpu->fp_status);
750 FDT2 = int32_to_float64(WT0, &env->fpu->fp_status);
fd4a04eb
TS		 751 update_fcr31();
752}
753FLOAT_OP(cvtd, l)
754{
ead9360e
TS		 755 set_float_exception_flags(0, &env->fpu->fp_status);
756 FDT2 = int64_to_float64(DT0, &env->fpu->fp_status);
fd4a04eb
TS		 757 update_fcr31();
758}
759FLOAT_OP(cvtl, d)
760{
ead9360e
TS		 761 set_float_exception_flags(0, &env->fpu->fp_status);
762 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
fd4a04eb 763 update_fcr31();
ead9360e 764 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 765 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 766}
767FLOAT_OP(cvtl, s)
768{
ead9360e
TS		 769 set_float_exception_flags(0, &env->fpu->fp_status);
770 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
fd4a04eb 771 update_fcr31();
ead9360e 772 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 773 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 774}
775
776FLOAT_OP(cvtps, pw)
777{
ead9360e
TS		 778 set_float_exception_flags(0, &env->fpu->fp_status);
779 FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
780 FSTH2 = int32_to_float32(WTH0, &env->fpu->fp_status);
fd4a04eb
TS		 781 update_fcr31();
782}
783FLOAT_OP(cvtpw, ps)
784{
ead9360e
TS		 785 set_float_exception_flags(0, &env->fpu->fp_status);
786 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
787 WTH2 = float32_to_int32(FSTH0, &env->fpu->fp_status);
fd4a04eb 788 update_fcr31();
ead9360e 789 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 790 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 791}
792FLOAT_OP(cvts, d)
793{
ead9360e
TS		 794 set_float_exception_flags(0, &env->fpu->fp_status);
795 FST2 = float64_to_float32(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 796 update_fcr31();
797}
798FLOAT_OP(cvts, w)
799{
ead9360e
TS		 800 set_float_exception_flags(0, &env->fpu->fp_status);
801 FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
fd4a04eb
TS		 802 update_fcr31();
803}
804FLOAT_OP(cvts, l)
805{
ead9360e
TS		 806 set_float_exception_flags(0, &env->fpu->fp_status);
807 FST2 = int64_to_float32(DT0, &env->fpu->fp_status);
fd4a04eb
TS		 808 update_fcr31();
809}
810FLOAT_OP(cvts, pl)
811{
ead9360e 812 set_float_exception_flags(0, &env->fpu->fp_status);
fd4a04eb
TS		 813 WT2 = WT0;
814 update_fcr31();
815}
816FLOAT_OP(cvts, pu)
817{
ead9360e 818 set_float_exception_flags(0, &env->fpu->fp_status);
fd4a04eb
TS		 819 WT2 = WTH0;
820 update_fcr31();
821}
822FLOAT_OP(cvtw, s)
823{
ead9360e
TS		 824 set_float_exception_flags(0, &env->fpu->fp_status);
825 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
fd4a04eb 826 update_fcr31();
ead9360e 827 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 828 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 829}
830FLOAT_OP(cvtw, d)
831{
ead9360e
TS		 832 set_float_exception_flags(0, &env->fpu->fp_status);
833 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
fd4a04eb 834 update_fcr31();
ead9360e 835 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 836 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 837}
838
839FLOAT_OP(roundl, d)
840{
ead9360e
TS		 841 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
842 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 843 RESTORE_ROUNDING_MODE;
844 update_fcr31();
ead9360e 845 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 846 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 847}
848FLOAT_OP(roundl, s)
849{
ead9360e
TS		 850 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
851 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 852 RESTORE_ROUNDING_MODE;
853 update_fcr31();
ead9360e 854 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 855 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 856}
857FLOAT_OP(roundw, d)
858{
ead9360e
TS		 859 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
860 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 861 RESTORE_ROUNDING_MODE;
862 update_fcr31();
ead9360e 863 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 864 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 865}
866FLOAT_OP(roundw, s)
867{
ead9360e
TS		 868 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
869 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 870 RESTORE_ROUNDING_MODE;
871 update_fcr31();
ead9360e 872 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 873 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 874}
875
876FLOAT_OP(truncl, d)
877{
ead9360e 878 DT2 = float64_to_int64_round_to_zero(FDT0, &env->fpu->fp_status);
fd4a04eb 879 update_fcr31();
ead9360e 880 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 881 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 882}
883FLOAT_OP(truncl, s)
884{
ead9360e 885 DT2 = float32_to_int64_round_to_zero(FST0, &env->fpu->fp_status);
fd4a04eb 886 update_fcr31();
ead9360e 887 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 888 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 889}
890FLOAT_OP(truncw, d)
891{
ead9360e 892 WT2 = float64_to_int32_round_to_zero(FDT0, &env->fpu->fp_status);
fd4a04eb 893 update_fcr31();
ead9360e 894 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 895 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 896}
897FLOAT_OP(truncw, s)
898{
ead9360e 899 WT2 = float32_to_int32_round_to_zero(FST0, &env->fpu->fp_status);
fd4a04eb 900 update_fcr31();
ead9360e 901 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 902 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 903}
904
905FLOAT_OP(ceill, d)
906{
ead9360e
TS		 907 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
908 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 909 RESTORE_ROUNDING_MODE;
910 update_fcr31();
ead9360e 911 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 912 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 913}
914FLOAT_OP(ceill, s)
915{
ead9360e
TS		 916 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
917 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 918 RESTORE_ROUNDING_MODE;
919 update_fcr31();
ead9360e 920 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 921 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 922}
923FLOAT_OP(ceilw, d)
924{
ead9360e
TS		 925 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
926 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 927 RESTORE_ROUNDING_MODE;
928 update_fcr31();
ead9360e 929 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 930 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 931}
932FLOAT_OP(ceilw, s)
933{
ead9360e
TS		 934 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
935 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 936 RESTORE_ROUNDING_MODE;
937 update_fcr31();
ead9360e 938 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 939 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 940}
941
942FLOAT_OP(floorl, d)
943{
ead9360e
TS		 944 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
945 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 946 RESTORE_ROUNDING_MODE;
947 update_fcr31();
ead9360e 948 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 949 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 950}
951FLOAT_OP(floorl, s)
952{
ead9360e
TS		 953 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
954 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 955 RESTORE_ROUNDING_MODE;
956 update_fcr31();
ead9360e 957 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 958 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 959}
960FLOAT_OP(floorw, d)
961{
ead9360e
TS		 962 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
963 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 964 RESTORE_ROUNDING_MODE;
965 update_fcr31();
ead9360e 966 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 967 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 968}
969FLOAT_OP(floorw, s)
970{
ead9360e
TS		 971 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
972 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 973 RESTORE_ROUNDING_MODE;
974 update_fcr31();
ead9360e 975 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 976 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 977}
978
8dfdb87c
TS		 979/* MIPS specific unary operations */
980FLOAT_OP(recip, d)
981{
ead9360e
TS		 982 set_float_exception_flags(0, &env->fpu->fp_status);
983 FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
8dfdb87c
TS		 984 update_fcr31();
985}
986FLOAT_OP(recip, s)
987{
ead9360e
TS		 988 set_float_exception_flags(0, &env->fpu->fp_status);
989 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
8dfdb87c 990 update_fcr31();
57fa1fb3 991}
57fa1fb3 992
8dfdb87c
TS		 993FLOAT_OP(rsqrt, d)
994{
ead9360e
TS		 995 set_float_exception_flags(0, &env->fpu->fp_status);
996 FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
997 FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
8dfdb87c
TS		 998 update_fcr31();
999}
1000FLOAT_OP(rsqrt, s)
1001{
ead9360e
TS		 1002 set_float_exception_flags(0, &env->fpu->fp_status);
1003 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1004 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
8dfdb87c
TS		 1005 update_fcr31();
1006}
1007
1008FLOAT_OP(recip1, d)
1009{
ead9360e
TS		 1010 set_float_exception_flags(0, &env->fpu->fp_status);
1011 FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
8dfdb87c
TS		 1012 update_fcr31();
1013}
1014FLOAT_OP(recip1, s)
1015{
ead9360e
TS		 1016 set_float_exception_flags(0, &env->fpu->fp_status);
1017 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
8dfdb87c
TS		 1018 update_fcr31();
1019}
1020FLOAT_OP(recip1, ps)
1021{
ead9360e
TS		 1022 set_float_exception_flags(0, &env->fpu->fp_status);
1023 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
1024 FSTH2 = float32_div(FLOAT_ONE32, FSTH0, &env->fpu->fp_status);
8dfdb87c
TS		 1025 update_fcr31();
1026}
1027
1028FLOAT_OP(rsqrt1, d)
1029{
ead9360e
TS		 1030 set_float_exception_flags(0, &env->fpu->fp_status);
1031 FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
1032 FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
8dfdb87c
TS		 1033 update_fcr31();
1034}
1035FLOAT_OP(rsqrt1, s)
1036{
ead9360e
TS		 1037 set_float_exception_flags(0, &env->fpu->fp_status);
1038 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1039 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
8dfdb87c
TS		 1040 update_fcr31();
1041}
1042FLOAT_OP(rsqrt1, ps)
1043{
ead9360e
TS		 1044 set_float_exception_flags(0, &env->fpu->fp_status);
1045 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1046 FSTH2 = float32_sqrt(FSTH0, &env->fpu->fp_status);
1047 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
1048 FSTH2 = float32_div(FLOAT_ONE32, FSTH2, &env->fpu->fp_status);
8dfdb87c 1049 update_fcr31();
57fa1fb3 1050}
57fa1fb3 1051
fd4a04eb
TS		 1052/* binary operations */
1053#define FLOAT_BINOP(name) \
1054FLOAT_OP(name, d) \
1055{ \
ead9360e
TS		 1056 set_float_exception_flags(0, &env->fpu->fp_status); \
1057 FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \
1058 update_fcr31(); \
1059 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
5747c073 1060 DT2 = FLOAT_QNAN64; \
fd4a04eb
TS		 1061} \
1062FLOAT_OP(name, s) \
1063{ \
ead9360e
TS		 1064 set_float_exception_flags(0, &env->fpu->fp_status); \
1065 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
1066 update_fcr31(); \
1067 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
5747c073 1068 WT2 = FLOAT_QNAN32; \
fd4a04eb
TS		 1069} \
1070FLOAT_OP(name, ps) \
1071{ \
ead9360e
TS		 1072 set_float_exception_flags(0, &env->fpu->fp_status); \
1073 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
1074 FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \
fd4a04eb 1075 update_fcr31(); \
ead9360e 1076 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
5747c073
PB		 1077 WT2 = FLOAT_QNAN32; \
1078 WTH2 = FLOAT_QNAN32; \
3a5b360d 1079 } \
fd4a04eb
TS		 1080}
1081FLOAT_BINOP(add)
1082FLOAT_BINOP(sub)
1083FLOAT_BINOP(mul)
1084FLOAT_BINOP(div)
1085#undef FLOAT_BINOP
1086
8dfdb87c
TS		 1087/* MIPS specific binary operations */
1088FLOAT_OP(recip2, d)
1089{
ead9360e
TS		 1090 set_float_exception_flags(0, &env->fpu->fp_status);
1091 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
5747c073 1092 FDT2 = float64_chs(float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status));
8dfdb87c
TS		 1093 update_fcr31();
1094}
1095FLOAT_OP(recip2, s)
1096{
ead9360e
TS		 1097 set_float_exception_flags(0, &env->fpu->fp_status);
1098 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
5747c073 1099 FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
8dfdb87c
TS		 1100 update_fcr31();
1101}
1102FLOAT_OP(recip2, ps)
1103{
ead9360e
TS		 1104 set_float_exception_flags(0, &env->fpu->fp_status);
1105 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1106 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
5747c073
PB		 1107 FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
1108 FSTH2 = float32_chs(float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status));
8dfdb87c
TS		 1109 update_fcr31();
1110}
1111
1112FLOAT_OP(rsqrt2, d)
1113{
ead9360e
TS		 1114 set_float_exception_flags(0, &env->fpu->fp_status);
1115 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
1116 FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status);
5747c073 1117 FDT2 = float64_chs(float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status));
8dfdb87c
TS		 1118 update_fcr31();
1119}
1120FLOAT_OP(rsqrt2, s)
1121{
ead9360e
TS		 1122 set_float_exception_flags(0, &env->fpu->fp_status);
1123 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1124 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
5747c073 1125 FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
8dfdb87c
TS		 1126 update_fcr31();
1127}
1128FLOAT_OP(rsqrt2, ps)
1129{
ead9360e
TS		 1130 set_float_exception_flags(0, &env->fpu->fp_status);
1131 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1132 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
1133 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
1134 FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status);
5747c073
PB		 1135 FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
1136 FSTH2 = float32_chs(float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status));
8dfdb87c 1137 update_fcr31();
57fa1fb3 1138}
57fa1fb3 1139
fd4a04eb
TS		 1140FLOAT_OP(addr, ps)
1141{
ead9360e
TS		 1142 set_float_exception_flags(0, &env->fpu->fp_status);
1143 FST2 = float32_add (FST0, FSTH0, &env->fpu->fp_status);
1144 FSTH2 = float32_add (FST1, FSTH1, &env->fpu->fp_status);
fd4a04eb
TS		 1145 update_fcr31();
1146}
1147
57fa1fb3
TS		 1148FLOAT_OP(mulr, ps)
1149{
ead9360e
TS		 1150 set_float_exception_flags(0, &env->fpu->fp_status);
1151 FST2 = float32_mul (FST0, FSTH0, &env->fpu->fp_status);
1152 FSTH2 = float32_mul (FST1, FSTH1, &env->fpu->fp_status);
57fa1fb3
TS		 1153 update_fcr31();
1154}
1155
8dfdb87c 1156/* compare operations */
fd4a04eb
TS		 1157#define FOP_COND_D(op, cond) \
1158void do_cmp_d_ ## op (long cc) \
1159{ \
1160 int c = cond; \
1161 update_fcr31(); \
1162 if (c) \
ead9360e 1163 SET_FP_COND(cc, env->fpu); \
fd4a04eb 1164 else \
ead9360e 1165 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb
TS		 1166} \
1167void do_cmpabs_d_ ## op (long cc) \
1168{ \
1169 int c; \
5747c073
PB		 1170 FDT0 = float64_chs(FDT0); \
1171 FDT1 = float64_chs(FDT1); \
fd4a04eb
TS		 1172 c = cond; \
1173 update_fcr31(); \
1174 if (c) \
ead9360e 1175 SET_FP_COND(cc, env->fpu); \
fd4a04eb 1176 else \
ead9360e 1177 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb
TS		 1178}
1179
1180int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
1181{
1182 if (float64_is_signaling_nan(a) ||
1183 float64_is_signaling_nan(b) ||
1184 (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
1185 float_raise(float_flag_invalid, status);
1186 return 1;
1187 } else if (float64_is_nan(a) || float64_is_nan(b)) {
1188 return 1;
1189 } else {
1190 return 0;
1191 }
1192}
1193
1194/* NOTE: the comma operator will make "cond" to eval to false,
1195 * but float*_is_unordered() is still called. */
ead9360e
TS		 1196FOP_COND_D(f, (float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status), 0))
1197FOP_COND_D(un, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status))
1198FOP_COND_D(eq, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1199FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1200FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1201FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1202FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
1203FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
fd4a04eb
TS		 1204/* NOTE: the comma operator will make "cond" to eval to false,
1205 * but float*_is_unordered() is still called. */
ead9360e
TS		 1206FOP_COND_D(sf, (float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status), 0))
1207FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status))
1208FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1209FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1210FOP_COND_D(lt, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1211FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1212FOP_COND_D(le, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
1213FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
fd4a04eb
TS		 1214
1215#define FOP_COND_S(op, cond) \
1216void do_cmp_s_ ## op (long cc) \
1217{ \
1218 int c = cond; \
1219 update_fcr31(); \
1220 if (c) \
ead9360e 1221 SET_FP_COND(cc, env->fpu); \
fd4a04eb 1222 else \
ead9360e 1223 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb
TS		 1224} \
1225void do_cmpabs_s_ ## op (long cc) \
1226{ \
1227 int c; \
5747c073
PB		 1228 FST0 = float32_abs(FST0); \
1229 FST1 = float32_abs(FST1); \
fd4a04eb
TS		 1230 c = cond; \
1231 update_fcr31(); \
1232 if (c) \
ead9360e 1233 SET_FP_COND(cc, env->fpu); \
fd4a04eb 1234 else \
ead9360e 1235 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb
TS		 1236}
1237
1238flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
1239{
fd4a04eb
TS		 1240 if (float32_is_signaling_nan(a) ||
1241 float32_is_signaling_nan(b) ||
1242 (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
1243 float_raise(float_flag_invalid, status);
1244 return 1;
1245 } else if (float32_is_nan(a) || float32_is_nan(b)) {
1246 return 1;
1247 } else {
1248 return 0;
1249 }
1250}
1251
1252/* NOTE: the comma operator will make "cond" to eval to false,
1253 * but float*_is_unordered() is still called. */
ead9360e
TS		 1254FOP_COND_S(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0))
1255FOP_COND_S(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status))
1256FOP_COND_S(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
1257FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
1258FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
1259FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
1260FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
1261FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
fd4a04eb
TS		 1262/* NOTE: the comma operator will make "cond" to eval to false,
1263 * but float*_is_unordered() is still called. */
ead9360e
TS		 1264FOP_COND_S(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0))
1265FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status))
1266FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
1267FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
1268FOP_COND_S(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
1269FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
1270FOP_COND_S(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
1271FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
fd4a04eb
TS		 1272
1273#define FOP_COND_PS(op, condl, condh) \
1274void do_cmp_ps_ ## op (long cc) \
1275{ \
1276 int cl = condl; \
1277 int ch = condh; \
1278 update_fcr31(); \
1279 if (cl) \
ead9360e 1280 SET_FP_COND(cc, env->fpu); \
fd4a04eb 1281 else \
ead9360e 1282 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb 1283 if (ch) \
ead9360e 1284 SET_FP_COND(cc + 1, env->fpu); \
fd4a04eb 1285 else \
ead9360e 1286 CLEAR_FP_COND(cc + 1, env->fpu); \
fd4a04eb
TS		 1287} \
1288void do_cmpabs_ps_ ## op (long cc) \
1289{ \
1290 int cl, ch; \
5747c073
PB		 1291 FST0 = float32_abs(FST0); \
1292 FSTH0 = float32_abs(FSTH0); \
1293 FST1 = float32_abs(FST1); \
1294 FSTH1 = float32_abs(FSTH1); \
fd4a04eb
TS		 1295 cl = condl; \
1296 ch = condh; \
1297 update_fcr31(); \
1298 if (cl) \
ead9360e 1299 SET_FP_COND(cc, env->fpu); \
fd4a04eb 1300 else \
ead9360e 1301 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb 1302 if (ch) \
ead9360e 1303 SET_FP_COND(cc + 1, env->fpu); \
fd4a04eb 1304 else \
ead9360e 1305 CLEAR_FP_COND(cc + 1, env->fpu); \
fd4a04eb
TS		 1306}
1307
1308/* NOTE: the comma operator will make "cond" to eval to false,
1309 * but float*_is_unordered() is still called. */
ead9360e
TS		 1310FOP_COND_PS(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0),
1311 (float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status), 0))
1312FOP_COND_PS(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status),
1313 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status))
1314FOP_COND_PS(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
1315 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1316FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
1317 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1318FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
1319 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1320FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
1321 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1322FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
1323 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1324FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
1325 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
fd4a04eb
TS		 1326/* NOTE: the comma operator will make "cond" to eval to false,
1327 * but float*_is_unordered() is still called. */
ead9360e
TS		 1328FOP_COND_PS(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0),
1329 (float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status), 0))
1330FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status),
1331 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status))
1332FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
1333 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1334FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
1335 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1336FOP_COND_PS(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
1337 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1338FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
1339 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1340FOP_COND_PS(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
1341 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1342FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
1343 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
Qemu copy for testing