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[qemu.git] / target-mips / op_helper.c
CommitLineData
6af0bf9c
FB		 1/*
2 * MIPS emulation helpers for qemu.
5fafdf24 3 *
6af0bf9c
FB		 4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
2d0e944d 20#include <stdlib.h>
6af0bf9c
FB		 21#include "exec.h"
22
05f778c8
TS		 23#include "host-utils.h"
24
a7812ae4 25#include "helper.h"
6af0bf9c
FB		 26/*****************************************************************************/
27/* Exceptions processing helpers */
6af0bf9c 28
6af0bf9c
FB		 29void do_raise_exception_err (uint32_t exception, int error_code)
30{
31#if 1
32 if (logfile && exception < 0x100)
33 fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
34#endif
35 env->exception_index = exception;
36 env->error_code = error_code;
6af0bf9c
FB		 37 cpu_loop_exit();
38}
39
6af0bf9c
FB		 40void do_raise_exception (uint32_t exception)
41{
42 do_raise_exception_err(exception, 0);
43}
44
48d38ca5
TS		 45void do_interrupt_restart (void)
46{
47 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
48 !(env->CP0_Status & (1 << CP0St_ERL)) &&
49 !(env->hflags & MIPS_HFLAG_DM) &&
50 (env->CP0_Status & (1 << CP0St_IE)) &&
51 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
52 env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
53 do_raise_exception(EXCP_EXT_INTERRUPT);
54 }
55}
56
4ad40f36
FB		 57void do_restore_state (void *pc_ptr)
58{
a607922c
FB		 59 TranslationBlock *tb;
60 unsigned long pc = (unsigned long) pc_ptr;
61
62 tb = tb_find_pc (pc);
63 if (tb) {
64 cpu_restore_state (tb, env, pc, NULL);
65 }
4ad40f36
FB		 66}
67
be24bb4f 68target_ulong do_clo (target_ulong t0)
30898801 69{
be24bb4f 70 return clo32(t0);
30898801
TS		 71}
72
be24bb4f 73target_ulong do_clz (target_ulong t0)
30898801 74{
be24bb4f 75 return clz32(t0);
30898801
TS		 76}
77
d26bc211 78#if defined(TARGET_MIPS64)
be24bb4f 79target_ulong do_dclo (target_ulong t0)
05f778c8 80{
be24bb4f 81 return clo64(t0);
05f778c8
TS		 82}
83
be24bb4f 84target_ulong do_dclz (target_ulong t0)
05f778c8 85{
be24bb4f 86 return clz64(t0);
05f778c8 87}
d26bc211 88#endif /* TARGET_MIPS64 */
c570fd16 89
6af0bf9c 90/* 64 bits arithmetic for 32 bits hosts */
c904ef0e 91static inline uint64_t get_HILO (void)
6af0bf9c 92{
b5dc7732 93 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
6af0bf9c
FB		 94}
95
c904ef0e 96static inline void set_HILO (uint64_t HILO)
6af0bf9c 97{
b5dc7732
TS		 98 env->active_tc.LO[0] = (int32_t)HILO;
99 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
6af0bf9c
FB		 100}
101
c904ef0e 102static inline void set_HIT0_LO (target_ulong t0, uint64_t HILO)
e9c71dd1 103{
b5dc7732
TS		 104 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
105 t0 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
e9c71dd1
TS		 106}
107
c904ef0e 108static inline void set_HI_LOT0 (target_ulong t0, uint64_t HILO)
e9c71dd1 109{
b5dc7732
TS		 110 t0 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
111 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
e9c71dd1
TS		 112}
113
92af06d2 114#if TARGET_LONG_BITS > HOST_LONG_BITS
be24bb4f 115void do_madd (target_ulong t0, target_ulong t1)
6af0bf9c
FB		 116{
117 int64_t tmp;
118
be24bb4f 119 tmp = ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
6af0bf9c
FB		 120 set_HILO((int64_t)get_HILO() + tmp);
121}
122
be24bb4f 123void do_maddu (target_ulong t0, target_ulong t1)
6af0bf9c
FB		 124{
125 uint64_t tmp;
126
be24bb4f 127 tmp = ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
6af0bf9c
FB		 128 set_HILO(get_HILO() + tmp);
129}
130
be24bb4f 131void do_msub (target_ulong t0, target_ulong t1)
6af0bf9c
FB		 132{
133 int64_t tmp;
134
be24bb4f 135 tmp = ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
6af0bf9c
FB		 136 set_HILO((int64_t)get_HILO() - tmp);
137}
138
be24bb4f 139void do_msubu (target_ulong t0, target_ulong t1)
6af0bf9c
FB		 140{
141 uint64_t tmp;
142
be24bb4f 143 tmp = ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
6af0bf9c
FB		 144 set_HILO(get_HILO() - tmp);
145}
92af06d2 146#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
e9c71dd1
TS		 147
148/* Multiplication variants of the vr54xx. */
be24bb4f 149target_ulong do_muls (target_ulong t0, target_ulong t1)
e9c71dd1 150{
be24bb4f
TS		 151 set_HI_LOT0(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
152
153 return t0;
e9c71dd1
TS		 154}
155
be24bb4f 156target_ulong do_mulsu (target_ulong t0, target_ulong t1)
e9c71dd1 157{
be24bb4f
TS		 158 set_HI_LOT0(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
159
160 return t0;
e9c71dd1
TS		 161}
162
be24bb4f 163target_ulong do_macc (target_ulong t0, target_ulong t1)
e9c71dd1 164{
be24bb4f
TS		 165 set_HI_LOT0(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
166
167 return t0;
e9c71dd1
TS		 168}
169
be24bb4f 170target_ulong do_macchi (target_ulong t0, target_ulong t1)
e9c71dd1 171{
be24bb4f
TS		 172 set_HIT0_LO(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
173
174 return t0;
e9c71dd1
TS		 175}
176
be24bb4f 177target_ulong do_maccu (target_ulong t0, target_ulong t1)
e9c71dd1 178{
be24bb4f
TS		 179 set_HI_LOT0(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
180
181 return t0;
e9c71dd1
TS		 182}
183
be24bb4f 184target_ulong do_macchiu (target_ulong t0, target_ulong t1)
e9c71dd1 185{
be24bb4f
TS		 186 set_HIT0_LO(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
187
188 return t0;
e9c71dd1
TS		 189}
190
be24bb4f 191target_ulong do_msac (target_ulong t0, target_ulong t1)
e9c71dd1 192{
be24bb4f
TS		 193 set_HI_LOT0(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
194
195 return t0;
e9c71dd1
TS		 196}
197
be24bb4f 198target_ulong do_msachi (target_ulong t0, target_ulong t1)
e9c71dd1 199{
be24bb4f
TS		 200 set_HIT0_LO(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
201
202 return t0;
e9c71dd1
TS		 203}
204
be24bb4f 205target_ulong do_msacu (target_ulong t0, target_ulong t1)
e9c71dd1 206{
be24bb4f
TS		 207 set_HI_LOT0(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
208
209 return t0;
e9c71dd1
TS		 210}
211
be24bb4f 212target_ulong do_msachiu (target_ulong t0, target_ulong t1)
e9c71dd1 213{
be24bb4f
TS		 214 set_HIT0_LO(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
215
216 return t0;
e9c71dd1
TS		 217}
218
be24bb4f 219target_ulong do_mulhi (target_ulong t0, target_ulong t1)
e9c71dd1 220{
be24bb4f
TS		 221 set_HIT0_LO(t0, (int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
222
223 return t0;
e9c71dd1
TS		 224}
225
be24bb4f 226target_ulong do_mulhiu (target_ulong t0, target_ulong t1)
e9c71dd1 227{
be24bb4f
TS		 228 set_HIT0_LO(t0, (uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
229
230 return t0;
e9c71dd1
TS		 231}
232
be24bb4f 233target_ulong do_mulshi (target_ulong t0, target_ulong t1)
e9c71dd1 234{
be24bb4f
TS		 235 set_HIT0_LO(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
236
237 return t0;
e9c71dd1
TS		 238}
239
be24bb4f 240target_ulong do_mulshiu (target_ulong t0, target_ulong t1)
e9c71dd1 241{
be24bb4f
TS		 242 set_HIT0_LO(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
243
244 return t0;
e9c71dd1 245}
6af0bf9c 246
214c465f 247#ifdef TARGET_MIPS64
be24bb4f 248void do_dmult (target_ulong t0, target_ulong t1)
214c465f 249{
b5dc7732 250 muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), t0, t1);
214c465f
TS		 251}
252
be24bb4f 253void do_dmultu (target_ulong t0, target_ulong t1)
214c465f 254{
b5dc7732 255 mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), t0, t1);
214c465f
TS		 256}
257#endif
258
c8c2227e
TS		 259#ifdef TARGET_WORDS_BIGENDIAN
260#define GET_LMASK(v) ((v) & 3)
261#define GET_OFFSET(addr, offset) (addr + (offset))
262#else
263#define GET_LMASK(v) (((v) & 3) ^ 3)
264#define GET_OFFSET(addr, offset) (addr - (offset))
265#endif
266
be24bb4f 267target_ulong do_lwl(target_ulong t0, target_ulong t1, int mem_idx)
c8c2227e
TS		 268{
269 target_ulong tmp;
270
271#ifdef CONFIG_USER_ONLY
272#define ldfun ldub_raw
273#else
274 int (*ldfun)(target_ulong);
275
276 switch (mem_idx)
277 {
278 case 0: ldfun = ldub_kernel; break;
279 case 1: ldfun = ldub_super; break;
280 default:
281 case 2: ldfun = ldub_user; break;
282 }
283#endif
be24bb4f
TS		 284 tmp = ldfun(t0);
285 t1 = (t1 & 0x00FFFFFF) | (tmp << 24);
c8c2227e 286
be24bb4f
TS		 287 if (GET_LMASK(t0) <= 2) {
288 tmp = ldfun(GET_OFFSET(t0, 1));
289 t1 = (t1 & 0xFF00FFFF) | (tmp << 16);
c8c2227e
TS		 290 }
291
be24bb4f
TS		 292 if (GET_LMASK(t0) <= 1) {
293 tmp = ldfun(GET_OFFSET(t0, 2));
294 t1 = (t1 & 0xFFFF00FF) | (tmp << 8);
c8c2227e
TS		 295 }
296
be24bb4f
TS		 297 if (GET_LMASK(t0) == 0) {
298 tmp = ldfun(GET_OFFSET(t0, 3));
299 t1 = (t1 & 0xFFFFFF00) | tmp;
c8c2227e 300 }
be24bb4f 301 return (int32_t)t1;
c8c2227e
TS		 302}
303
be24bb4f 304target_ulong do_lwr(target_ulong t0, target_ulong t1, int mem_idx)
c8c2227e
TS		 305{
306 target_ulong tmp;
307
308#ifdef CONFIG_USER_ONLY
309#define ldfun ldub_raw
310#else
311 int (*ldfun)(target_ulong);
312
313 switch (mem_idx)
314 {
315 case 0: ldfun = ldub_kernel; break;
316 case 1: ldfun = ldub_super; break;
317 default:
318 case 2: ldfun = ldub_user; break;
319 }
320#endif
be24bb4f
TS		 321 tmp = ldfun(t0);
322 t1 = (t1 & 0xFFFFFF00) | tmp;
c8c2227e 323
be24bb4f
TS		 324 if (GET_LMASK(t0) >= 1) {
325 tmp = ldfun(GET_OFFSET(t0, -1));
326 t1 = (t1 & 0xFFFF00FF) | (tmp << 8);
c8c2227e
TS		 327 }
328
be24bb4f
TS		 329 if (GET_LMASK(t0) >= 2) {
330 tmp = ldfun(GET_OFFSET(t0, -2));
331 t1 = (t1 & 0xFF00FFFF) | (tmp << 16);
c8c2227e
TS		 332 }
333
be24bb4f
TS		 334 if (GET_LMASK(t0) == 3) {
335 tmp = ldfun(GET_OFFSET(t0, -3));
336 t1 = (t1 & 0x00FFFFFF) | (tmp << 24);
c8c2227e 337 }
be24bb4f 338 return (int32_t)t1;
c8c2227e
TS		 339}
340
be24bb4f 341void do_swl(target_ulong t0, target_ulong t1, int mem_idx)
c8c2227e
TS		 342{
343#ifdef CONFIG_USER_ONLY
344#define stfun stb_raw
345#else
346 void (*stfun)(target_ulong, int);
347
348 switch (mem_idx)
349 {
350 case 0: stfun = stb_kernel; break;
351 case 1: stfun = stb_super; break;
352 default:
353 case 2: stfun = stb_user; break;
354 }
355#endif
be24bb4f 356 stfun(t0, (uint8_t)(t1 >> 24));
c8c2227e 357
be24bb4f
TS		 358 if (GET_LMASK(t0) <= 2)
359 stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 16));
c8c2227e 360
be24bb4f
TS		 361 if (GET_LMASK(t0) <= 1)
362 stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 8));
c8c2227e 363
be24bb4f
TS		 364 if (GET_LMASK(t0) == 0)
365 stfun(GET_OFFSET(t0, 3), (uint8_t)t1);
c8c2227e
TS		 366}
367
be24bb4f 368void do_swr(target_ulong t0, target_ulong t1, int mem_idx)
c8c2227e
TS		 369{
370#ifdef CONFIG_USER_ONLY
371#define stfun stb_raw
372#else
373 void (*stfun)(target_ulong, int);
374
375 switch (mem_idx)
376 {
377 case 0: stfun = stb_kernel; break;
378 case 1: stfun = stb_super; break;
379 default:
380 case 2: stfun = stb_user; break;
381 }
382#endif
be24bb4f 383 stfun(t0, (uint8_t)t1);
c8c2227e 384
be24bb4f
TS		 385 if (GET_LMASK(t0) >= 1)
386 stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));
c8c2227e 387
be24bb4f
TS		 388 if (GET_LMASK(t0) >= 2)
389 stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));
c8c2227e 390
be24bb4f
TS		 391 if (GET_LMASK(t0) == 3)
392 stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));
c8c2227e
TS		 393}
394
395#if defined(TARGET_MIPS64)
396/* "half" load and stores. We must do the memory access inline,
397 or fault handling won't work. */
398
399#ifdef TARGET_WORDS_BIGENDIAN
400#define GET_LMASK64(v) ((v) & 7)
401#else
402#define GET_LMASK64(v) (((v) & 7) ^ 7)
403#endif
404
be24bb4f 405target_ulong do_ldl(target_ulong t0, target_ulong t1, int mem_idx)
c8c2227e
TS		 406{
407 uint64_t tmp;
408
409#ifdef CONFIG_USER_ONLY
410#define ldfun ldub_raw
411#else
be24bb4f 412 int (*ldfun)(target_ulong);
c8c2227e
TS		 413
414 switch (mem_idx)
415 {
416 case 0: ldfun = ldub_kernel; break;
417 case 1: ldfun = ldub_super; break;
418 default:
419 case 2: ldfun = ldub_user; break;
420 }
421#endif
be24bb4f
TS		 422 tmp = ldfun(t0);
423 t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
c8c2227e 424
be24bb4f
TS		 425 if (GET_LMASK64(t0) <= 6) {
426 tmp = ldfun(GET_OFFSET(t0, 1));
427 t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
c8c2227e
TS		 428 }
429
be24bb4f
TS		 430 if (GET_LMASK64(t0) <= 5) {
431 tmp = ldfun(GET_OFFSET(t0, 2));
432 t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
c8c2227e
TS		 433 }
434
be24bb4f
TS		 435 if (GET_LMASK64(t0) <= 4) {
436 tmp = ldfun(GET_OFFSET(t0, 3));
437 t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
c8c2227e
TS		 438 }
439
be24bb4f
TS		 440 if (GET_LMASK64(t0) <= 3) {
441 tmp = ldfun(GET_OFFSET(t0, 4));
442 t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
c8c2227e
TS		 443 }
444
be24bb4f
TS		 445 if (GET_LMASK64(t0) <= 2) {
446 tmp = ldfun(GET_OFFSET(t0, 5));
447 t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
c8c2227e
TS		 448 }
449
be24bb4f
TS		 450 if (GET_LMASK64(t0) <= 1) {
451 tmp = ldfun(GET_OFFSET(t0, 6));
452 t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
c8c2227e
TS		 453 }
454
be24bb4f
TS		 455 if (GET_LMASK64(t0) == 0) {
456 tmp = ldfun(GET_OFFSET(t0, 7));
457 t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
c8c2227e 458 }
be24bb4f
TS		 459
460 return t1;
c8c2227e
TS		 461}
462
be24bb4f 463target_ulong do_ldr(target_ulong t0, target_ulong t1, int mem_idx)
c8c2227e
TS		 464{
465 uint64_t tmp;
466
467#ifdef CONFIG_USER_ONLY
468#define ldfun ldub_raw
469#else
be24bb4f 470 int (*ldfun)(target_ulong);
c8c2227e
TS		 471
472 switch (mem_idx)
473 {
474 case 0: ldfun = ldub_kernel; break;
475 case 1: ldfun = ldub_super; break;
476 default:
477 case 2: ldfun = ldub_user; break;
478 }
479#endif
be24bb4f
TS		 480 tmp = ldfun(t0);
481 t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
c8c2227e 482
be24bb4f
TS		 483 if (GET_LMASK64(t0) >= 1) {
484 tmp = ldfun(GET_OFFSET(t0, -1));
485 t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
c8c2227e
TS		 486 }
487
be24bb4f
TS		 488 if (GET_LMASK64(t0) >= 2) {
489 tmp = ldfun(GET_OFFSET(t0, -2));
490 t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
c8c2227e
TS		 491 }
492
be24bb4f
TS		 493 if (GET_LMASK64(t0) >= 3) {
494 tmp = ldfun(GET_OFFSET(t0, -3));
495 t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
c8c2227e
TS		 496 }
497
be24bb4f
TS		 498 if (GET_LMASK64(t0) >= 4) {
499 tmp = ldfun(GET_OFFSET(t0, -4));
500 t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
c8c2227e
TS		 501 }
502
be24bb4f
TS		 503 if (GET_LMASK64(t0) >= 5) {
504 tmp = ldfun(GET_OFFSET(t0, -5));
505 t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
c8c2227e
TS		 506 }
507
be24bb4f
TS		 508 if (GET_LMASK64(t0) >= 6) {
509 tmp = ldfun(GET_OFFSET(t0, -6));
510 t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
c8c2227e
TS		 511 }
512
be24bb4f
TS		 513 if (GET_LMASK64(t0) == 7) {
514 tmp = ldfun(GET_OFFSET(t0, -7));
515 t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
c8c2227e 516 }
be24bb4f
TS		 517
518 return t1;
c8c2227e
TS		 519}
520
be24bb4f 521void do_sdl(target_ulong t0, target_ulong t1, int mem_idx)
c8c2227e
TS		 522{
523#ifdef CONFIG_USER_ONLY
524#define stfun stb_raw
525#else
526 void (*stfun)(target_ulong, int);
527
528 switch (mem_idx)
529 {
530 case 0: stfun = stb_kernel; break;
531 case 1: stfun = stb_super; break;
532 default:
533 case 2: stfun = stb_user; break;
534 }
535#endif
be24bb4f 536 stfun(t0, (uint8_t)(t1 >> 56));
c8c2227e 537
be24bb4f
TS		 538 if (GET_LMASK64(t0) <= 6)
539 stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 48));
c8c2227e 540
be24bb4f
TS		 541 if (GET_LMASK64(t0) <= 5)
542 stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 40));
c8c2227e 543
be24bb4f
TS		 544 if (GET_LMASK64(t0) <= 4)
545 stfun(GET_OFFSET(t0, 3), (uint8_t)(t1 >> 32));
c8c2227e 546
be24bb4f
TS		 547 if (GET_LMASK64(t0) <= 3)
548 stfun(GET_OFFSET(t0, 4), (uint8_t)(t1 >> 24));
c8c2227e 549
be24bb4f
TS		 550 if (GET_LMASK64(t0) <= 2)
551 stfun(GET_OFFSET(t0, 5), (uint8_t)(t1 >> 16));
c8c2227e 552
be24bb4f
TS		 553 if (GET_LMASK64(t0) <= 1)
554 stfun(GET_OFFSET(t0, 6), (uint8_t)(t1 >> 8));
c8c2227e 555
be24bb4f
TS		 556 if (GET_LMASK64(t0) <= 0)
557 stfun(GET_OFFSET(t0, 7), (uint8_t)t1);
c8c2227e
TS		 558}
559
be24bb4f 560void do_sdr(target_ulong t0, target_ulong t1, int mem_idx)
c8c2227e
TS		 561{
562#ifdef CONFIG_USER_ONLY
563#define stfun stb_raw
564#else
565 void (*stfun)(target_ulong, int);
566
567 switch (mem_idx)
568 {
569 case 0: stfun = stb_kernel; break;
570 case 1: stfun = stb_super; break;
571 default:
572 case 2: stfun = stb_user; break;
573 }
574#endif
be24bb4f 575 stfun(t0, (uint8_t)t1);
c8c2227e 576
be24bb4f
TS		 577 if (GET_LMASK64(t0) >= 1)
578 stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));
c8c2227e 579
be24bb4f
TS		 580 if (GET_LMASK64(t0) >= 2)
581 stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));
c8c2227e 582
be24bb4f
TS		 583 if (GET_LMASK64(t0) >= 3)
584 stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));
c8c2227e 585
be24bb4f
TS		 586 if (GET_LMASK64(t0) >= 4)
587 stfun(GET_OFFSET(t0, -4), (uint8_t)(t1 >> 32));
c8c2227e 588
be24bb4f
TS		 589 if (GET_LMASK64(t0) >= 5)
590 stfun(GET_OFFSET(t0, -5), (uint8_t)(t1 >> 40));
c8c2227e 591
be24bb4f
TS		 592 if (GET_LMASK64(t0) >= 6)
593 stfun(GET_OFFSET(t0, -6), (uint8_t)(t1 >> 48));
c8c2227e 594
be24bb4f
TS		 595 if (GET_LMASK64(t0) == 7)
596 stfun(GET_OFFSET(t0, -7), (uint8_t)(t1 >> 56));
c8c2227e
TS		 597}
598#endif /* TARGET_MIPS64 */
599
0eaef5aa 600#ifndef CONFIG_USER_ONLY
6af0bf9c 601/* CP0 helpers */
1a3fd9c3 602target_ulong do_mfc0_mvpcontrol (void)
f1aa6320 603{
be24bb4f 604 return env->mvp->CP0_MVPControl;
f1aa6320
TS		 605}
606
1a3fd9c3 607target_ulong do_mfc0_mvpconf0 (void)
f1aa6320 608{
be24bb4f 609 return env->mvp->CP0_MVPConf0;
f1aa6320
TS		 610}
611
1a3fd9c3 612target_ulong do_mfc0_mvpconf1 (void)
f1aa6320 613{
be24bb4f 614 return env->mvp->CP0_MVPConf1;
f1aa6320
TS		 615}
616
1a3fd9c3 617target_ulong do_mfc0_random (void)
6af0bf9c 618{
be24bb4f 619 return (int32_t)cpu_mips_get_random(env);
873eb012 620}
6af0bf9c 621
1a3fd9c3 622target_ulong do_mfc0_tcstatus (void)
f1aa6320 623{
b5dc7732 624 return env->active_tc.CP0_TCStatus;
f1aa6320
TS		 625}
626
1a3fd9c3 627target_ulong do_mftc0_tcstatus(void)
f1aa6320
TS		 628{
629 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
630
b5dc7732
TS		 631 if (other_tc == env->current_tc)
632 return env->active_tc.CP0_TCStatus;
633 else
634 return env->tcs[other_tc].CP0_TCStatus;
f1aa6320
TS		 635}
636
1a3fd9c3 637target_ulong do_mfc0_tcbind (void)
f1aa6320 638{
b5dc7732 639 return env->active_tc.CP0_TCBind;
f1aa6320
TS		 640}
641
1a3fd9c3 642target_ulong do_mftc0_tcbind(void)
f1aa6320
TS		 643{
644 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
645
b5dc7732
TS		 646 if (other_tc == env->current_tc)
647 return env->active_tc.CP0_TCBind;
648 else
649 return env->tcs[other_tc].CP0_TCBind;
f1aa6320
TS		 650}
651
1a3fd9c3 652target_ulong do_mfc0_tcrestart (void)
f1aa6320 653{
b5dc7732 654 return env->active_tc.PC;
f1aa6320
TS		 655}
656
1a3fd9c3 657target_ulong do_mftc0_tcrestart(void)
f1aa6320
TS		 658{
659 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
660
b5dc7732
TS		 661 if (other_tc == env->current_tc)
662 return env->active_tc.PC;
663 else
664 return env->tcs[other_tc].PC;
f1aa6320
TS		 665}
666
1a3fd9c3 667target_ulong do_mfc0_tchalt (void)
f1aa6320 668{
b5dc7732 669 return env->active_tc.CP0_TCHalt;
f1aa6320
TS		 670}
671
1a3fd9c3 672target_ulong do_mftc0_tchalt(void)
f1aa6320
TS		 673{
674 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
675
b5dc7732
TS		 676 if (other_tc == env->current_tc)
677 return env->active_tc.CP0_TCHalt;
678 else
679 return env->tcs[other_tc].CP0_TCHalt;
f1aa6320
TS		 680}
681
1a3fd9c3 682target_ulong do_mfc0_tccontext (void)
f1aa6320 683{
b5dc7732 684 return env->active_tc.CP0_TCContext;
f1aa6320
TS		 685}
686
1a3fd9c3 687target_ulong do_mftc0_tccontext(void)
f1aa6320
TS		 688{
689 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
690
b5dc7732
TS		 691 if (other_tc == env->current_tc)
692 return env->active_tc.CP0_TCContext;
693 else
694 return env->tcs[other_tc].CP0_TCContext;
f1aa6320
TS		 695}
696
1a3fd9c3 697target_ulong do_mfc0_tcschedule (void)
f1aa6320 698{
b5dc7732 699 return env->active_tc.CP0_TCSchedule;
f1aa6320
TS		 700}
701
1a3fd9c3 702target_ulong do_mftc0_tcschedule(void)
f1aa6320
TS		 703{
704 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
705
b5dc7732
TS		 706 if (other_tc == env->current_tc)
707 return env->active_tc.CP0_TCSchedule;
708 else
709 return env->tcs[other_tc].CP0_TCSchedule;
f1aa6320
TS		 710}
711
1a3fd9c3 712target_ulong do_mfc0_tcschefback (void)
f1aa6320 713{
b5dc7732 714 return env->active_tc.CP0_TCScheFBack;
f1aa6320
TS		 715}
716
1a3fd9c3 717target_ulong do_mftc0_tcschefback(void)
f1aa6320
TS		 718{
719 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
720
b5dc7732
TS		 721 if (other_tc == env->current_tc)
722 return env->active_tc.CP0_TCScheFBack;
723 else
724 return env->tcs[other_tc].CP0_TCScheFBack;
f1aa6320
TS		 725}
726
1a3fd9c3 727target_ulong do_mfc0_count (void)
873eb012 728{
be24bb4f 729 return (int32_t)cpu_mips_get_count(env);
6af0bf9c
FB		 730}
731
1a3fd9c3 732target_ulong do_mftc0_entryhi(void)
f1aa6320
TS		 733{
734 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
b5dc7732 735 int32_t tcstatus;
f1aa6320 736
b5dc7732
TS		 737 if (other_tc == env->current_tc)
738 tcstatus = env->active_tc.CP0_TCStatus;
739 else
740 tcstatus = env->tcs[other_tc].CP0_TCStatus;
741
742 return (env->CP0_EntryHi & ~0xff) | (tcstatus & 0xff);
f1aa6320
TS		 743}
744
1a3fd9c3 745target_ulong do_mftc0_status(void)
f1aa6320
TS		 746{
747 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1a3fd9c3 748 target_ulong t0;
b5dc7732
TS		 749 int32_t tcstatus;
750
751 if (other_tc == env->current_tc)
752 tcstatus = env->active_tc.CP0_TCStatus;
753 else
754 tcstatus = env->tcs[other_tc].CP0_TCStatus;
f1aa6320 755
be24bb4f
TS		 756 t0 = env->CP0_Status & ~0xf1000018;
757 t0 |= tcstatus & (0xf << CP0TCSt_TCU0);
758 t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
759 t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
760
761 return t0;
f1aa6320
TS		 762}
763
1a3fd9c3 764target_ulong do_mfc0_lladdr (void)
f1aa6320 765{
be24bb4f 766 return (int32_t)env->CP0_LLAddr >> 4;
f1aa6320
TS		 767}
768
1a3fd9c3 769target_ulong do_mfc0_watchlo (uint32_t sel)
f1aa6320 770{
be24bb4f 771 return (int32_t)env->CP0_WatchLo[sel];
f1aa6320
TS		 772}
773
1a3fd9c3 774target_ulong do_mfc0_watchhi (uint32_t sel)
f1aa6320 775{
be24bb4f 776 return env->CP0_WatchHi[sel];
f1aa6320
TS		 777}
778
1a3fd9c3 779target_ulong do_mfc0_debug (void)
f1aa6320 780{
1a3fd9c3 781 target_ulong t0 = env->CP0_Debug;
f1aa6320 782 if (env->hflags & MIPS_HFLAG_DM)
be24bb4f
TS		 783 t0 |= 1 << CP0DB_DM;
784
785 return t0;
f1aa6320
TS		 786}
787
1a3fd9c3 788target_ulong do_mftc0_debug(void)
f1aa6320
TS		 789{
790 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
b5dc7732
TS		 791 int32_t tcstatus;
792
793 if (other_tc == env->current_tc)
794 tcstatus = env->active_tc.CP0_Debug_tcstatus;
795 else
796 tcstatus = env->tcs[other_tc].CP0_Debug_tcstatus;
f1aa6320
TS		 797
798 /* XXX: Might be wrong, check with EJTAG spec. */
be24bb4f 799 return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
b5dc7732 800 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
f1aa6320
TS		 801}
802
803#if defined(TARGET_MIPS64)
1a3fd9c3 804target_ulong do_dmfc0_tcrestart (void)
f1aa6320 805{
b5dc7732 806 return env->active_tc.PC;
f1aa6320
TS		 807}
808
1a3fd9c3 809target_ulong do_dmfc0_tchalt (void)
f1aa6320 810{
b5dc7732 811 return env->active_tc.CP0_TCHalt;
f1aa6320
TS		 812}
813
1a3fd9c3 814target_ulong do_dmfc0_tccontext (void)
f1aa6320 815{
b5dc7732 816 return env->active_tc.CP0_TCContext;
f1aa6320
TS		 817}
818
1a3fd9c3 819target_ulong do_dmfc0_tcschedule (void)
f1aa6320 820{
b5dc7732 821 return env->active_tc.CP0_TCSchedule;
f1aa6320
TS		 822}
823
1a3fd9c3 824target_ulong do_dmfc0_tcschefback (void)
f1aa6320 825{
b5dc7732 826 return env->active_tc.CP0_TCScheFBack;
f1aa6320
TS		 827}
828
1a3fd9c3 829target_ulong do_dmfc0_lladdr (void)
f1aa6320 830{
be24bb4f 831 return env->CP0_LLAddr >> 4;
f1aa6320
TS		 832}
833
1a3fd9c3 834target_ulong do_dmfc0_watchlo (uint32_t sel)
f1aa6320 835{
be24bb4f 836 return env->CP0_WatchLo[sel];
f1aa6320
TS		 837}
838#endif /* TARGET_MIPS64 */
839
be24bb4f 840void do_mtc0_index (target_ulong t0)
f1aa6320
TS		 841{
842 int num = 1;
843 unsigned int tmp = env->tlb->nb_tlb;
844
845 do {
846 tmp >>= 1;
847 num <<= 1;
848 } while (tmp);
be24bb4f 849 env->CP0_Index = (env->CP0_Index & 0x80000000) | (t0 & (num - 1));
f1aa6320
TS		 850}
851
be24bb4f 852void do_mtc0_mvpcontrol (target_ulong t0)
f1aa6320
TS		 853{
854 uint32_t mask = 0;
855 uint32_t newval;
856
857 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
858 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
859 (1 << CP0MVPCo_EVP);
860 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
861 mask |= (1 << CP0MVPCo_STLB);
be24bb4f 862 newval = (env->mvp->CP0_MVPControl & ~mask) | (t0 & mask);
f1aa6320
TS		 863
864 // TODO: Enable/disable shared TLB, enable/disable VPEs.
865
866 env->mvp->CP0_MVPControl = newval;
867}
868
be24bb4f 869void do_mtc0_vpecontrol (target_ulong t0)
f1aa6320
TS		 870{
871 uint32_t mask;
872 uint32_t newval;
873
874 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
875 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
be24bb4f 876 newval = (env->CP0_VPEControl & ~mask) | (t0 & mask);
f1aa6320
TS		 877
878 /* Yield scheduler intercept not implemented. */
879 /* Gating storage scheduler intercept not implemented. */
880
881 // TODO: Enable/disable TCs.
882
883 env->CP0_VPEControl = newval;
884}
885
be24bb4f 886void do_mtc0_vpeconf0 (target_ulong t0)
f1aa6320
TS		 887{
888 uint32_t mask = 0;
889 uint32_t newval;
890
891 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
892 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
893 mask |= (0xff << CP0VPEC0_XTC);
894 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
895 }
be24bb4f 896 newval = (env->CP0_VPEConf0 & ~mask) | (t0 & mask);
f1aa6320
TS		 897
898 // TODO: TC exclusive handling due to ERL/EXL.
899
900 env->CP0_VPEConf0 = newval;
901}
902
be24bb4f 903void do_mtc0_vpeconf1 (target_ulong t0)
f1aa6320
TS		 904{
905 uint32_t mask = 0;
906 uint32_t newval;
907
908 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
909 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
910 (0xff << CP0VPEC1_NCP1);
be24bb4f 911 newval = (env->CP0_VPEConf1 & ~mask) | (t0 & mask);
f1aa6320
TS		 912
913 /* UDI not implemented. */
914 /* CP2 not implemented. */
915
916 // TODO: Handle FPU (CP1) binding.
917
918 env->CP0_VPEConf1 = newval;
919}
920
be24bb4f 921void do_mtc0_yqmask (target_ulong t0)
f1aa6320
TS		 922{
923 /* Yield qualifier inputs not implemented. */
924 env->CP0_YQMask = 0x00000000;
925}
926
be24bb4f 927void do_mtc0_vpeopt (target_ulong t0)
f1aa6320 928{
be24bb4f 929 env->CP0_VPEOpt = t0 & 0x0000ffff;
f1aa6320
TS		 930}
931
be24bb4f 932void do_mtc0_entrylo0 (target_ulong t0)
f1aa6320
TS		 933{
934 /* Large physaddr (PABITS) not implemented */
935 /* 1k pages not implemented */
be24bb4f 936 env->CP0_EntryLo0 = t0 & 0x3FFFFFFF;
f1aa6320
TS		 937}
938
be24bb4f 939void do_mtc0_tcstatus (target_ulong t0)
f1aa6320
TS		 940{
941 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
942 uint32_t newval;
943
b5dc7732 944 newval = (env->active_tc.CP0_TCStatus & ~mask) | (t0 & mask);
f1aa6320
TS		 945
946 // TODO: Sync with CP0_Status.
947
b5dc7732 948 env->active_tc.CP0_TCStatus = newval;
f1aa6320
TS		 949}
950
be24bb4f 951void do_mttc0_tcstatus (target_ulong t0)
f1aa6320
TS		 952{
953 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
954
955 // TODO: Sync with CP0_Status.
956
b5dc7732
TS		 957 if (other_tc == env->current_tc)
958 env->active_tc.CP0_TCStatus = t0;
959 else
960 env->tcs[other_tc].CP0_TCStatus = t0;
f1aa6320
TS		 961}
962
be24bb4f 963void do_mtc0_tcbind (target_ulong t0)
f1aa6320
TS		 964{
965 uint32_t mask = (1 << CP0TCBd_TBE);
966 uint32_t newval;
967
968 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
969 mask |= (1 << CP0TCBd_CurVPE);
b5dc7732
TS		 970 newval = (env->active_tc.CP0_TCBind & ~mask) | (t0 & mask);
971 env->active_tc.CP0_TCBind = newval;
f1aa6320
TS		 972}
973
be24bb4f 974void do_mttc0_tcbind (target_ulong t0)
f1aa6320
TS		 975{
976 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
977 uint32_t mask = (1 << CP0TCBd_TBE);
978 uint32_t newval;
979
980 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
981 mask |= (1 << CP0TCBd_CurVPE);
b5dc7732
TS		 982 if (other_tc == env->current_tc) {
983 newval = (env->active_tc.CP0_TCBind & ~mask) | (t0 & mask);
984 env->active_tc.CP0_TCBind = newval;
985 } else {
986 newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (t0 & mask);
987 env->tcs[other_tc].CP0_TCBind = newval;
988 }
f1aa6320
TS		 989}
990
be24bb4f 991void do_mtc0_tcrestart (target_ulong t0)
f1aa6320 992{
b5dc7732
TS		 993 env->active_tc.PC = t0;
994 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
f1aa6320
TS		 995 env->CP0_LLAddr = 0ULL;
996 /* MIPS16 not implemented. */
997}
998
be24bb4f 999void do_mttc0_tcrestart (target_ulong t0)
f1aa6320
TS		 1000{
1001 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1002
b5dc7732
TS		 1003 if (other_tc == env->current_tc) {
1004 env->active_tc.PC = t0;
1005 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1006 env->CP0_LLAddr = 0ULL;
1007 /* MIPS16 not implemented. */
1008 } else {
1009 env->tcs[other_tc].PC = t0;
1010 env->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1011 env->CP0_LLAddr = 0ULL;
1012 /* MIPS16 not implemented. */
1013 }
f1aa6320
TS		 1014}
1015
be24bb4f 1016void do_mtc0_tchalt (target_ulong t0)
f1aa6320 1017{
b5dc7732 1018 env->active_tc.CP0_TCHalt = t0 & 0x1;
f1aa6320
TS		 1019
1020 // TODO: Halt TC / Restart (if allocated+active) TC.
1021}
1022
be24bb4f 1023void do_mttc0_tchalt (target_ulong t0)
f1aa6320
TS		 1024{
1025 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1026
1027 // TODO: Halt TC / Restart (if allocated+active) TC.
1028
b5dc7732
TS		 1029 if (other_tc == env->current_tc)
1030 env->active_tc.CP0_TCHalt = t0;
1031 else
1032 env->tcs[other_tc].CP0_TCHalt = t0;
f1aa6320
TS		 1033}
1034
be24bb4f 1035void do_mtc0_tccontext (target_ulong t0)
f1aa6320 1036{
b5dc7732 1037 env->active_tc.CP0_TCContext = t0;
f1aa6320
TS		 1038}
1039
be24bb4f 1040void do_mttc0_tccontext (target_ulong t0)
f1aa6320
TS		 1041{
1042 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1043
b5dc7732
TS		 1044 if (other_tc == env->current_tc)
1045 env->active_tc.CP0_TCContext = t0;
1046 else
1047 env->tcs[other_tc].CP0_TCContext = t0;
f1aa6320
TS		 1048}
1049
be24bb4f 1050void do_mtc0_tcschedule (target_ulong t0)
f1aa6320 1051{
b5dc7732 1052 env->active_tc.CP0_TCSchedule = t0;
f1aa6320
TS		 1053}
1054
be24bb4f 1055void do_mttc0_tcschedule (target_ulong t0)
f1aa6320
TS		 1056{
1057 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1058
b5dc7732
TS		 1059 if (other_tc == env->current_tc)
1060 env->active_tc.CP0_TCSchedule = t0;
1061 else
1062 env->tcs[other_tc].CP0_TCSchedule = t0;
f1aa6320
TS		 1063}
1064
be24bb4f 1065void do_mtc0_tcschefback (target_ulong t0)
f1aa6320 1066{
b5dc7732 1067 env->active_tc.CP0_TCScheFBack = t0;
f1aa6320
TS		 1068}
1069
be24bb4f 1070void do_mttc0_tcschefback (target_ulong t0)
f1aa6320
TS		 1071{
1072 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1073
b5dc7732
TS		 1074 if (other_tc == env->current_tc)
1075 env->active_tc.CP0_TCScheFBack = t0;
1076 else
1077 env->tcs[other_tc].CP0_TCScheFBack = t0;
f1aa6320
TS		 1078}
1079
be24bb4f 1080void do_mtc0_entrylo1 (target_ulong t0)
f1aa6320
TS		 1081{
1082 /* Large physaddr (PABITS) not implemented */
1083 /* 1k pages not implemented */
be24bb4f 1084 env->CP0_EntryLo1 = t0 & 0x3FFFFFFF;
f1aa6320
TS		 1085}
1086
be24bb4f 1087void do_mtc0_context (target_ulong t0)
f1aa6320 1088{
be24bb4f 1089 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (t0 & ~0x007FFFFF);
f1aa6320
TS		 1090}
1091
be24bb4f 1092void do_mtc0_pagemask (target_ulong t0)
f1aa6320
TS		 1093{
1094 /* 1k pages not implemented */
be24bb4f 1095 env->CP0_PageMask = t0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
f1aa6320
TS		 1096}
1097
be24bb4f 1098void do_mtc0_pagegrain (target_ulong t0)
f1aa6320
TS		 1099{
1100 /* SmartMIPS not implemented */
1101 /* Large physaddr (PABITS) not implemented */
1102 /* 1k pages not implemented */
1103 env->CP0_PageGrain = 0;
1104}
1105
be24bb4f 1106void do_mtc0_wired (target_ulong t0)
f1aa6320 1107{
be24bb4f 1108 env->CP0_Wired = t0 % env->tlb->nb_tlb;
f1aa6320
TS		 1109}
1110
be24bb4f 1111void do_mtc0_srsconf0 (target_ulong t0)
f1aa6320 1112{
be24bb4f 1113 env->CP0_SRSConf0 |= t0 & env->CP0_SRSConf0_rw_bitmask;
f1aa6320
TS		 1114}
1115
be24bb4f 1116void do_mtc0_srsconf1 (target_ulong t0)
f1aa6320 1117{
be24bb4f 1118 env->CP0_SRSConf1 |= t0 & env->CP0_SRSConf1_rw_bitmask;
f1aa6320
TS		 1119}
1120
be24bb4f 1121void do_mtc0_srsconf2 (target_ulong t0)
f1aa6320 1122{
be24bb4f 1123 env->CP0_SRSConf2 |= t0 & env->CP0_SRSConf2_rw_bitmask;
f1aa6320
TS		 1124}
1125
be24bb4f 1126void do_mtc0_srsconf3 (target_ulong t0)
f1aa6320 1127{
be24bb4f 1128 env->CP0_SRSConf3 |= t0 & env->CP0_SRSConf3_rw_bitmask;
f1aa6320
TS		 1129}
1130
be24bb4f 1131void do_mtc0_srsconf4 (target_ulong t0)
f1aa6320 1132{
be24bb4f 1133 env->CP0_SRSConf4 |= t0 & env->CP0_SRSConf4_rw_bitmask;
f1aa6320
TS		 1134}
1135
be24bb4f 1136void do_mtc0_hwrena (target_ulong t0)
f1aa6320 1137{
be24bb4f 1138 env->CP0_HWREna = t0 & 0x0000000F;
f1aa6320
TS		 1139}
1140
be24bb4f 1141void do_mtc0_count (target_ulong t0)
f1aa6320 1142{
be24bb4f 1143 cpu_mips_store_count(env, t0);
f1aa6320
TS		 1144}
1145
be24bb4f 1146void do_mtc0_entryhi (target_ulong t0)
f1aa6320
TS		 1147{
1148 target_ulong old, val;
1149
1150 /* 1k pages not implemented */
be24bb4f 1151 val = t0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
f1aa6320
TS		 1152#if defined(TARGET_MIPS64)
1153 val &= env->SEGMask;
1154#endif
1155 old = env->CP0_EntryHi;
1156 env->CP0_EntryHi = val;
1157 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
b5dc7732
TS		 1158 uint32_t tcst = env->active_tc.CP0_TCStatus & ~0xff;
1159 env->active_tc.CP0_TCStatus = tcst | (val & 0xff);
f1aa6320
TS		 1160 }
1161 /* If the ASID changes, flush qemu's TLB. */
1162 if ((old & 0xFF) != (val & 0xFF))
1163 cpu_mips_tlb_flush(env, 1);
1164}
1165
be24bb4f 1166void do_mttc0_entryhi(target_ulong t0)
f1aa6320
TS		 1167{
1168 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
b5dc7732 1169 int32_t tcstatus;
f1aa6320 1170
be24bb4f 1171 env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (t0 & ~0xff);
b5dc7732
TS		 1172 if (other_tc == env->current_tc) {
1173 tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (t0 & 0xff);
1174 env->active_tc.CP0_TCStatus = tcstatus;
1175 } else {
1176 tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (t0 & 0xff);
1177 env->tcs[other_tc].CP0_TCStatus = tcstatus;
1178 }
f1aa6320
TS		 1179}
1180
be24bb4f 1181void do_mtc0_compare (target_ulong t0)
f1aa6320 1182{
be24bb4f 1183 cpu_mips_store_compare(env, t0);
f1aa6320
TS		 1184}
1185
be24bb4f 1186void do_mtc0_status (target_ulong t0)
f1aa6320
TS		 1187{
1188 uint32_t val, old;
1189 uint32_t mask = env->CP0_Status_rw_bitmask;
1190
be24bb4f 1191 val = t0 & mask;
f1aa6320
TS		 1192 old = env->CP0_Status;
1193 env->CP0_Status = (env->CP0_Status & ~mask) | val;
1194 compute_hflags(env);
1195 if (loglevel & CPU_LOG_EXEC)
1196 do_mtc0_status_debug(old, val);
1197 cpu_mips_update_irq(env);
1198}
1199
be24bb4f 1200void do_mttc0_status(target_ulong t0)
f1aa6320
TS		 1201{
1202 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
b5dc7732 1203 int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus;
f1aa6320 1204
be24bb4f
TS		 1205 env->CP0_Status = t0 & ~0xf1000018;
1206 tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (t0 & (0xf << CP0St_CU0));
1207 tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((t0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
1208 tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((t0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
b5dc7732
TS		 1209 if (other_tc == env->current_tc)
1210 env->active_tc.CP0_TCStatus = tcstatus;
1211 else
1212 env->tcs[other_tc].CP0_TCStatus = tcstatus;
f1aa6320
TS		 1213}
1214
be24bb4f 1215void do_mtc0_intctl (target_ulong t0)
f1aa6320
TS		 1216{
1217 /* vectored interrupts not implemented, no performance counters. */
be24bb4f 1218 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (t0 & 0x000002e0);
f1aa6320
TS		 1219}
1220
be24bb4f 1221void do_mtc0_srsctl (target_ulong t0)
f1aa6320
TS		 1222{
1223 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
be24bb4f 1224 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (t0 & mask);
f1aa6320
TS		 1225}
1226
be24bb4f 1227void do_mtc0_cause (target_ulong t0)
f1aa6320
TS		 1228{
1229 uint32_t mask = 0x00C00300;
1230 uint32_t old = env->CP0_Cause;
1231
1232 if (env->insn_flags & ISA_MIPS32R2)
1233 mask |= 1 << CP0Ca_DC;
1234
be24bb4f 1235 env->CP0_Cause = (env->CP0_Cause & ~mask) | (t0 & mask);
f1aa6320
TS		 1236
1237 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
1238 if (env->CP0_Cause & (1 << CP0Ca_DC))
1239 cpu_mips_stop_count(env);
1240 else
1241 cpu_mips_start_count(env);
1242 }
1243
1244 /* Handle the software interrupt as an hardware one, as they
1245 are very similar */
be24bb4f 1246 if (t0 & CP0Ca_IP_mask) {
f1aa6320
TS		 1247 cpu_mips_update_irq(env);
1248 }
1249}
1250
be24bb4f 1251void do_mtc0_ebase (target_ulong t0)
f1aa6320
TS		 1252{
1253 /* vectored interrupts not implemented */
1254 /* Multi-CPU not implemented */
be24bb4f 1255 env->CP0_EBase = 0x80000000 | (t0 & 0x3FFFF000);
f1aa6320
TS		 1256}
1257
be24bb4f 1258void do_mtc0_config0 (target_ulong t0)
f1aa6320 1259{
be24bb4f 1260 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (t0 & 0x00000007);
f1aa6320
TS		 1261}
1262
be24bb4f 1263void do_mtc0_config2 (target_ulong t0)
f1aa6320
TS		 1264{
1265 /* tertiary/secondary caches not implemented */
1266 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1267}
1268
be24bb4f 1269void do_mtc0_watchlo (target_ulong t0, uint32_t sel)
f1aa6320
TS		 1270{
1271 /* Watch exceptions for instructions, data loads, data stores
1272 not implemented. */
be24bb4f 1273 env->CP0_WatchLo[sel] = (t0 & ~0x7);
f1aa6320
TS		 1274}
1275
be24bb4f 1276void do_mtc0_watchhi (target_ulong t0, uint32_t sel)
f1aa6320 1277{
be24bb4f
TS		 1278 env->CP0_WatchHi[sel] = (t0 & 0x40FF0FF8);
1279 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & t0 & 0x7);
f1aa6320
TS		 1280}
1281
be24bb4f 1282void do_mtc0_xcontext (target_ulong t0)
f1aa6320
TS		 1283{
1284 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
be24bb4f 1285 env->CP0_XContext = (env->CP0_XContext & mask) | (t0 & ~mask);
f1aa6320
TS		 1286}
1287
be24bb4f 1288void do_mtc0_framemask (target_ulong t0)
f1aa6320 1289{
be24bb4f 1290 env->CP0_Framemask = t0; /* XXX */
f1aa6320
TS		 1291}
1292
be24bb4f 1293void do_mtc0_debug (target_ulong t0)
f1aa6320 1294{
be24bb4f
TS		 1295 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (t0 & 0x13300120);
1296 if (t0 & (1 << CP0DB_DM))
f1aa6320
TS		 1297 env->hflags |= MIPS_HFLAG_DM;
1298 else
1299 env->hflags &= ~MIPS_HFLAG_DM;
1300}
1301
be24bb4f 1302void do_mttc0_debug(target_ulong t0)
f1aa6320
TS		 1303{
1304 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
b5dc7732 1305 uint32_t val = t0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
f1aa6320
TS		 1306
1307 /* XXX: Might be wrong, check with EJTAG spec. */
b5dc7732
TS		 1308 if (other_tc == env->current_tc)
1309 env->active_tc.CP0_Debug_tcstatus = val;
1310 else
1311 env->tcs[other_tc].CP0_Debug_tcstatus = val;
f1aa6320 1312 env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
be24bb4f 1313 (t0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
f1aa6320
TS		 1314}
1315
be24bb4f 1316void do_mtc0_performance0 (target_ulong t0)
f1aa6320 1317{
be24bb4f 1318 env->CP0_Performance0 = t0 & 0x000007ff;
f1aa6320
TS		 1319}
1320
be24bb4f 1321void do_mtc0_taglo (target_ulong t0)
f1aa6320 1322{
be24bb4f 1323 env->CP0_TagLo = t0 & 0xFFFFFCF6;
f1aa6320
TS		 1324}
1325
be24bb4f 1326void do_mtc0_datalo (target_ulong t0)
f1aa6320 1327{
be24bb4f 1328 env->CP0_DataLo = t0; /* XXX */
f1aa6320
TS		 1329}
1330
be24bb4f 1331void do_mtc0_taghi (target_ulong t0)
f1aa6320 1332{
be24bb4f 1333 env->CP0_TagHi = t0; /* XXX */
f1aa6320
TS		 1334}
1335
be24bb4f 1336void do_mtc0_datahi (target_ulong t0)
f1aa6320 1337{
be24bb4f 1338 env->CP0_DataHi = t0; /* XXX */
f1aa6320
TS		 1339}
1340
8c0fdd85 1341void do_mtc0_status_debug(uint32_t old, uint32_t val)
6af0bf9c 1342{
f41c52f1
TS		 1343 fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
1344 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1345 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1346 env->CP0_Cause);
623a930e
TS		 1347 switch (env->hflags & MIPS_HFLAG_KSU) {
1348 case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break;
1349 case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break;
1350 case MIPS_HFLAG_KM: fputs("\n", logfile); break;
1351 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1352 }
8c0fdd85
TS		 1353}
1354
1355void do_mtc0_status_irqraise_debug(void)
1356{
1357 fprintf(logfile, "Raise pending IRQs\n");
6af0bf9c 1358}
f1aa6320
TS		 1359#endif /* !CONFIG_USER_ONLY */
1360
1361/* MIPS MT functions */
add69063 1362target_ulong do_mftgpr(uint32_t sel)
f1aa6320
TS		 1363{
1364 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1365
b5dc7732
TS		 1366 if (other_tc == env->current_tc)
1367 return env->active_tc.gpr[sel];
1368 else
1369 return env->tcs[other_tc].gpr[sel];
f1aa6320
TS		 1370}
1371
add69063 1372target_ulong do_mftlo(uint32_t sel)
f1aa6320
TS		 1373{
1374 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1375
b5dc7732
TS		 1376 if (other_tc == env->current_tc)
1377 return env->active_tc.LO[sel];
1378 else
1379 return env->tcs[other_tc].LO[sel];
f1aa6320
TS		 1380}
1381
add69063 1382target_ulong do_mfthi(uint32_t sel)
f1aa6320
TS		 1383{
1384 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1385
b5dc7732
TS		 1386 if (other_tc == env->current_tc)
1387 return env->active_tc.HI[sel];
1388 else
1389 return env->tcs[other_tc].HI[sel];
f1aa6320
TS		 1390}
1391
add69063 1392target_ulong do_mftacx(uint32_t sel)
f1aa6320
TS		 1393{
1394 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1395
b5dc7732
TS		 1396 if (other_tc == env->current_tc)
1397 return env->active_tc.ACX[sel];
1398 else
1399 return env->tcs[other_tc].ACX[sel];
f1aa6320
TS		 1400}
1401
add69063 1402target_ulong do_mftdsp(void)
f1aa6320
TS		 1403{
1404 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1405
b5dc7732
TS		 1406 if (other_tc == env->current_tc)
1407 return env->active_tc.DSPControl;
1408 else
1409 return env->tcs[other_tc].DSPControl;
f1aa6320 1410}
6af0bf9c 1411
be24bb4f 1412void do_mttgpr(target_ulong t0, uint32_t sel)
f1aa6320
TS		 1413{
1414 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1415
b5dc7732
TS		 1416 if (other_tc == env->current_tc)
1417 env->active_tc.gpr[sel] = t0;
1418 else
1419 env->tcs[other_tc].gpr[sel] = t0;
f1aa6320
TS		 1420}
1421
be24bb4f 1422void do_mttlo(target_ulong t0, uint32_t sel)
f1aa6320
TS		 1423{
1424 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1425
b5dc7732
TS		 1426 if (other_tc == env->current_tc)
1427 env->active_tc.LO[sel] = t0;
1428 else
1429 env->tcs[other_tc].LO[sel] = t0;
f1aa6320
TS		 1430}
1431
be24bb4f 1432void do_mtthi(target_ulong t0, uint32_t sel)
f1aa6320
TS		 1433{
1434 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1435
b5dc7732
TS		 1436 if (other_tc == env->current_tc)
1437 env->active_tc.HI[sel] = t0;
1438 else
1439 env->tcs[other_tc].HI[sel] = t0;
f1aa6320
TS		 1440}
1441
be24bb4f 1442void do_mttacx(target_ulong t0, uint32_t sel)
f1aa6320
TS		 1443{
1444 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1445
b5dc7732
TS		 1446 if (other_tc == env->current_tc)
1447 env->active_tc.ACX[sel] = t0;
1448 else
1449 env->tcs[other_tc].ACX[sel] = t0;
f1aa6320
TS		 1450}
1451
be24bb4f 1452void do_mttdsp(target_ulong t0)
f1aa6320
TS		 1453{
1454 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1455
b5dc7732
TS		 1456 if (other_tc == env->current_tc)
1457 env->active_tc.DSPControl = t0;
1458 else
1459 env->tcs[other_tc].DSPControl = t0;
f1aa6320
TS		 1460}
1461
1462/* MIPS MT functions */
be24bb4f 1463target_ulong do_dmt(target_ulong t0)
f1aa6320
TS		 1464{
1465 // TODO
be24bb4f
TS		 1466 t0 = 0;
1467 // rt = t0
1468
1469 return t0;
f1aa6320
TS		 1470}
1471
be24bb4f 1472target_ulong do_emt(target_ulong t0)
f1aa6320
TS		 1473{
1474 // TODO
be24bb4f
TS		 1475 t0 = 0;
1476 // rt = t0
1477
1478 return t0;
f1aa6320
TS		 1479}
1480
be24bb4f 1481target_ulong do_dvpe(target_ulong t0)
f1aa6320
TS		 1482{
1483 // TODO
be24bb4f
TS		 1484 t0 = 0;
1485 // rt = t0
1486
1487 return t0;
f1aa6320
TS		 1488}
1489
be24bb4f 1490target_ulong do_evpe(target_ulong t0)
f1aa6320
TS		 1491{
1492 // TODO
be24bb4f
TS		 1493 t0 = 0;
1494 // rt = t0
1495
1496 return t0;
f1aa6320
TS		 1497}
1498
6c5c1e20 1499void do_fork(target_ulong t0, target_ulong t1)
f1aa6320 1500{
be24bb4f
TS		 1501 // t0 = rt, t1 = rs
1502 t0 = 0;
f1aa6320
TS		 1503 // TODO: store to TC register
1504}
1505
be24bb4f 1506target_ulong do_yield(target_ulong t0)
f1aa6320 1507{
be24bb4f 1508 if (t0 < 0) {
f1aa6320 1509 /* No scheduling policy implemented. */
be24bb4f 1510 if (t0 != -2) {
f1aa6320 1511 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
b5dc7732 1512 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
f1aa6320
TS		 1513 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1514 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1515 do_raise_exception(EXCP_THREAD);
1516 }
1517 }
be24bb4f 1518 } else if (t0 == 0) {
f1aa6320
TS		 1519 if (0 /* TODO: TC underflow */) {
1520 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1521 do_raise_exception(EXCP_THREAD);
1522 } else {
1523 // TODO: Deallocate TC
1524 }
be24bb4f 1525 } else if (t0 > 0) {
f1aa6320
TS		 1526 /* Yield qualifier inputs not implemented. */
1527 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1528 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1529 do_raise_exception(EXCP_THREAD);
1530 }
be24bb4f 1531 return env->CP0_YQMask;
f1aa6320
TS		 1532}
1533
f1aa6320 1534#ifndef CONFIG_USER_ONLY
6af0bf9c 1535/* TLB management */
814b9a47
TS		 1536void cpu_mips_tlb_flush (CPUState *env, int flush_global)
1537{
1538 /* Flush qemu's TLB and discard all shadowed entries. */
1539 tlb_flush (env, flush_global);
ead9360e 1540 env->tlb->tlb_in_use = env->tlb->nb_tlb;
814b9a47
TS		 1541}
1542
29929e34 1543static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
814b9a47
TS		 1544{
1545 /* Discard entries from env->tlb[first] onwards. */
ead9360e
TS		 1546 while (env->tlb->tlb_in_use > first) {
1547 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
814b9a47
TS		 1548 }
1549}
1550
29929e34 1551static void r4k_fill_tlb (int idx)
6af0bf9c 1552{
29929e34 1553 r4k_tlb_t *tlb;
6af0bf9c
FB		 1554
1555 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
ead9360e 1556 tlb = &env->tlb->mmu.r4k.tlb[idx];
f2e9ebef 1557 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
d26bc211 1558#if defined(TARGET_MIPS64)
e034e2c3 1559 tlb->VPN &= env->SEGMask;
100ce988 1560#endif
98c1b82b 1561 tlb->ASID = env->CP0_EntryHi & 0xFF;
3b1c8be4 1562 tlb->PageMask = env->CP0_PageMask;
6af0bf9c 1563 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
98c1b82b
PB		 1564 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1565 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1566 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
6af0bf9c 1567 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
98c1b82b
PB		 1568 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1569 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1570 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
6af0bf9c
FB		 1571 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1572}
1573
29929e34 1574void r4k_do_tlbwi (void)
6af0bf9c 1575{
bbc0d79c
AJ		 1576 int idx;
1577
1578 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1579
814b9a47
TS		 1580 /* Discard cached TLB entries. We could avoid doing this if the
1581 tlbwi is just upgrading access permissions on the current entry;
1582 that might be a further win. */
ead9360e 1583 r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
814b9a47 1584
bbc0d79c
AJ		 1585 r4k_invalidate_tlb(env, idx, 0);
1586 r4k_fill_tlb(idx);
6af0bf9c
FB		 1587}
1588
29929e34 1589void r4k_do_tlbwr (void)
6af0bf9c
FB		 1590{
1591 int r = cpu_mips_get_random(env);
1592
29929e34
TS		 1593 r4k_invalidate_tlb(env, r, 1);
1594 r4k_fill_tlb(r);
6af0bf9c
FB		 1595}
1596
29929e34 1597void r4k_do_tlbp (void)
6af0bf9c 1598{
29929e34 1599 r4k_tlb_t *tlb;
f2e9ebef 1600 target_ulong mask;
6af0bf9c 1601 target_ulong tag;
f2e9ebef 1602 target_ulong VPN;
6af0bf9c
FB		 1603 uint8_t ASID;
1604 int i;
1605
3d9fb9fe 1606 ASID = env->CP0_EntryHi & 0xFF;
ead9360e
TS		 1607 for (i = 0; i < env->tlb->nb_tlb; i++) {
1608 tlb = &env->tlb->mmu.r4k.tlb[i];
f2e9ebef
TS		 1609 /* 1k pages are not supported. */
1610 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1611 tag = env->CP0_EntryHi & ~mask;
1612 VPN = tlb->VPN & ~mask;
6af0bf9c 1613 /* Check ASID, virtual page number & size */
f2e9ebef 1614 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
6af0bf9c 1615 /* TLB match */
9c2149c8 1616 env->CP0_Index = i;
6af0bf9c
FB		 1617 break;
1618 }
1619 }
ead9360e 1620 if (i == env->tlb->nb_tlb) {
814b9a47 1621 /* No match. Discard any shadow entries, if any of them match. */
ead9360e
TS		 1622 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1623 tlb = &env->tlb->mmu.r4k.tlb[i];
f2e9ebef
TS		 1624 /* 1k pages are not supported. */
1625 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1626 tag = env->CP0_EntryHi & ~mask;
1627 VPN = tlb->VPN & ~mask;
814b9a47 1628 /* Check ASID, virtual page number & size */
f2e9ebef 1629 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
29929e34 1630 r4k_mips_tlb_flush_extra (env, i);
814b9a47
TS		 1631 break;
1632 }
1633 }
1634
9c2149c8 1635 env->CP0_Index |= 0x80000000;
6af0bf9c
FB		 1636 }
1637}
1638
29929e34 1639void r4k_do_tlbr (void)
6af0bf9c 1640{
29929e34 1641 r4k_tlb_t *tlb;
09c56b84 1642 uint8_t ASID;
bbc0d79c 1643 int idx;
6af0bf9c 1644
09c56b84 1645 ASID = env->CP0_EntryHi & 0xFF;
bbc0d79c
AJ		 1646 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1647 tlb = &env->tlb->mmu.r4k.tlb[idx];
4ad40f36
FB		 1648
1649 /* If this will change the current ASID, flush qemu's TLB. */
814b9a47
TS		 1650 if (ASID != tlb->ASID)
1651 cpu_mips_tlb_flush (env, 1);
1652
ead9360e 1653 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
4ad40f36 1654
6af0bf9c 1655 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
3b1c8be4 1656 env->CP0_PageMask = tlb->PageMask;
7495fd0f
TS		 1657 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1658 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1659 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1660 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
6af0bf9c 1661}
6af0bf9c 1662
a7812ae4
PB		 1663void do_tlbwi(void)
1664{
1665 env->tlb->do_tlbwi();
1666}
1667
1668void do_tlbwr(void)
1669{
1670 env->tlb->do_tlbwr();
1671}
1672
1673void do_tlbp(void)
1674{
1675 env->tlb->do_tlbp();
1676}
1677
1678void do_tlbr(void)
1679{
1680 env->tlb->do_tlbr();
1681}
1682
2b0233ab 1683/* Specials */
2796188e 1684target_ulong do_di (void)
2b0233ab 1685{
2796188e
TS		 1686 target_ulong t0 = env->CP0_Status;
1687
be24bb4f 1688 env->CP0_Status = t0 & ~(1 << CP0St_IE);
2b0233ab 1689 cpu_mips_update_irq(env);
be24bb4f
TS		 1690
1691 return t0;
2b0233ab
TS		 1692}
1693
2796188e 1694target_ulong do_ei (void)
2b0233ab 1695{
2796188e
TS		 1696 target_ulong t0 = env->CP0_Status;
1697
be24bb4f 1698 env->CP0_Status = t0 | (1 << CP0St_IE);
2b0233ab 1699 cpu_mips_update_irq(env);
be24bb4f
TS		 1700
1701 return t0;
2b0233ab
TS		 1702}
1703
f41c52f1 1704void debug_pre_eret (void)
6af0bf9c 1705{
f41c52f1 1706 fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
b5dc7732 1707 env->active_tc.PC, env->CP0_EPC);
f41c52f1
TS		 1708 if (env->CP0_Status & (1 << CP0St_ERL))
1709 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1710 if (env->hflags & MIPS_HFLAG_DM)
1711 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1712 fputs("\n", logfile);
1713}
1714
1715void debug_post_eret (void)
1716{
744e0915 1717 fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
b5dc7732 1718 env->active_tc.PC, env->CP0_EPC);
f41c52f1
TS		 1719 if (env->CP0_Status & (1 << CP0St_ERL))
1720 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1721 if (env->hflags & MIPS_HFLAG_DM)
1722 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
623a930e
TS		 1723 switch (env->hflags & MIPS_HFLAG_KSU) {
1724 case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break;
1725 case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break;
1726 case MIPS_HFLAG_KM: fputs("\n", logfile); break;
1727 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1728 }
6af0bf9c
FB		 1729}
1730
6c5c1e20 1731void do_eret (void)
2b0233ab
TS		 1732{
1733 if (loglevel & CPU_LOG_EXEC)
1734 debug_pre_eret();
1735 if (env->CP0_Status & (1 << CP0St_ERL)) {
b5dc7732 1736 env->active_tc.PC = env->CP0_ErrorEPC;
2b0233ab
TS		 1737 env->CP0_Status &= ~(1 << CP0St_ERL);
1738 } else {
b5dc7732 1739 env->active_tc.PC = env->CP0_EPC;
2b0233ab
TS		 1740 env->CP0_Status &= ~(1 << CP0St_EXL);
1741 }
1742 compute_hflags(env);
1743 if (loglevel & CPU_LOG_EXEC)
1744 debug_post_eret();
1745 env->CP0_LLAddr = 1;
1746}
1747
6c5c1e20 1748void do_deret (void)
2b0233ab
TS		 1749{
1750 if (loglevel & CPU_LOG_EXEC)
1751 debug_pre_eret();
b5dc7732 1752 env->active_tc.PC = env->CP0_DEPC;
2b0233ab
TS		 1753 env->hflags &= MIPS_HFLAG_DM;
1754 compute_hflags(env);
1755 if (loglevel & CPU_LOG_EXEC)
1756 debug_post_eret();
1757 env->CP0_LLAddr = 1;
1758}
0eaef5aa 1759#endif /* !CONFIG_USER_ONLY */
2b0233ab 1760
2796188e 1761target_ulong do_rdhwr_cpunum(void)
2b0233ab
TS		 1762{
1763 if ((env->hflags & MIPS_HFLAG_CP0) ||
1764 (env->CP0_HWREna & (1 << 0)))
2796188e 1765 return env->CP0_EBase & 0x3ff;
2b0233ab
TS		 1766 else
1767 do_raise_exception(EXCP_RI);
be24bb4f 1768
2796188e 1769 return 0;
2b0233ab
TS		 1770}
1771
2796188e 1772target_ulong do_rdhwr_synci_step(void)
2b0233ab
TS		 1773{
1774 if ((env->hflags & MIPS_HFLAG_CP0) ||
1775 (env->CP0_HWREna & (1 << 1)))
2796188e 1776 return env->SYNCI_Step;
2b0233ab
TS		 1777 else
1778 do_raise_exception(EXCP_RI);
be24bb4f 1779
2796188e 1780 return 0;
2b0233ab
TS		 1781}
1782
2796188e 1783target_ulong do_rdhwr_cc(void)
2b0233ab
TS		 1784{
1785 if ((env->hflags & MIPS_HFLAG_CP0) ||
1786 (env->CP0_HWREna & (1 << 2)))
2796188e 1787 return env->CP0_Count;
2b0233ab
TS		 1788 else
1789 do_raise_exception(EXCP_RI);
be24bb4f 1790
2796188e 1791 return 0;
2b0233ab
TS		 1792}
1793
2796188e 1794target_ulong do_rdhwr_ccres(void)
2b0233ab
TS		 1795{
1796 if ((env->hflags & MIPS_HFLAG_CP0) ||
1797 (env->CP0_HWREna & (1 << 3)))
2796188e 1798 return env->CCRes;
2b0233ab
TS		 1799 else
1800 do_raise_exception(EXCP_RI);
be24bb4f 1801
2796188e 1802 return 0;
2b0233ab
TS		 1803}
1804
6af0bf9c
FB		 1805void do_pmon (int function)
1806{
1807 function /= 2;
1808 switch (function) {
1809 case 2: /* TODO: char inbyte(int waitflag); */
b5dc7732
TS		 1810 if (env->active_tc.gpr[4] == 0)
1811 env->active_tc.gpr[2] = -1;
6af0bf9c
FB		 1812 /* Fall through */
1813 case 11: /* TODO: char inbyte (void); */
b5dc7732 1814 env->active_tc.gpr[2] = -1;
6af0bf9c
FB		 1815 break;
1816 case 3:
1817 case 12:
b5dc7732 1818 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
6af0bf9c
FB		 1819 break;
1820 case 17:
1821 break;
1822 case 158:
1823 {
b5dc7732 1824 unsigned char *fmt = (void *)(unsigned long)env->active_tc.gpr[4];
6af0bf9c
FB		 1825 printf("%s", fmt);
1826 }
1827 break;
1828 }
1829}
e37e863f 1830
08ba7963
TS		 1831void do_wait (void)
1832{
1833 env->halted = 1;
1834 do_raise_exception(EXCP_HLT);
1835}
1836
5fafdf24 1837#if !defined(CONFIG_USER_ONLY)
e37e863f 1838
4ad40f36
FB		 1839static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
1840
e37e863f 1841#define MMUSUFFIX _mmu
4ad40f36 1842#define ALIGNED_ONLY
e37e863f
FB		 1843
1844#define SHIFT 0
1845#include "softmmu_template.h"
1846
1847#define SHIFT 1
1848#include "softmmu_template.h"
1849
1850#define SHIFT 2
1851#include "softmmu_template.h"
1852
1853#define SHIFT 3
1854#include "softmmu_template.h"
1855
4ad40f36
FB		 1856static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
1857{
1858 env->CP0_BadVAddr = addr;
1859 do_restore_state (retaddr);
1860 do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
1861}
1862
6ebbf390 1863void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
e37e863f
FB		 1864{
1865 TranslationBlock *tb;
1866 CPUState *saved_env;
1867 unsigned long pc;
1868 int ret;
1869
1870 /* XXX: hack to restore env in all cases, even if not called from
1871 generated code */
1872 saved_env = env;
1873 env = cpu_single_env;
6ebbf390 1874 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
e37e863f
FB		 1875 if (ret) {
1876 if (retaddr) {
1877 /* now we have a real cpu fault */
1878 pc = (unsigned long)retaddr;
1879 tb = tb_find_pc(pc);
1880 if (tb) {
1881 /* the PC is inside the translated code. It means that we have
1882 a virtual CPU fault */
1883 cpu_restore_state(tb, env, pc, NULL);
1884 }
1885 }
1886 do_raise_exception_err(env->exception_index, env->error_code);
1887 }
1888 env = saved_env;
1889}
1890
647de6ca 1891void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
e18231a3 1892 int unused, int size)
647de6ca
TS		 1893{
1894 if (is_exec)
1895 do_raise_exception(EXCP_IBE);
1896 else
1897 do_raise_exception(EXCP_DBE);
1898}
f1aa6320 1899#endif /* !CONFIG_USER_ONLY */
fd4a04eb
TS		 1900
1901/* Complex FPU operations which may need stack space. */
1902
f090c9d4
PB		 1903#define FLOAT_ONE32 make_float32(0x3f8 << 20)
1904#define FLOAT_ONE64 make_float64(0x3ffULL << 52)
1905#define FLOAT_TWO32 make_float32(1 << 30)
1906#define FLOAT_TWO64 make_float64(1ULL << 62)
54454097
TS		 1907#define FLOAT_QNAN32 0x7fbfffff
1908#define FLOAT_QNAN64 0x7ff7ffffffffffffULL
1909#define FLOAT_SNAN32 0x7fffffff
1910#define FLOAT_SNAN64 0x7fffffffffffffffULL
8dfdb87c 1911
fd4a04eb
TS		 1912/* convert MIPS rounding mode in FCR31 to IEEE library */
1913unsigned int ieee_rm[] = {
1914 float_round_nearest_even,
1915 float_round_to_zero,
1916 float_round_up,
1917 float_round_down
1918};
1919
1920#define RESTORE_ROUNDING_MODE \
f01be154 1921 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
fd4a04eb 1922
6c5c1e20 1923target_ulong do_cfc1 (uint32_t reg)
fd4a04eb 1924{
6c5c1e20
TS		 1925 target_ulong t0;
1926
ead9360e
TS		 1927 switch (reg) {
1928 case 0:
f01be154 1929 t0 = (int32_t)env->active_fpu.fcr0;
ead9360e
TS		 1930 break;
1931 case 25:
f01be154 1932 t0 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
ead9360e
TS		 1933 break;
1934 case 26:
f01be154 1935 t0 = env->active_fpu.fcr31 & 0x0003f07c;
ead9360e
TS		 1936 break;
1937 case 28:
f01be154 1938 t0 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
ead9360e
TS		 1939 break;
1940 default:
f01be154 1941 t0 = (int32_t)env->active_fpu.fcr31;
ead9360e
TS		 1942 break;
1943 }
be24bb4f
TS		 1944
1945 return t0;
ead9360e
TS		 1946}
1947
be24bb4f 1948void do_ctc1 (target_ulong t0, uint32_t reg)
ead9360e
TS		 1949{
1950 switch(reg) {
fd4a04eb 1951 case 25:
be24bb4f 1952 if (t0 & 0xffffff00)
fd4a04eb 1953 return;
f01be154 1954 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((t0 & 0xfe) << 24) |
be24bb4f 1955 ((t0 & 0x1) << 23);
fd4a04eb
TS		 1956 break;
1957 case 26:
be24bb4f 1958 if (t0 & 0x007c0000)
fd4a04eb 1959 return;
f01be154 1960 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (t0 & 0x0003f07c);
fd4a04eb
TS		 1961 break;
1962 case 28:
be24bb4f 1963 if (t0 & 0x007c0000)
fd4a04eb 1964 return;
f01be154 1965 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (t0 & 0x00000f83) |
be24bb4f 1966 ((t0 & 0x4) << 22);
fd4a04eb
TS		 1967 break;
1968 case 31:
be24bb4f 1969 if (t0 & 0x007c0000)
fd4a04eb 1970 return;
f01be154 1971 env->active_fpu.fcr31 = t0;
fd4a04eb
TS		 1972 break;
1973 default:
1974 return;
1975 }
1976 /* set rounding mode */
1977 RESTORE_ROUNDING_MODE;
f01be154
TS		 1978 set_float_exception_flags(0, &env->active_fpu.fp_status);
1979 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
fd4a04eb
TS		 1980 do_raise_exception(EXCP_FPE);
1981}
1982
c904ef0e 1983static inline char ieee_ex_to_mips(char xcpt)
fd4a04eb
TS		 1984{
1985 return (xcpt & float_flag_inexact) >> 5 |
1986 (xcpt & float_flag_underflow) >> 3 |
1987 (xcpt & float_flag_overflow) >> 1 |
1988 (xcpt & float_flag_divbyzero) << 1 |
1989 (xcpt & float_flag_invalid) << 4;
1990}
1991
c904ef0e 1992static inline char mips_ex_to_ieee(char xcpt)
fd4a04eb
TS		 1993{
1994 return (xcpt & FP_INEXACT) << 5 |
1995 (xcpt & FP_UNDERFLOW) << 3 |
1996 (xcpt & FP_OVERFLOW) << 1 |
1997 (xcpt & FP_DIV0) >> 1 |
1998 (xcpt & FP_INVALID) >> 4;
1999}
2000
c904ef0e 2001static inline void update_fcr31(void)
fd4a04eb 2002{
f01be154 2003 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
fd4a04eb 2004
f01be154
TS		 2005 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2006 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp)
fd4a04eb
TS		 2007 do_raise_exception(EXCP_FPE);
2008 else
f01be154 2009 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
fd4a04eb
TS		 2010}
2011
a16336e4
TS		 2012/* Float support.
2013 Single precition routines have a "s" suffix, double precision a
2014 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2015 paired single lower "pl", paired single upper "pu". */
2016
a16336e4 2017/* unary operations, modifying fp status */
b6d96bed
TS		 2018uint64_t do_float_sqrt_d(uint64_t fdt0)
2019{
f01be154 2020 return float64_sqrt(fdt0, &env->active_fpu.fp_status);
b6d96bed
TS		 2021}
2022
2023uint32_t do_float_sqrt_s(uint32_t fst0)
2024{
f01be154 2025 return float32_sqrt(fst0, &env->active_fpu.fp_status);
b6d96bed 2026}
a16336e4 2027
b6d96bed 2028uint64_t do_float_cvtd_s(uint32_t fst0)
fd4a04eb 2029{
b6d96bed
TS		 2030 uint64_t fdt2;
2031
f01be154
TS		 2032 set_float_exception_flags(0, &env->active_fpu.fp_status);
2033 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
fd4a04eb 2034 update_fcr31();
b6d96bed 2035 return fdt2;
fd4a04eb 2036}
b6d96bed
TS		 2037
2038uint64_t do_float_cvtd_w(uint32_t wt0)
fd4a04eb 2039{
b6d96bed
TS		 2040 uint64_t fdt2;
2041
f01be154
TS		 2042 set_float_exception_flags(0, &env->active_fpu.fp_status);
2043 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
fd4a04eb 2044 update_fcr31();
b6d96bed 2045 return fdt2;
fd4a04eb 2046}
b6d96bed
TS		 2047
2048uint64_t do_float_cvtd_l(uint64_t dt0)
fd4a04eb 2049{
b6d96bed
TS		 2050 uint64_t fdt2;
2051
f01be154
TS		 2052 set_float_exception_flags(0, &env->active_fpu.fp_status);
2053 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
fd4a04eb 2054 update_fcr31();
b6d96bed 2055 return fdt2;
fd4a04eb 2056}
b6d96bed
TS		 2057
2058uint64_t do_float_cvtl_d(uint64_t fdt0)
fd4a04eb 2059{
b6d96bed
TS		 2060 uint64_t dt2;
2061
f01be154
TS		 2062 set_float_exception_flags(0, &env->active_fpu.fp_status);
2063 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2064 update_fcr31();
f01be154 2065 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2066 dt2 = FLOAT_SNAN64;
2067 return dt2;
fd4a04eb 2068}
b6d96bed
TS		 2069
2070uint64_t do_float_cvtl_s(uint32_t fst0)
fd4a04eb 2071{
b6d96bed
TS		 2072 uint64_t dt2;
2073
f01be154
TS		 2074 set_float_exception_flags(0, &env->active_fpu.fp_status);
2075 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
fd4a04eb 2076 update_fcr31();
f01be154 2077 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2078 dt2 = FLOAT_SNAN64;
2079 return dt2;
fd4a04eb
TS		 2080}
2081
b6d96bed 2082uint64_t do_float_cvtps_pw(uint64_t dt0)
fd4a04eb 2083{
b6d96bed
TS		 2084 uint32_t fst2;
2085 uint32_t fsth2;
2086
f01be154
TS		 2087 set_float_exception_flags(0, &env->active_fpu.fp_status);
2088 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2089 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
fd4a04eb 2090 update_fcr31();
b6d96bed 2091 return ((uint64_t)fsth2 << 32) | fst2;
fd4a04eb 2092}
b6d96bed
TS		 2093
2094uint64_t do_float_cvtpw_ps(uint64_t fdt0)
fd4a04eb 2095{
b6d96bed
TS		 2096 uint32_t wt2;
2097 uint32_t wth2;
2098
f01be154
TS		 2099 set_float_exception_flags(0, &env->active_fpu.fp_status);
2100 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2101 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
fd4a04eb 2102 update_fcr31();
f01be154 2103 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) {
b6d96bed
TS		 2104 wt2 = FLOAT_SNAN32;
2105 wth2 = FLOAT_SNAN32;
2106 }
2107 return ((uint64_t)wth2 << 32) | wt2;
fd4a04eb 2108}
b6d96bed
TS		 2109
2110uint32_t do_float_cvts_d(uint64_t fdt0)
fd4a04eb 2111{
b6d96bed
TS		 2112 uint32_t fst2;
2113
f01be154
TS		 2114 set_float_exception_flags(0, &env->active_fpu.fp_status);
2115 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2116 update_fcr31();
b6d96bed 2117 return fst2;
fd4a04eb 2118}
b6d96bed
TS		 2119
2120uint32_t do_float_cvts_w(uint32_t wt0)
fd4a04eb 2121{
b6d96bed
TS		 2122 uint32_t fst2;
2123
f01be154
TS		 2124 set_float_exception_flags(0, &env->active_fpu.fp_status);
2125 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
fd4a04eb 2126 update_fcr31();
b6d96bed 2127 return fst2;
fd4a04eb 2128}
b6d96bed
TS		 2129
2130uint32_t do_float_cvts_l(uint64_t dt0)
fd4a04eb 2131{
b6d96bed
TS		 2132 uint32_t fst2;
2133
f01be154
TS		 2134 set_float_exception_flags(0, &env->active_fpu.fp_status);
2135 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
fd4a04eb 2136 update_fcr31();
b6d96bed 2137 return fst2;
fd4a04eb 2138}
b6d96bed
TS		 2139
2140uint32_t do_float_cvts_pl(uint32_t wt0)
fd4a04eb 2141{
b6d96bed
TS		 2142 uint32_t wt2;
2143
f01be154 2144 set_float_exception_flags(0, &env->active_fpu.fp_status);
b6d96bed 2145 wt2 = wt0;
fd4a04eb 2146 update_fcr31();
b6d96bed 2147 return wt2;
fd4a04eb 2148}
b6d96bed
TS		 2149
2150uint32_t do_float_cvts_pu(uint32_t wth0)
fd4a04eb 2151{
b6d96bed
TS		 2152 uint32_t wt2;
2153
f01be154 2154 set_float_exception_flags(0, &env->active_fpu.fp_status);
b6d96bed 2155 wt2 = wth0;
fd4a04eb 2156 update_fcr31();
b6d96bed 2157 return wt2;
fd4a04eb 2158}
b6d96bed
TS		 2159
2160uint32_t do_float_cvtw_s(uint32_t fst0)
fd4a04eb 2161{
b6d96bed
TS		 2162 uint32_t wt2;
2163
f01be154
TS		 2164 set_float_exception_flags(0, &env->active_fpu.fp_status);
2165 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
fd4a04eb 2166 update_fcr31();
f01be154 2167 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2168 wt2 = FLOAT_SNAN32;
2169 return wt2;
fd4a04eb 2170}
b6d96bed
TS		 2171
2172uint32_t do_float_cvtw_d(uint64_t fdt0)
fd4a04eb 2173{
b6d96bed
TS		 2174 uint32_t wt2;
2175
f01be154
TS		 2176 set_float_exception_flags(0, &env->active_fpu.fp_status);
2177 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2178 update_fcr31();
f01be154 2179 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2180 wt2 = FLOAT_SNAN32;
2181 return wt2;
fd4a04eb
TS		 2182}
2183
b6d96bed 2184uint64_t do_float_roundl_d(uint64_t fdt0)
fd4a04eb 2185{
b6d96bed
TS		 2186 uint64_t dt2;
2187
f01be154
TS		 2188 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2189 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2190 RESTORE_ROUNDING_MODE;
2191 update_fcr31();
f01be154 2192 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2193 dt2 = FLOAT_SNAN64;
2194 return dt2;
fd4a04eb 2195}
b6d96bed
TS		 2196
2197uint64_t do_float_roundl_s(uint32_t fst0)
fd4a04eb 2198{
b6d96bed
TS		 2199 uint64_t dt2;
2200
f01be154
TS		 2201 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2202 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2203 RESTORE_ROUNDING_MODE;
2204 update_fcr31();
f01be154 2205 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2206 dt2 = FLOAT_SNAN64;
2207 return dt2;
fd4a04eb 2208}
b6d96bed
TS		 2209
2210uint32_t do_float_roundw_d(uint64_t fdt0)
fd4a04eb 2211{
b6d96bed
TS		 2212 uint32_t wt2;
2213
f01be154
TS		 2214 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2215 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2216 RESTORE_ROUNDING_MODE;
2217 update_fcr31();
f01be154 2218 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2219 wt2 = FLOAT_SNAN32;
2220 return wt2;
fd4a04eb 2221}
b6d96bed
TS		 2222
2223uint32_t do_float_roundw_s(uint32_t fst0)
fd4a04eb 2224{
b6d96bed
TS		 2225 uint32_t wt2;
2226
f01be154
TS		 2227 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2228 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2229 RESTORE_ROUNDING_MODE;
2230 update_fcr31();
f01be154 2231 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2232 wt2 = FLOAT_SNAN32;
2233 return wt2;
fd4a04eb
TS		 2234}
2235
b6d96bed 2236uint64_t do_float_truncl_d(uint64_t fdt0)
fd4a04eb 2237{
b6d96bed
TS		 2238 uint64_t dt2;
2239
f01be154 2240 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2241 update_fcr31();
f01be154 2242 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2243 dt2 = FLOAT_SNAN64;
2244 return dt2;
fd4a04eb 2245}
b6d96bed
TS		 2246
2247uint64_t do_float_truncl_s(uint32_t fst0)
fd4a04eb 2248{
b6d96bed
TS		 2249 uint64_t dt2;
2250
f01be154 2251 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
fd4a04eb 2252 update_fcr31();
f01be154 2253 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2254 dt2 = FLOAT_SNAN64;
2255 return dt2;
fd4a04eb 2256}
b6d96bed
TS		 2257
2258uint32_t do_float_truncw_d(uint64_t fdt0)
fd4a04eb 2259{
b6d96bed
TS		 2260 uint32_t wt2;
2261
f01be154 2262 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2263 update_fcr31();
f01be154 2264 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2265 wt2 = FLOAT_SNAN32;
2266 return wt2;
fd4a04eb 2267}
b6d96bed
TS		 2268
2269uint32_t do_float_truncw_s(uint32_t fst0)
fd4a04eb 2270{
b6d96bed
TS		 2271 uint32_t wt2;
2272
f01be154 2273 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
fd4a04eb 2274 update_fcr31();
f01be154 2275 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2276 wt2 = FLOAT_SNAN32;
2277 return wt2;
fd4a04eb
TS		 2278}
2279
b6d96bed 2280uint64_t do_float_ceill_d(uint64_t fdt0)
fd4a04eb 2281{
b6d96bed
TS		 2282 uint64_t dt2;
2283
f01be154
TS		 2284 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2285 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2286 RESTORE_ROUNDING_MODE;
2287 update_fcr31();
f01be154 2288 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2289 dt2 = FLOAT_SNAN64;
2290 return dt2;
fd4a04eb 2291}
b6d96bed
TS		 2292
2293uint64_t do_float_ceill_s(uint32_t fst0)
fd4a04eb 2294{
b6d96bed
TS		 2295 uint64_t dt2;
2296
f01be154
TS		 2297 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2298 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2299 RESTORE_ROUNDING_MODE;
2300 update_fcr31();
f01be154 2301 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2302 dt2 = FLOAT_SNAN64;
2303 return dt2;
fd4a04eb 2304}
b6d96bed
TS		 2305
2306uint32_t do_float_ceilw_d(uint64_t fdt0)
fd4a04eb 2307{
b6d96bed
TS		 2308 uint32_t wt2;
2309
f01be154
TS		 2310 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2311 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2312 RESTORE_ROUNDING_MODE;
2313 update_fcr31();
f01be154 2314 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2315 wt2 = FLOAT_SNAN32;
2316 return wt2;
fd4a04eb 2317}
b6d96bed
TS		 2318
2319uint32_t do_float_ceilw_s(uint32_t fst0)
fd4a04eb 2320{
b6d96bed
TS		 2321 uint32_t wt2;
2322
f01be154
TS		 2323 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2324 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2325 RESTORE_ROUNDING_MODE;
2326 update_fcr31();
f01be154 2327 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2328 wt2 = FLOAT_SNAN32;
2329 return wt2;
fd4a04eb
TS		 2330}
2331
b6d96bed 2332uint64_t do_float_floorl_d(uint64_t fdt0)
fd4a04eb 2333{
b6d96bed
TS		 2334 uint64_t dt2;
2335
f01be154
TS		 2336 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2337 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2338 RESTORE_ROUNDING_MODE;
2339 update_fcr31();
f01be154 2340 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2341 dt2 = FLOAT_SNAN64;
2342 return dt2;
fd4a04eb 2343}
b6d96bed
TS		 2344
2345uint64_t do_float_floorl_s(uint32_t fst0)
fd4a04eb 2346{
b6d96bed
TS		 2347 uint64_t dt2;
2348
f01be154
TS		 2349 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2350 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2351 RESTORE_ROUNDING_MODE;
2352 update_fcr31();
f01be154 2353 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2354 dt2 = FLOAT_SNAN64;
2355 return dt2;
fd4a04eb 2356}
b6d96bed
TS		 2357
2358uint32_t do_float_floorw_d(uint64_t fdt0)
fd4a04eb 2359{
b6d96bed
TS		 2360 uint32_t wt2;
2361
f01be154
TS		 2362 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2363 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2364 RESTORE_ROUNDING_MODE;
2365 update_fcr31();
f01be154 2366 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2367 wt2 = FLOAT_SNAN32;
2368 return wt2;
fd4a04eb 2369}
b6d96bed
TS		 2370
2371uint32_t do_float_floorw_s(uint32_t fst0)
fd4a04eb 2372{
b6d96bed
TS		 2373 uint32_t wt2;
2374
f01be154
TS		 2375 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2376 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2377 RESTORE_ROUNDING_MODE;
2378 update_fcr31();
f01be154 2379 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2380 wt2 = FLOAT_SNAN32;
2381 return wt2;
fd4a04eb
TS		 2382}
2383
a16336e4 2384/* unary operations, not modifying fp status */
b6d96bed
TS		 2385#define FLOAT_UNOP(name) \
2386uint64_t do_float_ ## name ## _d(uint64_t fdt0) \
2387{ \
2388 return float64_ ## name(fdt0); \
2389} \
2390uint32_t do_float_ ## name ## _s(uint32_t fst0) \
2391{ \
2392 return float32_ ## name(fst0); \
2393} \
2394uint64_t do_float_ ## name ## _ps(uint64_t fdt0) \
2395{ \
2396 uint32_t wt0; \
2397 uint32_t wth0; \
2398 \
2399 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
2400 wth0 = float32_ ## name(fdt0 >> 32); \
2401 return ((uint64_t)wth0 << 32) | wt0; \
a16336e4
TS		 2402}
2403FLOAT_UNOP(abs)
2404FLOAT_UNOP(chs)
2405#undef FLOAT_UNOP
2406
8dfdb87c 2407/* MIPS specific unary operations */
b6d96bed 2408uint64_t do_float_recip_d(uint64_t fdt0)
8dfdb87c 2409{
b6d96bed
TS		 2410 uint64_t fdt2;
2411
f01be154
TS		 2412 set_float_exception_flags(0, &env->active_fpu.fp_status);
2413 fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
8dfdb87c 2414 update_fcr31();
b6d96bed 2415 return fdt2;
8dfdb87c 2416}
b6d96bed
TS		 2417
2418uint32_t do_float_recip_s(uint32_t fst0)
8dfdb87c 2419{
b6d96bed
TS		 2420 uint32_t fst2;
2421
f01be154
TS		 2422 set_float_exception_flags(0, &env->active_fpu.fp_status);
2423 fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
8dfdb87c 2424 update_fcr31();
b6d96bed 2425 return fst2;
57fa1fb3 2426}
57fa1fb3 2427
b6d96bed 2428uint64_t do_float_rsqrt_d(uint64_t fdt0)
8dfdb87c 2429{
b6d96bed
TS		 2430 uint64_t fdt2;
2431
f01be154
TS		 2432 set_float_exception_flags(0, &env->active_fpu.fp_status);
2433 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2434 fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
8dfdb87c 2435 update_fcr31();
b6d96bed 2436 return fdt2;
8dfdb87c 2437}
b6d96bed
TS		 2438
2439uint32_t do_float_rsqrt_s(uint32_t fst0)
8dfdb87c 2440{
b6d96bed
TS		 2441 uint32_t fst2;
2442
f01be154
TS		 2443 set_float_exception_flags(0, &env->active_fpu.fp_status);
2444 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2445 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
8dfdb87c 2446 update_fcr31();
b6d96bed 2447 return fst2;
8dfdb87c
TS		 2448}
2449
b6d96bed 2450uint64_t do_float_recip1_d(uint64_t fdt0)
8dfdb87c 2451{
b6d96bed
TS		 2452 uint64_t fdt2;
2453
f01be154
TS		 2454 set_float_exception_flags(0, &env->active_fpu.fp_status);
2455 fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
8dfdb87c 2456 update_fcr31();
b6d96bed 2457 return fdt2;
8dfdb87c 2458}
b6d96bed
TS		 2459
2460uint32_t do_float_recip1_s(uint32_t fst0)
8dfdb87c 2461{
b6d96bed
TS		 2462 uint32_t fst2;
2463
f01be154
TS		 2464 set_float_exception_flags(0, &env->active_fpu.fp_status);
2465 fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
8dfdb87c 2466 update_fcr31();
b6d96bed 2467 return fst2;
8dfdb87c 2468}
b6d96bed
TS		 2469
2470uint64_t do_float_recip1_ps(uint64_t fdt0)
8dfdb87c 2471{
b6d96bed
TS		 2472 uint32_t fst2;
2473 uint32_t fsth2;
2474
f01be154
TS		 2475 set_float_exception_flags(0, &env->active_fpu.fp_status);
2476 fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2477 fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status);
8dfdb87c 2478 update_fcr31();
b6d96bed 2479 return ((uint64_t)fsth2 << 32) | fst2;
8dfdb87c
TS		 2480}
2481
b6d96bed 2482uint64_t do_float_rsqrt1_d(uint64_t fdt0)
8dfdb87c 2483{
b6d96bed
TS		 2484 uint64_t fdt2;
2485
f01be154
TS		 2486 set_float_exception_flags(0, &env->active_fpu.fp_status);
2487 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2488 fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
8dfdb87c 2489 update_fcr31();
b6d96bed 2490 return fdt2;
8dfdb87c 2491}
b6d96bed
TS		 2492
2493uint32_t do_float_rsqrt1_s(uint32_t fst0)
8dfdb87c 2494{
b6d96bed
TS		 2495 uint32_t fst2;
2496
f01be154
TS		 2497 set_float_exception_flags(0, &env->active_fpu.fp_status);
2498 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2499 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
8dfdb87c 2500 update_fcr31();
b6d96bed 2501 return fst2;
8dfdb87c 2502}
b6d96bed
TS		 2503
2504uint64_t do_float_rsqrt1_ps(uint64_t fdt0)
8dfdb87c 2505{
b6d96bed
TS		 2506 uint32_t fst2;
2507 uint32_t fsth2;
2508
f01be154
TS		 2509 set_float_exception_flags(0, &env->active_fpu.fp_status);
2510 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2511 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2512 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2513 fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status);
8dfdb87c 2514 update_fcr31();
b6d96bed 2515 return ((uint64_t)fsth2 << 32) | fst2;
57fa1fb3 2516}
57fa1fb3 2517
b6d96bed
TS		 2518#define FLOAT_OP(name, p) void do_float_##name##_##p(void)
2519
fd4a04eb 2520/* binary operations */
b6d96bed
TS		 2521#define FLOAT_BINOP(name) \
2522uint64_t do_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \
2523{ \
2524 uint64_t dt2; \
2525 \
f01be154
TS		 2526 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2527 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
ead9360e 2528 update_fcr31(); \
f01be154 2529 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
b6d96bed
TS		 2530 dt2 = FLOAT_QNAN64; \
2531 return dt2; \
2532} \
2533 \
2534uint32_t do_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \
2535{ \
2536 uint32_t wt2; \
2537 \
f01be154
TS		 2538 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2539 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
ead9360e 2540 update_fcr31(); \
f01be154 2541 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
b6d96bed
TS		 2542 wt2 = FLOAT_QNAN32; \
2543 return wt2; \
2544} \
2545 \
2546uint64_t do_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \
2547{ \
2548 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2549 uint32_t fsth0 = fdt0 >> 32; \
2550 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2551 uint32_t fsth1 = fdt1 >> 32; \
2552 uint32_t wt2; \
2553 uint32_t wth2; \
2554 \
f01be154
TS		 2555 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2556 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2557 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
b6d96bed 2558 update_fcr31(); \
f01be154 2559 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \
b6d96bed
TS		 2560 wt2 = FLOAT_QNAN32; \
2561 wth2 = FLOAT_QNAN32; \
2562 } \
2563 return ((uint64_t)wth2 << 32) | wt2; \
fd4a04eb 2564}
b6d96bed 2565
fd4a04eb
TS		 2566FLOAT_BINOP(add)
2567FLOAT_BINOP(sub)
2568FLOAT_BINOP(mul)
2569FLOAT_BINOP(div)
2570#undef FLOAT_BINOP
2571
a16336e4 2572/* ternary operations */
b6d96bed
TS		 2573#define FLOAT_TERNOP(name1, name2) \
2574uint64_t do_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
2575 uint64_t fdt2) \
2576{ \
f01be154
TS		 2577 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2578 return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2579} \
2580 \
2581uint32_t do_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
2582 uint32_t fst2) \
2583{ \
f01be154
TS		 2584 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2585 return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2586} \
2587 \
2588uint64_t do_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \
2589 uint64_t fdt2) \
2590{ \
2591 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2592 uint32_t fsth0 = fdt0 >> 32; \
2593 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2594 uint32_t fsth1 = fdt1 >> 32; \
2595 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2596 uint32_t fsth2 = fdt2 >> 32; \
2597 \
f01be154
TS		 2598 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2599 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
2600 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2601 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
b6d96bed 2602 return ((uint64_t)fsth2 << 32) | fst2; \
a16336e4 2603}
b6d96bed 2604
a16336e4
TS		 2605FLOAT_TERNOP(mul, add)
2606FLOAT_TERNOP(mul, sub)
2607#undef FLOAT_TERNOP
2608
2609/* negated ternary operations */
b6d96bed
TS		 2610#define FLOAT_NTERNOP(name1, name2) \
2611uint64_t do_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
2612 uint64_t fdt2) \
2613{ \
f01be154
TS		 2614 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2615 fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2616 return float64_chs(fdt2); \
2617} \
2618 \
2619uint32_t do_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
2620 uint32_t fst2) \
2621{ \
f01be154
TS		 2622 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2623 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2624 return float32_chs(fst2); \
2625} \
2626 \
2627uint64_t do_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\
2628 uint64_t fdt2) \
2629{ \
2630 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2631 uint32_t fsth0 = fdt0 >> 32; \
2632 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2633 uint32_t fsth1 = fdt1 >> 32; \
2634 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2635 uint32_t fsth2 = fdt2 >> 32; \
2636 \
f01be154
TS		 2637 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2638 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
2639 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2640 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2641 fst2 = float32_chs(fst2); \
2642 fsth2 = float32_chs(fsth2); \
2643 return ((uint64_t)fsth2 << 32) | fst2; \
a16336e4 2644}
b6d96bed 2645
a16336e4
TS		 2646FLOAT_NTERNOP(mul, add)
2647FLOAT_NTERNOP(mul, sub)
2648#undef FLOAT_NTERNOP
2649
8dfdb87c 2650/* MIPS specific binary operations */
b6d96bed 2651uint64_t do_float_recip2_d(uint64_t fdt0, uint64_t fdt2)
8dfdb87c 2652{
f01be154
TS		 2653 set_float_exception_flags(0, &env->active_fpu.fp_status);
2654 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2655 fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status));
8dfdb87c 2656 update_fcr31();
b6d96bed 2657 return fdt2;
8dfdb87c 2658}
b6d96bed
TS		 2659
2660uint32_t do_float_recip2_s(uint32_t fst0, uint32_t fst2)
8dfdb87c 2661{
f01be154
TS		 2662 set_float_exception_flags(0, &env->active_fpu.fp_status);
2663 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2664 fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
8dfdb87c 2665 update_fcr31();
b6d96bed 2666 return fst2;
8dfdb87c 2667}
b6d96bed
TS		 2668
2669uint64_t do_float_recip2_ps(uint64_t fdt0, uint64_t fdt2)
8dfdb87c 2670{
b6d96bed
TS		 2671 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2672 uint32_t fsth0 = fdt0 >> 32;
2673 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2674 uint32_t fsth2 = fdt2 >> 32;
2675
f01be154
TS		 2676 set_float_exception_flags(0, &env->active_fpu.fp_status);
2677 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2678 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2679 fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
2680 fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status));
8dfdb87c 2681 update_fcr31();
b6d96bed 2682 return ((uint64_t)fsth2 << 32) | fst2;
8dfdb87c
TS		 2683}
2684
b6d96bed 2685uint64_t do_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2)
8dfdb87c 2686{
f01be154
TS		 2687 set_float_exception_flags(0, &env->active_fpu.fp_status);
2688 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2689 fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status);
2690 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
8dfdb87c 2691 update_fcr31();
b6d96bed 2692 return fdt2;
8dfdb87c 2693}
b6d96bed
TS		 2694
2695uint32_t do_float_rsqrt2_s(uint32_t fst0, uint32_t fst2)
8dfdb87c 2696{
f01be154
TS		 2697 set_float_exception_flags(0, &env->active_fpu.fp_status);
2698 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2699 fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
2700 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
8dfdb87c 2701 update_fcr31();
b6d96bed 2702 return fst2;
8dfdb87c 2703}
b6d96bed
TS		 2704
2705uint64_t do_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2)
8dfdb87c 2706{
b6d96bed
TS		 2707 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2708 uint32_t fsth0 = fdt0 >> 32;
2709 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2710 uint32_t fsth2 = fdt2 >> 32;
2711
f01be154
TS		 2712 set_float_exception_flags(0, &env->active_fpu.fp_status);
2713 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2714 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2715 fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
2716 fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status);
2717 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2718 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
8dfdb87c 2719 update_fcr31();
b6d96bed 2720 return ((uint64_t)fsth2 << 32) | fst2;
57fa1fb3 2721}
57fa1fb3 2722
b6d96bed 2723uint64_t do_float_addr_ps(uint64_t fdt0, uint64_t fdt1)
fd4a04eb 2724{
b6d96bed
TS		 2725 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2726 uint32_t fsth0 = fdt0 >> 32;
2727 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2728 uint32_t fsth1 = fdt1 >> 32;
2729 uint32_t fst2;
2730 uint32_t fsth2;
2731
f01be154
TS		 2732 set_float_exception_flags(0, &env->active_fpu.fp_status);
2733 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
2734 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
fd4a04eb 2735 update_fcr31();
b6d96bed 2736 return ((uint64_t)fsth2 << 32) | fst2;
fd4a04eb
TS		 2737}
2738
b6d96bed 2739uint64_t do_float_mulr_ps(uint64_t fdt0, uint64_t fdt1)
57fa1fb3 2740{
b6d96bed
TS		 2741 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2742 uint32_t fsth0 = fdt0 >> 32;
2743 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2744 uint32_t fsth1 = fdt1 >> 32;
2745 uint32_t fst2;
2746 uint32_t fsth2;
2747
f01be154
TS		 2748 set_float_exception_flags(0, &env->active_fpu.fp_status);
2749 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
2750 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
57fa1fb3 2751 update_fcr31();
b6d96bed 2752 return ((uint64_t)fsth2 << 32) | fst2;
57fa1fb3
TS		 2753}
2754
8dfdb87c 2755/* compare operations */
b6d96bed
TS		 2756#define FOP_COND_D(op, cond) \
2757void do_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2758{ \
2759 int c = cond; \
2760 update_fcr31(); \
2761 if (c) \
f01be154 2762 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2763 else \
f01be154 2764 CLEAR_FP_COND(cc, env->active_fpu); \
b6d96bed
TS		 2765} \
2766void do_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2767{ \
2768 int c; \
2769 fdt0 = float64_abs(fdt0); \
2770 fdt1 = float64_abs(fdt1); \
2771 c = cond; \
2772 update_fcr31(); \
2773 if (c) \
f01be154 2774 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2775 else \
f01be154 2776 CLEAR_FP_COND(cc, env->active_fpu); \
fd4a04eb
TS		 2777}
2778
2779int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
2780{
2781 if (float64_is_signaling_nan(a) ||
2782 float64_is_signaling_nan(b) ||
2783 (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
2784 float_raise(float_flag_invalid, status);
2785 return 1;
2786 } else if (float64_is_nan(a) || float64_is_nan(b)) {
2787 return 1;
2788 } else {
2789 return 0;
2790 }
2791}
2792
2793/* NOTE: the comma operator will make "cond" to eval to false,
2794 * but float*_is_unordered() is still called. */
f01be154
TS		 2795FOP_COND_D(f, (float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status), 0))
2796FOP_COND_D(un, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status))
2797FOP_COND_D(eq, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2798FOP_COND_D(ueq, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2799FOP_COND_D(olt, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2800FOP_COND_D(ult, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2801FOP_COND_D(ole, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2802FOP_COND_D(ule, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
fd4a04eb
TS		 2803/* NOTE: the comma operator will make "cond" to eval to false,
2804 * but float*_is_unordered() is still called. */
f01be154
TS		 2805FOP_COND_D(sf, (float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status), 0))
2806FOP_COND_D(ngle,float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status))
2807FOP_COND_D(seq, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2808FOP_COND_D(ngl, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2809FOP_COND_D(lt, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2810FOP_COND_D(nge, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2811FOP_COND_D(le, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2812FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
b6d96bed
TS		 2813
2814#define FOP_COND_S(op, cond) \
2815void do_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
2816{ \
2817 int c = cond; \
2818 update_fcr31(); \
2819 if (c) \
f01be154 2820 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2821 else \
f01be154 2822 CLEAR_FP_COND(cc, env->active_fpu); \
b6d96bed
TS		 2823} \
2824void do_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
2825{ \
2826 int c; \
2827 fst0 = float32_abs(fst0); \
2828 fst1 = float32_abs(fst1); \
2829 c = cond; \
2830 update_fcr31(); \
2831 if (c) \
f01be154 2832 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2833 else \
f01be154 2834 CLEAR_FP_COND(cc, env->active_fpu); \
fd4a04eb
TS		 2835}
2836
2837flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
2838{
fd4a04eb
TS		 2839 if (float32_is_signaling_nan(a) ||
2840 float32_is_signaling_nan(b) ||
2841 (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
2842 float_raise(float_flag_invalid, status);
2843 return 1;
2844 } else if (float32_is_nan(a) || float32_is_nan(b)) {
2845 return 1;
2846 } else {
2847 return 0;
2848 }
2849}
2850
2851/* NOTE: the comma operator will make "cond" to eval to false,
2852 * but float*_is_unordered() is still called. */
f01be154
TS		 2853FOP_COND_S(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0))
2854FOP_COND_S(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status))
2855FOP_COND_S(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2856FOP_COND_S(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2857FOP_COND_S(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2858FOP_COND_S(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2859FOP_COND_S(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
2860FOP_COND_S(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
fd4a04eb
TS		 2861/* NOTE: the comma operator will make "cond" to eval to false,
2862 * but float*_is_unordered() is still called. */
f01be154
TS		 2863FOP_COND_S(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0))
2864FOP_COND_S(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status))
2865FOP_COND_S(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2866FOP_COND_S(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2867FOP_COND_S(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2868FOP_COND_S(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2869FOP_COND_S(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
2870FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
b6d96bed
TS		 2871
2872#define FOP_COND_PS(op, condl, condh) \
2873void do_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2874{ \
2875 uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
2876 uint32_t fsth0 = float32_abs(fdt0 >> 32); \
2877 uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
2878 uint32_t fsth1 = float32_abs(fdt1 >> 32); \
2879 int cl = condl; \
2880 int ch = condh; \
2881 \
2882 update_fcr31(); \
2883 if (cl) \
f01be154 2884 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2885 else \
f01be154 2886 CLEAR_FP_COND(cc, env->active_fpu); \
b6d96bed 2887 if (ch) \
f01be154 2888 SET_FP_COND(cc + 1, env->active_fpu); \
b6d96bed 2889 else \
f01be154 2890 CLEAR_FP_COND(cc + 1, env->active_fpu); \
b6d96bed
TS		 2891} \
2892void do_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2893{ \
2894 uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
2895 uint32_t fsth0 = float32_abs(fdt0 >> 32); \
2896 uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
2897 uint32_t fsth1 = float32_abs(fdt1 >> 32); \
2898 int cl = condl; \
2899 int ch = condh; \
2900 \
2901 update_fcr31(); \
2902 if (cl) \
f01be154 2903 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2904 else \
f01be154 2905 CLEAR_FP_COND(cc, env->active_fpu); \
b6d96bed 2906 if (ch) \
f01be154 2907 SET_FP_COND(cc + 1, env->active_fpu); \
b6d96bed 2908 else \
f01be154 2909 CLEAR_FP_COND(cc + 1, env->active_fpu); \
fd4a04eb
TS		 2910}
2911
2912/* NOTE: the comma operator will make "cond" to eval to false,
2913 * but float*_is_unordered() is still called. */
f01be154
TS		 2914FOP_COND_PS(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0),
2915 (float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status), 0))
2916FOP_COND_PS(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status),
2917 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status))
2918FOP_COND_PS(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2919 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2920FOP_COND_PS(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2921 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2922FOP_COND_PS(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2923 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2924FOP_COND_PS(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2925 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2926FOP_COND_PS(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status),
2927 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
2928FOP_COND_PS(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
2929 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
fd4a04eb
TS		 2930/* NOTE: the comma operator will make "cond" to eval to false,
2931 * but float*_is_unordered() is still called. */
f01be154
TS		 2932FOP_COND_PS(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0),
2933 (float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status), 0))
2934FOP_COND_PS(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status),
2935 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status))
2936FOP_COND_PS(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2937 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2938FOP_COND_PS(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2939 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2940FOP_COND_PS(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2941 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2942FOP_COND_PS(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2943 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2944FOP_COND_PS(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status),
2945 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
2946FOP_COND_PS(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
2947 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
Qemu copy for testing