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remove unused stuff from */exec.h
[qemu.git] / target-mips / op_helper.c
CommitLineData
6af0bf9c
FB		 1/*
2 * MIPS emulation helpers for qemu.
5fafdf24 3 *
6af0bf9c
FB		 4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
6af0bf9c 18 */
2d0e944d 19#include <stdlib.h>
6af0bf9c
FB		 20#include "exec.h"
21
05f778c8
TS		 22#include "host-utils.h"
23
a7812ae4 24#include "helper.h"
83dae095
PB		 25
26#ifndef CONFIG_USER_ONLY
27static inline void cpu_mips_tlb_flush (CPUState *env, int flush_global);
28#endif
29
6af0bf9c
FB		 30/*****************************************************************************/
31/* Exceptions processing helpers */
6af0bf9c 32
c01fccd2 33void helper_raise_exception_err (uint32_t exception, int error_code)
6af0bf9c
FB		 34{
35#if 1
93fcfe39
AL		 36 if (exception < 0x100)
37 qemu_log("%s: %d %d\n", __func__, exception, error_code);
6af0bf9c
FB		 38#endif
39 env->exception_index = exception;
40 env->error_code = error_code;
6af0bf9c
FB		 41 cpu_loop_exit();
42}
43
c01fccd2 44void helper_raise_exception (uint32_t exception)
6af0bf9c 45{
c01fccd2 46 helper_raise_exception_err(exception, 0);
6af0bf9c
FB		 47}
48
c01fccd2 49void helper_interrupt_restart (void)
48d38ca5
TS		 50{
51 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
52 !(env->CP0_Status & (1 << CP0St_ERL)) &&
53 !(env->hflags & MIPS_HFLAG_DM) &&
54 (env->CP0_Status & (1 << CP0St_IE)) &&
55 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
56 env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
c01fccd2 57 helper_raise_exception(EXCP_EXT_INTERRUPT);
48d38ca5
TS		 58 }
59}
60
f9480ffc
TS		 61#if !defined(CONFIG_USER_ONLY)
62static void do_restore_state (void *pc_ptr)
4ad40f36 63{
a607922c
FB		 64 TranslationBlock *tb;
65 unsigned long pc = (unsigned long) pc_ptr;
66
67 tb = tb_find_pc (pc);
68 if (tb) {
69 cpu_restore_state (tb, env, pc, NULL);
70 }
4ad40f36 71}
f9480ffc 72#endif
4ad40f36 73
0ae43045
AJ		 74#if defined(CONFIG_USER_ONLY)
75#define HELPER_LD(name, insn, type) \
76static inline type do_##name(target_ulong addr, int mem_idx) \
77{ \
78 return (type) insn##_raw(addr); \
79}
80#else
81#define HELPER_LD(name, insn, type) \
82static inline type do_##name(target_ulong addr, int mem_idx) \
83{ \
84 switch (mem_idx) \
85 { \
86 case 0: return (type) insn##_kernel(addr); break; \
87 case 1: return (type) insn##_super(addr); break; \
88 default: \
89 case 2: return (type) insn##_user(addr); break; \
90 } \
91}
92#endif
93HELPER_LD(lbu, ldub, uint8_t)
94HELPER_LD(lw, ldl, int32_t)
95#ifdef TARGET_MIPS64
96HELPER_LD(ld, ldq, int64_t)
97#endif
98#undef HELPER_LD
99
100#if defined(CONFIG_USER_ONLY)
101#define HELPER_ST(name, insn, type) \
102static inline void do_##name(target_ulong addr, type val, int mem_idx) \
103{ \
104 insn##_raw(addr, val); \
105}
106#else
107#define HELPER_ST(name, insn, type) \
108static inline void do_##name(target_ulong addr, type val, int mem_idx) \
109{ \
110 switch (mem_idx) \
111 { \
112 case 0: insn##_kernel(addr, val); break; \
113 case 1: insn##_super(addr, val); break; \
114 default: \
115 case 2: insn##_user(addr, val); break; \
116 } \
117}
118#endif
119HELPER_ST(sb, stb, uint8_t)
120HELPER_ST(sw, stl, uint32_t)
121#ifdef TARGET_MIPS64
122HELPER_ST(sd, stq, uint64_t)
123#endif
124#undef HELPER_ST
125
d9bea114 126target_ulong helper_clo (target_ulong arg1)
30898801 127{
d9bea114 128 return clo32(arg1);
30898801
TS		 129}
130
d9bea114 131target_ulong helper_clz (target_ulong arg1)
30898801 132{
d9bea114 133 return clz32(arg1);
30898801
TS		 134}
135
d26bc211 136#if defined(TARGET_MIPS64)
d9bea114 137target_ulong helper_dclo (target_ulong arg1)
05f778c8 138{
d9bea114 139 return clo64(arg1);
05f778c8
TS		 140}
141
d9bea114 142target_ulong helper_dclz (target_ulong arg1)
05f778c8 143{
d9bea114 144 return clz64(arg1);
05f778c8 145}
d26bc211 146#endif /* TARGET_MIPS64 */
c570fd16 147
6af0bf9c 148/* 64 bits arithmetic for 32 bits hosts */
c904ef0e 149static inline uint64_t get_HILO (void)
6af0bf9c 150{
b5dc7732 151 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
6af0bf9c
FB		 152}
153
c904ef0e 154static inline void set_HILO (uint64_t HILO)
6af0bf9c 155{
b5dc7732
TS		 156 env->active_tc.LO[0] = (int32_t)HILO;
157 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
6af0bf9c
FB		 158}
159
d9bea114 160static inline void set_HIT0_LO (target_ulong arg1, uint64_t HILO)
e9c71dd1 161{
b5dc7732 162 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
d9bea114 163 arg1 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
e9c71dd1
TS		 164}
165
d9bea114 166static inline void set_HI_LOT0 (target_ulong arg1, uint64_t HILO)
e9c71dd1 167{
d9bea114 168 arg1 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
b5dc7732 169 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
e9c71dd1
TS		 170}
171
e9c71dd1 172/* Multiplication variants of the vr54xx. */
d9bea114 173target_ulong helper_muls (target_ulong arg1, target_ulong arg2)
e9c71dd1 174{
d9bea114 175 set_HI_LOT0(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 176
d9bea114 177 return arg1;
e9c71dd1
TS		 178}
179
d9bea114 180target_ulong helper_mulsu (target_ulong arg1, target_ulong arg2)
e9c71dd1 181{
d9bea114 182 set_HI_LOT0(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 183
d9bea114 184 return arg1;
e9c71dd1
TS		 185}
186
d9bea114 187target_ulong helper_macc (target_ulong arg1, target_ulong arg2)
e9c71dd1 188{
d9bea114 189 set_HI_LOT0(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 190
d9bea114 191 return arg1;
e9c71dd1
TS		 192}
193
d9bea114 194target_ulong helper_macchi (target_ulong arg1, target_ulong arg2)
e9c71dd1 195{
d9bea114 196 set_HIT0_LO(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 197
d9bea114 198 return arg1;
e9c71dd1
TS		 199}
200
d9bea114 201target_ulong helper_maccu (target_ulong arg1, target_ulong arg2)
e9c71dd1 202{
d9bea114 203 set_HI_LOT0(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 204
d9bea114 205 return arg1;
e9c71dd1
TS		 206}
207
d9bea114 208target_ulong helper_macchiu (target_ulong arg1, target_ulong arg2)
e9c71dd1 209{
d9bea114 210 set_HIT0_LO(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 211
d9bea114 212 return arg1;
e9c71dd1
TS		 213}
214
d9bea114 215target_ulong helper_msac (target_ulong arg1, target_ulong arg2)
e9c71dd1 216{
d9bea114 217 set_HI_LOT0(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 218
d9bea114 219 return arg1;
e9c71dd1
TS		 220}
221
d9bea114 222target_ulong helper_msachi (target_ulong arg1, target_ulong arg2)
e9c71dd1 223{
d9bea114 224 set_HIT0_LO(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 225
d9bea114 226 return arg1;
e9c71dd1
TS		 227}
228
d9bea114 229target_ulong helper_msacu (target_ulong arg1, target_ulong arg2)
e9c71dd1 230{
d9bea114 231 set_HI_LOT0(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 232
d9bea114 233 return arg1;
e9c71dd1
TS		 234}
235
d9bea114 236target_ulong helper_msachiu (target_ulong arg1, target_ulong arg2)
e9c71dd1 237{
d9bea114 238 set_HIT0_LO(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 239
d9bea114 240 return arg1;
e9c71dd1
TS		 241}
242
d9bea114 243target_ulong helper_mulhi (target_ulong arg1, target_ulong arg2)
e9c71dd1 244{
d9bea114 245 set_HIT0_LO(arg1, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
be24bb4f 246
d9bea114 247 return arg1;
e9c71dd1
TS		 248}
249
d9bea114 250target_ulong helper_mulhiu (target_ulong arg1, target_ulong arg2)
e9c71dd1 251{
d9bea114 252 set_HIT0_LO(arg1, (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
be24bb4f 253
d9bea114 254 return arg1;
e9c71dd1
TS		 255}
256
d9bea114 257target_ulong helper_mulshi (target_ulong arg1, target_ulong arg2)
e9c71dd1 258{
d9bea114 259 set_HIT0_LO(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
be24bb4f 260
d9bea114 261 return arg1;
e9c71dd1
TS		 262}
263
d9bea114 264target_ulong helper_mulshiu (target_ulong arg1, target_ulong arg2)
e9c71dd1 265{
d9bea114 266 set_HIT0_LO(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
be24bb4f 267
d9bea114 268 return arg1;
e9c71dd1 269}
6af0bf9c 270
214c465f 271#ifdef TARGET_MIPS64
d9bea114 272void helper_dmult (target_ulong arg1, target_ulong arg2)
214c465f 273{
d9bea114 274 muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
214c465f
TS		 275}
276
d9bea114 277void helper_dmultu (target_ulong arg1, target_ulong arg2)
214c465f 278{
d9bea114 279 mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
214c465f
TS		 280}
281#endif
282
e7139c44 283#ifndef CONFIG_USER_ONLY
c36bbb28
AJ		 284
285static inline target_phys_addr_t do_translate_address(target_ulong address, int rw)
286{
287 target_phys_addr_t lladdr;
288
289 lladdr = cpu_mips_translate_address(env, address, rw);
290
291 if (lladdr == -1LL) {
292 cpu_loop_exit();
293 } else {
294 return lladdr;
295 }
296}
297
e7139c44
AJ		 298#define HELPER_LD_ATOMIC(name, insn) \
299target_ulong helper_##name(target_ulong arg, int mem_idx) \
300{ \
c36bbb28 301 env->lladdr = do_translate_address(arg, 0); \
e7139c44
AJ		 302 env->llval = do_##insn(arg, mem_idx); \
303 return env->llval; \
304}
305HELPER_LD_ATOMIC(ll, lw)
306#ifdef TARGET_MIPS64
307HELPER_LD_ATOMIC(lld, ld)
308#endif
309#undef HELPER_LD_ATOMIC
310
311#define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
312target_ulong helper_##name(target_ulong arg1, target_ulong arg2, int mem_idx) \
313{ \
314 target_long tmp; \
315 \
316 if (arg2 & almask) { \
317 env->CP0_BadVAddr = arg2; \
318 helper_raise_exception(EXCP_AdES); \
319 } \
c36bbb28 320 if (do_translate_address(arg2, 1) == env->lladdr) { \
e7139c44
AJ		 321 tmp = do_##ld_insn(arg2, mem_idx); \
322 if (tmp == env->llval) { \
323 do_##st_insn(arg2, arg1, mem_idx); \
324 return 1; \
325 } \
326 } \
327 return 0; \
328}
329HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
330#ifdef TARGET_MIPS64
331HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
332#endif
333#undef HELPER_ST_ATOMIC
334#endif
335
c8c2227e
TS		 336#ifdef TARGET_WORDS_BIGENDIAN
337#define GET_LMASK(v) ((v) & 3)
338#define GET_OFFSET(addr, offset) (addr + (offset))
339#else
340#define GET_LMASK(v) (((v) & 3) ^ 3)
341#define GET_OFFSET(addr, offset) (addr - (offset))
342#endif
343
d9bea114 344target_ulong helper_lwl(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e
TS		 345{
346 target_ulong tmp;
347
0ae43045 348 tmp = do_lbu(arg2, mem_idx);
d9bea114 349 arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
c8c2227e 350
d9bea114 351 if (GET_LMASK(arg2) <= 2) {
0ae43045 352 tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx);
d9bea114 353 arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
c8c2227e
TS		 354 }
355
d9bea114 356 if (GET_LMASK(arg2) <= 1) {
0ae43045 357 tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx);
d9bea114 358 arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
c8c2227e
TS		 359 }
360
d9bea114 361 if (GET_LMASK(arg2) == 0) {
0ae43045 362 tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx);
d9bea114 363 arg1 = (arg1 & 0xFFFFFF00) | tmp;
c8c2227e 364 }
d9bea114 365 return (int32_t)arg1;
c8c2227e
TS		 366}
367
d9bea114 368target_ulong helper_lwr(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e
TS		 369{
370 target_ulong tmp;
371
0ae43045 372 tmp = do_lbu(arg2, mem_idx);
d9bea114 373 arg1 = (arg1 & 0xFFFFFF00) | tmp;
c8c2227e 374
d9bea114 375 if (GET_LMASK(arg2) >= 1) {
0ae43045 376 tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx);
d9bea114 377 arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
c8c2227e
TS		 378 }
379
d9bea114 380 if (GET_LMASK(arg2) >= 2) {
0ae43045 381 tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx);
d9bea114 382 arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
c8c2227e
TS		 383 }
384
d9bea114 385 if (GET_LMASK(arg2) == 3) {
0ae43045 386 tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx);
d9bea114 387 arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
c8c2227e 388 }
d9bea114 389 return (int32_t)arg1;
c8c2227e
TS		 390}
391
d9bea114 392void helper_swl(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e 393{
0ae43045 394 do_sb(arg2, (uint8_t)(arg1 >> 24), mem_idx);
c8c2227e 395
d9bea114 396 if (GET_LMASK(arg2) <= 2)
0ae43045 397 do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
c8c2227e 398
d9bea114 399 if (GET_LMASK(arg2) <= 1)
0ae43045 400 do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
c8c2227e 401
d9bea114 402 if (GET_LMASK(arg2) == 0)
0ae43045 403 do_sb(GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
c8c2227e
TS		 404}
405
d9bea114 406void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e 407{
0ae43045 408 do_sb(arg2, (uint8_t)arg1, mem_idx);
c8c2227e 409
d9bea114 410 if (GET_LMASK(arg2) >= 1)
0ae43045 411 do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
c8c2227e 412
d9bea114 413 if (GET_LMASK(arg2) >= 2)
0ae43045 414 do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
c8c2227e 415
d9bea114 416 if (GET_LMASK(arg2) == 3)
0ae43045 417 do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
c8c2227e
TS		 418}
419
420#if defined(TARGET_MIPS64)
421/* "half" load and stores. We must do the memory access inline,
422 or fault handling won't work. */
423
424#ifdef TARGET_WORDS_BIGENDIAN
425#define GET_LMASK64(v) ((v) & 7)
426#else
427#define GET_LMASK64(v) (((v) & 7) ^ 7)
428#endif
429
d9bea114 430target_ulong helper_ldl(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e
TS		 431{
432 uint64_t tmp;
433
0ae43045 434 tmp = do_lbu(arg2, mem_idx);
d9bea114 435 arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
c8c2227e 436
d9bea114 437 if (GET_LMASK64(arg2) <= 6) {
0ae43045 438 tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx);
d9bea114 439 arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
c8c2227e
TS		 440 }
441
d9bea114 442 if (GET_LMASK64(arg2) <= 5) {
0ae43045 443 tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx);
d9bea114 444 arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
c8c2227e
TS		 445 }
446
d9bea114 447 if (GET_LMASK64(arg2) <= 4) {
0ae43045 448 tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx);
d9bea114 449 arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
c8c2227e
TS		 450 }
451
d9bea114 452 if (GET_LMASK64(arg2) <= 3) {
0ae43045 453 tmp = do_lbu(GET_OFFSET(arg2, 4), mem_idx);
d9bea114 454 arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
c8c2227e
TS		 455 }
456
d9bea114 457 if (GET_LMASK64(arg2) <= 2) {
0ae43045 458 tmp = do_lbu(GET_OFFSET(arg2, 5), mem_idx);
d9bea114 459 arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
c8c2227e
TS		 460 }
461
d9bea114 462 if (GET_LMASK64(arg2) <= 1) {
0ae43045 463 tmp = do_lbu(GET_OFFSET(arg2, 6), mem_idx);
d9bea114 464 arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
c8c2227e
TS		 465 }
466
d9bea114 467 if (GET_LMASK64(arg2) == 0) {
0ae43045 468 tmp = do_lbu(GET_OFFSET(arg2, 7), mem_idx);
d9bea114 469 arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
c8c2227e 470 }
be24bb4f 471
d9bea114 472 return arg1;
c8c2227e
TS		 473}
474
d9bea114 475target_ulong helper_ldr(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e
TS		 476{
477 uint64_t tmp;
478
0ae43045 479 tmp = do_lbu(arg2, mem_idx);
d9bea114 480 arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
c8c2227e 481
d9bea114 482 if (GET_LMASK64(arg2) >= 1) {
0ae43045 483 tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx);
d9bea114 484 arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
c8c2227e
TS		 485 }
486
d9bea114 487 if (GET_LMASK64(arg2) >= 2) {
0ae43045 488 tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx);
d9bea114 489 arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
c8c2227e
TS		 490 }
491
d9bea114 492 if (GET_LMASK64(arg2) >= 3) {
0ae43045 493 tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx);
d9bea114 494 arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
c8c2227e
TS		 495 }
496
d9bea114 497 if (GET_LMASK64(arg2) >= 4) {
0ae43045 498 tmp = do_lbu(GET_OFFSET(arg2, -4), mem_idx);
d9bea114 499 arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
c8c2227e
TS		 500 }
501
d9bea114 502 if (GET_LMASK64(arg2) >= 5) {
0ae43045 503 tmp = do_lbu(GET_OFFSET(arg2, -5), mem_idx);
d9bea114 504 arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
c8c2227e
TS		 505 }
506
d9bea114 507 if (GET_LMASK64(arg2) >= 6) {
0ae43045 508 tmp = do_lbu(GET_OFFSET(arg2, -6), mem_idx);
d9bea114 509 arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
c8c2227e
TS		 510 }
511
d9bea114 512 if (GET_LMASK64(arg2) == 7) {
0ae43045 513 tmp = do_lbu(GET_OFFSET(arg2, -7), mem_idx);
d9bea114 514 arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
c8c2227e 515 }
be24bb4f 516
d9bea114 517 return arg1;
c8c2227e
TS		 518}
519
d9bea114 520void helper_sdl(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e 521{
0ae43045 522 do_sb(arg2, (uint8_t)(arg1 >> 56), mem_idx);
c8c2227e 523
d9bea114 524 if (GET_LMASK64(arg2) <= 6)
0ae43045 525 do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
c8c2227e 526
d9bea114 527 if (GET_LMASK64(arg2) <= 5)
0ae43045 528 do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
c8c2227e 529
d9bea114 530 if (GET_LMASK64(arg2) <= 4)
0ae43045 531 do_sb(GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
c8c2227e 532
d9bea114 533 if (GET_LMASK64(arg2) <= 3)
0ae43045 534 do_sb(GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
c8c2227e 535
d9bea114 536 if (GET_LMASK64(arg2) <= 2)
0ae43045 537 do_sb(GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
c8c2227e 538
d9bea114 539 if (GET_LMASK64(arg2) <= 1)
0ae43045 540 do_sb(GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
c8c2227e 541
d9bea114 542 if (GET_LMASK64(arg2) <= 0)
0ae43045 543 do_sb(GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
c8c2227e
TS		 544}
545
d9bea114 546void helper_sdr(target_ulong arg1, target_ulong arg2, int mem_idx)
c8c2227e 547{
0ae43045 548 do_sb(arg2, (uint8_t)arg1, mem_idx);
c8c2227e 549
d9bea114 550 if (GET_LMASK64(arg2) >= 1)
0ae43045 551 do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
c8c2227e 552
d9bea114 553 if (GET_LMASK64(arg2) >= 2)
0ae43045 554 do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
c8c2227e 555
d9bea114 556 if (GET_LMASK64(arg2) >= 3)
0ae43045 557 do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
c8c2227e 558
d9bea114 559 if (GET_LMASK64(arg2) >= 4)
0ae43045 560 do_sb(GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
c8c2227e 561
d9bea114 562 if (GET_LMASK64(arg2) >= 5)
0ae43045 563 do_sb(GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
c8c2227e 564
d9bea114 565 if (GET_LMASK64(arg2) >= 6)
0ae43045 566 do_sb(GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
c8c2227e 567
d9bea114 568 if (GET_LMASK64(arg2) == 7)
0ae43045 569 do_sb(GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
c8c2227e
TS		 570}
571#endif /* TARGET_MIPS64 */
572
3c824109
NF		 573static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
574
575void helper_lwm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
576{
577 target_ulong base_reglist = reglist & 0xf;
578 target_ulong do_r31 = reglist & 0x10;
579#ifdef CONFIG_USER_ONLY
580#undef ldfun
581#define ldfun ldl_raw
582#else
583 uint32_t (*ldfun)(target_ulong);
584
585 switch (mem_idx)
586 {
587 case 0: ldfun = ldl_kernel; break;
588 case 1: ldfun = ldl_super; break;
589 default:
590 case 2: ldfun = ldl_user; break;
591 }
592#endif
593
594 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
595 target_ulong i;
596
597 for (i = 0; i < base_reglist; i++) {
598 env->active_tc.gpr[multiple_regs[i]] = (target_long) ldfun(addr);
599 addr += 4;
600 }
601 }
602
603 if (do_r31) {
604 env->active_tc.gpr[31] = (target_long) ldfun(addr);
605 }
606}
607
608void helper_swm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
609{
610 target_ulong base_reglist = reglist & 0xf;
611 target_ulong do_r31 = reglist & 0x10;
612#ifdef CONFIG_USER_ONLY
613#undef stfun
614#define stfun stl_raw
615#else
616 void (*stfun)(target_ulong, uint32_t);
617
618 switch (mem_idx)
619 {
620 case 0: stfun = stl_kernel; break;
621 case 1: stfun = stl_super; break;
622 default:
623 case 2: stfun = stl_user; break;
624 }
625#endif
626
627 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
628 target_ulong i;
629
630 for (i = 0; i < base_reglist; i++) {
631 stfun(addr, env->active_tc.gpr[multiple_regs[i]]);
632 addr += 4;
633 }
634 }
635
636 if (do_r31) {
637 stfun(addr, env->active_tc.gpr[31]);
638 }
639}
640
641#if defined(TARGET_MIPS64)
642void helper_ldm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
643{
644 target_ulong base_reglist = reglist & 0xf;
645 target_ulong do_r31 = reglist & 0x10;
646#ifdef CONFIG_USER_ONLY
647#undef ldfun
648#define ldfun ldq_raw
649#else
650 uint64_t (*ldfun)(target_ulong);
651
652 switch (mem_idx)
653 {
654 case 0: ldfun = ldq_kernel; break;
655 case 1: ldfun = ldq_super; break;
656 default:
657 case 2: ldfun = ldq_user; break;
658 }
659#endif
660
661 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
662 target_ulong i;
663
664 for (i = 0; i < base_reglist; i++) {
665 env->active_tc.gpr[multiple_regs[i]] = ldfun(addr);
666 addr += 8;
667 }
668 }
669
670 if (do_r31) {
671 env->active_tc.gpr[31] = ldfun(addr);
672 }
673}
674
675void helper_sdm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
676{
677 target_ulong base_reglist = reglist & 0xf;
678 target_ulong do_r31 = reglist & 0x10;
679#ifdef CONFIG_USER_ONLY
680#undef stfun
681#define stfun stq_raw
682#else
683 void (*stfun)(target_ulong, uint64_t);
684
685 switch (mem_idx)
686 {
687 case 0: stfun = stq_kernel; break;
688 case 1: stfun = stq_super; break;
689 default:
690 case 2: stfun = stq_user; break;
691 }
692#endif
693
694 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
695 target_ulong i;
696
697 for (i = 0; i < base_reglist; i++) {
698 stfun(addr, env->active_tc.gpr[multiple_regs[i]]);
699 addr += 8;
700 }
701 }
702
703 if (do_r31) {
704 stfun(addr, env->active_tc.gpr[31]);
705 }
706}
707#endif
708
0eaef5aa 709#ifndef CONFIG_USER_ONLY
6af0bf9c 710/* CP0 helpers */
c01fccd2 711target_ulong helper_mfc0_mvpcontrol (void)
f1aa6320 712{
be24bb4f 713 return env->mvp->CP0_MVPControl;
f1aa6320
TS		 714}
715
c01fccd2 716target_ulong helper_mfc0_mvpconf0 (void)
f1aa6320 717{
be24bb4f 718 return env->mvp->CP0_MVPConf0;
f1aa6320
TS		 719}
720
c01fccd2 721target_ulong helper_mfc0_mvpconf1 (void)
f1aa6320 722{
be24bb4f 723 return env->mvp->CP0_MVPConf1;
f1aa6320
TS		 724}
725
c01fccd2 726target_ulong helper_mfc0_random (void)
6af0bf9c 727{
be24bb4f 728 return (int32_t)cpu_mips_get_random(env);
873eb012 729}
6af0bf9c 730
c01fccd2 731target_ulong helper_mfc0_tcstatus (void)
f1aa6320 732{
b5dc7732 733 return env->active_tc.CP0_TCStatus;
f1aa6320
TS		 734}
735
c01fccd2 736target_ulong helper_mftc0_tcstatus(void)
f1aa6320
TS		 737{
738 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
739
b5dc7732
TS		 740 if (other_tc == env->current_tc)
741 return env->active_tc.CP0_TCStatus;
742 else
743 return env->tcs[other_tc].CP0_TCStatus;
f1aa6320
TS		 744}
745
c01fccd2 746target_ulong helper_mfc0_tcbind (void)
f1aa6320 747{
b5dc7732 748 return env->active_tc.CP0_TCBind;
f1aa6320
TS		 749}
750
c01fccd2 751target_ulong helper_mftc0_tcbind(void)
f1aa6320
TS		 752{
753 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
754
b5dc7732
TS		 755 if (other_tc == env->current_tc)
756 return env->active_tc.CP0_TCBind;
757 else
758 return env->tcs[other_tc].CP0_TCBind;
f1aa6320
TS		 759}
760
c01fccd2 761target_ulong helper_mfc0_tcrestart (void)
f1aa6320 762{
b5dc7732 763 return env->active_tc.PC;
f1aa6320
TS		 764}
765
c01fccd2 766target_ulong helper_mftc0_tcrestart(void)
f1aa6320
TS		 767{
768 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
769
b5dc7732
TS		 770 if (other_tc == env->current_tc)
771 return env->active_tc.PC;
772 else
773 return env->tcs[other_tc].PC;
f1aa6320
TS		 774}
775
c01fccd2 776target_ulong helper_mfc0_tchalt (void)
f1aa6320 777{
b5dc7732 778 return env->active_tc.CP0_TCHalt;
f1aa6320
TS		 779}
780
c01fccd2 781target_ulong helper_mftc0_tchalt(void)
f1aa6320
TS		 782{
783 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
784
b5dc7732
TS		 785 if (other_tc == env->current_tc)
786 return env->active_tc.CP0_TCHalt;
787 else
788 return env->tcs[other_tc].CP0_TCHalt;
f1aa6320
TS		 789}
790
c01fccd2 791target_ulong helper_mfc0_tccontext (void)
f1aa6320 792{
b5dc7732 793 return env->active_tc.CP0_TCContext;
f1aa6320
TS		 794}
795
c01fccd2 796target_ulong helper_mftc0_tccontext(void)
f1aa6320
TS		 797{
798 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
799
b5dc7732
TS		 800 if (other_tc == env->current_tc)
801 return env->active_tc.CP0_TCContext;
802 else
803 return env->tcs[other_tc].CP0_TCContext;
f1aa6320
TS		 804}
805
c01fccd2 806target_ulong helper_mfc0_tcschedule (void)
f1aa6320 807{
b5dc7732 808 return env->active_tc.CP0_TCSchedule;
f1aa6320
TS		 809}
810
c01fccd2 811target_ulong helper_mftc0_tcschedule(void)
f1aa6320
TS		 812{
813 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
814
b5dc7732
TS		 815 if (other_tc == env->current_tc)
816 return env->active_tc.CP0_TCSchedule;
817 else
818 return env->tcs[other_tc].CP0_TCSchedule;
f1aa6320
TS		 819}
820
c01fccd2 821target_ulong helper_mfc0_tcschefback (void)
f1aa6320 822{
b5dc7732 823 return env->active_tc.CP0_TCScheFBack;
f1aa6320
TS		 824}
825
c01fccd2 826target_ulong helper_mftc0_tcschefback(void)
f1aa6320
TS		 827{
828 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
829
b5dc7732
TS		 830 if (other_tc == env->current_tc)
831 return env->active_tc.CP0_TCScheFBack;
832 else
833 return env->tcs[other_tc].CP0_TCScheFBack;
f1aa6320
TS		 834}
835
c01fccd2 836target_ulong helper_mfc0_count (void)
873eb012 837{
be24bb4f 838 return (int32_t)cpu_mips_get_count(env);
6af0bf9c
FB		 839}
840
c01fccd2 841target_ulong helper_mftc0_entryhi(void)
f1aa6320
TS		 842{
843 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
b5dc7732 844 int32_t tcstatus;
f1aa6320 845
b5dc7732
TS		 846 if (other_tc == env->current_tc)
847 tcstatus = env->active_tc.CP0_TCStatus;
848 else
849 tcstatus = env->tcs[other_tc].CP0_TCStatus;
850
851 return (env->CP0_EntryHi & ~0xff) | (tcstatus & 0xff);
f1aa6320
TS		 852}
853
c01fccd2 854target_ulong helper_mftc0_status(void)
f1aa6320
TS		 855{
856 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1a3fd9c3 857 target_ulong t0;
b5dc7732
TS		 858 int32_t tcstatus;
859
860 if (other_tc == env->current_tc)
861 tcstatus = env->active_tc.CP0_TCStatus;
862 else
863 tcstatus = env->tcs[other_tc].CP0_TCStatus;
f1aa6320 864
be24bb4f
TS		 865 t0 = env->CP0_Status & ~0xf1000018;
866 t0 |= tcstatus & (0xf << CP0TCSt_TCU0);
867 t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
868 t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
869
870 return t0;
f1aa6320
TS		 871}
872
c01fccd2 873target_ulong helper_mfc0_lladdr (void)
f1aa6320 874{
2a6e32dd 875 return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
f1aa6320
TS		 876}
877
c01fccd2 878target_ulong helper_mfc0_watchlo (uint32_t sel)
f1aa6320 879{
be24bb4f 880 return (int32_t)env->CP0_WatchLo[sel];
f1aa6320
TS		 881}
882
c01fccd2 883target_ulong helper_mfc0_watchhi (uint32_t sel)
f1aa6320 884{
be24bb4f 885 return env->CP0_WatchHi[sel];
f1aa6320
TS		 886}
887
c01fccd2 888target_ulong helper_mfc0_debug (void)
f1aa6320 889{
1a3fd9c3 890 target_ulong t0 = env->CP0_Debug;
f1aa6320 891 if (env->hflags & MIPS_HFLAG_DM)
be24bb4f
TS		 892 t0 |= 1 << CP0DB_DM;
893
894 return t0;
f1aa6320
TS		 895}
896
c01fccd2 897target_ulong helper_mftc0_debug(void)
f1aa6320
TS		 898{
899 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
b5dc7732
TS		 900 int32_t tcstatus;
901
902 if (other_tc == env->current_tc)
903 tcstatus = env->active_tc.CP0_Debug_tcstatus;
904 else
905 tcstatus = env->tcs[other_tc].CP0_Debug_tcstatus;
f1aa6320
TS		 906
907 /* XXX: Might be wrong, check with EJTAG spec. */
be24bb4f 908 return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
b5dc7732 909 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
f1aa6320
TS		 910}
911
912#if defined(TARGET_MIPS64)
c01fccd2 913target_ulong helper_dmfc0_tcrestart (void)
f1aa6320 914{
b5dc7732 915 return env->active_tc.PC;
f1aa6320
TS		 916}
917
c01fccd2 918target_ulong helper_dmfc0_tchalt (void)
f1aa6320 919{
b5dc7732 920 return env->active_tc.CP0_TCHalt;
f1aa6320
TS		 921}
922
c01fccd2 923target_ulong helper_dmfc0_tccontext (void)
f1aa6320 924{
b5dc7732 925 return env->active_tc.CP0_TCContext;
f1aa6320
TS		 926}
927
c01fccd2 928target_ulong helper_dmfc0_tcschedule (void)
f1aa6320 929{
b5dc7732 930 return env->active_tc.CP0_TCSchedule;
f1aa6320
TS		 931}
932
c01fccd2 933target_ulong helper_dmfc0_tcschefback (void)
f1aa6320 934{
b5dc7732 935 return env->active_tc.CP0_TCScheFBack;
f1aa6320
TS		 936}
937
c01fccd2 938target_ulong helper_dmfc0_lladdr (void)
f1aa6320 939{
2a6e32dd 940 return env->lladdr >> env->CP0_LLAddr_shift;
f1aa6320
TS		 941}
942
c01fccd2 943target_ulong helper_dmfc0_watchlo (uint32_t sel)
f1aa6320 944{
be24bb4f 945 return env->CP0_WatchLo[sel];
f1aa6320
TS		 946}
947#endif /* TARGET_MIPS64 */
948
d9bea114 949void helper_mtc0_index (target_ulong arg1)
f1aa6320
TS		 950{
951 int num = 1;
952 unsigned int tmp = env->tlb->nb_tlb;
953
954 do {
955 tmp >>= 1;
956 num <<= 1;
957 } while (tmp);
d9bea114 958 env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
f1aa6320
TS		 959}
960
d9bea114 961void helper_mtc0_mvpcontrol (target_ulong arg1)
f1aa6320
TS		 962{
963 uint32_t mask = 0;
964 uint32_t newval;
965
966 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
967 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
968 (1 << CP0MVPCo_EVP);
969 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
970 mask |= (1 << CP0MVPCo_STLB);
d9bea114 971 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
f1aa6320
TS		 972
973 // TODO: Enable/disable shared TLB, enable/disable VPEs.
974
975 env->mvp->CP0_MVPControl = newval;
976}
977
d9bea114 978void helper_mtc0_vpecontrol (target_ulong arg1)
f1aa6320
TS		 979{
980 uint32_t mask;
981 uint32_t newval;
982
983 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
984 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
d9bea114 985 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
f1aa6320
TS		 986
987 /* Yield scheduler intercept not implemented. */
988 /* Gating storage scheduler intercept not implemented. */
989
990 // TODO: Enable/disable TCs.
991
992 env->CP0_VPEControl = newval;
993}
994
d9bea114 995void helper_mtc0_vpeconf0 (target_ulong arg1)
f1aa6320
TS		 996{
997 uint32_t mask = 0;
998 uint32_t newval;
999
1000 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1001 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1002 mask |= (0xff << CP0VPEC0_XTC);
1003 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1004 }
d9bea114 1005 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
f1aa6320
TS		 1006
1007 // TODO: TC exclusive handling due to ERL/EXL.
1008
1009 env->CP0_VPEConf0 = newval;
1010}
1011
d9bea114 1012void helper_mtc0_vpeconf1 (target_ulong arg1)
f1aa6320
TS		 1013{
1014 uint32_t mask = 0;
1015 uint32_t newval;
1016
1017 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1018 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1019 (0xff << CP0VPEC1_NCP1);
d9bea114 1020 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
f1aa6320
TS		 1021
1022 /* UDI not implemented. */
1023 /* CP2 not implemented. */
1024
1025 // TODO: Handle FPU (CP1) binding.
1026
1027 env->CP0_VPEConf1 = newval;
1028}
1029
d9bea114 1030void helper_mtc0_yqmask (target_ulong arg1)
f1aa6320
TS		 1031{
1032 /* Yield qualifier inputs not implemented. */
1033 env->CP0_YQMask = 0x00000000;
1034}
1035
d9bea114 1036void helper_mtc0_vpeopt (target_ulong arg1)
f1aa6320 1037{
d9bea114 1038 env->CP0_VPEOpt = arg1 & 0x0000ffff;
f1aa6320
TS		 1039}
1040
d9bea114 1041void helper_mtc0_entrylo0 (target_ulong arg1)
f1aa6320
TS		 1042{
1043 /* Large physaddr (PABITS) not implemented */
1044 /* 1k pages not implemented */
d9bea114 1045 env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
f1aa6320
TS		 1046}
1047
d9bea114 1048void helper_mtc0_tcstatus (target_ulong arg1)
f1aa6320
TS		 1049{
1050 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1051 uint32_t newval;
1052
d9bea114 1053 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
f1aa6320
TS		 1054
1055 // TODO: Sync with CP0_Status.
1056
b5dc7732 1057 env->active_tc.CP0_TCStatus = newval;
f1aa6320
TS		 1058}
1059
d9bea114 1060void helper_mttc0_tcstatus (target_ulong arg1)
f1aa6320
TS		 1061{
1062 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1063
1064 // TODO: Sync with CP0_Status.
1065
b5dc7732 1066 if (other_tc == env->current_tc)
d9bea114 1067 env->active_tc.CP0_TCStatus = arg1;
b5dc7732 1068 else
d9bea114 1069 env->tcs[other_tc].CP0_TCStatus = arg1;
f1aa6320
TS		 1070}
1071
d9bea114 1072void helper_mtc0_tcbind (target_ulong arg1)
f1aa6320
TS		 1073{
1074 uint32_t mask = (1 << CP0TCBd_TBE);
1075 uint32_t newval;
1076
1077 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1078 mask |= (1 << CP0TCBd_CurVPE);
d9bea114 1079 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
b5dc7732 1080 env->active_tc.CP0_TCBind = newval;
f1aa6320
TS		 1081}
1082
d9bea114 1083void helper_mttc0_tcbind (target_ulong arg1)
f1aa6320
TS		 1084{
1085 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1086 uint32_t mask = (1 << CP0TCBd_TBE);
1087 uint32_t newval;
1088
1089 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1090 mask |= (1 << CP0TCBd_CurVPE);
b5dc7732 1091 if (other_tc == env->current_tc) {
d9bea114 1092 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
b5dc7732
TS		 1093 env->active_tc.CP0_TCBind = newval;
1094 } else {
d9bea114 1095 newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
b5dc7732
TS		 1096 env->tcs[other_tc].CP0_TCBind = newval;
1097 }
f1aa6320
TS		 1098}
1099
d9bea114 1100void helper_mtc0_tcrestart (target_ulong arg1)
f1aa6320 1101{
d9bea114 1102 env->active_tc.PC = arg1;
b5dc7732 1103 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
5499b6ff 1104 env->lladdr = 0ULL;
f1aa6320
TS		 1105 /* MIPS16 not implemented. */
1106}
1107
d9bea114 1108void helper_mttc0_tcrestart (target_ulong arg1)
f1aa6320
TS		 1109{
1110 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1111
b5dc7732 1112 if (other_tc == env->current_tc) {
d9bea114 1113 env->active_tc.PC = arg1;
b5dc7732 1114 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
5499b6ff 1115 env->lladdr = 0ULL;
b5dc7732
TS		 1116 /* MIPS16 not implemented. */
1117 } else {
d9bea114 1118 env->tcs[other_tc].PC = arg1;
b5dc7732 1119 env->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
5499b6ff 1120 env->lladdr = 0ULL;
b5dc7732
TS		 1121 /* MIPS16 not implemented. */
1122 }
f1aa6320
TS		 1123}
1124
d9bea114 1125void helper_mtc0_tchalt (target_ulong arg1)
f1aa6320 1126{
d9bea114 1127 env->active_tc.CP0_TCHalt = arg1 & 0x1;
f1aa6320
TS		 1128
1129 // TODO: Halt TC / Restart (if allocated+active) TC.
1130}
1131
d9bea114 1132void helper_mttc0_tchalt (target_ulong arg1)
f1aa6320
TS		 1133{
1134 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1135
1136 // TODO: Halt TC / Restart (if allocated+active) TC.
1137
b5dc7732 1138 if (other_tc == env->current_tc)
d9bea114 1139 env->active_tc.CP0_TCHalt = arg1;
b5dc7732 1140 else
d9bea114 1141 env->tcs[other_tc].CP0_TCHalt = arg1;
f1aa6320
TS		 1142}
1143
d9bea114 1144void helper_mtc0_tccontext (target_ulong arg1)
f1aa6320 1145{
d9bea114 1146 env->active_tc.CP0_TCContext = arg1;
f1aa6320
TS		 1147}
1148
d9bea114 1149void helper_mttc0_tccontext (target_ulong arg1)
f1aa6320
TS		 1150{
1151 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1152
b5dc7732 1153 if (other_tc == env->current_tc)
d9bea114 1154 env->active_tc.CP0_TCContext = arg1;
b5dc7732 1155 else
d9bea114 1156 env->tcs[other_tc].CP0_TCContext = arg1;
f1aa6320
TS		 1157}
1158
d9bea114 1159void helper_mtc0_tcschedule (target_ulong arg1)
f1aa6320 1160{
d9bea114 1161 env->active_tc.CP0_TCSchedule = arg1;
f1aa6320
TS		 1162}
1163
d9bea114 1164void helper_mttc0_tcschedule (target_ulong arg1)
f1aa6320
TS		 1165{
1166 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1167
b5dc7732 1168 if (other_tc == env->current_tc)
d9bea114 1169 env->active_tc.CP0_TCSchedule = arg1;
b5dc7732 1170 else
d9bea114 1171 env->tcs[other_tc].CP0_TCSchedule = arg1;
f1aa6320
TS		 1172}
1173
d9bea114 1174void helper_mtc0_tcschefback (target_ulong arg1)
f1aa6320 1175{
d9bea114 1176 env->active_tc.CP0_TCScheFBack = arg1;
f1aa6320
TS		 1177}
1178
d9bea114 1179void helper_mttc0_tcschefback (target_ulong arg1)
f1aa6320
TS		 1180{
1181 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1182
b5dc7732 1183 if (other_tc == env->current_tc)
d9bea114 1184 env->active_tc.CP0_TCScheFBack = arg1;
b5dc7732 1185 else
d9bea114 1186 env->tcs[other_tc].CP0_TCScheFBack = arg1;
f1aa6320
TS		 1187}
1188
d9bea114 1189void helper_mtc0_entrylo1 (target_ulong arg1)
f1aa6320
TS		 1190{
1191 /* Large physaddr (PABITS) not implemented */
1192 /* 1k pages not implemented */
d9bea114 1193 env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
f1aa6320
TS		 1194}
1195
d9bea114 1196void helper_mtc0_context (target_ulong arg1)
f1aa6320 1197{
d9bea114 1198 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
f1aa6320
TS		 1199}
1200
d9bea114 1201void helper_mtc0_pagemask (target_ulong arg1)
f1aa6320
TS		 1202{
1203 /* 1k pages not implemented */
d9bea114 1204 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
f1aa6320
TS		 1205}
1206
d9bea114 1207void helper_mtc0_pagegrain (target_ulong arg1)
f1aa6320
TS		 1208{
1209 /* SmartMIPS not implemented */
1210 /* Large physaddr (PABITS) not implemented */
1211 /* 1k pages not implemented */
1212 env->CP0_PageGrain = 0;
1213}
1214
d9bea114 1215void helper_mtc0_wired (target_ulong arg1)
f1aa6320 1216{
d9bea114 1217 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
f1aa6320
TS		 1218}
1219
d9bea114 1220void helper_mtc0_srsconf0 (target_ulong arg1)
f1aa6320 1221{
d9bea114 1222 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
f1aa6320
TS		 1223}
1224
d9bea114 1225void helper_mtc0_srsconf1 (target_ulong arg1)
f1aa6320 1226{
d9bea114 1227 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
f1aa6320
TS		 1228}
1229
d9bea114 1230void helper_mtc0_srsconf2 (target_ulong arg1)
f1aa6320 1231{
d9bea114 1232 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
f1aa6320
TS		 1233}
1234
d9bea114 1235void helper_mtc0_srsconf3 (target_ulong arg1)
f1aa6320 1236{
d9bea114 1237 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
f1aa6320
TS		 1238}
1239
d9bea114 1240void helper_mtc0_srsconf4 (target_ulong arg1)
f1aa6320 1241{
d9bea114 1242 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
f1aa6320
TS		 1243}
1244
d9bea114 1245void helper_mtc0_hwrena (target_ulong arg1)
f1aa6320 1246{
d9bea114 1247 env->CP0_HWREna = arg1 & 0x0000000F;
f1aa6320
TS		 1248}
1249
d9bea114 1250void helper_mtc0_count (target_ulong arg1)
f1aa6320 1251{
d9bea114 1252 cpu_mips_store_count(env, arg1);
f1aa6320
TS		 1253}
1254
d9bea114 1255void helper_mtc0_entryhi (target_ulong arg1)
f1aa6320
TS		 1256{
1257 target_ulong old, val;
1258
1259 /* 1k pages not implemented */
d9bea114 1260 val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
f1aa6320
TS		 1261#if defined(TARGET_MIPS64)
1262 val &= env->SEGMask;
1263#endif
1264 old = env->CP0_EntryHi;
1265 env->CP0_EntryHi = val;
1266 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
b5dc7732
TS		 1267 uint32_t tcst = env->active_tc.CP0_TCStatus & ~0xff;
1268 env->active_tc.CP0_TCStatus = tcst | (val & 0xff);
f1aa6320
TS		 1269 }
1270 /* If the ASID changes, flush qemu's TLB. */
1271 if ((old & 0xFF) != (val & 0xFF))
1272 cpu_mips_tlb_flush(env, 1);
1273}
1274
d9bea114 1275void helper_mttc0_entryhi(target_ulong arg1)
f1aa6320
TS		 1276{
1277 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
b5dc7732 1278 int32_t tcstatus;
f1aa6320 1279
d9bea114 1280 env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (arg1 & ~0xff);
b5dc7732 1281 if (other_tc == env->current_tc) {
d9bea114 1282 tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (arg1 & 0xff);
b5dc7732
TS		 1283 env->active_tc.CP0_TCStatus = tcstatus;
1284 } else {
d9bea114 1285 tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (arg1 & 0xff);
b5dc7732
TS		 1286 env->tcs[other_tc].CP0_TCStatus = tcstatus;
1287 }
f1aa6320
TS		 1288}
1289
d9bea114 1290void helper_mtc0_compare (target_ulong arg1)
f1aa6320 1291{
d9bea114 1292 cpu_mips_store_compare(env, arg1);
f1aa6320
TS		 1293}
1294
d9bea114 1295void helper_mtc0_status (target_ulong arg1)
f1aa6320
TS		 1296{
1297 uint32_t val, old;
1298 uint32_t mask = env->CP0_Status_rw_bitmask;
1299
d9bea114 1300 val = arg1 & mask;
f1aa6320
TS		 1301 old = env->CP0_Status;
1302 env->CP0_Status = (env->CP0_Status & ~mask) | val;
1303 compute_hflags(env);
c01fccd2
AJ		 1304 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1305 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1306 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1307 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1308 env->CP0_Cause);
1309 switch (env->hflags & MIPS_HFLAG_KSU) {
1310 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1311 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1312 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1313 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
31e3104f 1314 }
c01fccd2 1315 }
f1aa6320
TS		 1316 cpu_mips_update_irq(env);
1317}
1318
d9bea114 1319void helper_mttc0_status(target_ulong arg1)
f1aa6320
TS		 1320{
1321 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
b5dc7732 1322 int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus;
f1aa6320 1323
d9bea114
AJ		 1324 env->CP0_Status = arg1 & ~0xf1000018;
1325 tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (arg1 & (0xf << CP0St_CU0));
1326 tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((arg1 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
1327 tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((arg1 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
b5dc7732
TS		 1328 if (other_tc == env->current_tc)
1329 env->active_tc.CP0_TCStatus = tcstatus;
1330 else
1331 env->tcs[other_tc].CP0_TCStatus = tcstatus;
f1aa6320
TS		 1332}
1333
d9bea114 1334void helper_mtc0_intctl (target_ulong arg1)
f1aa6320
TS		 1335{
1336 /* vectored interrupts not implemented, no performance counters. */
d9bea114 1337 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (arg1 & 0x000002e0);
f1aa6320
TS		 1338}
1339
d9bea114 1340void helper_mtc0_srsctl (target_ulong arg1)
f1aa6320
TS		 1341{
1342 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
d9bea114 1343 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
f1aa6320
TS		 1344}
1345
d9bea114 1346void helper_mtc0_cause (target_ulong arg1)
f1aa6320
TS		 1347{
1348 uint32_t mask = 0x00C00300;
1349 uint32_t old = env->CP0_Cause;
1350
1351 if (env->insn_flags & ISA_MIPS32R2)
1352 mask |= 1 << CP0Ca_DC;
1353
d9bea114 1354 env->CP0_Cause = (env->CP0_Cause & ~mask) | (arg1 & mask);
f1aa6320
TS		 1355
1356 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
1357 if (env->CP0_Cause & (1 << CP0Ca_DC))
1358 cpu_mips_stop_count(env);
1359 else
1360 cpu_mips_start_count(env);
1361 }
1362
1363 /* Handle the software interrupt as an hardware one, as they
1364 are very similar */
d9bea114 1365 if (arg1 & CP0Ca_IP_mask) {
f1aa6320
TS		 1366 cpu_mips_update_irq(env);
1367 }
1368}
1369
d9bea114 1370void helper_mtc0_ebase (target_ulong arg1)
f1aa6320
TS		 1371{
1372 /* vectored interrupts not implemented */
1373 /* Multi-CPU not implemented */
d9bea114 1374 env->CP0_EBase = 0x80000000 | (arg1 & 0x3FFFF000);
f1aa6320
TS		 1375}
1376
d9bea114 1377void helper_mtc0_config0 (target_ulong arg1)
f1aa6320 1378{
d9bea114 1379 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
f1aa6320
TS		 1380}
1381
d9bea114 1382void helper_mtc0_config2 (target_ulong arg1)
f1aa6320
TS		 1383{
1384 /* tertiary/secondary caches not implemented */
1385 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1386}
1387
2a6e32dd
AJ		 1388void helper_mtc0_lladdr (target_ulong arg1)
1389{
1390 target_long mask = env->CP0_LLAddr_rw_bitmask;
1391 arg1 = arg1 << env->CP0_LLAddr_shift;
1392 env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1393}
1394
d9bea114 1395void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel)
f1aa6320
TS		 1396{
1397 /* Watch exceptions for instructions, data loads, data stores
1398 not implemented. */
d9bea114 1399 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
f1aa6320
TS		 1400}
1401
d9bea114 1402void helper_mtc0_watchhi (target_ulong arg1, uint32_t sel)
f1aa6320 1403{
d9bea114
AJ		 1404 env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1405 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
f1aa6320
TS		 1406}
1407
d9bea114 1408void helper_mtc0_xcontext (target_ulong arg1)
f1aa6320
TS		 1409{
1410 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
d9bea114 1411 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
f1aa6320
TS		 1412}
1413
d9bea114 1414void helper_mtc0_framemask (target_ulong arg1)
f1aa6320 1415{
d9bea114 1416 env->CP0_Framemask = arg1; /* XXX */
f1aa6320
TS		 1417}
1418
d9bea114 1419void helper_mtc0_debug (target_ulong arg1)
f1aa6320 1420{
d9bea114
AJ		 1421 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1422 if (arg1 & (1 << CP0DB_DM))
f1aa6320
TS		 1423 env->hflags |= MIPS_HFLAG_DM;
1424 else
1425 env->hflags &= ~MIPS_HFLAG_DM;
1426}
1427
d9bea114 1428void helper_mttc0_debug(target_ulong arg1)
f1aa6320
TS		 1429{
1430 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
d9bea114 1431 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
f1aa6320
TS		 1432
1433 /* XXX: Might be wrong, check with EJTAG spec. */
b5dc7732
TS		 1434 if (other_tc == env->current_tc)
1435 env->active_tc.CP0_Debug_tcstatus = val;
1436 else
1437 env->tcs[other_tc].CP0_Debug_tcstatus = val;
f1aa6320 1438 env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
d9bea114 1439 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
f1aa6320
TS		 1440}
1441
d9bea114 1442void helper_mtc0_performance0 (target_ulong arg1)
f1aa6320 1443{
d9bea114 1444 env->CP0_Performance0 = arg1 & 0x000007ff;
f1aa6320
TS		 1445}
1446
d9bea114 1447void helper_mtc0_taglo (target_ulong arg1)
f1aa6320 1448{
d9bea114 1449 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
f1aa6320
TS		 1450}
1451
d9bea114 1452void helper_mtc0_datalo (target_ulong arg1)
f1aa6320 1453{
d9bea114 1454 env->CP0_DataLo = arg1; /* XXX */
f1aa6320
TS		 1455}
1456
d9bea114 1457void helper_mtc0_taghi (target_ulong arg1)
f1aa6320 1458{
d9bea114 1459 env->CP0_TagHi = arg1; /* XXX */
f1aa6320
TS		 1460}
1461
d9bea114 1462void helper_mtc0_datahi (target_ulong arg1)
f1aa6320 1463{
d9bea114 1464 env->CP0_DataHi = arg1; /* XXX */
f1aa6320
TS		 1465}
1466
f1aa6320 1467/* MIPS MT functions */
c01fccd2 1468target_ulong helper_mftgpr(uint32_t sel)
f1aa6320
TS		 1469{
1470 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1471
b5dc7732
TS		 1472 if (other_tc == env->current_tc)
1473 return env->active_tc.gpr[sel];
1474 else
1475 return env->tcs[other_tc].gpr[sel];
f1aa6320
TS		 1476}
1477
c01fccd2 1478target_ulong helper_mftlo(uint32_t sel)
f1aa6320
TS		 1479{
1480 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1481
b5dc7732
TS		 1482 if (other_tc == env->current_tc)
1483 return env->active_tc.LO[sel];
1484 else
1485 return env->tcs[other_tc].LO[sel];
f1aa6320
TS		 1486}
1487
c01fccd2 1488target_ulong helper_mfthi(uint32_t sel)
f1aa6320
TS		 1489{
1490 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1491
b5dc7732
TS		 1492 if (other_tc == env->current_tc)
1493 return env->active_tc.HI[sel];
1494 else
1495 return env->tcs[other_tc].HI[sel];
f1aa6320
TS		 1496}
1497
c01fccd2 1498target_ulong helper_mftacx(uint32_t sel)
f1aa6320
TS		 1499{
1500 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1501
b5dc7732
TS		 1502 if (other_tc == env->current_tc)
1503 return env->active_tc.ACX[sel];
1504 else
1505 return env->tcs[other_tc].ACX[sel];
f1aa6320
TS		 1506}
1507
c01fccd2 1508target_ulong helper_mftdsp(void)
f1aa6320
TS		 1509{
1510 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1511
b5dc7732
TS		 1512 if (other_tc == env->current_tc)
1513 return env->active_tc.DSPControl;
1514 else
1515 return env->tcs[other_tc].DSPControl;
f1aa6320 1516}
6af0bf9c 1517
d9bea114 1518void helper_mttgpr(target_ulong arg1, uint32_t sel)
f1aa6320
TS		 1519{
1520 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1521
b5dc7732 1522 if (other_tc == env->current_tc)
d9bea114 1523 env->active_tc.gpr[sel] = arg1;
b5dc7732 1524 else
d9bea114 1525 env->tcs[other_tc].gpr[sel] = arg1;
f1aa6320
TS		 1526}
1527
d9bea114 1528void helper_mttlo(target_ulong arg1, uint32_t sel)
f1aa6320
TS		 1529{
1530 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1531
b5dc7732 1532 if (other_tc == env->current_tc)
d9bea114 1533 env->active_tc.LO[sel] = arg1;
b5dc7732 1534 else
d9bea114 1535 env->tcs[other_tc].LO[sel] = arg1;
f1aa6320
TS		 1536}
1537
d9bea114 1538void helper_mtthi(target_ulong arg1, uint32_t sel)
f1aa6320
TS		 1539{
1540 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1541
b5dc7732 1542 if (other_tc == env->current_tc)
d9bea114 1543 env->active_tc.HI[sel] = arg1;
b5dc7732 1544 else
d9bea114 1545 env->tcs[other_tc].HI[sel] = arg1;
f1aa6320
TS		 1546}
1547
d9bea114 1548void helper_mttacx(target_ulong arg1, uint32_t sel)
f1aa6320
TS		 1549{
1550 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1551
b5dc7732 1552 if (other_tc == env->current_tc)
d9bea114 1553 env->active_tc.ACX[sel] = arg1;
b5dc7732 1554 else
d9bea114 1555 env->tcs[other_tc].ACX[sel] = arg1;
f1aa6320
TS		 1556}
1557
d9bea114 1558void helper_mttdsp(target_ulong arg1)
f1aa6320
TS		 1559{
1560 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1561
b5dc7732 1562 if (other_tc == env->current_tc)
d9bea114 1563 env->active_tc.DSPControl = arg1;
b5dc7732 1564 else
d9bea114 1565 env->tcs[other_tc].DSPControl = arg1;
f1aa6320
TS		 1566}
1567
1568/* MIPS MT functions */
d9bea114 1569target_ulong helper_dmt(target_ulong arg1)
f1aa6320
TS		 1570{
1571 // TODO
d9bea114
AJ		 1572 arg1 = 0;
1573 // rt = arg1
be24bb4f 1574
d9bea114 1575 return arg1;
f1aa6320
TS		 1576}
1577
d9bea114 1578target_ulong helper_emt(target_ulong arg1)
f1aa6320
TS		 1579{
1580 // TODO
d9bea114
AJ		 1581 arg1 = 0;
1582 // rt = arg1
be24bb4f 1583
d9bea114 1584 return arg1;
f1aa6320
TS		 1585}
1586
d9bea114 1587target_ulong helper_dvpe(target_ulong arg1)
f1aa6320
TS		 1588{
1589 // TODO
d9bea114
AJ		 1590 arg1 = 0;
1591 // rt = arg1
be24bb4f 1592
d9bea114 1593 return arg1;
f1aa6320
TS		 1594}
1595
d9bea114 1596target_ulong helper_evpe(target_ulong arg1)
f1aa6320
TS		 1597{
1598 // TODO
d9bea114
AJ		 1599 arg1 = 0;
1600 // rt = arg1
be24bb4f 1601
d9bea114 1602 return arg1;
f1aa6320 1603}
f9480ffc 1604#endif /* !CONFIG_USER_ONLY */
f1aa6320 1605
d9bea114 1606void helper_fork(target_ulong arg1, target_ulong arg2)
f1aa6320 1607{
d9bea114
AJ		 1608 // arg1 = rt, arg2 = rs
1609 arg1 = 0;
f1aa6320
TS		 1610 // TODO: store to TC register
1611}
1612
d9bea114 1613target_ulong helper_yield(target_ulong arg1)
f1aa6320 1614{
d9bea114 1615 if (arg1 < 0) {
f1aa6320 1616 /* No scheduling policy implemented. */
d9bea114 1617 if (arg1 != -2) {
f1aa6320 1618 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
b5dc7732 1619 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
f1aa6320
TS		 1620 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1621 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
c01fccd2 1622 helper_raise_exception(EXCP_THREAD);
f1aa6320
TS		 1623 }
1624 }
d9bea114 1625 } else if (arg1 == 0) {
6958549d 1626 if (0 /* TODO: TC underflow */) {
f1aa6320 1627 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
c01fccd2 1628 helper_raise_exception(EXCP_THREAD);
f1aa6320
TS		 1629 } else {
1630 // TODO: Deallocate TC
1631 }
d9bea114 1632 } else if (arg1 > 0) {
f1aa6320
TS		 1633 /* Yield qualifier inputs not implemented. */
1634 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1635 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
c01fccd2 1636 helper_raise_exception(EXCP_THREAD);
f1aa6320 1637 }
be24bb4f 1638 return env->CP0_YQMask;
f1aa6320
TS		 1639}
1640
f1aa6320 1641#ifndef CONFIG_USER_ONLY
6af0bf9c 1642/* TLB management */
83dae095 1643static void cpu_mips_tlb_flush (CPUState *env, int flush_global)
814b9a47
TS		 1644{
1645 /* Flush qemu's TLB and discard all shadowed entries. */
1646 tlb_flush (env, flush_global);
ead9360e 1647 env->tlb->tlb_in_use = env->tlb->nb_tlb;
814b9a47
TS		 1648}
1649
29929e34 1650static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
814b9a47
TS		 1651{
1652 /* Discard entries from env->tlb[first] onwards. */
ead9360e
TS		 1653 while (env->tlb->tlb_in_use > first) {
1654 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
814b9a47
TS		 1655 }
1656}
1657
29929e34 1658static void r4k_fill_tlb (int idx)
6af0bf9c 1659{
c227f099 1660 r4k_tlb_t *tlb;
6af0bf9c
FB		 1661
1662 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
ead9360e 1663 tlb = &env->tlb->mmu.r4k.tlb[idx];
f2e9ebef 1664 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
d26bc211 1665#if defined(TARGET_MIPS64)
e034e2c3 1666 tlb->VPN &= env->SEGMask;
100ce988 1667#endif
98c1b82b 1668 tlb->ASID = env->CP0_EntryHi & 0xFF;
3b1c8be4 1669 tlb->PageMask = env->CP0_PageMask;
6af0bf9c 1670 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
98c1b82b
PB		 1671 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1672 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1673 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
6af0bf9c 1674 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
98c1b82b
PB		 1675 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1676 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1677 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
6af0bf9c
FB		 1678 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1679}
1680
c01fccd2 1681void r4k_helper_tlbwi (void)
6af0bf9c 1682{
bbc0d79c
AJ		 1683 int idx;
1684
1685 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1686
814b9a47
TS		 1687 /* Discard cached TLB entries. We could avoid doing this if the
1688 tlbwi is just upgrading access permissions on the current entry;
1689 that might be a further win. */
ead9360e 1690 r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
814b9a47 1691
bbc0d79c
AJ		 1692 r4k_invalidate_tlb(env, idx, 0);
1693 r4k_fill_tlb(idx);
6af0bf9c
FB		 1694}
1695
c01fccd2 1696void r4k_helper_tlbwr (void)
6af0bf9c
FB		 1697{
1698 int r = cpu_mips_get_random(env);
1699
29929e34
TS		 1700 r4k_invalidate_tlb(env, r, 1);
1701 r4k_fill_tlb(r);
6af0bf9c
FB		 1702}
1703
c01fccd2 1704void r4k_helper_tlbp (void)
6af0bf9c 1705{
c227f099 1706 r4k_tlb_t *tlb;
f2e9ebef 1707 target_ulong mask;
6af0bf9c 1708 target_ulong tag;
f2e9ebef 1709 target_ulong VPN;
6af0bf9c
FB		 1710 uint8_t ASID;
1711 int i;
1712
3d9fb9fe 1713 ASID = env->CP0_EntryHi & 0xFF;
ead9360e
TS		 1714 for (i = 0; i < env->tlb->nb_tlb; i++) {
1715 tlb = &env->tlb->mmu.r4k.tlb[i];
f2e9ebef
TS		 1716 /* 1k pages are not supported. */
1717 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1718 tag = env->CP0_EntryHi & ~mask;
1719 VPN = tlb->VPN & ~mask;
6af0bf9c 1720 /* Check ASID, virtual page number & size */
f2e9ebef 1721 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
6af0bf9c 1722 /* TLB match */
9c2149c8 1723 env->CP0_Index = i;
6af0bf9c
FB		 1724 break;
1725 }
1726 }
ead9360e 1727 if (i == env->tlb->nb_tlb) {
814b9a47 1728 /* No match. Discard any shadow entries, if any of them match. */
ead9360e 1729 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
6958549d
AJ		 1730 tlb = &env->tlb->mmu.r4k.tlb[i];
1731 /* 1k pages are not supported. */
1732 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1733 tag = env->CP0_EntryHi & ~mask;
1734 VPN = tlb->VPN & ~mask;
1735 /* Check ASID, virtual page number & size */
1736 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
29929e34 1737 r4k_mips_tlb_flush_extra (env, i);
6958549d
AJ		 1738 break;
1739 }
1740 }
814b9a47 1741
9c2149c8 1742 env->CP0_Index |= 0x80000000;
6af0bf9c
FB		 1743 }
1744}
1745
c01fccd2 1746void r4k_helper_tlbr (void)
6af0bf9c 1747{
c227f099 1748 r4k_tlb_t *tlb;
09c56b84 1749 uint8_t ASID;
bbc0d79c 1750 int idx;
6af0bf9c 1751
09c56b84 1752 ASID = env->CP0_EntryHi & 0xFF;
bbc0d79c
AJ		 1753 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1754 tlb = &env->tlb->mmu.r4k.tlb[idx];
4ad40f36
FB		 1755
1756 /* If this will change the current ASID, flush qemu's TLB. */
814b9a47
TS		 1757 if (ASID != tlb->ASID)
1758 cpu_mips_tlb_flush (env, 1);
1759
ead9360e 1760 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
4ad40f36 1761
6af0bf9c 1762 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
3b1c8be4 1763 env->CP0_PageMask = tlb->PageMask;
7495fd0f
TS		 1764 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1765 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1766 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1767 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
6af0bf9c 1768}
6af0bf9c 1769
c01fccd2 1770void helper_tlbwi(void)
a7812ae4 1771{
c01fccd2 1772 env->tlb->helper_tlbwi();
a7812ae4
PB		 1773}
1774
c01fccd2 1775void helper_tlbwr(void)
a7812ae4 1776{
c01fccd2 1777 env->tlb->helper_tlbwr();
a7812ae4
PB		 1778}
1779
c01fccd2 1780void helper_tlbp(void)
a7812ae4 1781{
c01fccd2 1782 env->tlb->helper_tlbp();
a7812ae4
PB		 1783}
1784
c01fccd2 1785void helper_tlbr(void)
a7812ae4 1786{
c01fccd2 1787 env->tlb->helper_tlbr();
a7812ae4
PB		 1788}
1789
2b0233ab 1790/* Specials */
c01fccd2 1791target_ulong helper_di (void)
2b0233ab 1792{
2796188e
TS		 1793 target_ulong t0 = env->CP0_Status;
1794
be24bb4f 1795 env->CP0_Status = t0 & ~(1 << CP0St_IE);
2b0233ab 1796 cpu_mips_update_irq(env);
be24bb4f
TS		 1797
1798 return t0;
2b0233ab
TS		 1799}
1800
c01fccd2 1801target_ulong helper_ei (void)
2b0233ab 1802{
2796188e
TS		 1803 target_ulong t0 = env->CP0_Status;
1804
be24bb4f 1805 env->CP0_Status = t0 | (1 << CP0St_IE);
2b0233ab 1806 cpu_mips_update_irq(env);
be24bb4f
TS		 1807
1808 return t0;
2b0233ab
TS		 1809}
1810
cd5158ea 1811static void debug_pre_eret (void)
6af0bf9c 1812{
8fec2b8c 1813 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
93fcfe39
AL		 1814 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1815 env->active_tc.PC, env->CP0_EPC);
1816 if (env->CP0_Status & (1 << CP0St_ERL))
1817 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1818 if (env->hflags & MIPS_HFLAG_DM)
1819 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1820 qemu_log("\n");
1821 }
f41c52f1
TS		 1822}
1823
cd5158ea 1824static void debug_post_eret (void)
f41c52f1 1825{
8fec2b8c 1826 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
93fcfe39
AL		 1827 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1828 env->active_tc.PC, env->CP0_EPC);
1829 if (env->CP0_Status & (1 << CP0St_ERL))
1830 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1831 if (env->hflags & MIPS_HFLAG_DM)
1832 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1833 switch (env->hflags & MIPS_HFLAG_KSU) {
1834 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1835 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1836 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1837 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1838 }
623a930e 1839 }
6af0bf9c
FB		 1840}
1841
32188a03
NF		 1842static void set_pc (target_ulong error_pc)
1843{
1844 env->active_tc.PC = error_pc & ~(target_ulong)1;
1845 if (error_pc & 1) {
1846 env->hflags |= MIPS_HFLAG_M16;
1847 } else {
1848 env->hflags &= ~(MIPS_HFLAG_M16);
1849 }
1850}
1851
c01fccd2 1852void helper_eret (void)
2b0233ab 1853{
93fcfe39 1854 debug_pre_eret();
2b0233ab 1855 if (env->CP0_Status & (1 << CP0St_ERL)) {
32188a03 1856 set_pc(env->CP0_ErrorEPC);
2b0233ab
TS		 1857 env->CP0_Status &= ~(1 << CP0St_ERL);
1858 } else {
32188a03 1859 set_pc(env->CP0_EPC);
2b0233ab
TS		 1860 env->CP0_Status &= ~(1 << CP0St_EXL);
1861 }
1862 compute_hflags(env);
93fcfe39 1863 debug_post_eret();
5499b6ff 1864 env->lladdr = 1;
2b0233ab
TS		 1865}
1866
c01fccd2 1867void helper_deret (void)
2b0233ab 1868{
93fcfe39 1869 debug_pre_eret();
32188a03
NF		 1870 set_pc(env->CP0_DEPC);
1871
2b0233ab
TS		 1872 env->hflags &= MIPS_HFLAG_DM;
1873 compute_hflags(env);
93fcfe39 1874 debug_post_eret();
5499b6ff 1875 env->lladdr = 1;
2b0233ab 1876}
0eaef5aa 1877#endif /* !CONFIG_USER_ONLY */
2b0233ab 1878
c01fccd2 1879target_ulong helper_rdhwr_cpunum(void)
2b0233ab
TS		 1880{
1881 if ((env->hflags & MIPS_HFLAG_CP0) ||
1882 (env->CP0_HWREna & (1 << 0)))
2796188e 1883 return env->CP0_EBase & 0x3ff;
2b0233ab 1884 else
c01fccd2 1885 helper_raise_exception(EXCP_RI);
be24bb4f 1886
2796188e 1887 return 0;
2b0233ab
TS		 1888}
1889
c01fccd2 1890target_ulong helper_rdhwr_synci_step(void)
2b0233ab
TS		 1891{
1892 if ((env->hflags & MIPS_HFLAG_CP0) ||
1893 (env->CP0_HWREna & (1 << 1)))
2796188e 1894 return env->SYNCI_Step;
2b0233ab 1895 else
c01fccd2 1896 helper_raise_exception(EXCP_RI);
be24bb4f 1897
2796188e 1898 return 0;
2b0233ab
TS		 1899}
1900
c01fccd2 1901target_ulong helper_rdhwr_cc(void)
2b0233ab
TS		 1902{
1903 if ((env->hflags & MIPS_HFLAG_CP0) ||
1904 (env->CP0_HWREna & (1 << 2)))
2796188e 1905 return env->CP0_Count;
2b0233ab 1906 else
c01fccd2 1907 helper_raise_exception(EXCP_RI);
be24bb4f 1908
2796188e 1909 return 0;
2b0233ab
TS		 1910}
1911
c01fccd2 1912target_ulong helper_rdhwr_ccres(void)
2b0233ab
TS		 1913{
1914 if ((env->hflags & MIPS_HFLAG_CP0) ||
1915 (env->CP0_HWREna & (1 << 3)))
2796188e 1916 return env->CCRes;
2b0233ab 1917 else
c01fccd2 1918 helper_raise_exception(EXCP_RI);
be24bb4f 1919
2796188e 1920 return 0;
2b0233ab
TS		 1921}
1922
c01fccd2 1923void helper_pmon (int function)
6af0bf9c
FB		 1924{
1925 function /= 2;
1926 switch (function) {
1927 case 2: /* TODO: char inbyte(int waitflag); */
b5dc7732
TS		 1928 if (env->active_tc.gpr[4] == 0)
1929 env->active_tc.gpr[2] = -1;
6af0bf9c
FB		 1930 /* Fall through */
1931 case 11: /* TODO: char inbyte (void); */
b5dc7732 1932 env->active_tc.gpr[2] = -1;
6af0bf9c
FB		 1933 break;
1934 case 3:
1935 case 12:
b5dc7732 1936 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
6af0bf9c
FB		 1937 break;
1938 case 17:
1939 break;
1940 case 158:
1941 {
b5dc7732 1942 unsigned char *fmt = (void *)(unsigned long)env->active_tc.gpr[4];
6af0bf9c
FB		 1943 printf("%s", fmt);
1944 }
1945 break;
1946 }
1947}
e37e863f 1948
c01fccd2 1949void helper_wait (void)
08ba7963
TS		 1950{
1951 env->halted = 1;
c01fccd2 1952 helper_raise_exception(EXCP_HLT);
08ba7963
TS		 1953}
1954
5fafdf24 1955#if !defined(CONFIG_USER_ONLY)
e37e863f 1956
4ad40f36
FB		 1957static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
1958
e37e863f 1959#define MMUSUFFIX _mmu
4ad40f36 1960#define ALIGNED_ONLY
e37e863f
FB		 1961
1962#define SHIFT 0
1963#include "softmmu_template.h"
1964
1965#define SHIFT 1
1966#include "softmmu_template.h"
1967
1968#define SHIFT 2
1969#include "softmmu_template.h"
1970
1971#define SHIFT 3
1972#include "softmmu_template.h"
1973
4ad40f36
FB		 1974static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
1975{
1976 env->CP0_BadVAddr = addr;
1977 do_restore_state (retaddr);
c01fccd2 1978 helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
4ad40f36
FB		 1979}
1980
6ebbf390 1981void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
e37e863f
FB		 1982{
1983 TranslationBlock *tb;
1984 CPUState *saved_env;
1985 unsigned long pc;
1986 int ret;
1987
1988 /* XXX: hack to restore env in all cases, even if not called from
1989 generated code */
1990 saved_env = env;
1991 env = cpu_single_env;
6ebbf390 1992 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
e37e863f
FB		 1993 if (ret) {
1994 if (retaddr) {
1995 /* now we have a real cpu fault */
1996 pc = (unsigned long)retaddr;
1997 tb = tb_find_pc(pc);
1998 if (tb) {
1999 /* the PC is inside the translated code. It means that we have
2000 a virtual CPU fault */
2001 cpu_restore_state(tb, env, pc, NULL);
2002 }
2003 }
c01fccd2 2004 helper_raise_exception_err(env->exception_index, env->error_code);
e37e863f
FB		 2005 }
2006 env = saved_env;
2007}
2008
c227f099 2009void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
e18231a3 2010 int unused, int size)
647de6ca
TS		 2011{
2012 if (is_exec)
c01fccd2 2013 helper_raise_exception(EXCP_IBE);
647de6ca 2014 else
c01fccd2 2015 helper_raise_exception(EXCP_DBE);
647de6ca 2016}
f1aa6320 2017#endif /* !CONFIG_USER_ONLY */
fd4a04eb
TS		 2018
2019/* Complex FPU operations which may need stack space. */
2020
f090c9d4
PB		 2021#define FLOAT_ONE32 make_float32(0x3f8 << 20)
2022#define FLOAT_ONE64 make_float64(0x3ffULL << 52)
2023#define FLOAT_TWO32 make_float32(1 << 30)
2024#define FLOAT_TWO64 make_float64(1ULL << 62)
54454097
TS		 2025#define FLOAT_QNAN32 0x7fbfffff
2026#define FLOAT_QNAN64 0x7ff7ffffffffffffULL
2027#define FLOAT_SNAN32 0x7fffffff
2028#define FLOAT_SNAN64 0x7fffffffffffffffULL
8dfdb87c 2029
fd4a04eb 2030/* convert MIPS rounding mode in FCR31 to IEEE library */
6f4fc367 2031static unsigned int ieee_rm[] = {
fd4a04eb
TS		 2032 float_round_nearest_even,
2033 float_round_to_zero,
2034 float_round_up,
2035 float_round_down
2036};
2037
2038#define RESTORE_ROUNDING_MODE \
f01be154 2039 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
fd4a04eb 2040
41e0c701
AJ		 2041#define RESTORE_FLUSH_MODE \
2042 set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status);
2043
c01fccd2 2044target_ulong helper_cfc1 (uint32_t reg)
fd4a04eb 2045{
d9bea114 2046 target_ulong arg1;
6c5c1e20 2047
ead9360e
TS		 2048 switch (reg) {
2049 case 0:
d9bea114 2050 arg1 = (int32_t)env->active_fpu.fcr0;
ead9360e
TS		 2051 break;
2052 case 25:
d9bea114 2053 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
ead9360e
TS		 2054 break;
2055 case 26:
d9bea114 2056 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
ead9360e
TS		 2057 break;
2058 case 28:
d9bea114 2059 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
ead9360e
TS		 2060 break;
2061 default:
d9bea114 2062 arg1 = (int32_t)env->active_fpu.fcr31;
ead9360e
TS		 2063 break;
2064 }
be24bb4f 2065
d9bea114 2066 return arg1;
ead9360e
TS		 2067}
2068
d9bea114 2069void helper_ctc1 (target_ulong arg1, uint32_t reg)
ead9360e
TS		 2070{
2071 switch(reg) {
fd4a04eb 2072 case 25:
d9bea114 2073 if (arg1 & 0xffffff00)
fd4a04eb 2074 return;
d9bea114
AJ		 2075 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2076 ((arg1 & 0x1) << 23);
fd4a04eb
TS		 2077 break;
2078 case 26:
d9bea114 2079 if (arg1 & 0x007c0000)
fd4a04eb 2080 return;
d9bea114 2081 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
fd4a04eb
TS		 2082 break;
2083 case 28:
d9bea114 2084 if (arg1 & 0x007c0000)
fd4a04eb 2085 return;
d9bea114
AJ		 2086 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2087 ((arg1 & 0x4) << 22);
fd4a04eb
TS		 2088 break;
2089 case 31:
d9bea114 2090 if (arg1 & 0x007c0000)
fd4a04eb 2091 return;
d9bea114 2092 env->active_fpu.fcr31 = arg1;
fd4a04eb
TS		 2093 break;
2094 default:
2095 return;
2096 }
2097 /* set rounding mode */
2098 RESTORE_ROUNDING_MODE;
41e0c701
AJ		 2099 /* set flush-to-zero mode */
2100 RESTORE_FLUSH_MODE;
f01be154
TS		 2101 set_float_exception_flags(0, &env->active_fpu.fp_status);
2102 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
c01fccd2 2103 helper_raise_exception(EXCP_FPE);
fd4a04eb
TS		 2104}
2105
c904ef0e 2106static inline char ieee_ex_to_mips(char xcpt)
fd4a04eb
TS		 2107{
2108 return (xcpt & float_flag_inexact) >> 5 |
2109 (xcpt & float_flag_underflow) >> 3 |
2110 (xcpt & float_flag_overflow) >> 1 |
2111 (xcpt & float_flag_divbyzero) << 1 |
2112 (xcpt & float_flag_invalid) << 4;
2113}
2114
c904ef0e 2115static inline char mips_ex_to_ieee(char xcpt)
fd4a04eb
TS		 2116{
2117 return (xcpt & FP_INEXACT) << 5 |
2118 (xcpt & FP_UNDERFLOW) << 3 |
2119 (xcpt & FP_OVERFLOW) << 1 |
2120 (xcpt & FP_DIV0) >> 1 |
2121 (xcpt & FP_INVALID) >> 4;
2122}
2123
c904ef0e 2124static inline void update_fcr31(void)
fd4a04eb 2125{
f01be154 2126 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
fd4a04eb 2127
f01be154
TS		 2128 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2129 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp)
c01fccd2 2130 helper_raise_exception(EXCP_FPE);
fd4a04eb 2131 else
f01be154 2132 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
fd4a04eb
TS		 2133}
2134
a16336e4
TS		 2135/* Float support.
2136 Single precition routines have a "s" suffix, double precision a
2137 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2138 paired single lower "pl", paired single upper "pu". */
2139
a16336e4 2140/* unary operations, modifying fp status */
c01fccd2 2141uint64_t helper_float_sqrt_d(uint64_t fdt0)
b6d96bed 2142{
f01be154 2143 return float64_sqrt(fdt0, &env->active_fpu.fp_status);
b6d96bed
TS		 2144}
2145
c01fccd2 2146uint32_t helper_float_sqrt_s(uint32_t fst0)
b6d96bed 2147{
f01be154 2148 return float32_sqrt(fst0, &env->active_fpu.fp_status);
b6d96bed 2149}
a16336e4 2150
c01fccd2 2151uint64_t helper_float_cvtd_s(uint32_t fst0)
fd4a04eb 2152{
b6d96bed
TS		 2153 uint64_t fdt2;
2154
f01be154
TS		 2155 set_float_exception_flags(0, &env->active_fpu.fp_status);
2156 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
fd4a04eb 2157 update_fcr31();
b6d96bed 2158 return fdt2;
fd4a04eb 2159}
b6d96bed 2160
c01fccd2 2161uint64_t helper_float_cvtd_w(uint32_t wt0)
fd4a04eb 2162{
b6d96bed
TS		 2163 uint64_t fdt2;
2164
f01be154
TS		 2165 set_float_exception_flags(0, &env->active_fpu.fp_status);
2166 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
fd4a04eb 2167 update_fcr31();
b6d96bed 2168 return fdt2;
fd4a04eb 2169}
b6d96bed 2170
c01fccd2 2171uint64_t helper_float_cvtd_l(uint64_t dt0)
fd4a04eb 2172{
b6d96bed
TS		 2173 uint64_t fdt2;
2174
f01be154
TS		 2175 set_float_exception_flags(0, &env->active_fpu.fp_status);
2176 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
fd4a04eb 2177 update_fcr31();
b6d96bed 2178 return fdt2;
fd4a04eb 2179}
b6d96bed 2180
c01fccd2 2181uint64_t helper_float_cvtl_d(uint64_t fdt0)
fd4a04eb 2182{
b6d96bed
TS		 2183 uint64_t dt2;
2184
f01be154
TS		 2185 set_float_exception_flags(0, &env->active_fpu.fp_status);
2186 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2187 update_fcr31();
f01be154 2188 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2189 dt2 = FLOAT_SNAN64;
2190 return dt2;
fd4a04eb 2191}
b6d96bed 2192
c01fccd2 2193uint64_t helper_float_cvtl_s(uint32_t fst0)
fd4a04eb 2194{
b6d96bed
TS		 2195 uint64_t dt2;
2196
f01be154
TS		 2197 set_float_exception_flags(0, &env->active_fpu.fp_status);
2198 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
fd4a04eb 2199 update_fcr31();
f01be154 2200 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2201 dt2 = FLOAT_SNAN64;
2202 return dt2;
fd4a04eb
TS		 2203}
2204
c01fccd2 2205uint64_t helper_float_cvtps_pw(uint64_t dt0)
fd4a04eb 2206{
b6d96bed
TS		 2207 uint32_t fst2;
2208 uint32_t fsth2;
2209
f01be154
TS		 2210 set_float_exception_flags(0, &env->active_fpu.fp_status);
2211 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2212 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
fd4a04eb 2213 update_fcr31();
b6d96bed 2214 return ((uint64_t)fsth2 << 32) | fst2;
fd4a04eb 2215}
b6d96bed 2216
c01fccd2 2217uint64_t helper_float_cvtpw_ps(uint64_t fdt0)
fd4a04eb 2218{
b6d96bed
TS		 2219 uint32_t wt2;
2220 uint32_t wth2;
2221
f01be154
TS		 2222 set_float_exception_flags(0, &env->active_fpu.fp_status);
2223 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2224 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
fd4a04eb 2225 update_fcr31();
f01be154 2226 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) {
b6d96bed
TS		 2227 wt2 = FLOAT_SNAN32;
2228 wth2 = FLOAT_SNAN32;
2229 }
2230 return ((uint64_t)wth2 << 32) | wt2;
fd4a04eb 2231}
b6d96bed 2232
c01fccd2 2233uint32_t helper_float_cvts_d(uint64_t fdt0)
fd4a04eb 2234{
b6d96bed
TS		 2235 uint32_t fst2;
2236
f01be154
TS		 2237 set_float_exception_flags(0, &env->active_fpu.fp_status);
2238 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2239 update_fcr31();
b6d96bed 2240 return fst2;
fd4a04eb 2241}
b6d96bed 2242
c01fccd2 2243uint32_t helper_float_cvts_w(uint32_t wt0)
fd4a04eb 2244{
b6d96bed
TS		 2245 uint32_t fst2;
2246
f01be154
TS		 2247 set_float_exception_flags(0, &env->active_fpu.fp_status);
2248 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
fd4a04eb 2249 update_fcr31();
b6d96bed 2250 return fst2;
fd4a04eb 2251}
b6d96bed 2252
c01fccd2 2253uint32_t helper_float_cvts_l(uint64_t dt0)
fd4a04eb 2254{
b6d96bed
TS		 2255 uint32_t fst2;
2256
f01be154
TS		 2257 set_float_exception_flags(0, &env->active_fpu.fp_status);
2258 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
fd4a04eb 2259 update_fcr31();
b6d96bed 2260 return fst2;
fd4a04eb 2261}
b6d96bed 2262
c01fccd2 2263uint32_t helper_float_cvts_pl(uint32_t wt0)
fd4a04eb 2264{
b6d96bed
TS		 2265 uint32_t wt2;
2266
f01be154 2267 set_float_exception_flags(0, &env->active_fpu.fp_status);
b6d96bed 2268 wt2 = wt0;
fd4a04eb 2269 update_fcr31();
b6d96bed 2270 return wt2;
fd4a04eb 2271}
b6d96bed 2272
c01fccd2 2273uint32_t helper_float_cvts_pu(uint32_t wth0)
fd4a04eb 2274{
b6d96bed
TS		 2275 uint32_t wt2;
2276
f01be154 2277 set_float_exception_flags(0, &env->active_fpu.fp_status);
b6d96bed 2278 wt2 = wth0;
fd4a04eb 2279 update_fcr31();
b6d96bed 2280 return wt2;
fd4a04eb 2281}
b6d96bed 2282
c01fccd2 2283uint32_t helper_float_cvtw_s(uint32_t fst0)
fd4a04eb 2284{
b6d96bed
TS		 2285 uint32_t wt2;
2286
f01be154
TS		 2287 set_float_exception_flags(0, &env->active_fpu.fp_status);
2288 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
fd4a04eb 2289 update_fcr31();
f01be154 2290 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2291 wt2 = FLOAT_SNAN32;
2292 return wt2;
fd4a04eb 2293}
b6d96bed 2294
c01fccd2 2295uint32_t helper_float_cvtw_d(uint64_t fdt0)
fd4a04eb 2296{
b6d96bed
TS		 2297 uint32_t wt2;
2298
f01be154
TS		 2299 set_float_exception_flags(0, &env->active_fpu.fp_status);
2300 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2301 update_fcr31();
f01be154 2302 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2303 wt2 = FLOAT_SNAN32;
2304 return wt2;
fd4a04eb
TS		 2305}
2306
c01fccd2 2307uint64_t helper_float_roundl_d(uint64_t fdt0)
fd4a04eb 2308{
b6d96bed
TS		 2309 uint64_t dt2;
2310
f01be154
TS		 2311 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2312 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2313 RESTORE_ROUNDING_MODE;
2314 update_fcr31();
f01be154 2315 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2316 dt2 = FLOAT_SNAN64;
2317 return dt2;
fd4a04eb 2318}
b6d96bed 2319
c01fccd2 2320uint64_t helper_float_roundl_s(uint32_t fst0)
fd4a04eb 2321{
b6d96bed
TS		 2322 uint64_t dt2;
2323
f01be154
TS		 2324 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2325 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2326 RESTORE_ROUNDING_MODE;
2327 update_fcr31();
f01be154 2328 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2329 dt2 = FLOAT_SNAN64;
2330 return dt2;
fd4a04eb 2331}
b6d96bed 2332
c01fccd2 2333uint32_t helper_float_roundw_d(uint64_t fdt0)
fd4a04eb 2334{
b6d96bed
TS		 2335 uint32_t wt2;
2336
f01be154
TS		 2337 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2338 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2339 RESTORE_ROUNDING_MODE;
2340 update_fcr31();
f01be154 2341 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2342 wt2 = FLOAT_SNAN32;
2343 return wt2;
fd4a04eb 2344}
b6d96bed 2345
c01fccd2 2346uint32_t helper_float_roundw_s(uint32_t fst0)
fd4a04eb 2347{
b6d96bed
TS		 2348 uint32_t wt2;
2349
f01be154
TS		 2350 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2351 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2352 RESTORE_ROUNDING_MODE;
2353 update_fcr31();
f01be154 2354 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2355 wt2 = FLOAT_SNAN32;
2356 return wt2;
fd4a04eb
TS		 2357}
2358
c01fccd2 2359uint64_t helper_float_truncl_d(uint64_t fdt0)
fd4a04eb 2360{
b6d96bed
TS		 2361 uint64_t dt2;
2362
f01be154 2363 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2364 update_fcr31();
f01be154 2365 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2366 dt2 = FLOAT_SNAN64;
2367 return dt2;
fd4a04eb 2368}
b6d96bed 2369
c01fccd2 2370uint64_t helper_float_truncl_s(uint32_t fst0)
fd4a04eb 2371{
b6d96bed
TS		 2372 uint64_t dt2;
2373
f01be154 2374 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
fd4a04eb 2375 update_fcr31();
f01be154 2376 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2377 dt2 = FLOAT_SNAN64;
2378 return dt2;
fd4a04eb 2379}
b6d96bed 2380
c01fccd2 2381uint32_t helper_float_truncw_d(uint64_t fdt0)
fd4a04eb 2382{
b6d96bed
TS		 2383 uint32_t wt2;
2384
f01be154 2385 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
fd4a04eb 2386 update_fcr31();
f01be154 2387 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2388 wt2 = FLOAT_SNAN32;
2389 return wt2;
fd4a04eb 2390}
b6d96bed 2391
c01fccd2 2392uint32_t helper_float_truncw_s(uint32_t fst0)
fd4a04eb 2393{
b6d96bed
TS		 2394 uint32_t wt2;
2395
f01be154 2396 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
fd4a04eb 2397 update_fcr31();
f01be154 2398 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2399 wt2 = FLOAT_SNAN32;
2400 return wt2;
fd4a04eb
TS		 2401}
2402
c01fccd2 2403uint64_t helper_float_ceill_d(uint64_t fdt0)
fd4a04eb 2404{
b6d96bed
TS		 2405 uint64_t dt2;
2406
f01be154
TS		 2407 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2408 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2409 RESTORE_ROUNDING_MODE;
2410 update_fcr31();
f01be154 2411 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2412 dt2 = FLOAT_SNAN64;
2413 return dt2;
fd4a04eb 2414}
b6d96bed 2415
c01fccd2 2416uint64_t helper_float_ceill_s(uint32_t fst0)
fd4a04eb 2417{
b6d96bed
TS		 2418 uint64_t dt2;
2419
f01be154
TS		 2420 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2421 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2422 RESTORE_ROUNDING_MODE;
2423 update_fcr31();
f01be154 2424 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2425 dt2 = FLOAT_SNAN64;
2426 return dt2;
fd4a04eb 2427}
b6d96bed 2428
c01fccd2 2429uint32_t helper_float_ceilw_d(uint64_t fdt0)
fd4a04eb 2430{
b6d96bed
TS		 2431 uint32_t wt2;
2432
f01be154
TS		 2433 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2434 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2435 RESTORE_ROUNDING_MODE;
2436 update_fcr31();
f01be154 2437 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2438 wt2 = FLOAT_SNAN32;
2439 return wt2;
fd4a04eb 2440}
b6d96bed 2441
c01fccd2 2442uint32_t helper_float_ceilw_s(uint32_t fst0)
fd4a04eb 2443{
b6d96bed
TS		 2444 uint32_t wt2;
2445
f01be154
TS		 2446 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2447 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2448 RESTORE_ROUNDING_MODE;
2449 update_fcr31();
f01be154 2450 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2451 wt2 = FLOAT_SNAN32;
2452 return wt2;
fd4a04eb
TS		 2453}
2454
c01fccd2 2455uint64_t helper_float_floorl_d(uint64_t fdt0)
fd4a04eb 2456{
b6d96bed
TS		 2457 uint64_t dt2;
2458
f01be154
TS		 2459 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2460 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2461 RESTORE_ROUNDING_MODE;
2462 update_fcr31();
f01be154 2463 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2464 dt2 = FLOAT_SNAN64;
2465 return dt2;
fd4a04eb 2466}
b6d96bed 2467
c01fccd2 2468uint64_t helper_float_floorl_s(uint32_t fst0)
fd4a04eb 2469{
b6d96bed
TS		 2470 uint64_t dt2;
2471
f01be154
TS		 2472 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2473 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2474 RESTORE_ROUNDING_MODE;
2475 update_fcr31();
f01be154 2476 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2477 dt2 = FLOAT_SNAN64;
2478 return dt2;
fd4a04eb 2479}
b6d96bed 2480
c01fccd2 2481uint32_t helper_float_floorw_d(uint64_t fdt0)
fd4a04eb 2482{
b6d96bed
TS		 2483 uint32_t wt2;
2484
f01be154
TS		 2485 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2486 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2487 RESTORE_ROUNDING_MODE;
2488 update_fcr31();
f01be154 2489 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2490 wt2 = FLOAT_SNAN32;
2491 return wt2;
fd4a04eb 2492}
b6d96bed 2493
c01fccd2 2494uint32_t helper_float_floorw_s(uint32_t fst0)
fd4a04eb 2495{
b6d96bed
TS		 2496 uint32_t wt2;
2497
f01be154
TS		 2498 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2499 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
fd4a04eb
TS		 2500 RESTORE_ROUNDING_MODE;
2501 update_fcr31();
f01be154 2502 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
b6d96bed
TS		 2503 wt2 = FLOAT_SNAN32;
2504 return wt2;
fd4a04eb
TS		 2505}
2506
a16336e4 2507/* unary operations, not modifying fp status */
b6d96bed 2508#define FLOAT_UNOP(name) \
c01fccd2 2509uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
b6d96bed
TS		 2510{ \
2511 return float64_ ## name(fdt0); \
2512} \
c01fccd2 2513uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
b6d96bed
TS		 2514{ \
2515 return float32_ ## name(fst0); \
2516} \
c01fccd2 2517uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
b6d96bed
TS		 2518{ \
2519 uint32_t wt0; \
2520 uint32_t wth0; \
2521 \
2522 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
2523 wth0 = float32_ ## name(fdt0 >> 32); \
2524 return ((uint64_t)wth0 << 32) | wt0; \
a16336e4
TS		 2525}
2526FLOAT_UNOP(abs)
2527FLOAT_UNOP(chs)
2528#undef FLOAT_UNOP
2529
8dfdb87c 2530/* MIPS specific unary operations */
c01fccd2 2531uint64_t helper_float_recip_d(uint64_t fdt0)
8dfdb87c 2532{
b6d96bed
TS		 2533 uint64_t fdt2;
2534
f01be154
TS		 2535 set_float_exception_flags(0, &env->active_fpu.fp_status);
2536 fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
8dfdb87c 2537 update_fcr31();
b6d96bed 2538 return fdt2;
8dfdb87c 2539}
b6d96bed 2540
c01fccd2 2541uint32_t helper_float_recip_s(uint32_t fst0)
8dfdb87c 2542{
b6d96bed
TS		 2543 uint32_t fst2;
2544
f01be154
TS		 2545 set_float_exception_flags(0, &env->active_fpu.fp_status);
2546 fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
8dfdb87c 2547 update_fcr31();
b6d96bed 2548 return fst2;
57fa1fb3 2549}
57fa1fb3 2550
c01fccd2 2551uint64_t helper_float_rsqrt_d(uint64_t fdt0)
8dfdb87c 2552{
b6d96bed
TS		 2553 uint64_t fdt2;
2554
f01be154
TS		 2555 set_float_exception_flags(0, &env->active_fpu.fp_status);
2556 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2557 fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
8dfdb87c 2558 update_fcr31();
b6d96bed 2559 return fdt2;
8dfdb87c 2560}
b6d96bed 2561
c01fccd2 2562uint32_t helper_float_rsqrt_s(uint32_t fst0)
8dfdb87c 2563{
b6d96bed
TS		 2564 uint32_t fst2;
2565
f01be154
TS		 2566 set_float_exception_flags(0, &env->active_fpu.fp_status);
2567 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2568 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
8dfdb87c 2569 update_fcr31();
b6d96bed 2570 return fst2;
8dfdb87c
TS		 2571}
2572
c01fccd2 2573uint64_t helper_float_recip1_d(uint64_t fdt0)
8dfdb87c 2574{
b6d96bed
TS		 2575 uint64_t fdt2;
2576
f01be154
TS		 2577 set_float_exception_flags(0, &env->active_fpu.fp_status);
2578 fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
8dfdb87c 2579 update_fcr31();
b6d96bed 2580 return fdt2;
8dfdb87c 2581}
b6d96bed 2582
c01fccd2 2583uint32_t helper_float_recip1_s(uint32_t fst0)
8dfdb87c 2584{
b6d96bed
TS		 2585 uint32_t fst2;
2586
f01be154
TS		 2587 set_float_exception_flags(0, &env->active_fpu.fp_status);
2588 fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
8dfdb87c 2589 update_fcr31();
b6d96bed 2590 return fst2;
8dfdb87c 2591}
b6d96bed 2592
c01fccd2 2593uint64_t helper_float_recip1_ps(uint64_t fdt0)
8dfdb87c 2594{
b6d96bed
TS		 2595 uint32_t fst2;
2596 uint32_t fsth2;
2597
f01be154
TS		 2598 set_float_exception_flags(0, &env->active_fpu.fp_status);
2599 fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2600 fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status);
8dfdb87c 2601 update_fcr31();
b6d96bed 2602 return ((uint64_t)fsth2 << 32) | fst2;
8dfdb87c
TS		 2603}
2604
c01fccd2 2605uint64_t helper_float_rsqrt1_d(uint64_t fdt0)
8dfdb87c 2606{
b6d96bed
TS		 2607 uint64_t fdt2;
2608
f01be154
TS		 2609 set_float_exception_flags(0, &env->active_fpu.fp_status);
2610 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2611 fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
8dfdb87c 2612 update_fcr31();
b6d96bed 2613 return fdt2;
8dfdb87c 2614}
b6d96bed 2615
c01fccd2 2616uint32_t helper_float_rsqrt1_s(uint32_t fst0)
8dfdb87c 2617{
b6d96bed
TS		 2618 uint32_t fst2;
2619
f01be154
TS		 2620 set_float_exception_flags(0, &env->active_fpu.fp_status);
2621 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2622 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
8dfdb87c 2623 update_fcr31();
b6d96bed 2624 return fst2;
8dfdb87c 2625}
b6d96bed 2626
c01fccd2 2627uint64_t helper_float_rsqrt1_ps(uint64_t fdt0)
8dfdb87c 2628{
b6d96bed
TS		 2629 uint32_t fst2;
2630 uint32_t fsth2;
2631
f01be154
TS		 2632 set_float_exception_flags(0, &env->active_fpu.fp_status);
2633 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2634 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2635 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2636 fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status);
8dfdb87c 2637 update_fcr31();
b6d96bed 2638 return ((uint64_t)fsth2 << 32) | fst2;
57fa1fb3 2639}
57fa1fb3 2640
c01fccd2 2641#define FLOAT_OP(name, p) void helper_float_##name##_##p(void)
b6d96bed 2642
fd4a04eb 2643/* binary operations */
b6d96bed 2644#define FLOAT_BINOP(name) \
c01fccd2 2645uint64_t helper_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \
b6d96bed
TS		 2646{ \
2647 uint64_t dt2; \
2648 \
f01be154
TS		 2649 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2650 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
ead9360e 2651 update_fcr31(); \
f01be154 2652 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
b6d96bed
TS		 2653 dt2 = FLOAT_QNAN64; \
2654 return dt2; \
2655} \
2656 \
c01fccd2 2657uint32_t helper_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \
b6d96bed
TS		 2658{ \
2659 uint32_t wt2; \
2660 \
f01be154
TS		 2661 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2662 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
ead9360e 2663 update_fcr31(); \
f01be154 2664 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
b6d96bed
TS		 2665 wt2 = FLOAT_QNAN32; \
2666 return wt2; \
2667} \
2668 \
c01fccd2 2669uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \
b6d96bed
TS		 2670{ \
2671 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2672 uint32_t fsth0 = fdt0 >> 32; \
2673 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2674 uint32_t fsth1 = fdt1 >> 32; \
2675 uint32_t wt2; \
2676 uint32_t wth2; \
2677 \
f01be154
TS		 2678 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2679 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2680 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
b6d96bed 2681 update_fcr31(); \
f01be154 2682 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \
b6d96bed
TS		 2683 wt2 = FLOAT_QNAN32; \
2684 wth2 = FLOAT_QNAN32; \
2685 } \
2686 return ((uint64_t)wth2 << 32) | wt2; \
fd4a04eb 2687}
b6d96bed 2688
fd4a04eb
TS		 2689FLOAT_BINOP(add)
2690FLOAT_BINOP(sub)
2691FLOAT_BINOP(mul)
2692FLOAT_BINOP(div)
2693#undef FLOAT_BINOP
2694
a16336e4 2695/* ternary operations */
b6d96bed 2696#define FLOAT_TERNOP(name1, name2) \
c01fccd2 2697uint64_t helper_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
b6d96bed
TS		 2698 uint64_t fdt2) \
2699{ \
f01be154
TS		 2700 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2701 return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2702} \
2703 \
c01fccd2 2704uint32_t helper_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
b6d96bed
TS		 2705 uint32_t fst2) \
2706{ \
f01be154
TS		 2707 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2708 return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2709} \
2710 \
c01fccd2 2711uint64_t helper_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \
b6d96bed
TS		 2712 uint64_t fdt2) \
2713{ \
2714 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2715 uint32_t fsth0 = fdt0 >> 32; \
2716 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2717 uint32_t fsth1 = fdt1 >> 32; \
2718 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2719 uint32_t fsth2 = fdt2 >> 32; \
2720 \
f01be154
TS		 2721 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2722 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
2723 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2724 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
b6d96bed 2725 return ((uint64_t)fsth2 << 32) | fst2; \
a16336e4 2726}
b6d96bed 2727
a16336e4
TS		 2728FLOAT_TERNOP(mul, add)
2729FLOAT_TERNOP(mul, sub)
2730#undef FLOAT_TERNOP
2731
2732/* negated ternary operations */
b6d96bed 2733#define FLOAT_NTERNOP(name1, name2) \
c01fccd2 2734uint64_t helper_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
b6d96bed
TS		 2735 uint64_t fdt2) \
2736{ \
f01be154
TS		 2737 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2738 fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2739 return float64_chs(fdt2); \
2740} \
2741 \
c01fccd2 2742uint32_t helper_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
b6d96bed
TS		 2743 uint32_t fst2) \
2744{ \
f01be154
TS		 2745 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2746 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2747 return float32_chs(fst2); \
2748} \
2749 \
c01fccd2 2750uint64_t helper_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\
b6d96bed
TS		 2751 uint64_t fdt2) \
2752{ \
2753 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2754 uint32_t fsth0 = fdt0 >> 32; \
2755 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2756 uint32_t fsth1 = fdt1 >> 32; \
2757 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2758 uint32_t fsth2 = fdt2 >> 32; \
2759 \
f01be154
TS		 2760 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2761 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
2762 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2763 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
b6d96bed
TS		 2764 fst2 = float32_chs(fst2); \
2765 fsth2 = float32_chs(fsth2); \
2766 return ((uint64_t)fsth2 << 32) | fst2; \
a16336e4 2767}
b6d96bed 2768
a16336e4
TS		 2769FLOAT_NTERNOP(mul, add)
2770FLOAT_NTERNOP(mul, sub)
2771#undef FLOAT_NTERNOP
2772
8dfdb87c 2773/* MIPS specific binary operations */
c01fccd2 2774uint64_t helper_float_recip2_d(uint64_t fdt0, uint64_t fdt2)
8dfdb87c 2775{
f01be154
TS		 2776 set_float_exception_flags(0, &env->active_fpu.fp_status);
2777 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2778 fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status));
8dfdb87c 2779 update_fcr31();
b6d96bed 2780 return fdt2;
8dfdb87c 2781}
b6d96bed 2782
c01fccd2 2783uint32_t helper_float_recip2_s(uint32_t fst0, uint32_t fst2)
8dfdb87c 2784{
f01be154
TS		 2785 set_float_exception_flags(0, &env->active_fpu.fp_status);
2786 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2787 fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
8dfdb87c 2788 update_fcr31();
b6d96bed 2789 return fst2;
8dfdb87c 2790}
b6d96bed 2791
c01fccd2 2792uint64_t helper_float_recip2_ps(uint64_t fdt0, uint64_t fdt2)
8dfdb87c 2793{
b6d96bed
TS		 2794 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2795 uint32_t fsth0 = fdt0 >> 32;
2796 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2797 uint32_t fsth2 = fdt2 >> 32;
2798
f01be154
TS		 2799 set_float_exception_flags(0, &env->active_fpu.fp_status);
2800 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2801 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2802 fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
2803 fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status));
8dfdb87c 2804 update_fcr31();
b6d96bed 2805 return ((uint64_t)fsth2 << 32) | fst2;
8dfdb87c
TS		 2806}
2807
c01fccd2 2808uint64_t helper_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2)
8dfdb87c 2809{
f01be154
TS		 2810 set_float_exception_flags(0, &env->active_fpu.fp_status);
2811 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2812 fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status);
2813 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
8dfdb87c 2814 update_fcr31();
b6d96bed 2815 return fdt2;
8dfdb87c 2816}
b6d96bed 2817
c01fccd2 2818uint32_t helper_float_rsqrt2_s(uint32_t fst0, uint32_t fst2)
8dfdb87c 2819{
f01be154
TS		 2820 set_float_exception_flags(0, &env->active_fpu.fp_status);
2821 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2822 fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
2823 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
8dfdb87c 2824 update_fcr31();
b6d96bed 2825 return fst2;
8dfdb87c 2826}
b6d96bed 2827
c01fccd2 2828uint64_t helper_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2)
8dfdb87c 2829{
b6d96bed
TS		 2830 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2831 uint32_t fsth0 = fdt0 >> 32;
2832 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2833 uint32_t fsth2 = fdt2 >> 32;
2834
f01be154
TS		 2835 set_float_exception_flags(0, &env->active_fpu.fp_status);
2836 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2837 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2838 fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
2839 fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status);
2840 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2841 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
8dfdb87c 2842 update_fcr31();
b6d96bed 2843 return ((uint64_t)fsth2 << 32) | fst2;
57fa1fb3 2844}
57fa1fb3 2845
c01fccd2 2846uint64_t helper_float_addr_ps(uint64_t fdt0, uint64_t fdt1)
fd4a04eb 2847{
b6d96bed
TS		 2848 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2849 uint32_t fsth0 = fdt0 >> 32;
2850 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2851 uint32_t fsth1 = fdt1 >> 32;
2852 uint32_t fst2;
2853 uint32_t fsth2;
2854
f01be154
TS		 2855 set_float_exception_flags(0, &env->active_fpu.fp_status);
2856 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
2857 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
fd4a04eb 2858 update_fcr31();
b6d96bed 2859 return ((uint64_t)fsth2 << 32) | fst2;
fd4a04eb
TS		 2860}
2861
c01fccd2 2862uint64_t helper_float_mulr_ps(uint64_t fdt0, uint64_t fdt1)
57fa1fb3 2863{
b6d96bed
TS		 2864 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2865 uint32_t fsth0 = fdt0 >> 32;
2866 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2867 uint32_t fsth1 = fdt1 >> 32;
2868 uint32_t fst2;
2869 uint32_t fsth2;
2870
f01be154
TS		 2871 set_float_exception_flags(0, &env->active_fpu.fp_status);
2872 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
2873 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
57fa1fb3 2874 update_fcr31();
b6d96bed 2875 return ((uint64_t)fsth2 << 32) | fst2;
57fa1fb3
TS		 2876}
2877
8dfdb87c 2878/* compare operations */
b6d96bed 2879#define FOP_COND_D(op, cond) \
c01fccd2 2880void helper_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
b6d96bed
TS		 2881{ \
2882 int c = cond; \
2883 update_fcr31(); \
2884 if (c) \
f01be154 2885 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2886 else \
f01be154 2887 CLEAR_FP_COND(cc, env->active_fpu); \
b6d96bed 2888} \
c01fccd2 2889void helper_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
b6d96bed
TS		 2890{ \
2891 int c; \
2892 fdt0 = float64_abs(fdt0); \
2893 fdt1 = float64_abs(fdt1); \
2894 c = cond; \
2895 update_fcr31(); \
2896 if (c) \
f01be154 2897 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2898 else \
f01be154 2899 CLEAR_FP_COND(cc, env->active_fpu); \
fd4a04eb
TS		 2900}
2901
cd5158ea 2902static int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
fd4a04eb
TS		 2903{
2904 if (float64_is_signaling_nan(a) ||
2905 float64_is_signaling_nan(b) ||
2906 (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
2907 float_raise(float_flag_invalid, status);
2908 return 1;
2909 } else if (float64_is_nan(a) || float64_is_nan(b)) {
2910 return 1;
2911 } else {
2912 return 0;
2913 }
2914}
2915
2916/* NOTE: the comma operator will make "cond" to eval to false,
2917 * but float*_is_unordered() is still called. */
f01be154
TS		 2918FOP_COND_D(f, (float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status), 0))
2919FOP_COND_D(un, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status))
2920FOP_COND_D(eq, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2921FOP_COND_D(ueq, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2922FOP_COND_D(olt, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2923FOP_COND_D(ult, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2924FOP_COND_D(ole, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2925FOP_COND_D(ule, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
fd4a04eb
TS		 2926/* NOTE: the comma operator will make "cond" to eval to false,
2927 * but float*_is_unordered() is still called. */
f01be154
TS		 2928FOP_COND_D(sf, (float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status), 0))
2929FOP_COND_D(ngle,float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status))
2930FOP_COND_D(seq, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2931FOP_COND_D(ngl, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2932FOP_COND_D(lt, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2933FOP_COND_D(nge, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2934FOP_COND_D(le, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2935FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
b6d96bed
TS		 2936
2937#define FOP_COND_S(op, cond) \
c01fccd2 2938void helper_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
b6d96bed
TS		 2939{ \
2940 int c = cond; \
2941 update_fcr31(); \
2942 if (c) \
f01be154 2943 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2944 else \
f01be154 2945 CLEAR_FP_COND(cc, env->active_fpu); \
b6d96bed 2946} \
c01fccd2 2947void helper_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
b6d96bed
TS		 2948{ \
2949 int c; \
2950 fst0 = float32_abs(fst0); \
2951 fst1 = float32_abs(fst1); \
2952 c = cond; \
2953 update_fcr31(); \
2954 if (c) \
f01be154 2955 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 2956 else \
f01be154 2957 CLEAR_FP_COND(cc, env->active_fpu); \
fd4a04eb
TS		 2958}
2959
cd5158ea 2960static flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
fd4a04eb 2961{
fd4a04eb
TS		 2962 if (float32_is_signaling_nan(a) ||
2963 float32_is_signaling_nan(b) ||
2964 (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
2965 float_raise(float_flag_invalid, status);
2966 return 1;
2967 } else if (float32_is_nan(a) || float32_is_nan(b)) {
2968 return 1;
2969 } else {
2970 return 0;
2971 }
2972}
2973
2974/* NOTE: the comma operator will make "cond" to eval to false,
2975 * but float*_is_unordered() is still called. */
f01be154
TS		 2976FOP_COND_S(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0))
2977FOP_COND_S(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status))
2978FOP_COND_S(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2979FOP_COND_S(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2980FOP_COND_S(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2981FOP_COND_S(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2982FOP_COND_S(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
2983FOP_COND_S(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
fd4a04eb
TS		 2984/* NOTE: the comma operator will make "cond" to eval to false,
2985 * but float*_is_unordered() is still called. */
f01be154
TS		 2986FOP_COND_S(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0))
2987FOP_COND_S(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status))
2988FOP_COND_S(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2989FOP_COND_S(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2990FOP_COND_S(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2991FOP_COND_S(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2992FOP_COND_S(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
2993FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
b6d96bed
TS		 2994
2995#define FOP_COND_PS(op, condl, condh) \
c01fccd2 2996void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
b6d96bed
TS		 2997{ \
2998 uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
2999 uint32_t fsth0 = float32_abs(fdt0 >> 32); \
3000 uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
3001 uint32_t fsth1 = float32_abs(fdt1 >> 32); \
3002 int cl = condl; \
3003 int ch = condh; \
3004 \
3005 update_fcr31(); \
3006 if (cl) \
f01be154 3007 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 3008 else \
f01be154 3009 CLEAR_FP_COND(cc, env->active_fpu); \
b6d96bed 3010 if (ch) \
f01be154 3011 SET_FP_COND(cc + 1, env->active_fpu); \
b6d96bed 3012 else \
f01be154 3013 CLEAR_FP_COND(cc + 1, env->active_fpu); \
b6d96bed 3014} \
c01fccd2 3015void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
b6d96bed
TS		 3016{ \
3017 uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
3018 uint32_t fsth0 = float32_abs(fdt0 >> 32); \
3019 uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
3020 uint32_t fsth1 = float32_abs(fdt1 >> 32); \
3021 int cl = condl; \
3022 int ch = condh; \
3023 \
3024 update_fcr31(); \
3025 if (cl) \
f01be154 3026 SET_FP_COND(cc, env->active_fpu); \
b6d96bed 3027 else \
f01be154 3028 CLEAR_FP_COND(cc, env->active_fpu); \
b6d96bed 3029 if (ch) \
f01be154 3030 SET_FP_COND(cc + 1, env->active_fpu); \
b6d96bed 3031 else \
f01be154 3032 CLEAR_FP_COND(cc + 1, env->active_fpu); \
fd4a04eb
TS		 3033}
3034
3035/* NOTE: the comma operator will make "cond" to eval to false,
3036 * but float*_is_unordered() is still called. */
f01be154
TS		 3037FOP_COND_PS(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0),
3038 (float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status), 0))
3039FOP_COND_PS(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status),
3040 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status))
3041FOP_COND_PS(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3042 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3043FOP_COND_PS(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3044 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3045FOP_COND_PS(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3046 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3047FOP_COND_PS(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3048 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3049FOP_COND_PS(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status),
3050 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3051FOP_COND_PS(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3052 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
fd4a04eb
TS		 3053/* NOTE: the comma operator will make "cond" to eval to false,
3054 * but float*_is_unordered() is still called. */
f01be154
TS		 3055FOP_COND_PS(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0),
3056 (float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status), 0))
3057FOP_COND_PS(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status),
3058 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status))
3059FOP_COND_PS(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3060 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3061FOP_COND_PS(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3062 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3063FOP_COND_PS(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3064 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3065FOP_COND_PS(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3066 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3067FOP_COND_PS(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status),
3068 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3069FOP_COND_PS(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3070 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
Qemu copy for testing