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Don't install tools if $(TOOLS) is empty, by Thayne Harbaugh.
[qemu.git] / target-mips / op_helper.c
CommitLineData
6af0bf9c
FB		 1/*
2 * MIPS emulation helpers for qemu.
5fafdf24 3 *
6af0bf9c
FB		 4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
2d0e944d 20#include <stdlib.h>
6af0bf9c
FB		 21#include "exec.h"
22
4ad40f36
FB		 23#define GETPC() (__builtin_return_address(0))
24
6af0bf9c
FB		 25/*****************************************************************************/
26/* Exceptions processing helpers */
6af0bf9c 27
6af0bf9c
FB		 28void do_raise_exception_err (uint32_t exception, int error_code)
29{
30#if 1
31 if (logfile && exception < 0x100)
32 fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
33#endif
34 env->exception_index = exception;
35 env->error_code = error_code;
36 T0 = 0;
37 cpu_loop_exit();
38}
39
6af0bf9c
FB		 40void do_raise_exception (uint32_t exception)
41{
42 do_raise_exception_err(exception, 0);
43}
44
4ad40f36
FB		 45void do_restore_state (void *pc_ptr)
46{
47 TranslationBlock *tb;
48 unsigned long pc = (unsigned long) pc_ptr;
49
50 tb = tb_find_pc (pc);
51 cpu_restore_state (tb, env, pc, NULL);
52}
53
e397ee33 54void do_raise_exception_direct_err (uint32_t exception, int error_code)
4ad40f36
FB		 55{
56 do_restore_state (GETPC ());
e397ee33
TS		 57 do_raise_exception_err (exception, error_code);
58}
59
60void do_raise_exception_direct (uint32_t exception)
61{
62 do_raise_exception_direct_err (exception, 0);
4ad40f36
FB		 63}
64
540635ba 65#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
c570fd16
TS		 66#if TARGET_LONG_BITS > HOST_LONG_BITS
67/* Those might call libgcc functions. */
68void do_dsll (void)
69{
70 T0 = T0 << T1;
71}
72
73void do_dsll32 (void)
74{
75 T0 = T0 << (T1 + 32);
76}
77
78void do_dsra (void)
79{
80 T0 = (int64_t)T0 >> T1;
81}
82
83void do_dsra32 (void)
84{
85 T0 = (int64_t)T0 >> (T1 + 32);
86}
87
88void do_dsrl (void)
89{
90 T0 = T0 >> T1;
91}
92
93void do_dsrl32 (void)
94{
95 T0 = T0 >> (T1 + 32);
96}
97
98void do_drotr (void)
99{
100 target_ulong tmp;
101
102 if (T1) {
103 tmp = T0 << (0x40 - T1);
104 T0 = (T0 >> T1) | tmp;
5a63bcb2 105 }
c570fd16
TS		 106}
107
108void do_drotr32 (void)
109{
110 target_ulong tmp;
111
112 if (T1) {
113 tmp = T0 << (0x40 - (32 + T1));
114 T0 = (T0 >> (32 + T1)) | tmp;
5a63bcb2 115 }
c570fd16
TS		 116}
117
118void do_dsllv (void)
119{
120 T0 = T1 << (T0 & 0x3F);
121}
122
123void do_dsrav (void)
124{
125 T0 = (int64_t)T1 >> (T0 & 0x3F);
126}
127
128void do_dsrlv (void)
129{
130 T0 = T1 >> (T0 & 0x3F);
131}
132
133void do_drotrv (void)
134{
135 target_ulong tmp;
136
137 T0 &= 0x3F;
138 if (T0) {
139 tmp = T1 << (0x40 - T0);
140 T0 = (T1 >> T0) | tmp;
141 } else
142 T0 = T1;
143}
144#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
540635ba 145#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
c570fd16 146
6af0bf9c 147/* 64 bits arithmetic for 32 bits hosts */
c570fd16 148#if TARGET_LONG_BITS > HOST_LONG_BITS
aa343735 149static always_inline uint64_t get_HILO (void)
6af0bf9c 150{
ead9360e 151 return (env->HI[0][env->current_tc] << 32) | (uint32_t)env->LO[0][env->current_tc];
6af0bf9c
FB		 152}
153
aa343735 154static always_inline void set_HILO (uint64_t HILO)
6af0bf9c 155{
ead9360e
TS		 156 env->LO[0][env->current_tc] = (int32_t)HILO;
157 env->HI[0][env->current_tc] = (int32_t)(HILO >> 32);
6af0bf9c
FB		 158}
159
160void do_mult (void)
161{
4ad40f36 162 set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
6af0bf9c
FB		 163}
164
165void do_multu (void)
166{
c570fd16 167 set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
6af0bf9c
FB		 168}
169
170void do_madd (void)
171{
172 int64_t tmp;
173
4ad40f36 174 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
6af0bf9c
FB		 175 set_HILO((int64_t)get_HILO() + tmp);
176}
177
178void do_maddu (void)
179{
180 uint64_t tmp;
181
c570fd16 182 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
6af0bf9c
FB		 183 set_HILO(get_HILO() + tmp);
184}
185
186void do_msub (void)
187{
188 int64_t tmp;
189
4ad40f36 190 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
6af0bf9c
FB		 191 set_HILO((int64_t)get_HILO() - tmp);
192}
193
194void do_msubu (void)
195{
196 uint64_t tmp;
197
c570fd16 198 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
6af0bf9c
FB		 199 set_HILO(get_HILO() - tmp);
200}
201#endif
202
80c27194
TS		 203#if HOST_LONG_BITS < 64
204void do_div (void)
205{
206 /* 64bit datatypes because we may see overflow/underflow. */
207 if (T1 != 0) {
ead9360e
TS		 208 env->LO[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
209 env->HI[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
80c27194
TS		 210 }
211}
212#endif
213
540635ba 214#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
c570fd16
TS		 215void do_ddiv (void)
216{
217 if (T1 != 0) {
2d0e944d 218 lldiv_t res = lldiv((int64_t)T0, (int64_t)T1);
ead9360e
TS		 219 env->LO[0][env->current_tc] = res.quot;
220 env->HI[0][env->current_tc] = res.rem;
c570fd16
TS		 221 }
222}
223
12a4b2aa 224#if TARGET_LONG_BITS > HOST_LONG_BITS
c570fd16
TS		 225void do_ddivu (void)
226{
227 if (T1 != 0) {
ead9360e
TS		 228 env->LO[0][env->current_tc] = T0 / T1;
229 env->HI[0][env->current_tc] = T0 % T1;
c570fd16
TS		 230 }
231}
232#endif
540635ba 233#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
c570fd16 234
5fafdf24 235#if defined(CONFIG_USER_ONLY)
873eb012 236void do_mfc0_random (void)
048f6b4d 237{
873eb012 238 cpu_abort(env, "mfc0 random\n");
048f6b4d 239}
873eb012
TS		 240
241void do_mfc0_count (void)
242{
243 cpu_abort(env, "mfc0 count\n");
244}
245
8c0fdd85 246void cpu_mips_store_count(CPUState *env, uint32_t value)
048f6b4d 247{
8c0fdd85
TS		 248 cpu_abort(env, "mtc0 count\n");
249}
250
251void cpu_mips_store_compare(CPUState *env, uint32_t value)
252{
253 cpu_abort(env, "mtc0 compare\n");
254}
255
42532189
TS		 256void cpu_mips_start_count(CPUState *env)
257{
258 cpu_abort(env, "start count\n");
259}
260
261void cpu_mips_stop_count(CPUState *env)
262{
263 cpu_abort(env, "stop count\n");
264}
265
4de9b249
TS		 266void cpu_mips_update_irq(CPUState *env)
267{
268 cpu_abort(env, "mtc0 status / mtc0 cause\n");
269}
270
8c0fdd85
TS		 271void do_mtc0_status_debug(uint32_t old, uint32_t val)
272{
7a387fff 273 cpu_abort(env, "mtc0 status debug\n");
8c0fdd85
TS		 274}
275
7a387fff 276void do_mtc0_status_irqraise_debug (void)
8c0fdd85 277{
7a387fff 278 cpu_abort(env, "mtc0 status irqraise debug\n");
048f6b4d
FB		 279}
280
8c0fdd85
TS		 281void cpu_mips_tlb_flush (CPUState *env, int flush_global)
282{
283 cpu_abort(env, "mips_tlb_flush\n");
284}
285
048f6b4d
FB		 286#else
287
6af0bf9c 288/* CP0 helpers */
873eb012 289void do_mfc0_random (void)
6af0bf9c 290{
5dc4b744 291 T0 = (int32_t)cpu_mips_get_random(env);
873eb012 292}
6af0bf9c 293
873eb012
TS		 294void do_mfc0_count (void)
295{
5dc4b744 296 T0 = (int32_t)cpu_mips_get_count(env);
6af0bf9c
FB		 297}
298
8c0fdd85 299void do_mtc0_status_debug(uint32_t old, uint32_t val)
6af0bf9c 300{
f41c52f1
TS		 301 fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
302 old, old & env->CP0_Cause & CP0Ca_IP_mask,
303 val, val & env->CP0_Cause & CP0Ca_IP_mask,
304 env->CP0_Cause);
305 (env->hflags & MIPS_HFLAG_UM) ? fputs(", UM\n", logfile)
306 : fputs("\n", logfile);
8c0fdd85
TS		 307}
308
309void do_mtc0_status_irqraise_debug(void)
310{
311 fprintf(logfile, "Raise pending IRQs\n");
6af0bf9c
FB		 312}
313
6ea83fed
FB		 314void fpu_handle_exception(void)
315{
316#ifdef CONFIG_SOFTFLOAT
ead9360e 317 int flags = get_float_exception_flags(&env->fpu->fp_status);
6ea83fed
FB		 318 unsigned int cpuflags = 0, enable, cause = 0;
319
ead9360e 320 enable = GET_FP_ENABLE(env->fpu->fcr31);
6ea83fed 321
3b46e624 322 /* determine current flags */
6ea83fed
FB		 323 if (flags & float_flag_invalid) {
324 cpuflags |= FP_INVALID;
325 cause |= FP_INVALID & enable;
326 }
327 if (flags & float_flag_divbyzero) {
3b46e624 328 cpuflags |= FP_DIV0;
6ea83fed
FB		 329 cause |= FP_DIV0 & enable;
330 }
331 if (flags & float_flag_overflow) {
3b46e624 332 cpuflags |= FP_OVERFLOW;
6ea83fed
FB		 333 cause |= FP_OVERFLOW & enable;
334 }
335 if (flags & float_flag_underflow) {
3b46e624 336 cpuflags |= FP_UNDERFLOW;
6ea83fed
FB		 337 cause |= FP_UNDERFLOW & enable;
338 }
339 if (flags & float_flag_inexact) {
5fafdf24 340 cpuflags |= FP_INEXACT;
6ea83fed
FB		 341 cause |= FP_INEXACT & enable;
342 }
ead9360e
TS		 343 SET_FP_FLAGS(env->fpu->fcr31, cpuflags);
344 SET_FP_CAUSE(env->fpu->fcr31, cause);
6ea83fed 345#else
ead9360e
TS		 346 SET_FP_FLAGS(env->fpu->fcr31, 0);
347 SET_FP_CAUSE(env->fpu->fcr31, 0);
6ea83fed
FB		 348#endif
349}
6ea83fed 350
6af0bf9c 351/* TLB management */
814b9a47
TS		 352void cpu_mips_tlb_flush (CPUState *env, int flush_global)
353{
354 /* Flush qemu's TLB and discard all shadowed entries. */
355 tlb_flush (env, flush_global);
ead9360e 356 env->tlb->tlb_in_use = env->tlb->nb_tlb;
814b9a47
TS		 357}
358
29929e34 359static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
814b9a47
TS		 360{
361 /* Discard entries from env->tlb[first] onwards. */
ead9360e
TS		 362 while (env->tlb->tlb_in_use > first) {
363 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
814b9a47
TS		 364 }
365}
366
29929e34 367static void r4k_fill_tlb (int idx)
6af0bf9c 368{
29929e34 369 r4k_tlb_t *tlb;
6af0bf9c
FB		 370
371 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
ead9360e 372 tlb = &env->tlb->mmu.r4k.tlb[idx];
f2e9ebef 373 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
540635ba 374#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
e034e2c3 375 tlb->VPN &= env->SEGMask;
100ce988 376#endif
98c1b82b 377 tlb->ASID = env->CP0_EntryHi & 0xFF;
3b1c8be4 378 tlb->PageMask = env->CP0_PageMask;
6af0bf9c 379 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
98c1b82b
PB		 380 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
381 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
382 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
6af0bf9c 383 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
98c1b82b
PB		 384 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
385 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
386 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
6af0bf9c
FB		 387 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
388}
389
29929e34 390void r4k_do_tlbwi (void)
6af0bf9c 391{
814b9a47
TS		 392 /* Discard cached TLB entries. We could avoid doing this if the
393 tlbwi is just upgrading access permissions on the current entry;
394 that might be a further win. */
ead9360e 395 r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
814b9a47 396
ead9360e
TS		 397 r4k_invalidate_tlb(env, env->CP0_Index % env->tlb->nb_tlb, 0);
398 r4k_fill_tlb(env->CP0_Index % env->tlb->nb_tlb);
6af0bf9c
FB		 399}
400
29929e34 401void r4k_do_tlbwr (void)
6af0bf9c
FB		 402{
403 int r = cpu_mips_get_random(env);
404
29929e34
TS		 405 r4k_invalidate_tlb(env, r, 1);
406 r4k_fill_tlb(r);
6af0bf9c
FB		 407}
408
29929e34 409void r4k_do_tlbp (void)
6af0bf9c 410{
29929e34 411 r4k_tlb_t *tlb;
f2e9ebef 412 target_ulong mask;
6af0bf9c 413 target_ulong tag;
f2e9ebef 414 target_ulong VPN;
6af0bf9c
FB		 415 uint8_t ASID;
416 int i;
417
3d9fb9fe 418 ASID = env->CP0_EntryHi & 0xFF;
ead9360e
TS		 419 for (i = 0; i < env->tlb->nb_tlb; i++) {
420 tlb = &env->tlb->mmu.r4k.tlb[i];
f2e9ebef
TS		 421 /* 1k pages are not supported. */
422 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
423 tag = env->CP0_EntryHi & ~mask;
424 VPN = tlb->VPN & ~mask;
6af0bf9c 425 /* Check ASID, virtual page number & size */
f2e9ebef 426 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
6af0bf9c 427 /* TLB match */
9c2149c8 428 env->CP0_Index = i;
6af0bf9c
FB		 429 break;
430 }
431 }
ead9360e 432 if (i == env->tlb->nb_tlb) {
814b9a47 433 /* No match. Discard any shadow entries, if any of them match. */
ead9360e
TS		 434 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
435 tlb = &env->tlb->mmu.r4k.tlb[i];
f2e9ebef
TS		 436 /* 1k pages are not supported. */
437 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
438 tag = env->CP0_EntryHi & ~mask;
439 VPN = tlb->VPN & ~mask;
814b9a47 440 /* Check ASID, virtual page number & size */
f2e9ebef 441 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
29929e34 442 r4k_mips_tlb_flush_extra (env, i);
814b9a47
TS		 443 break;
444 }
445 }
446
9c2149c8 447 env->CP0_Index |= 0x80000000;
6af0bf9c
FB		 448 }
449}
450
29929e34 451void r4k_do_tlbr (void)
6af0bf9c 452{
29929e34 453 r4k_tlb_t *tlb;
09c56b84 454 uint8_t ASID;
6af0bf9c 455
09c56b84 456 ASID = env->CP0_EntryHi & 0xFF;
ead9360e 457 tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb];
4ad40f36
FB		 458
459 /* If this will change the current ASID, flush qemu's TLB. */
814b9a47
TS		 460 if (ASID != tlb->ASID)
461 cpu_mips_tlb_flush (env, 1);
462
ead9360e 463 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
4ad40f36 464
6af0bf9c 465 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
3b1c8be4 466 env->CP0_PageMask = tlb->PageMask;
7495fd0f
TS		 467 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
468 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
469 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
470 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
6af0bf9c 471}
6af0bf9c 472
048f6b4d
FB		 473#endif /* !CONFIG_USER_ONLY */
474
c570fd16 475void dump_ldst (const unsigned char *func)
6af0bf9c
FB		 476{
477 if (loglevel)
3594c774 478 fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
6af0bf9c
FB		 479}
480
481void dump_sc (void)
482{
483 if (loglevel) {
3594c774 484 fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
6af0bf9c
FB		 485 T1, T0, env->CP0_LLAddr);
486 }
487}
488
f41c52f1 489void debug_pre_eret (void)
6af0bf9c 490{
f41c52f1 491 fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
ead9360e 492 env->PC[env->current_tc], env->CP0_EPC);
f41c52f1
TS		 493 if (env->CP0_Status & (1 << CP0St_ERL))
494 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
495 if (env->hflags & MIPS_HFLAG_DM)
496 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
497 fputs("\n", logfile);
498}
499
500void debug_post_eret (void)
501{
744e0915 502 fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
ead9360e 503 env->PC[env->current_tc], env->CP0_EPC);
f41c52f1
TS		 504 if (env->CP0_Status & (1 << CP0St_ERL))
505 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
506 if (env->hflags & MIPS_HFLAG_DM)
507 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
508 if (env->hflags & MIPS_HFLAG_UM)
509 fputs(", UM\n", logfile);
510 else
24c7b0e3 511 fputs("\n", logfile);
6af0bf9c
FB		 512}
513
6af0bf9c
FB		 514void do_pmon (int function)
515{
516 function /= 2;
517 switch (function) {
518 case 2: /* TODO: char inbyte(int waitflag); */
ead9360e
TS		 519 if (env->gpr[4][env->current_tc] == 0)
520 env->gpr[2][env->current_tc] = -1;
6af0bf9c
FB		 521 /* Fall through */
522 case 11: /* TODO: char inbyte (void); */
ead9360e 523 env->gpr[2][env->current_tc] = -1;
6af0bf9c
FB		 524 break;
525 case 3:
526 case 12:
ead9360e 527 printf("%c", (char)(env->gpr[4][env->current_tc] & 0xFF));
6af0bf9c
FB		 528 break;
529 case 17:
530 break;
531 case 158:
532 {
ead9360e 533 unsigned char *fmt = (void *)(unsigned long)env->gpr[4][env->current_tc];
6af0bf9c
FB		 534 printf("%s", fmt);
535 }
536 break;
537 }
538}
e37e863f 539
5fafdf24 540#if !defined(CONFIG_USER_ONLY)
e37e863f 541
4ad40f36
FB		 542static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
543
e37e863f 544#define MMUSUFFIX _mmu
4ad40f36 545#define ALIGNED_ONLY
e37e863f
FB		 546
547#define SHIFT 0
548#include "softmmu_template.h"
549
550#define SHIFT 1
551#include "softmmu_template.h"
552
553#define SHIFT 2
554#include "softmmu_template.h"
555
556#define SHIFT 3
557#include "softmmu_template.h"
558
4ad40f36
FB		 559static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
560{
561 env->CP0_BadVAddr = addr;
562 do_restore_state (retaddr);
563 do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
564}
565
6ebbf390 566void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
e37e863f
FB		 567{
568 TranslationBlock *tb;
569 CPUState *saved_env;
570 unsigned long pc;
571 int ret;
572
573 /* XXX: hack to restore env in all cases, even if not called from
574 generated code */
575 saved_env = env;
576 env = cpu_single_env;
6ebbf390 577 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
e37e863f
FB		 578 if (ret) {
579 if (retaddr) {
580 /* now we have a real cpu fault */
581 pc = (unsigned long)retaddr;
582 tb = tb_find_pc(pc);
583 if (tb) {
584 /* the PC is inside the translated code. It means that we have
585 a virtual CPU fault */
586 cpu_restore_state(tb, env, pc, NULL);
587 }
588 }
589 do_raise_exception_err(env->exception_index, env->error_code);
590 }
591 env = saved_env;
592}
593
594#endif
fd4a04eb
TS		 595
596/* Complex FPU operations which may need stack space. */
597
8dfdb87c
TS		 598#define FLOAT_SIGN32 (1 << 31)
599#define FLOAT_SIGN64 (1ULL << 63)
600#define FLOAT_ONE32 (0x3f8 << 20)
601#define FLOAT_ONE64 (0x3ffULL << 52)
602#define FLOAT_TWO32 (1 << 30)
603#define FLOAT_TWO64 (1ULL << 62)
54454097
TS		 604#define FLOAT_QNAN32 0x7fbfffff
605#define FLOAT_QNAN64 0x7ff7ffffffffffffULL
606#define FLOAT_SNAN32 0x7fffffff
607#define FLOAT_SNAN64 0x7fffffffffffffffULL
8dfdb87c 608
fd4a04eb
TS		 609/* convert MIPS rounding mode in FCR31 to IEEE library */
610unsigned int ieee_rm[] = {
611 float_round_nearest_even,
612 float_round_to_zero,
613 float_round_up,
614 float_round_down
615};
616
617#define RESTORE_ROUNDING_MODE \
ead9360e 618 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
fd4a04eb 619
ead9360e 620void do_cfc1 (int reg)
fd4a04eb 621{
ead9360e
TS		 622 switch (reg) {
623 case 0:
624 T0 = (int32_t)env->fpu->fcr0;
625 break;
626 case 25:
627 T0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1);
628 break;
629 case 26:
630 T0 = env->fpu->fcr31 & 0x0003f07c;
631 break;
632 case 28:
633 T0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4);
634 break;
635 default:
636 T0 = (int32_t)env->fpu->fcr31;
637 break;
638 }
639}
640
641void do_ctc1 (int reg)
642{
643 switch(reg) {
fd4a04eb
TS		 644 case 25:
645 if (T0 & 0xffffff00)
646 return;
ead9360e 647 env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) |
fd4a04eb
TS		 648 ((T0 & 0x1) << 23);
649 break;
650 case 26:
651 if (T0 & 0x007c0000)
652 return;
ead9360e 653 env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c);
fd4a04eb
TS		 654 break;
655 case 28:
656 if (T0 & 0x007c0000)
657 return;
ead9360e 658 env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) |
fd4a04eb
TS		 659 ((T0 & 0x4) << 22);
660 break;
661 case 31:
662 if (T0 & 0x007c0000)
663 return;
ead9360e 664 env->fpu->fcr31 = T0;
fd4a04eb
TS		 665 break;
666 default:
667 return;
668 }
669 /* set rounding mode */
670 RESTORE_ROUNDING_MODE;
ead9360e
TS		 671 set_float_exception_flags(0, &env->fpu->fp_status);
672 if ((GET_FP_ENABLE(env->fpu->fcr31) | 0x20) & GET_FP_CAUSE(env->fpu->fcr31))
fd4a04eb
TS		 673 do_raise_exception(EXCP_FPE);
674}
675
aa343735 676static always_inline char ieee_ex_to_mips(char xcpt)
fd4a04eb
TS		 677{
678 return (xcpt & float_flag_inexact) >> 5 |
679 (xcpt & float_flag_underflow) >> 3 |
680 (xcpt & float_flag_overflow) >> 1 |
681 (xcpt & float_flag_divbyzero) << 1 |
682 (xcpt & float_flag_invalid) << 4;
683}
684
aa343735 685static always_inline char mips_ex_to_ieee(char xcpt)
fd4a04eb
TS		 686{
687 return (xcpt & FP_INEXACT) << 5 |
688 (xcpt & FP_UNDERFLOW) << 3 |
689 (xcpt & FP_OVERFLOW) << 1 |
690 (xcpt & FP_DIV0) >> 1 |
691 (xcpt & FP_INVALID) >> 4;
692}
693
aa343735 694static always_inline void update_fcr31(void)
fd4a04eb 695{
ead9360e 696 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status));
fd4a04eb 697
ead9360e
TS		 698 SET_FP_CAUSE(env->fpu->fcr31, tmp);
699 if (GET_FP_ENABLE(env->fpu->fcr31) & tmp)
fd4a04eb
TS		 700 do_raise_exception(EXCP_FPE);
701 else
ead9360e 702 UPDATE_FP_FLAGS(env->fpu->fcr31, tmp);
fd4a04eb
TS		 703}
704
705#define FLOAT_OP(name, p) void do_float_##name##_##p(void)
706
707FLOAT_OP(cvtd, s)
708{
ead9360e
TS		 709 set_float_exception_flags(0, &env->fpu->fp_status);
710 FDT2 = float32_to_float64(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 711 update_fcr31();
712}
713FLOAT_OP(cvtd, w)
714{
ead9360e
TS		 715 set_float_exception_flags(0, &env->fpu->fp_status);
716 FDT2 = int32_to_float64(WT0, &env->fpu->fp_status);
fd4a04eb
TS		 717 update_fcr31();
718}
719FLOAT_OP(cvtd, l)
720{
ead9360e
TS		 721 set_float_exception_flags(0, &env->fpu->fp_status);
722 FDT2 = int64_to_float64(DT0, &env->fpu->fp_status);
fd4a04eb
TS		 723 update_fcr31();
724}
725FLOAT_OP(cvtl, d)
726{
ead9360e
TS		 727 set_float_exception_flags(0, &env->fpu->fp_status);
728 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
fd4a04eb 729 update_fcr31();
ead9360e 730 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 731 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 732}
733FLOAT_OP(cvtl, s)
734{
ead9360e
TS		 735 set_float_exception_flags(0, &env->fpu->fp_status);
736 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
fd4a04eb 737 update_fcr31();
ead9360e 738 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 739 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 740}
741
742FLOAT_OP(cvtps, pw)
743{
ead9360e
TS		 744 set_float_exception_flags(0, &env->fpu->fp_status);
745 FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
746 FSTH2 = int32_to_float32(WTH0, &env->fpu->fp_status);
fd4a04eb
TS		 747 update_fcr31();
748}
749FLOAT_OP(cvtpw, ps)
750{
ead9360e
TS		 751 set_float_exception_flags(0, &env->fpu->fp_status);
752 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
753 WTH2 = float32_to_int32(FSTH0, &env->fpu->fp_status);
fd4a04eb 754 update_fcr31();
ead9360e 755 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 756 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 757}
758FLOAT_OP(cvts, d)
759{
ead9360e
TS		 760 set_float_exception_flags(0, &env->fpu->fp_status);
761 FST2 = float64_to_float32(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 762 update_fcr31();
763}
764FLOAT_OP(cvts, w)
765{
ead9360e
TS		 766 set_float_exception_flags(0, &env->fpu->fp_status);
767 FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
fd4a04eb
TS		 768 update_fcr31();
769}
770FLOAT_OP(cvts, l)
771{
ead9360e
TS		 772 set_float_exception_flags(0, &env->fpu->fp_status);
773 FST2 = int64_to_float32(DT0, &env->fpu->fp_status);
fd4a04eb
TS		 774 update_fcr31();
775}
776FLOAT_OP(cvts, pl)
777{
ead9360e 778 set_float_exception_flags(0, &env->fpu->fp_status);
fd4a04eb
TS		 779 WT2 = WT0;
780 update_fcr31();
781}
782FLOAT_OP(cvts, pu)
783{
ead9360e 784 set_float_exception_flags(0, &env->fpu->fp_status);
fd4a04eb
TS		 785 WT2 = WTH0;
786 update_fcr31();
787}
788FLOAT_OP(cvtw, s)
789{
ead9360e
TS		 790 set_float_exception_flags(0, &env->fpu->fp_status);
791 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
fd4a04eb 792 update_fcr31();
ead9360e 793 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 794 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 795}
796FLOAT_OP(cvtw, d)
797{
ead9360e
TS		 798 set_float_exception_flags(0, &env->fpu->fp_status);
799 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
fd4a04eb 800 update_fcr31();
ead9360e 801 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 802 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 803}
804
805FLOAT_OP(roundl, d)
806{
ead9360e
TS		 807 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
808 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 809 RESTORE_ROUNDING_MODE;
810 update_fcr31();
ead9360e 811 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 812 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 813}
814FLOAT_OP(roundl, s)
815{
ead9360e
TS		 816 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
817 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 818 RESTORE_ROUNDING_MODE;
819 update_fcr31();
ead9360e 820 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 821 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 822}
823FLOAT_OP(roundw, d)
824{
ead9360e
TS		 825 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
826 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 827 RESTORE_ROUNDING_MODE;
828 update_fcr31();
ead9360e 829 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 830 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 831}
832FLOAT_OP(roundw, s)
833{
ead9360e
TS		 834 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
835 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 836 RESTORE_ROUNDING_MODE;
837 update_fcr31();
ead9360e 838 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 839 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 840}
841
842FLOAT_OP(truncl, d)
843{
ead9360e 844 DT2 = float64_to_int64_round_to_zero(FDT0, &env->fpu->fp_status);
fd4a04eb 845 update_fcr31();
ead9360e 846 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 847 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 848}
849FLOAT_OP(truncl, s)
850{
ead9360e 851 DT2 = float32_to_int64_round_to_zero(FST0, &env->fpu->fp_status);
fd4a04eb 852 update_fcr31();
ead9360e 853 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 854 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 855}
856FLOAT_OP(truncw, d)
857{
ead9360e 858 WT2 = float64_to_int32_round_to_zero(FDT0, &env->fpu->fp_status);
fd4a04eb 859 update_fcr31();
ead9360e 860 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 861 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 862}
863FLOAT_OP(truncw, s)
864{
ead9360e 865 WT2 = float32_to_int32_round_to_zero(FST0, &env->fpu->fp_status);
fd4a04eb 866 update_fcr31();
ead9360e 867 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 868 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 869}
870
871FLOAT_OP(ceill, d)
872{
ead9360e
TS		 873 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
874 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 875 RESTORE_ROUNDING_MODE;
876 update_fcr31();
ead9360e 877 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 878 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 879}
880FLOAT_OP(ceill, s)
881{
ead9360e
TS		 882 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
883 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 884 RESTORE_ROUNDING_MODE;
885 update_fcr31();
ead9360e 886 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 887 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 888}
889FLOAT_OP(ceilw, d)
890{
ead9360e
TS		 891 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
892 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 893 RESTORE_ROUNDING_MODE;
894 update_fcr31();
ead9360e 895 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 896 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 897}
898FLOAT_OP(ceilw, s)
899{
ead9360e
TS		 900 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
901 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 902 RESTORE_ROUNDING_MODE;
903 update_fcr31();
ead9360e 904 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 905 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 906}
907
908FLOAT_OP(floorl, d)
909{
ead9360e
TS		 910 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
911 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 912 RESTORE_ROUNDING_MODE;
913 update_fcr31();
ead9360e 914 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 915 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 916}
917FLOAT_OP(floorl, s)
918{
ead9360e
TS		 919 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
920 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 921 RESTORE_ROUNDING_MODE;
922 update_fcr31();
ead9360e 923 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 924 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 925}
926FLOAT_OP(floorw, d)
927{
ead9360e
TS		 928 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
929 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 930 RESTORE_ROUNDING_MODE;
931 update_fcr31();
ead9360e 932 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 933 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 934}
935FLOAT_OP(floorw, s)
936{
ead9360e
TS		 937 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
938 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 939 RESTORE_ROUNDING_MODE;
940 update_fcr31();
ead9360e 941 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 942 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 943}
944
8dfdb87c
TS		 945/* MIPS specific unary operations */
946FLOAT_OP(recip, d)
947{
ead9360e
TS		 948 set_float_exception_flags(0, &env->fpu->fp_status);
949 FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
8dfdb87c
TS		 950 update_fcr31();
951}
952FLOAT_OP(recip, s)
953{
ead9360e
TS		 954 set_float_exception_flags(0, &env->fpu->fp_status);
955 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
8dfdb87c 956 update_fcr31();
57fa1fb3 957}
57fa1fb3 958
8dfdb87c
TS		 959FLOAT_OP(rsqrt, d)
960{
ead9360e
TS		 961 set_float_exception_flags(0, &env->fpu->fp_status);
962 FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
963 FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
8dfdb87c
TS		 964 update_fcr31();
965}
966FLOAT_OP(rsqrt, s)
967{
ead9360e
TS		 968 set_float_exception_flags(0, &env->fpu->fp_status);
969 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
970 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
8dfdb87c
TS		 971 update_fcr31();
972}
973
974FLOAT_OP(recip1, d)
975{
ead9360e
TS		 976 set_float_exception_flags(0, &env->fpu->fp_status);
977 FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
8dfdb87c
TS		 978 update_fcr31();
979}
980FLOAT_OP(recip1, s)
981{
ead9360e
TS		 982 set_float_exception_flags(0, &env->fpu->fp_status);
983 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
8dfdb87c
TS		 984 update_fcr31();
985}
986FLOAT_OP(recip1, ps)
987{
ead9360e
TS		 988 set_float_exception_flags(0, &env->fpu->fp_status);
989 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
990 FSTH2 = float32_div(FLOAT_ONE32, FSTH0, &env->fpu->fp_status);
8dfdb87c
TS		 991 update_fcr31();
992}
993
994FLOAT_OP(rsqrt1, d)
995{
ead9360e
TS		 996 set_float_exception_flags(0, &env->fpu->fp_status);
997 FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
998 FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
8dfdb87c
TS		 999 update_fcr31();
1000}
1001FLOAT_OP(rsqrt1, s)
1002{
ead9360e
TS		 1003 set_float_exception_flags(0, &env->fpu->fp_status);
1004 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1005 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
8dfdb87c
TS		 1006 update_fcr31();
1007}
1008FLOAT_OP(rsqrt1, ps)
1009{
ead9360e
TS		 1010 set_float_exception_flags(0, &env->fpu->fp_status);
1011 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1012 FSTH2 = float32_sqrt(FSTH0, &env->fpu->fp_status);
1013 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
1014 FSTH2 = float32_div(FLOAT_ONE32, FSTH2, &env->fpu->fp_status);
8dfdb87c 1015 update_fcr31();
57fa1fb3 1016}
57fa1fb3 1017
fd4a04eb
TS		 1018/* binary operations */
1019#define FLOAT_BINOP(name) \
1020FLOAT_OP(name, d) \
1021{ \
ead9360e
TS		 1022 set_float_exception_flags(0, &env->fpu->fp_status); \
1023 FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \
1024 update_fcr31(); \
1025 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
54454097 1026 FDT2 = FLOAT_QNAN64; \
fd4a04eb
TS		 1027} \
1028FLOAT_OP(name, s) \
1029{ \
ead9360e
TS		 1030 set_float_exception_flags(0, &env->fpu->fp_status); \
1031 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
1032 update_fcr31(); \
1033 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
54454097 1034 FST2 = FLOAT_QNAN32; \
fd4a04eb
TS		 1035} \
1036FLOAT_OP(name, ps) \
1037{ \
ead9360e
TS		 1038 set_float_exception_flags(0, &env->fpu->fp_status); \
1039 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
1040 FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \
fd4a04eb 1041 update_fcr31(); \
ead9360e 1042 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
54454097
TS		 1043 FST2 = FLOAT_QNAN32; \
1044 FSTH2 = FLOAT_QNAN32; \
3a5b360d 1045 } \
fd4a04eb
TS		 1046}
1047FLOAT_BINOP(add)
1048FLOAT_BINOP(sub)
1049FLOAT_BINOP(mul)
1050FLOAT_BINOP(div)
1051#undef FLOAT_BINOP
1052
8dfdb87c
TS		 1053/* MIPS specific binary operations */
1054FLOAT_OP(recip2, d)
1055{
ead9360e
TS		 1056 set_float_exception_flags(0, &env->fpu->fp_status);
1057 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
1058 FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status) ^ FLOAT_SIGN64;
8dfdb87c
TS		 1059 update_fcr31();
1060}
1061FLOAT_OP(recip2, s)
1062{
ead9360e
TS		 1063 set_float_exception_flags(0, &env->fpu->fp_status);
1064 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1065 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
8dfdb87c
TS		 1066 update_fcr31();
1067}
1068FLOAT_OP(recip2, ps)
1069{
ead9360e
TS		 1070 set_float_exception_flags(0, &env->fpu->fp_status);
1071 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1072 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
1073 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
1074 FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
8dfdb87c
TS		 1075 update_fcr31();
1076}
1077
1078FLOAT_OP(rsqrt2, d)
1079{
ead9360e
TS		 1080 set_float_exception_flags(0, &env->fpu->fp_status);
1081 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
1082 FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status);
1083 FDT2 = float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status) ^ FLOAT_SIGN64;
8dfdb87c
TS		 1084 update_fcr31();
1085}
1086FLOAT_OP(rsqrt2, s)
1087{
ead9360e
TS		 1088 set_float_exception_flags(0, &env->fpu->fp_status);
1089 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1090 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
1091 FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
8dfdb87c
TS		 1092 update_fcr31();
1093}
1094FLOAT_OP(rsqrt2, ps)
1095{
ead9360e
TS		 1096 set_float_exception_flags(0, &env->fpu->fp_status);
1097 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1098 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
1099 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
1100 FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status);
1101 FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
1102 FSTH2 = float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
8dfdb87c 1103 update_fcr31();
57fa1fb3 1104}
57fa1fb3 1105
fd4a04eb
TS		 1106FLOAT_OP(addr, ps)
1107{
ead9360e
TS		 1108 set_float_exception_flags(0, &env->fpu->fp_status);
1109 FST2 = float32_add (FST0, FSTH0, &env->fpu->fp_status);
1110 FSTH2 = float32_add (FST1, FSTH1, &env->fpu->fp_status);
fd4a04eb
TS		 1111 update_fcr31();
1112}
1113
57fa1fb3
TS		 1114FLOAT_OP(mulr, ps)
1115{
ead9360e
TS		 1116 set_float_exception_flags(0, &env->fpu->fp_status);
1117 FST2 = float32_mul (FST0, FSTH0, &env->fpu->fp_status);
1118 FSTH2 = float32_mul (FST1, FSTH1, &env->fpu->fp_status);
57fa1fb3
TS		 1119 update_fcr31();
1120}
1121
8dfdb87c 1122/* compare operations */
fd4a04eb
TS		 1123#define FOP_COND_D(op, cond) \
1124void do_cmp_d_ ## op (long cc) \
1125{ \
1126 int c = cond; \
1127 update_fcr31(); \
1128 if (c) \
ead9360e 1129 SET_FP_COND(cc, env->fpu); \
fd4a04eb 1130 else \
ead9360e 1131 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb
TS		 1132} \
1133void do_cmpabs_d_ ## op (long cc) \
1134{ \
1135 int c; \
8dfdb87c
TS		 1136 FDT0 &= ~FLOAT_SIGN64; \
1137 FDT1 &= ~FLOAT_SIGN64; \
fd4a04eb
TS		 1138 c = cond; \
1139 update_fcr31(); \
1140 if (c) \
ead9360e 1141 SET_FP_COND(cc, env->fpu); \
fd4a04eb 1142 else \
ead9360e 1143 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb
TS		 1144}
1145
1146int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
1147{
1148 if (float64_is_signaling_nan(a) ||
1149 float64_is_signaling_nan(b) ||
1150 (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
1151 float_raise(float_flag_invalid, status);
1152 return 1;
1153 } else if (float64_is_nan(a) || float64_is_nan(b)) {
1154 return 1;
1155 } else {
1156 return 0;
1157 }
1158}
1159
1160/* NOTE: the comma operator will make "cond" to eval to false,
1161 * but float*_is_unordered() is still called. */
ead9360e
TS		 1162FOP_COND_D(f, (float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status), 0))
1163FOP_COND_D(un, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status))
1164FOP_COND_D(eq, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1165FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1166FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1167FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1168FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
1169FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
fd4a04eb
TS		 1170/* NOTE: the comma operator will make "cond" to eval to false,
1171 * but float*_is_unordered() is still called. */
ead9360e
TS		 1172FOP_COND_D(sf, (float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status), 0))
1173FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status))
1174FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1175FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1176FOP_COND_D(lt, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1177FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1178FOP_COND_D(le, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
1179FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
fd4a04eb
TS		 1180
1181#define FOP_COND_S(op, cond) \
1182void do_cmp_s_ ## op (long cc) \
1183{ \
1184 int c = cond; \
1185 update_fcr31(); \
1186 if (c) \
ead9360e 1187 SET_FP_COND(cc, env->fpu); \
fd4a04eb 1188 else \
ead9360e 1189 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb
TS		 1190} \
1191void do_cmpabs_s_ ## op (long cc) \
1192{ \
1193 int c; \
8dfdb87c
TS		 1194 FST0 &= ~FLOAT_SIGN32; \
1195 FST1 &= ~FLOAT_SIGN32; \
fd4a04eb
TS		 1196 c = cond; \
1197 update_fcr31(); \
1198 if (c) \
ead9360e 1199 SET_FP_COND(cc, env->fpu); \
fd4a04eb 1200 else \
ead9360e 1201 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb
TS		 1202}
1203
1204flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
1205{
fd4a04eb
TS		 1206 if (float32_is_signaling_nan(a) ||
1207 float32_is_signaling_nan(b) ||
1208 (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
1209 float_raise(float_flag_invalid, status);
1210 return 1;
1211 } else if (float32_is_nan(a) || float32_is_nan(b)) {
1212 return 1;
1213 } else {
1214 return 0;
1215 }
1216}
1217
1218/* NOTE: the comma operator will make "cond" to eval to false,
1219 * but float*_is_unordered() is still called. */
ead9360e
TS		 1220FOP_COND_S(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0))
1221FOP_COND_S(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status))
1222FOP_COND_S(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
1223FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
1224FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
1225FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
1226FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
1227FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
fd4a04eb
TS		 1228/* NOTE: the comma operator will make "cond" to eval to false,
1229 * but float*_is_unordered() is still called. */
ead9360e
TS		 1230FOP_COND_S(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0))
1231FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status))
1232FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
1233FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
1234FOP_COND_S(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
1235FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
1236FOP_COND_S(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
1237FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
fd4a04eb
TS		 1238
1239#define FOP_COND_PS(op, condl, condh) \
1240void do_cmp_ps_ ## op (long cc) \
1241{ \
1242 int cl = condl; \
1243 int ch = condh; \
1244 update_fcr31(); \
1245 if (cl) \
ead9360e 1246 SET_FP_COND(cc, env->fpu); \
fd4a04eb 1247 else \
ead9360e 1248 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb 1249 if (ch) \
ead9360e 1250 SET_FP_COND(cc + 1, env->fpu); \
fd4a04eb 1251 else \
ead9360e 1252 CLEAR_FP_COND(cc + 1, env->fpu); \
fd4a04eb
TS		 1253} \
1254void do_cmpabs_ps_ ## op (long cc) \
1255{ \
1256 int cl, ch; \
8dfdb87c
TS		 1257 FST0 &= ~FLOAT_SIGN32; \
1258 FSTH0 &= ~FLOAT_SIGN32; \
1259 FST1 &= ~FLOAT_SIGN32; \
1260 FSTH1 &= ~FLOAT_SIGN32; \
fd4a04eb
TS		 1261 cl = condl; \
1262 ch = condh; \
1263 update_fcr31(); \
1264 if (cl) \
ead9360e 1265 SET_FP_COND(cc, env->fpu); \
fd4a04eb 1266 else \
ead9360e 1267 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb 1268 if (ch) \
ead9360e 1269 SET_FP_COND(cc + 1, env->fpu); \
fd4a04eb 1270 else \
ead9360e 1271 CLEAR_FP_COND(cc + 1, env->fpu); \
fd4a04eb
TS		 1272}
1273
1274/* NOTE: the comma operator will make "cond" to eval to false,
1275 * but float*_is_unordered() is still called. */
ead9360e
TS		 1276FOP_COND_PS(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0),
1277 (float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status), 0))
1278FOP_COND_PS(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status),
1279 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status))
1280FOP_COND_PS(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
1281 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1282FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
1283 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1284FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
1285 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1286FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
1287 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1288FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
1289 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1290FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
1291 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
fd4a04eb
TS		 1292/* NOTE: the comma operator will make "cond" to eval to false,
1293 * but float*_is_unordered() is still called. */
ead9360e
TS		 1294FOP_COND_PS(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0),
1295 (float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status), 0))
1296FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status),
1297 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status))
1298FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
1299 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1300FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
1301 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1302FOP_COND_PS(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
1303 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1304FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
1305 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1306FOP_COND_PS(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
1307 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1308FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
1309 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
Qemu copy for testing