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Commit | Line | Data |
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6af0bf9c FB |
1 | /* |
2 | * MIPS emulation helpers for qemu. | |
5fafdf24 | 3 | * |
6af0bf9c FB |
4 | * Copyright (c) 2004-2005 Jocelyn Mayer |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
6af0bf9c | 18 | */ |
2d0e944d | 19 | #include <stdlib.h> |
3e457172 | 20 | #include "cpu.h" |
1de7afc9 | 21 | #include "qemu/host-utils.h" |
05f778c8 | 22 | |
a7812ae4 | 23 | #include "helper.h" |
83dae095 | 24 | |
3e457172 | 25 | #if !defined(CONFIG_USER_ONLY) |
022c62cb | 26 | #include "exec/softmmu_exec.h" |
3e457172 BS |
27 | #endif /* !defined(CONFIG_USER_ONLY) */ |
28 | ||
83dae095 | 29 | #ifndef CONFIG_USER_ONLY |
7db13fae | 30 | static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global); |
83dae095 PB |
31 | #endif |
32 | ||
6af0bf9c FB |
33 | /*****************************************************************************/ |
34 | /* Exceptions processing helpers */ | |
6af0bf9c | 35 | |
5f7319cd AJ |
36 | static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, |
37 | uint32_t exception, | |
38 | int error_code, | |
39 | uintptr_t pc) | |
6af0bf9c | 40 | { |
0f0b9398 | 41 | if (exception < EXCP_SC) { |
93fcfe39 | 42 | qemu_log("%s: %d %d\n", __func__, exception, error_code); |
0f0b9398 | 43 | } |
6af0bf9c FB |
44 | env->exception_index = exception; |
45 | env->error_code = error_code; | |
5f7319cd AJ |
46 | |
47 | if (pc) { | |
48 | /* now we have a real cpu fault */ | |
a8a826a3 | 49 | cpu_restore_state(env, pc); |
5f7319cd AJ |
50 | } |
51 | ||
1162c041 | 52 | cpu_loop_exit(env); |
6af0bf9c FB |
53 | } |
54 | ||
5f7319cd AJ |
55 | static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, |
56 | uint32_t exception, | |
57 | uintptr_t pc) | |
6af0bf9c | 58 | { |
5f7319cd | 59 | do_raise_exception_err(env, exception, 0, pc); |
6af0bf9c FB |
60 | } |
61 | ||
5f7319cd AJ |
62 | void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception, |
63 | int error_code) | |
4ad40f36 | 64 | { |
5f7319cd AJ |
65 | do_raise_exception_err(env, exception, error_code, 0); |
66 | } | |
20503968 | 67 | |
5f7319cd AJ |
68 | void helper_raise_exception(CPUMIPSState *env, uint32_t exception) |
69 | { | |
70 | do_raise_exception(env, exception, 0); | |
4ad40f36 FB |
71 | } |
72 | ||
0ae43045 AJ |
73 | #if defined(CONFIG_USER_ONLY) |
74 | #define HELPER_LD(name, insn, type) \ | |
895c2d04 BS |
75 | static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ |
76 | int mem_idx) \ | |
0ae43045 AJ |
77 | { \ |
78 | return (type) insn##_raw(addr); \ | |
79 | } | |
80 | #else | |
81 | #define HELPER_LD(name, insn, type) \ | |
895c2d04 BS |
82 | static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ |
83 | int mem_idx) \ | |
0ae43045 AJ |
84 | { \ |
85 | switch (mem_idx) \ | |
86 | { \ | |
895c2d04 BS |
87 | case 0: return (type) cpu_##insn##_kernel(env, addr); break; \ |
88 | case 1: return (type) cpu_##insn##_super(env, addr); break; \ | |
0ae43045 | 89 | default: \ |
895c2d04 | 90 | case 2: return (type) cpu_##insn##_user(env, addr); break; \ |
0ae43045 AJ |
91 | } \ |
92 | } | |
93 | #endif | |
94 | HELPER_LD(lbu, ldub, uint8_t) | |
95 | HELPER_LD(lw, ldl, int32_t) | |
96 | #ifdef TARGET_MIPS64 | |
97 | HELPER_LD(ld, ldq, int64_t) | |
98 | #endif | |
99 | #undef HELPER_LD | |
100 | ||
101 | #if defined(CONFIG_USER_ONLY) | |
102 | #define HELPER_ST(name, insn, type) \ | |
895c2d04 BS |
103 | static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ |
104 | type val, int mem_idx) \ | |
0ae43045 AJ |
105 | { \ |
106 | insn##_raw(addr, val); \ | |
107 | } | |
108 | #else | |
109 | #define HELPER_ST(name, insn, type) \ | |
895c2d04 BS |
110 | static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ |
111 | type val, int mem_idx) \ | |
0ae43045 AJ |
112 | { \ |
113 | switch (mem_idx) \ | |
114 | { \ | |
895c2d04 BS |
115 | case 0: cpu_##insn##_kernel(env, addr, val); break; \ |
116 | case 1: cpu_##insn##_super(env, addr, val); break; \ | |
0ae43045 | 117 | default: \ |
895c2d04 | 118 | case 2: cpu_##insn##_user(env, addr, val); break; \ |
0ae43045 AJ |
119 | } \ |
120 | } | |
121 | #endif | |
122 | HELPER_ST(sb, stb, uint8_t) | |
123 | HELPER_ST(sw, stl, uint32_t) | |
124 | #ifdef TARGET_MIPS64 | |
125 | HELPER_ST(sd, stq, uint64_t) | |
126 | #endif | |
127 | #undef HELPER_ST | |
128 | ||
d9bea114 | 129 | target_ulong helper_clo (target_ulong arg1) |
30898801 | 130 | { |
d9bea114 | 131 | return clo32(arg1); |
30898801 TS |
132 | } |
133 | ||
d9bea114 | 134 | target_ulong helper_clz (target_ulong arg1) |
30898801 | 135 | { |
d9bea114 | 136 | return clz32(arg1); |
30898801 TS |
137 | } |
138 | ||
d26bc211 | 139 | #if defined(TARGET_MIPS64) |
d9bea114 | 140 | target_ulong helper_dclo (target_ulong arg1) |
05f778c8 | 141 | { |
d9bea114 | 142 | return clo64(arg1); |
05f778c8 TS |
143 | } |
144 | ||
d9bea114 | 145 | target_ulong helper_dclz (target_ulong arg1) |
05f778c8 | 146 | { |
d9bea114 | 147 | return clz64(arg1); |
05f778c8 | 148 | } |
d26bc211 | 149 | #endif /* TARGET_MIPS64 */ |
c570fd16 | 150 | |
6af0bf9c | 151 | /* 64 bits arithmetic for 32 bits hosts */ |
895c2d04 | 152 | static inline uint64_t get_HILO(CPUMIPSState *env) |
6af0bf9c | 153 | { |
b5dc7732 | 154 | return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0]; |
6af0bf9c FB |
155 | } |
156 | ||
895c2d04 | 157 | static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO) |
e9c71dd1 | 158 | { |
6fc97faf | 159 | target_ulong tmp; |
b5dc7732 | 160 | env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); |
6fc97faf SW |
161 | tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32); |
162 | return tmp; | |
e9c71dd1 TS |
163 | } |
164 | ||
895c2d04 | 165 | static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO) |
e9c71dd1 | 166 | { |
6fc97faf | 167 | target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); |
b5dc7732 | 168 | env->active_tc.HI[0] = (int32_t)(HILO >> 32); |
6fc97faf | 169 | return tmp; |
e9c71dd1 TS |
170 | } |
171 | ||
e9c71dd1 | 172 | /* Multiplication variants of the vr54xx. */ |
895c2d04 BS |
173 | target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1, |
174 | target_ulong arg2) | |
e9c71dd1 | 175 | { |
895c2d04 BS |
176 | return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 * |
177 | (int64_t)(int32_t)arg2)); | |
e9c71dd1 TS |
178 | } |
179 | ||
895c2d04 BS |
180 | target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1, |
181 | target_ulong arg2) | |
e9c71dd1 | 182 | { |
895c2d04 BS |
183 | return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 * |
184 | (uint64_t)(uint32_t)arg2); | |
e9c71dd1 TS |
185 | } |
186 | ||
895c2d04 BS |
187 | target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1, |
188 | target_ulong arg2) | |
e9c71dd1 | 189 | { |
895c2d04 BS |
190 | return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 * |
191 | (int64_t)(int32_t)arg2); | |
e9c71dd1 TS |
192 | } |
193 | ||
895c2d04 BS |
194 | target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1, |
195 | target_ulong arg2) | |
e9c71dd1 | 196 | { |
895c2d04 BS |
197 | return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 * |
198 | (int64_t)(int32_t)arg2); | |
e9c71dd1 TS |
199 | } |
200 | ||
895c2d04 BS |
201 | target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1, |
202 | target_ulong arg2) | |
e9c71dd1 | 203 | { |
895c2d04 BS |
204 | return set_HI_LOT0(env, (uint64_t)get_HILO(env) + |
205 | (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); | |
e9c71dd1 TS |
206 | } |
207 | ||
895c2d04 BS |
208 | target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1, |
209 | target_ulong arg2) | |
e9c71dd1 | 210 | { |
895c2d04 BS |
211 | return set_HIT0_LO(env, (uint64_t)get_HILO(env) + |
212 | (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); | |
e9c71dd1 TS |
213 | } |
214 | ||
895c2d04 BS |
215 | target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1, |
216 | target_ulong arg2) | |
e9c71dd1 | 217 | { |
895c2d04 BS |
218 | return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 * |
219 | (int64_t)(int32_t)arg2); | |
e9c71dd1 TS |
220 | } |
221 | ||
895c2d04 BS |
222 | target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1, |
223 | target_ulong arg2) | |
e9c71dd1 | 224 | { |
895c2d04 BS |
225 | return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 * |
226 | (int64_t)(int32_t)arg2); | |
e9c71dd1 TS |
227 | } |
228 | ||
895c2d04 BS |
229 | target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1, |
230 | target_ulong arg2) | |
e9c71dd1 | 231 | { |
895c2d04 BS |
232 | return set_HI_LOT0(env, (uint64_t)get_HILO(env) - |
233 | (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); | |
e9c71dd1 TS |
234 | } |
235 | ||
895c2d04 BS |
236 | target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1, |
237 | target_ulong arg2) | |
e9c71dd1 | 238 | { |
895c2d04 BS |
239 | return set_HIT0_LO(env, (uint64_t)get_HILO(env) - |
240 | (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); | |
e9c71dd1 TS |
241 | } |
242 | ||
895c2d04 BS |
243 | target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1, |
244 | target_ulong arg2) | |
e9c71dd1 | 245 | { |
895c2d04 | 246 | return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2); |
e9c71dd1 TS |
247 | } |
248 | ||
895c2d04 BS |
249 | target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1, |
250 | target_ulong arg2) | |
e9c71dd1 | 251 | { |
895c2d04 BS |
252 | return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 * |
253 | (uint64_t)(uint32_t)arg2); | |
e9c71dd1 TS |
254 | } |
255 | ||
895c2d04 BS |
256 | target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1, |
257 | target_ulong arg2) | |
e9c71dd1 | 258 | { |
895c2d04 BS |
259 | return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 * |
260 | (int64_t)(int32_t)arg2); | |
e9c71dd1 TS |
261 | } |
262 | ||
895c2d04 BS |
263 | target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1, |
264 | target_ulong arg2) | |
e9c71dd1 | 265 | { |
895c2d04 BS |
266 | return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 * |
267 | (uint64_t)(uint32_t)arg2); | |
e9c71dd1 | 268 | } |
6af0bf9c | 269 | |
214c465f | 270 | #ifdef TARGET_MIPS64 |
895c2d04 | 271 | void helper_dmult(CPUMIPSState *env, target_ulong arg1, target_ulong arg2) |
214c465f | 272 | { |
d9bea114 | 273 | muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2); |
214c465f TS |
274 | } |
275 | ||
895c2d04 | 276 | void helper_dmultu(CPUMIPSState *env, target_ulong arg1, target_ulong arg2) |
214c465f | 277 | { |
d9bea114 | 278 | mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2); |
214c465f TS |
279 | } |
280 | #endif | |
281 | ||
e7139c44 | 282 | #ifndef CONFIG_USER_ONLY |
c36bbb28 | 283 | |
a8170e5e | 284 | static inline hwaddr do_translate_address(CPUMIPSState *env, |
895c2d04 BS |
285 | target_ulong address, |
286 | int rw) | |
c36bbb28 | 287 | { |
a8170e5e | 288 | hwaddr lladdr; |
c36bbb28 AJ |
289 | |
290 | lladdr = cpu_mips_translate_address(env, address, rw); | |
291 | ||
292 | if (lladdr == -1LL) { | |
1162c041 | 293 | cpu_loop_exit(env); |
c36bbb28 AJ |
294 | } else { |
295 | return lladdr; | |
296 | } | |
297 | } | |
298 | ||
e7139c44 | 299 | #define HELPER_LD_ATOMIC(name, insn) \ |
895c2d04 | 300 | target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \ |
e7139c44 | 301 | { \ |
895c2d04 BS |
302 | env->lladdr = do_translate_address(env, arg, 0); \ |
303 | env->llval = do_##insn(env, arg, mem_idx); \ | |
e7139c44 AJ |
304 | return env->llval; \ |
305 | } | |
306 | HELPER_LD_ATOMIC(ll, lw) | |
307 | #ifdef TARGET_MIPS64 | |
308 | HELPER_LD_ATOMIC(lld, ld) | |
309 | #endif | |
310 | #undef HELPER_LD_ATOMIC | |
311 | ||
312 | #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \ | |
895c2d04 BS |
313 | target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \ |
314 | target_ulong arg2, int mem_idx) \ | |
e7139c44 AJ |
315 | { \ |
316 | target_long tmp; \ | |
317 | \ | |
318 | if (arg2 & almask) { \ | |
319 | env->CP0_BadVAddr = arg2; \ | |
895c2d04 | 320 | helper_raise_exception(env, EXCP_AdES); \ |
e7139c44 | 321 | } \ |
895c2d04 BS |
322 | if (do_translate_address(env, arg2, 1) == env->lladdr) { \ |
323 | tmp = do_##ld_insn(env, arg2, mem_idx); \ | |
e7139c44 | 324 | if (tmp == env->llval) { \ |
895c2d04 | 325 | do_##st_insn(env, arg2, arg1, mem_idx); \ |
e7139c44 AJ |
326 | return 1; \ |
327 | } \ | |
328 | } \ | |
329 | return 0; \ | |
330 | } | |
331 | HELPER_ST_ATOMIC(sc, lw, sw, 0x3) | |
332 | #ifdef TARGET_MIPS64 | |
333 | HELPER_ST_ATOMIC(scd, ld, sd, 0x7) | |
334 | #endif | |
335 | #undef HELPER_ST_ATOMIC | |
336 | #endif | |
337 | ||
c8c2227e TS |
338 | #ifdef TARGET_WORDS_BIGENDIAN |
339 | #define GET_LMASK(v) ((v) & 3) | |
340 | #define GET_OFFSET(addr, offset) (addr + (offset)) | |
341 | #else | |
342 | #define GET_LMASK(v) (((v) & 3) ^ 3) | |
343 | #define GET_OFFSET(addr, offset) (addr - (offset)) | |
344 | #endif | |
345 | ||
895c2d04 BS |
346 | void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, |
347 | int mem_idx) | |
c8c2227e | 348 | { |
895c2d04 | 349 | do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx); |
c8c2227e | 350 | |
d9bea114 | 351 | if (GET_LMASK(arg2) <= 2) |
895c2d04 | 352 | do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx); |
c8c2227e | 353 | |
d9bea114 | 354 | if (GET_LMASK(arg2) <= 1) |
895c2d04 | 355 | do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx); |
c8c2227e | 356 | |
d9bea114 | 357 | if (GET_LMASK(arg2) == 0) |
895c2d04 | 358 | do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx); |
c8c2227e TS |
359 | } |
360 | ||
895c2d04 BS |
361 | void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, |
362 | int mem_idx) | |
c8c2227e | 363 | { |
895c2d04 | 364 | do_sb(env, arg2, (uint8_t)arg1, mem_idx); |
c8c2227e | 365 | |
d9bea114 | 366 | if (GET_LMASK(arg2) >= 1) |
895c2d04 | 367 | do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); |
c8c2227e | 368 | |
d9bea114 | 369 | if (GET_LMASK(arg2) >= 2) |
895c2d04 | 370 | do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); |
c8c2227e | 371 | |
d9bea114 | 372 | if (GET_LMASK(arg2) == 3) |
895c2d04 | 373 | do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); |
c8c2227e TS |
374 | } |
375 | ||
376 | #if defined(TARGET_MIPS64) | |
377 | /* "half" load and stores. We must do the memory access inline, | |
378 | or fault handling won't work. */ | |
379 | ||
380 | #ifdef TARGET_WORDS_BIGENDIAN | |
381 | #define GET_LMASK64(v) ((v) & 7) | |
382 | #else | |
383 | #define GET_LMASK64(v) (((v) & 7) ^ 7) | |
384 | #endif | |
385 | ||
895c2d04 BS |
386 | void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, |
387 | int mem_idx) | |
c8c2227e | 388 | { |
895c2d04 | 389 | do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx); |
c8c2227e | 390 | |
d9bea114 | 391 | if (GET_LMASK64(arg2) <= 6) |
895c2d04 | 392 | do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx); |
c8c2227e | 393 | |
d9bea114 | 394 | if (GET_LMASK64(arg2) <= 5) |
895c2d04 | 395 | do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx); |
c8c2227e | 396 | |
d9bea114 | 397 | if (GET_LMASK64(arg2) <= 4) |
895c2d04 | 398 | do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx); |
c8c2227e | 399 | |
d9bea114 | 400 | if (GET_LMASK64(arg2) <= 3) |
895c2d04 | 401 | do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx); |
c8c2227e | 402 | |
d9bea114 | 403 | if (GET_LMASK64(arg2) <= 2) |
895c2d04 | 404 | do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx); |
c8c2227e | 405 | |
d9bea114 | 406 | if (GET_LMASK64(arg2) <= 1) |
895c2d04 | 407 | do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx); |
c8c2227e | 408 | |
d9bea114 | 409 | if (GET_LMASK64(arg2) <= 0) |
895c2d04 | 410 | do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx); |
c8c2227e TS |
411 | } |
412 | ||
895c2d04 BS |
413 | void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, |
414 | int mem_idx) | |
c8c2227e | 415 | { |
895c2d04 | 416 | do_sb(env, arg2, (uint8_t)arg1, mem_idx); |
c8c2227e | 417 | |
d9bea114 | 418 | if (GET_LMASK64(arg2) >= 1) |
895c2d04 | 419 | do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); |
c8c2227e | 420 | |
d9bea114 | 421 | if (GET_LMASK64(arg2) >= 2) |
895c2d04 | 422 | do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); |
c8c2227e | 423 | |
d9bea114 | 424 | if (GET_LMASK64(arg2) >= 3) |
895c2d04 | 425 | do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); |
c8c2227e | 426 | |
d9bea114 | 427 | if (GET_LMASK64(arg2) >= 4) |
895c2d04 | 428 | do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx); |
c8c2227e | 429 | |
d9bea114 | 430 | if (GET_LMASK64(arg2) >= 5) |
895c2d04 | 431 | do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx); |
c8c2227e | 432 | |
d9bea114 | 433 | if (GET_LMASK64(arg2) >= 6) |
895c2d04 | 434 | do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx); |
c8c2227e | 435 | |
d9bea114 | 436 | if (GET_LMASK64(arg2) == 7) |
895c2d04 | 437 | do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx); |
c8c2227e TS |
438 | } |
439 | #endif /* TARGET_MIPS64 */ | |
440 | ||
3c824109 NF |
441 | static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 }; |
442 | ||
895c2d04 BS |
443 | void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, |
444 | uint32_t mem_idx) | |
3c824109 NF |
445 | { |
446 | target_ulong base_reglist = reglist & 0xf; | |
447 | target_ulong do_r31 = reglist & 0x10; | |
3c824109 NF |
448 | |
449 | if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { | |
450 | target_ulong i; | |
451 | ||
452 | for (i = 0; i < base_reglist; i++) { | |
18bba4dc AJ |
453 | env->active_tc.gpr[multiple_regs[i]] = |
454 | (target_long)do_lw(env, addr, mem_idx); | |
3c824109 NF |
455 | addr += 4; |
456 | } | |
457 | } | |
458 | ||
459 | if (do_r31) { | |
18bba4dc | 460 | env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx); |
3c824109 NF |
461 | } |
462 | } | |
463 | ||
895c2d04 BS |
464 | void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, |
465 | uint32_t mem_idx) | |
3c824109 NF |
466 | { |
467 | target_ulong base_reglist = reglist & 0xf; | |
468 | target_ulong do_r31 = reglist & 0x10; | |
3c824109 NF |
469 | |
470 | if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { | |
471 | target_ulong i; | |
472 | ||
473 | for (i = 0; i < base_reglist; i++) { | |
18bba4dc | 474 | do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx); |
3c824109 NF |
475 | addr += 4; |
476 | } | |
477 | } | |
478 | ||
479 | if (do_r31) { | |
18bba4dc | 480 | do_sw(env, addr, env->active_tc.gpr[31], mem_idx); |
3c824109 NF |
481 | } |
482 | } | |
483 | ||
484 | #if defined(TARGET_MIPS64) | |
895c2d04 BS |
485 | void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, |
486 | uint32_t mem_idx) | |
3c824109 NF |
487 | { |
488 | target_ulong base_reglist = reglist & 0xf; | |
489 | target_ulong do_r31 = reglist & 0x10; | |
3c824109 NF |
490 | |
491 | if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { | |
492 | target_ulong i; | |
493 | ||
494 | for (i = 0; i < base_reglist; i++) { | |
18bba4dc | 495 | env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx); |
3c824109 NF |
496 | addr += 8; |
497 | } | |
498 | } | |
499 | ||
500 | if (do_r31) { | |
18bba4dc | 501 | env->active_tc.gpr[31] = do_ld(env, addr, mem_idx); |
3c824109 NF |
502 | } |
503 | } | |
504 | ||
895c2d04 BS |
505 | void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, |
506 | uint32_t mem_idx) | |
3c824109 NF |
507 | { |
508 | target_ulong base_reglist = reglist & 0xf; | |
509 | target_ulong do_r31 = reglist & 0x10; | |
3c824109 NF |
510 | |
511 | if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { | |
512 | target_ulong i; | |
513 | ||
514 | for (i = 0; i < base_reglist; i++) { | |
18bba4dc | 515 | do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx); |
3c824109 NF |
516 | addr += 8; |
517 | } | |
518 | } | |
519 | ||
520 | if (do_r31) { | |
18bba4dc | 521 | do_sd(env, addr, env->active_tc.gpr[31], mem_idx); |
3c824109 NF |
522 | } |
523 | } | |
524 | #endif | |
525 | ||
0eaef5aa | 526 | #ifndef CONFIG_USER_ONLY |
f249412c | 527 | /* SMP helpers. */ |
b35d77d7 | 528 | static bool mips_vpe_is_wfi(MIPSCPU *c) |
f249412c | 529 | { |
b35d77d7 AF |
530 | CPUMIPSState *env = &c->env; |
531 | ||
f249412c EI |
532 | /* If the VPE is halted but otherwise active, it means it's waiting for |
533 | an interrupt. */ | |
b35d77d7 | 534 | return env->halted && mips_vpe_active(env); |
f249412c EI |
535 | } |
536 | ||
7db13fae | 537 | static inline void mips_vpe_wake(CPUMIPSState *c) |
f249412c EI |
538 | { |
539 | /* Dont set ->halted = 0 directly, let it be done via cpu_has_work | |
540 | because there might be other conditions that state that c should | |
541 | be sleeping. */ | |
542 | cpu_interrupt(c, CPU_INTERRUPT_WAKE); | |
543 | } | |
544 | ||
6f4d6b09 | 545 | static inline void mips_vpe_sleep(MIPSCPU *cpu) |
f249412c | 546 | { |
6f4d6b09 AF |
547 | CPUMIPSState *c = &cpu->env; |
548 | ||
f249412c EI |
549 | /* The VPE was shut off, really go to bed. |
550 | Reset any old _WAKE requests. */ | |
551 | c->halted = 1; | |
552 | cpu_reset_interrupt(c, CPU_INTERRUPT_WAKE); | |
553 | } | |
554 | ||
135dd63a | 555 | static inline void mips_tc_wake(MIPSCPU *cpu, int tc) |
f249412c | 556 | { |
135dd63a AF |
557 | CPUMIPSState *c = &cpu->env; |
558 | ||
f249412c | 559 | /* FIXME: TC reschedule. */ |
b35d77d7 | 560 | if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) { |
f249412c EI |
561 | mips_vpe_wake(c); |
562 | } | |
563 | } | |
564 | ||
c6679e90 | 565 | static inline void mips_tc_sleep(MIPSCPU *cpu, int tc) |
f249412c | 566 | { |
c6679e90 AF |
567 | CPUMIPSState *c = &cpu->env; |
568 | ||
f249412c EI |
569 | /* FIXME: TC reschedule. */ |
570 | if (!mips_vpe_active(c)) { | |
6f4d6b09 | 571 | mips_vpe_sleep(cpu); |
f249412c EI |
572 | } |
573 | } | |
574 | ||
b93bbdcd EI |
575 | /* tc should point to an int with the value of the global TC index. |
576 | This function will transform it into a local index within the | |
7db13fae | 577 | returned CPUMIPSState. |
b93bbdcd EI |
578 | |
579 | FIXME: This code assumes that all VPEs have the same number of TCs, | |
580 | which depends on runtime setup. Can probably be fixed by | |
7db13fae | 581 | walking the list of CPUMIPSStates. */ |
895c2d04 | 582 | static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc) |
b93bbdcd | 583 | { |
ce3960eb | 584 | CPUState *cs; |
7db13fae | 585 | CPUMIPSState *other; |
ce3960eb | 586 | int vpe_idx; |
b93bbdcd EI |
587 | int tc_idx = *tc; |
588 | ||
589 | if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) { | |
590 | /* Not allowed to address other CPUs. */ | |
591 | *tc = env->current_tc; | |
592 | return env; | |
593 | } | |
594 | ||
ce3960eb AF |
595 | cs = CPU(mips_env_get_cpu(env)); |
596 | vpe_idx = tc_idx / cs->nr_threads; | |
597 | *tc = tc_idx % cs->nr_threads; | |
b93bbdcd EI |
598 | other = qemu_get_cpu(vpe_idx); |
599 | return other ? other : env; | |
600 | } | |
601 | ||
fe8dca8c EI |
602 | /* The per VPE CP0_Status register shares some fields with the per TC |
603 | CP0_TCStatus registers. These fields are wired to the same registers, | |
604 | so changes to either of them should be reflected on both registers. | |
605 | ||
606 | Also, EntryHi shares the bottom 8 bit ASID with TCStauts. | |
607 | ||
608 | These helper call synchronizes the regs for a given cpu. */ | |
609 | ||
610 | /* Called for updates to CP0_Status. */ | |
895c2d04 | 611 | static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) |
fe8dca8c EI |
612 | { |
613 | int32_t tcstatus, *tcst; | |
614 | uint32_t v = cpu->CP0_Status; | |
615 | uint32_t cu, mx, asid, ksu; | |
616 | uint32_t mask = ((1 << CP0TCSt_TCU3) | |
617 | | (1 << CP0TCSt_TCU2) | |
618 | | (1 << CP0TCSt_TCU1) | |
619 | | (1 << CP0TCSt_TCU0) | |
620 | | (1 << CP0TCSt_TMX) | |
621 | | (3 << CP0TCSt_TKSU) | |
622 | | (0xff << CP0TCSt_TASID)); | |
623 | ||
624 | cu = (v >> CP0St_CU0) & 0xf; | |
625 | mx = (v >> CP0St_MX) & 0x1; | |
626 | ksu = (v >> CP0St_KSU) & 0x3; | |
627 | asid = env->CP0_EntryHi & 0xff; | |
628 | ||
629 | tcstatus = cu << CP0TCSt_TCU0; | |
630 | tcstatus |= mx << CP0TCSt_TMX; | |
631 | tcstatus |= ksu << CP0TCSt_TKSU; | |
632 | tcstatus |= asid; | |
633 | ||
634 | if (tc == cpu->current_tc) { | |
635 | tcst = &cpu->active_tc.CP0_TCStatus; | |
636 | } else { | |
637 | tcst = &cpu->tcs[tc].CP0_TCStatus; | |
638 | } | |
639 | ||
640 | *tcst &= ~mask; | |
641 | *tcst |= tcstatus; | |
642 | compute_hflags(cpu); | |
643 | } | |
644 | ||
645 | /* Called for updates to CP0_TCStatus. */ | |
895c2d04 BS |
646 | static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc, |
647 | target_ulong v) | |
fe8dca8c EI |
648 | { |
649 | uint32_t status; | |
650 | uint32_t tcu, tmx, tasid, tksu; | |
651 | uint32_t mask = ((1 << CP0St_CU3) | |
652 | | (1 << CP0St_CU2) | |
653 | | (1 << CP0St_CU1) | |
654 | | (1 << CP0St_CU0) | |
655 | | (1 << CP0St_MX) | |
656 | | (3 << CP0St_KSU)); | |
657 | ||
658 | tcu = (v >> CP0TCSt_TCU0) & 0xf; | |
659 | tmx = (v >> CP0TCSt_TMX) & 0x1; | |
660 | tasid = v & 0xff; | |
661 | tksu = (v >> CP0TCSt_TKSU) & 0x3; | |
662 | ||
663 | status = tcu << CP0St_CU0; | |
664 | status |= tmx << CP0St_MX; | |
665 | status |= tksu << CP0St_KSU; | |
666 | ||
667 | cpu->CP0_Status &= ~mask; | |
668 | cpu->CP0_Status |= status; | |
669 | ||
670 | /* Sync the TASID with EntryHi. */ | |
671 | cpu->CP0_EntryHi &= ~0xff; | |
672 | cpu->CP0_EntryHi = tasid; | |
673 | ||
674 | compute_hflags(cpu); | |
675 | } | |
676 | ||
677 | /* Called for updates to CP0_EntryHi. */ | |
7db13fae | 678 | static void sync_c0_entryhi(CPUMIPSState *cpu, int tc) |
fe8dca8c EI |
679 | { |
680 | int32_t *tcst; | |
681 | uint32_t asid, v = cpu->CP0_EntryHi; | |
682 | ||
683 | asid = v & 0xff; | |
684 | ||
685 | if (tc == cpu->current_tc) { | |
686 | tcst = &cpu->active_tc.CP0_TCStatus; | |
687 | } else { | |
688 | tcst = &cpu->tcs[tc].CP0_TCStatus; | |
689 | } | |
690 | ||
691 | *tcst &= ~0xff; | |
692 | *tcst |= asid; | |
693 | } | |
694 | ||
6af0bf9c | 695 | /* CP0 helpers */ |
895c2d04 | 696 | target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env) |
f1aa6320 | 697 | { |
be24bb4f | 698 | return env->mvp->CP0_MVPControl; |
f1aa6320 TS |
699 | } |
700 | ||
895c2d04 | 701 | target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env) |
f1aa6320 | 702 | { |
be24bb4f | 703 | return env->mvp->CP0_MVPConf0; |
f1aa6320 TS |
704 | } |
705 | ||
895c2d04 | 706 | target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env) |
f1aa6320 | 707 | { |
be24bb4f | 708 | return env->mvp->CP0_MVPConf1; |
f1aa6320 TS |
709 | } |
710 | ||
895c2d04 | 711 | target_ulong helper_mfc0_random(CPUMIPSState *env) |
6af0bf9c | 712 | { |
be24bb4f | 713 | return (int32_t)cpu_mips_get_random(env); |
873eb012 | 714 | } |
6af0bf9c | 715 | |
895c2d04 | 716 | target_ulong helper_mfc0_tcstatus(CPUMIPSState *env) |
f1aa6320 | 717 | { |
b5dc7732 | 718 | return env->active_tc.CP0_TCStatus; |
f1aa6320 TS |
719 | } |
720 | ||
895c2d04 | 721 | target_ulong helper_mftc0_tcstatus(CPUMIPSState *env) |
f1aa6320 TS |
722 | { |
723 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 724 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 725 | |
b93bbdcd EI |
726 | if (other_tc == other->current_tc) |
727 | return other->active_tc.CP0_TCStatus; | |
b5dc7732 | 728 | else |
b93bbdcd | 729 | return other->tcs[other_tc].CP0_TCStatus; |
f1aa6320 TS |
730 | } |
731 | ||
895c2d04 | 732 | target_ulong helper_mfc0_tcbind(CPUMIPSState *env) |
f1aa6320 | 733 | { |
b5dc7732 | 734 | return env->active_tc.CP0_TCBind; |
f1aa6320 TS |
735 | } |
736 | ||
895c2d04 | 737 | target_ulong helper_mftc0_tcbind(CPUMIPSState *env) |
f1aa6320 TS |
738 | { |
739 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 740 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 741 | |
b93bbdcd EI |
742 | if (other_tc == other->current_tc) |
743 | return other->active_tc.CP0_TCBind; | |
b5dc7732 | 744 | else |
b93bbdcd | 745 | return other->tcs[other_tc].CP0_TCBind; |
f1aa6320 TS |
746 | } |
747 | ||
895c2d04 | 748 | target_ulong helper_mfc0_tcrestart(CPUMIPSState *env) |
f1aa6320 | 749 | { |
b5dc7732 | 750 | return env->active_tc.PC; |
f1aa6320 TS |
751 | } |
752 | ||
895c2d04 | 753 | target_ulong helper_mftc0_tcrestart(CPUMIPSState *env) |
f1aa6320 TS |
754 | { |
755 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 756 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 757 | |
b93bbdcd EI |
758 | if (other_tc == other->current_tc) |
759 | return other->active_tc.PC; | |
b5dc7732 | 760 | else |
b93bbdcd | 761 | return other->tcs[other_tc].PC; |
f1aa6320 TS |
762 | } |
763 | ||
895c2d04 | 764 | target_ulong helper_mfc0_tchalt(CPUMIPSState *env) |
f1aa6320 | 765 | { |
b5dc7732 | 766 | return env->active_tc.CP0_TCHalt; |
f1aa6320 TS |
767 | } |
768 | ||
895c2d04 | 769 | target_ulong helper_mftc0_tchalt(CPUMIPSState *env) |
f1aa6320 TS |
770 | { |
771 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 772 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 773 | |
b93bbdcd EI |
774 | if (other_tc == other->current_tc) |
775 | return other->active_tc.CP0_TCHalt; | |
b5dc7732 | 776 | else |
b93bbdcd | 777 | return other->tcs[other_tc].CP0_TCHalt; |
f1aa6320 TS |
778 | } |
779 | ||
895c2d04 | 780 | target_ulong helper_mfc0_tccontext(CPUMIPSState *env) |
f1aa6320 | 781 | { |
b5dc7732 | 782 | return env->active_tc.CP0_TCContext; |
f1aa6320 TS |
783 | } |
784 | ||
895c2d04 | 785 | target_ulong helper_mftc0_tccontext(CPUMIPSState *env) |
f1aa6320 TS |
786 | { |
787 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 788 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 789 | |
b93bbdcd EI |
790 | if (other_tc == other->current_tc) |
791 | return other->active_tc.CP0_TCContext; | |
b5dc7732 | 792 | else |
b93bbdcd | 793 | return other->tcs[other_tc].CP0_TCContext; |
f1aa6320 TS |
794 | } |
795 | ||
895c2d04 | 796 | target_ulong helper_mfc0_tcschedule(CPUMIPSState *env) |
f1aa6320 | 797 | { |
b5dc7732 | 798 | return env->active_tc.CP0_TCSchedule; |
f1aa6320 TS |
799 | } |
800 | ||
895c2d04 | 801 | target_ulong helper_mftc0_tcschedule(CPUMIPSState *env) |
f1aa6320 TS |
802 | { |
803 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 804 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 805 | |
b93bbdcd EI |
806 | if (other_tc == other->current_tc) |
807 | return other->active_tc.CP0_TCSchedule; | |
b5dc7732 | 808 | else |
b93bbdcd | 809 | return other->tcs[other_tc].CP0_TCSchedule; |
f1aa6320 TS |
810 | } |
811 | ||
895c2d04 | 812 | target_ulong helper_mfc0_tcschefback(CPUMIPSState *env) |
f1aa6320 | 813 | { |
b5dc7732 | 814 | return env->active_tc.CP0_TCScheFBack; |
f1aa6320 TS |
815 | } |
816 | ||
895c2d04 | 817 | target_ulong helper_mftc0_tcschefback(CPUMIPSState *env) |
f1aa6320 TS |
818 | { |
819 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 820 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 821 | |
b93bbdcd EI |
822 | if (other_tc == other->current_tc) |
823 | return other->active_tc.CP0_TCScheFBack; | |
b5dc7732 | 824 | else |
b93bbdcd | 825 | return other->tcs[other_tc].CP0_TCScheFBack; |
f1aa6320 TS |
826 | } |
827 | ||
895c2d04 | 828 | target_ulong helper_mfc0_count(CPUMIPSState *env) |
873eb012 | 829 | { |
be24bb4f | 830 | return (int32_t)cpu_mips_get_count(env); |
6af0bf9c FB |
831 | } |
832 | ||
895c2d04 | 833 | target_ulong helper_mftc0_entryhi(CPUMIPSState *env) |
f1aa6320 TS |
834 | { |
835 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 836 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 837 | |
fe8dca8c | 838 | return other->CP0_EntryHi; |
f1aa6320 TS |
839 | } |
840 | ||
895c2d04 | 841 | target_ulong helper_mftc0_cause(CPUMIPSState *env) |
5a25ce94 EI |
842 | { |
843 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
844 | int32_t tccause; | |
895c2d04 | 845 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
5a25ce94 EI |
846 | |
847 | if (other_tc == other->current_tc) { | |
848 | tccause = other->CP0_Cause; | |
849 | } else { | |
850 | tccause = other->CP0_Cause; | |
851 | } | |
852 | ||
853 | return tccause; | |
854 | } | |
855 | ||
895c2d04 | 856 | target_ulong helper_mftc0_status(CPUMIPSState *env) |
f1aa6320 TS |
857 | { |
858 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 859 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
b5dc7732 | 860 | |
fe8dca8c | 861 | return other->CP0_Status; |
f1aa6320 TS |
862 | } |
863 | ||
895c2d04 | 864 | target_ulong helper_mfc0_lladdr(CPUMIPSState *env) |
f1aa6320 | 865 | { |
2a6e32dd | 866 | return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift); |
f1aa6320 TS |
867 | } |
868 | ||
895c2d04 | 869 | target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel) |
f1aa6320 | 870 | { |
be24bb4f | 871 | return (int32_t)env->CP0_WatchLo[sel]; |
f1aa6320 TS |
872 | } |
873 | ||
895c2d04 | 874 | target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel) |
f1aa6320 | 875 | { |
be24bb4f | 876 | return env->CP0_WatchHi[sel]; |
f1aa6320 TS |
877 | } |
878 | ||
895c2d04 | 879 | target_ulong helper_mfc0_debug(CPUMIPSState *env) |
f1aa6320 | 880 | { |
1a3fd9c3 | 881 | target_ulong t0 = env->CP0_Debug; |
f1aa6320 | 882 | if (env->hflags & MIPS_HFLAG_DM) |
be24bb4f TS |
883 | t0 |= 1 << CP0DB_DM; |
884 | ||
885 | return t0; | |
f1aa6320 TS |
886 | } |
887 | ||
895c2d04 | 888 | target_ulong helper_mftc0_debug(CPUMIPSState *env) |
f1aa6320 TS |
889 | { |
890 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
b5dc7732 | 891 | int32_t tcstatus; |
895c2d04 | 892 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
b5dc7732 | 893 | |
b93bbdcd EI |
894 | if (other_tc == other->current_tc) |
895 | tcstatus = other->active_tc.CP0_Debug_tcstatus; | |
b5dc7732 | 896 | else |
b93bbdcd | 897 | tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus; |
f1aa6320 TS |
898 | |
899 | /* XXX: Might be wrong, check with EJTAG spec. */ | |
b93bbdcd | 900 | return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
b5dc7732 | 901 | (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
f1aa6320 TS |
902 | } |
903 | ||
904 | #if defined(TARGET_MIPS64) | |
895c2d04 | 905 | target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env) |
f1aa6320 | 906 | { |
b5dc7732 | 907 | return env->active_tc.PC; |
f1aa6320 TS |
908 | } |
909 | ||
895c2d04 | 910 | target_ulong helper_dmfc0_tchalt(CPUMIPSState *env) |
f1aa6320 | 911 | { |
b5dc7732 | 912 | return env->active_tc.CP0_TCHalt; |
f1aa6320 TS |
913 | } |
914 | ||
895c2d04 | 915 | target_ulong helper_dmfc0_tccontext(CPUMIPSState *env) |
f1aa6320 | 916 | { |
b5dc7732 | 917 | return env->active_tc.CP0_TCContext; |
f1aa6320 TS |
918 | } |
919 | ||
895c2d04 | 920 | target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env) |
f1aa6320 | 921 | { |
b5dc7732 | 922 | return env->active_tc.CP0_TCSchedule; |
f1aa6320 TS |
923 | } |
924 | ||
895c2d04 | 925 | target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env) |
f1aa6320 | 926 | { |
b5dc7732 | 927 | return env->active_tc.CP0_TCScheFBack; |
f1aa6320 TS |
928 | } |
929 | ||
895c2d04 | 930 | target_ulong helper_dmfc0_lladdr(CPUMIPSState *env) |
f1aa6320 | 931 | { |
2a6e32dd | 932 | return env->lladdr >> env->CP0_LLAddr_shift; |
f1aa6320 TS |
933 | } |
934 | ||
895c2d04 | 935 | target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel) |
f1aa6320 | 936 | { |
be24bb4f | 937 | return env->CP0_WatchLo[sel]; |
f1aa6320 TS |
938 | } |
939 | #endif /* TARGET_MIPS64 */ | |
940 | ||
895c2d04 | 941 | void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
942 | { |
943 | int num = 1; | |
944 | unsigned int tmp = env->tlb->nb_tlb; | |
945 | ||
946 | do { | |
947 | tmp >>= 1; | |
948 | num <<= 1; | |
949 | } while (tmp); | |
d9bea114 | 950 | env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1)); |
f1aa6320 TS |
951 | } |
952 | ||
895c2d04 | 953 | void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
954 | { |
955 | uint32_t mask = 0; | |
956 | uint32_t newval; | |
957 | ||
958 | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) | |
959 | mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | | |
960 | (1 << CP0MVPCo_EVP); | |
961 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) | |
962 | mask |= (1 << CP0MVPCo_STLB); | |
d9bea114 | 963 | newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask); |
f1aa6320 TS |
964 | |
965 | // TODO: Enable/disable shared TLB, enable/disable VPEs. | |
966 | ||
967 | env->mvp->CP0_MVPControl = newval; | |
968 | } | |
969 | ||
895c2d04 | 970 | void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
971 | { |
972 | uint32_t mask; | |
973 | uint32_t newval; | |
974 | ||
975 | mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | | |
976 | (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); | |
d9bea114 | 977 | newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask); |
f1aa6320 TS |
978 | |
979 | /* Yield scheduler intercept not implemented. */ | |
980 | /* Gating storage scheduler intercept not implemented. */ | |
981 | ||
982 | // TODO: Enable/disable TCs. | |
983 | ||
984 | env->CP0_VPEControl = newval; | |
985 | } | |
986 | ||
895c2d04 | 987 | void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1) |
5a25ce94 EI |
988 | { |
989 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 990 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
5a25ce94 EI |
991 | uint32_t mask; |
992 | uint32_t newval; | |
993 | ||
994 | mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | | |
995 | (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); | |
996 | newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask); | |
997 | ||
998 | /* TODO: Enable/disable TCs. */ | |
999 | ||
1000 | other->CP0_VPEControl = newval; | |
1001 | } | |
1002 | ||
895c2d04 | 1003 | target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env) |
5a25ce94 EI |
1004 | { |
1005 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1006 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
5a25ce94 EI |
1007 | /* FIXME: Mask away return zero on read bits. */ |
1008 | return other->CP0_VPEControl; | |
1009 | } | |
1010 | ||
895c2d04 | 1011 | target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env) |
5a25ce94 EI |
1012 | { |
1013 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1014 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
5a25ce94 EI |
1015 | |
1016 | return other->CP0_VPEConf0; | |
1017 | } | |
1018 | ||
895c2d04 | 1019 | void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1020 | { |
1021 | uint32_t mask = 0; | |
1022 | uint32_t newval; | |
1023 | ||
1024 | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { | |
1025 | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) | |
1026 | mask |= (0xff << CP0VPEC0_XTC); | |
1027 | mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); | |
1028 | } | |
d9bea114 | 1029 | newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask); |
f1aa6320 TS |
1030 | |
1031 | // TODO: TC exclusive handling due to ERL/EXL. | |
1032 | ||
1033 | env->CP0_VPEConf0 = newval; | |
1034 | } | |
1035 | ||
895c2d04 | 1036 | void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1) |
5a25ce94 EI |
1037 | { |
1038 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1039 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
5a25ce94 EI |
1040 | uint32_t mask = 0; |
1041 | uint32_t newval; | |
1042 | ||
1043 | mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); | |
1044 | newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask); | |
1045 | ||
1046 | /* TODO: TC exclusive handling due to ERL/EXL. */ | |
1047 | other->CP0_VPEConf0 = newval; | |
1048 | } | |
1049 | ||
895c2d04 | 1050 | void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1051 | { |
1052 | uint32_t mask = 0; | |
1053 | uint32_t newval; | |
1054 | ||
1055 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) | |
1056 | mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) | | |
1057 | (0xff << CP0VPEC1_NCP1); | |
d9bea114 | 1058 | newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask); |
f1aa6320 TS |
1059 | |
1060 | /* UDI not implemented. */ | |
1061 | /* CP2 not implemented. */ | |
1062 | ||
1063 | // TODO: Handle FPU (CP1) binding. | |
1064 | ||
1065 | env->CP0_VPEConf1 = newval; | |
1066 | } | |
1067 | ||
895c2d04 | 1068 | void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1069 | { |
1070 | /* Yield qualifier inputs not implemented. */ | |
1071 | env->CP0_YQMask = 0x00000000; | |
1072 | } | |
1073 | ||
895c2d04 | 1074 | void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1075 | { |
d9bea114 | 1076 | env->CP0_VPEOpt = arg1 & 0x0000ffff; |
f1aa6320 TS |
1077 | } |
1078 | ||
895c2d04 | 1079 | void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1080 | { |
1081 | /* Large physaddr (PABITS) not implemented */ | |
1082 | /* 1k pages not implemented */ | |
d9bea114 | 1083 | env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF; |
f1aa6320 TS |
1084 | } |
1085 | ||
895c2d04 | 1086 | void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1087 | { |
1088 | uint32_t mask = env->CP0_TCStatus_rw_bitmask; | |
1089 | uint32_t newval; | |
1090 | ||
d9bea114 | 1091 | newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask); |
f1aa6320 | 1092 | |
b5dc7732 | 1093 | env->active_tc.CP0_TCStatus = newval; |
fe8dca8c | 1094 | sync_c0_tcstatus(env, env->current_tc, newval); |
f1aa6320 TS |
1095 | } |
1096 | ||
895c2d04 | 1097 | void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1098 | { |
1099 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1100 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1101 | |
b93bbdcd EI |
1102 | if (other_tc == other->current_tc) |
1103 | other->active_tc.CP0_TCStatus = arg1; | |
b5dc7732 | 1104 | else |
b93bbdcd | 1105 | other->tcs[other_tc].CP0_TCStatus = arg1; |
fe8dca8c | 1106 | sync_c0_tcstatus(other, other_tc, arg1); |
f1aa6320 TS |
1107 | } |
1108 | ||
895c2d04 | 1109 | void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1110 | { |
1111 | uint32_t mask = (1 << CP0TCBd_TBE); | |
1112 | uint32_t newval; | |
1113 | ||
1114 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) | |
1115 | mask |= (1 << CP0TCBd_CurVPE); | |
d9bea114 | 1116 | newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); |
b5dc7732 | 1117 | env->active_tc.CP0_TCBind = newval; |
f1aa6320 TS |
1118 | } |
1119 | ||
895c2d04 | 1120 | void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1121 | { |
1122 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1123 | uint32_t mask = (1 << CP0TCBd_TBE); | |
1124 | uint32_t newval; | |
895c2d04 | 1125 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1126 | |
b93bbdcd | 1127 | if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
f1aa6320 | 1128 | mask |= (1 << CP0TCBd_CurVPE); |
b93bbdcd EI |
1129 | if (other_tc == other->current_tc) { |
1130 | newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); | |
1131 | other->active_tc.CP0_TCBind = newval; | |
b5dc7732 | 1132 | } else { |
b93bbdcd EI |
1133 | newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask); |
1134 | other->tcs[other_tc].CP0_TCBind = newval; | |
b5dc7732 | 1135 | } |
f1aa6320 TS |
1136 | } |
1137 | ||
895c2d04 | 1138 | void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1139 | { |
d9bea114 | 1140 | env->active_tc.PC = arg1; |
b5dc7732 | 1141 | env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); |
5499b6ff | 1142 | env->lladdr = 0ULL; |
f1aa6320 TS |
1143 | /* MIPS16 not implemented. */ |
1144 | } | |
1145 | ||
895c2d04 | 1146 | void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1147 | { |
1148 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1149 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1150 | |
b93bbdcd EI |
1151 | if (other_tc == other->current_tc) { |
1152 | other->active_tc.PC = arg1; | |
1153 | other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); | |
1154 | other->lladdr = 0ULL; | |
b5dc7732 TS |
1155 | /* MIPS16 not implemented. */ |
1156 | } else { | |
b93bbdcd EI |
1157 | other->tcs[other_tc].PC = arg1; |
1158 | other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS); | |
1159 | other->lladdr = 0ULL; | |
b5dc7732 TS |
1160 | /* MIPS16 not implemented. */ |
1161 | } | |
f1aa6320 TS |
1162 | } |
1163 | ||
895c2d04 | 1164 | void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1165 | { |
135dd63a AF |
1166 | MIPSCPU *cpu = mips_env_get_cpu(env); |
1167 | ||
d9bea114 | 1168 | env->active_tc.CP0_TCHalt = arg1 & 0x1; |
f1aa6320 TS |
1169 | |
1170 | // TODO: Halt TC / Restart (if allocated+active) TC. | |
f249412c | 1171 | if (env->active_tc.CP0_TCHalt & 1) { |
c6679e90 | 1172 | mips_tc_sleep(cpu, env->current_tc); |
f249412c | 1173 | } else { |
135dd63a | 1174 | mips_tc_wake(cpu, env->current_tc); |
f249412c | 1175 | } |
f1aa6320 TS |
1176 | } |
1177 | ||
895c2d04 | 1178 | void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1179 | { |
1180 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1181 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
135dd63a | 1182 | MIPSCPU *other_cpu = mips_env_get_cpu(other); |
f1aa6320 TS |
1183 | |
1184 | // TODO: Halt TC / Restart (if allocated+active) TC. | |
1185 | ||
b93bbdcd EI |
1186 | if (other_tc == other->current_tc) |
1187 | other->active_tc.CP0_TCHalt = arg1; | |
b5dc7732 | 1188 | else |
b93bbdcd | 1189 | other->tcs[other_tc].CP0_TCHalt = arg1; |
f249412c EI |
1190 | |
1191 | if (arg1 & 1) { | |
c6679e90 | 1192 | mips_tc_sleep(other_cpu, other_tc); |
f249412c | 1193 | } else { |
135dd63a | 1194 | mips_tc_wake(other_cpu, other_tc); |
f249412c | 1195 | } |
f1aa6320 TS |
1196 | } |
1197 | ||
895c2d04 | 1198 | void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1199 | { |
d9bea114 | 1200 | env->active_tc.CP0_TCContext = arg1; |
f1aa6320 TS |
1201 | } |
1202 | ||
895c2d04 | 1203 | void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1204 | { |
1205 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1206 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1207 | |
b93bbdcd EI |
1208 | if (other_tc == other->current_tc) |
1209 | other->active_tc.CP0_TCContext = arg1; | |
b5dc7732 | 1210 | else |
b93bbdcd | 1211 | other->tcs[other_tc].CP0_TCContext = arg1; |
f1aa6320 TS |
1212 | } |
1213 | ||
895c2d04 | 1214 | void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1215 | { |
d9bea114 | 1216 | env->active_tc.CP0_TCSchedule = arg1; |
f1aa6320 TS |
1217 | } |
1218 | ||
895c2d04 | 1219 | void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1220 | { |
1221 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1222 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1223 | |
b93bbdcd EI |
1224 | if (other_tc == other->current_tc) |
1225 | other->active_tc.CP0_TCSchedule = arg1; | |
b5dc7732 | 1226 | else |
b93bbdcd | 1227 | other->tcs[other_tc].CP0_TCSchedule = arg1; |
f1aa6320 TS |
1228 | } |
1229 | ||
895c2d04 | 1230 | void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1231 | { |
d9bea114 | 1232 | env->active_tc.CP0_TCScheFBack = arg1; |
f1aa6320 TS |
1233 | } |
1234 | ||
895c2d04 | 1235 | void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1236 | { |
1237 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1238 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1239 | |
b93bbdcd EI |
1240 | if (other_tc == other->current_tc) |
1241 | other->active_tc.CP0_TCScheFBack = arg1; | |
b5dc7732 | 1242 | else |
b93bbdcd | 1243 | other->tcs[other_tc].CP0_TCScheFBack = arg1; |
f1aa6320 TS |
1244 | } |
1245 | ||
895c2d04 | 1246 | void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1247 | { |
1248 | /* Large physaddr (PABITS) not implemented */ | |
1249 | /* 1k pages not implemented */ | |
d9bea114 | 1250 | env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF; |
f1aa6320 TS |
1251 | } |
1252 | ||
895c2d04 | 1253 | void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1254 | { |
d9bea114 | 1255 | env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF); |
f1aa6320 TS |
1256 | } |
1257 | ||
895c2d04 | 1258 | void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1259 | { |
1260 | /* 1k pages not implemented */ | |
d9bea114 | 1261 | env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); |
f1aa6320 TS |
1262 | } |
1263 | ||
895c2d04 | 1264 | void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1265 | { |
1266 | /* SmartMIPS not implemented */ | |
1267 | /* Large physaddr (PABITS) not implemented */ | |
1268 | /* 1k pages not implemented */ | |
1269 | env->CP0_PageGrain = 0; | |
1270 | } | |
1271 | ||
895c2d04 | 1272 | void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1273 | { |
d9bea114 | 1274 | env->CP0_Wired = arg1 % env->tlb->nb_tlb; |
f1aa6320 TS |
1275 | } |
1276 | ||
895c2d04 | 1277 | void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1278 | { |
d9bea114 | 1279 | env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask; |
f1aa6320 TS |
1280 | } |
1281 | ||
895c2d04 | 1282 | void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1283 | { |
d9bea114 | 1284 | env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask; |
f1aa6320 TS |
1285 | } |
1286 | ||
895c2d04 | 1287 | void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1288 | { |
d9bea114 | 1289 | env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask; |
f1aa6320 TS |
1290 | } |
1291 | ||
895c2d04 | 1292 | void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1293 | { |
d9bea114 | 1294 | env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask; |
f1aa6320 TS |
1295 | } |
1296 | ||
895c2d04 | 1297 | void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1298 | { |
d9bea114 | 1299 | env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask; |
f1aa6320 TS |
1300 | } |
1301 | ||
895c2d04 | 1302 | void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1303 | { |
d9bea114 | 1304 | env->CP0_HWREna = arg1 & 0x0000000F; |
f1aa6320 TS |
1305 | } |
1306 | ||
895c2d04 | 1307 | void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1308 | { |
d9bea114 | 1309 | cpu_mips_store_count(env, arg1); |
f1aa6320 TS |
1310 | } |
1311 | ||
895c2d04 | 1312 | void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1313 | { |
1314 | target_ulong old, val; | |
1315 | ||
1316 | /* 1k pages not implemented */ | |
d9bea114 | 1317 | val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF); |
f1aa6320 TS |
1318 | #if defined(TARGET_MIPS64) |
1319 | val &= env->SEGMask; | |
1320 | #endif | |
1321 | old = env->CP0_EntryHi; | |
1322 | env->CP0_EntryHi = val; | |
1323 | if (env->CP0_Config3 & (1 << CP0C3_MT)) { | |
fe8dca8c | 1324 | sync_c0_entryhi(env, env->current_tc); |
f1aa6320 TS |
1325 | } |
1326 | /* If the ASID changes, flush qemu's TLB. */ | |
1327 | if ((old & 0xFF) != (val & 0xFF)) | |
1328 | cpu_mips_tlb_flush(env, 1); | |
1329 | } | |
1330 | ||
895c2d04 | 1331 | void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1332 | { |
1333 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1334 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1335 | |
fe8dca8c EI |
1336 | other->CP0_EntryHi = arg1; |
1337 | sync_c0_entryhi(other, other_tc); | |
f1aa6320 TS |
1338 | } |
1339 | ||
895c2d04 | 1340 | void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1341 | { |
d9bea114 | 1342 | cpu_mips_store_compare(env, arg1); |
f1aa6320 TS |
1343 | } |
1344 | ||
895c2d04 | 1345 | void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1346 | { |
1347 | uint32_t val, old; | |
1348 | uint32_t mask = env->CP0_Status_rw_bitmask; | |
1349 | ||
d9bea114 | 1350 | val = arg1 & mask; |
f1aa6320 TS |
1351 | old = env->CP0_Status; |
1352 | env->CP0_Status = (env->CP0_Status & ~mask) | val; | |
fe8dca8c | 1353 | if (env->CP0_Config3 & (1 << CP0C3_MT)) { |
895c2d04 | 1354 | sync_c0_status(env, env, env->current_tc); |
fe8dca8c EI |
1355 | } else { |
1356 | compute_hflags(env); | |
1357 | } | |
1358 | ||
c01fccd2 AJ |
1359 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { |
1360 | qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x", | |
1361 | old, old & env->CP0_Cause & CP0Ca_IP_mask, | |
1362 | val, val & env->CP0_Cause & CP0Ca_IP_mask, | |
1363 | env->CP0_Cause); | |
1364 | switch (env->hflags & MIPS_HFLAG_KSU) { | |
1365 | case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; | |
1366 | case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; | |
1367 | case MIPS_HFLAG_KM: qemu_log("\n"); break; | |
1368 | default: cpu_abort(env, "Invalid MMU mode!\n"); break; | |
31e3104f | 1369 | } |
c01fccd2 | 1370 | } |
f1aa6320 TS |
1371 | } |
1372 | ||
895c2d04 | 1373 | void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1374 | { |
1375 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1376 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1377 | |
b93bbdcd | 1378 | other->CP0_Status = arg1 & ~0xf1000018; |
895c2d04 | 1379 | sync_c0_status(env, other, other_tc); |
f1aa6320 TS |
1380 | } |
1381 | ||
895c2d04 | 1382 | void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1383 | { |
1384 | /* vectored interrupts not implemented, no performance counters. */ | |
bc45a67a | 1385 | env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0); |
f1aa6320 TS |
1386 | } |
1387 | ||
895c2d04 | 1388 | void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1389 | { |
1390 | uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); | |
d9bea114 | 1391 | env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask); |
f1aa6320 TS |
1392 | } |
1393 | ||
7db13fae | 1394 | static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1) |
f1aa6320 TS |
1395 | { |
1396 | uint32_t mask = 0x00C00300; | |
5a25ce94 | 1397 | uint32_t old = cpu->CP0_Cause; |
5dc5d9f0 | 1398 | int i; |
f1aa6320 | 1399 | |
5a25ce94 | 1400 | if (cpu->insn_flags & ISA_MIPS32R2) { |
f1aa6320 | 1401 | mask |= 1 << CP0Ca_DC; |
5a25ce94 | 1402 | } |
f1aa6320 | 1403 | |
5a25ce94 | 1404 | cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask); |
f1aa6320 | 1405 | |
5a25ce94 EI |
1406 | if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) { |
1407 | if (cpu->CP0_Cause & (1 << CP0Ca_DC)) { | |
1408 | cpu_mips_stop_count(cpu); | |
1409 | } else { | |
1410 | cpu_mips_start_count(cpu); | |
1411 | } | |
f1aa6320 | 1412 | } |
5dc5d9f0 AJ |
1413 | |
1414 | /* Set/reset software interrupts */ | |
1415 | for (i = 0 ; i < 2 ; i++) { | |
5a25ce94 EI |
1416 | if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) { |
1417 | cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i))); | |
5dc5d9f0 AJ |
1418 | } |
1419 | } | |
f1aa6320 TS |
1420 | } |
1421 | ||
895c2d04 | 1422 | void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1) |
5a25ce94 EI |
1423 | { |
1424 | mtc0_cause(env, arg1); | |
1425 | } | |
1426 | ||
895c2d04 | 1427 | void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1) |
5a25ce94 EI |
1428 | { |
1429 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1430 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
5a25ce94 EI |
1431 | |
1432 | mtc0_cause(other, arg1); | |
1433 | } | |
1434 | ||
895c2d04 | 1435 | target_ulong helper_mftc0_epc(CPUMIPSState *env) |
5a25ce94 EI |
1436 | { |
1437 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1438 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
5a25ce94 EI |
1439 | |
1440 | return other->CP0_EPC; | |
1441 | } | |
1442 | ||
895c2d04 | 1443 | target_ulong helper_mftc0_ebase(CPUMIPSState *env) |
5a25ce94 EI |
1444 | { |
1445 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1446 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
5a25ce94 EI |
1447 | |
1448 | return other->CP0_EBase; | |
1449 | } | |
1450 | ||
895c2d04 | 1451 | void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1452 | { |
1453 | /* vectored interrupts not implemented */ | |
671b0f36 | 1454 | env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000); |
f1aa6320 TS |
1455 | } |
1456 | ||
895c2d04 | 1457 | void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1) |
5a25ce94 EI |
1458 | { |
1459 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1460 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
5a25ce94 EI |
1461 | other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000); |
1462 | } | |
1463 | ||
895c2d04 | 1464 | target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx) |
5a25ce94 EI |
1465 | { |
1466 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1467 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
5a25ce94 EI |
1468 | |
1469 | switch (idx) { | |
1470 | case 0: return other->CP0_Config0; | |
1471 | case 1: return other->CP0_Config1; | |
1472 | case 2: return other->CP0_Config2; | |
1473 | case 3: return other->CP0_Config3; | |
1474 | /* 4 and 5 are reserved. */ | |
1475 | case 6: return other->CP0_Config6; | |
1476 | case 7: return other->CP0_Config7; | |
1477 | default: | |
1478 | break; | |
1479 | } | |
1480 | return 0; | |
1481 | } | |
1482 | ||
895c2d04 | 1483 | void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1484 | { |
d9bea114 | 1485 | env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007); |
f1aa6320 TS |
1486 | } |
1487 | ||
895c2d04 | 1488 | void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1489 | { |
1490 | /* tertiary/secondary caches not implemented */ | |
1491 | env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); | |
1492 | } | |
1493 | ||
895c2d04 | 1494 | void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1) |
2a6e32dd AJ |
1495 | { |
1496 | target_long mask = env->CP0_LLAddr_rw_bitmask; | |
1497 | arg1 = arg1 << env->CP0_LLAddr_shift; | |
1498 | env->lladdr = (env->lladdr & ~mask) | (arg1 & mask); | |
1499 | } | |
1500 | ||
895c2d04 | 1501 | void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) |
f1aa6320 TS |
1502 | { |
1503 | /* Watch exceptions for instructions, data loads, data stores | |
1504 | not implemented. */ | |
d9bea114 | 1505 | env->CP0_WatchLo[sel] = (arg1 & ~0x7); |
f1aa6320 TS |
1506 | } |
1507 | ||
895c2d04 | 1508 | void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) |
f1aa6320 | 1509 | { |
d9bea114 AJ |
1510 | env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8); |
1511 | env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7); | |
f1aa6320 TS |
1512 | } |
1513 | ||
895c2d04 | 1514 | void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1515 | { |
1516 | target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; | |
d9bea114 | 1517 | env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask); |
f1aa6320 TS |
1518 | } |
1519 | ||
895c2d04 | 1520 | void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1521 | { |
d9bea114 | 1522 | env->CP0_Framemask = arg1; /* XXX */ |
f1aa6320 TS |
1523 | } |
1524 | ||
895c2d04 | 1525 | void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1526 | { |
d9bea114 AJ |
1527 | env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120); |
1528 | if (arg1 & (1 << CP0DB_DM)) | |
f1aa6320 TS |
1529 | env->hflags |= MIPS_HFLAG_DM; |
1530 | else | |
1531 | env->hflags &= ~MIPS_HFLAG_DM; | |
1532 | } | |
1533 | ||
895c2d04 | 1534 | void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1535 | { |
1536 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
d9bea114 | 1537 | uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); |
895c2d04 | 1538 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 TS |
1539 | |
1540 | /* XXX: Might be wrong, check with EJTAG spec. */ | |
b93bbdcd EI |
1541 | if (other_tc == other->current_tc) |
1542 | other->active_tc.CP0_Debug_tcstatus = val; | |
b5dc7732 | 1543 | else |
b93bbdcd EI |
1544 | other->tcs[other_tc].CP0_Debug_tcstatus = val; |
1545 | other->CP0_Debug = (other->CP0_Debug & | |
1546 | ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | | |
d9bea114 | 1547 | (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
f1aa6320 TS |
1548 | } |
1549 | ||
895c2d04 | 1550 | void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1551 | { |
d9bea114 | 1552 | env->CP0_Performance0 = arg1 & 0x000007ff; |
f1aa6320 TS |
1553 | } |
1554 | ||
895c2d04 | 1555 | void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1556 | { |
d9bea114 | 1557 | env->CP0_TagLo = arg1 & 0xFFFFFCF6; |
f1aa6320 TS |
1558 | } |
1559 | ||
895c2d04 | 1560 | void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1561 | { |
d9bea114 | 1562 | env->CP0_DataLo = arg1; /* XXX */ |
f1aa6320 TS |
1563 | } |
1564 | ||
895c2d04 | 1565 | void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1566 | { |
d9bea114 | 1567 | env->CP0_TagHi = arg1; /* XXX */ |
f1aa6320 TS |
1568 | } |
1569 | ||
895c2d04 | 1570 | void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 | 1571 | { |
d9bea114 | 1572 | env->CP0_DataHi = arg1; /* XXX */ |
f1aa6320 TS |
1573 | } |
1574 | ||
f1aa6320 | 1575 | /* MIPS MT functions */ |
895c2d04 | 1576 | target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel) |
f1aa6320 TS |
1577 | { |
1578 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1579 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1580 | |
b93bbdcd EI |
1581 | if (other_tc == other->current_tc) |
1582 | return other->active_tc.gpr[sel]; | |
b5dc7732 | 1583 | else |
b93bbdcd | 1584 | return other->tcs[other_tc].gpr[sel]; |
f1aa6320 TS |
1585 | } |
1586 | ||
895c2d04 | 1587 | target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel) |
f1aa6320 TS |
1588 | { |
1589 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1590 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1591 | |
b93bbdcd EI |
1592 | if (other_tc == other->current_tc) |
1593 | return other->active_tc.LO[sel]; | |
b5dc7732 | 1594 | else |
b93bbdcd | 1595 | return other->tcs[other_tc].LO[sel]; |
f1aa6320 TS |
1596 | } |
1597 | ||
895c2d04 | 1598 | target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel) |
f1aa6320 TS |
1599 | { |
1600 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1601 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1602 | |
b93bbdcd EI |
1603 | if (other_tc == other->current_tc) |
1604 | return other->active_tc.HI[sel]; | |
b5dc7732 | 1605 | else |
b93bbdcd | 1606 | return other->tcs[other_tc].HI[sel]; |
f1aa6320 TS |
1607 | } |
1608 | ||
895c2d04 | 1609 | target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel) |
f1aa6320 TS |
1610 | { |
1611 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1612 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1613 | |
b93bbdcd EI |
1614 | if (other_tc == other->current_tc) |
1615 | return other->active_tc.ACX[sel]; | |
b5dc7732 | 1616 | else |
b93bbdcd | 1617 | return other->tcs[other_tc].ACX[sel]; |
f1aa6320 TS |
1618 | } |
1619 | ||
895c2d04 | 1620 | target_ulong helper_mftdsp(CPUMIPSState *env) |
f1aa6320 TS |
1621 | { |
1622 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1623 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1624 | |
b93bbdcd EI |
1625 | if (other_tc == other->current_tc) |
1626 | return other->active_tc.DSPControl; | |
b5dc7732 | 1627 | else |
b93bbdcd | 1628 | return other->tcs[other_tc].DSPControl; |
f1aa6320 | 1629 | } |
6af0bf9c | 1630 | |
895c2d04 | 1631 | void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel) |
f1aa6320 TS |
1632 | { |
1633 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1634 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1635 | |
b93bbdcd EI |
1636 | if (other_tc == other->current_tc) |
1637 | other->active_tc.gpr[sel] = arg1; | |
b5dc7732 | 1638 | else |
b93bbdcd | 1639 | other->tcs[other_tc].gpr[sel] = arg1; |
f1aa6320 TS |
1640 | } |
1641 | ||
895c2d04 | 1642 | void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) |
f1aa6320 TS |
1643 | { |
1644 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1645 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1646 | |
b93bbdcd EI |
1647 | if (other_tc == other->current_tc) |
1648 | other->active_tc.LO[sel] = arg1; | |
b5dc7732 | 1649 | else |
b93bbdcd | 1650 | other->tcs[other_tc].LO[sel] = arg1; |
f1aa6320 TS |
1651 | } |
1652 | ||
895c2d04 | 1653 | void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) |
f1aa6320 TS |
1654 | { |
1655 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1656 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1657 | |
b93bbdcd EI |
1658 | if (other_tc == other->current_tc) |
1659 | other->active_tc.HI[sel] = arg1; | |
b5dc7732 | 1660 | else |
b93bbdcd | 1661 | other->tcs[other_tc].HI[sel] = arg1; |
f1aa6320 TS |
1662 | } |
1663 | ||
895c2d04 | 1664 | void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel) |
f1aa6320 TS |
1665 | { |
1666 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1667 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1668 | |
b93bbdcd EI |
1669 | if (other_tc == other->current_tc) |
1670 | other->active_tc.ACX[sel] = arg1; | |
b5dc7732 | 1671 | else |
b93bbdcd | 1672 | other->tcs[other_tc].ACX[sel] = arg1; |
f1aa6320 TS |
1673 | } |
1674 | ||
895c2d04 | 1675 | void helper_mttdsp(CPUMIPSState *env, target_ulong arg1) |
f1aa6320 TS |
1676 | { |
1677 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
895c2d04 | 1678 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
f1aa6320 | 1679 | |
b93bbdcd EI |
1680 | if (other_tc == other->current_tc) |
1681 | other->active_tc.DSPControl = arg1; | |
b5dc7732 | 1682 | else |
b93bbdcd | 1683 | other->tcs[other_tc].DSPControl = arg1; |
f1aa6320 TS |
1684 | } |
1685 | ||
1686 | /* MIPS MT functions */ | |
9ed5726c | 1687 | target_ulong helper_dmt(void) |
f1aa6320 TS |
1688 | { |
1689 | // TODO | |
9ed5726c | 1690 | return 0; |
f1aa6320 TS |
1691 | } |
1692 | ||
9ed5726c | 1693 | target_ulong helper_emt(void) |
f1aa6320 TS |
1694 | { |
1695 | // TODO | |
9ed5726c | 1696 | return 0; |
f1aa6320 TS |
1697 | } |
1698 | ||
895c2d04 | 1699 | target_ulong helper_dvpe(CPUMIPSState *env) |
f1aa6320 | 1700 | { |
81bad50e | 1701 | CPUMIPSState *other_cpu_env = first_cpu; |
f249412c EI |
1702 | target_ulong prev = env->mvp->CP0_MVPControl; |
1703 | ||
1704 | do { | |
1705 | /* Turn off all VPEs except the one executing the dvpe. */ | |
81bad50e | 1706 | if (other_cpu_env != env) { |
6f4d6b09 AF |
1707 | MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env); |
1708 | ||
81bad50e | 1709 | other_cpu_env->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP); |
6f4d6b09 | 1710 | mips_vpe_sleep(other_cpu); |
f249412c | 1711 | } |
81bad50e AF |
1712 | other_cpu_env = other_cpu_env->next_cpu; |
1713 | } while (other_cpu_env); | |
f249412c | 1714 | return prev; |
f1aa6320 TS |
1715 | } |
1716 | ||
895c2d04 | 1717 | target_ulong helper_evpe(CPUMIPSState *env) |
f1aa6320 | 1718 | { |
81bad50e | 1719 | CPUMIPSState *other_cpu_env = first_cpu; |
f249412c EI |
1720 | target_ulong prev = env->mvp->CP0_MVPControl; |
1721 | ||
1722 | do { | |
b35d77d7 AF |
1723 | MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env); |
1724 | ||
81bad50e AF |
1725 | if (other_cpu_env != env |
1726 | /* If the VPE is WFI, don't disturb its sleep. */ | |
b35d77d7 | 1727 | && !mips_vpe_is_wfi(other_cpu)) { |
f249412c | 1728 | /* Enable the VPE. */ |
81bad50e AF |
1729 | other_cpu_env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); |
1730 | mips_vpe_wake(other_cpu_env); /* And wake it up. */ | |
f249412c | 1731 | } |
81bad50e AF |
1732 | other_cpu_env = other_cpu_env->next_cpu; |
1733 | } while (other_cpu_env); | |
f249412c | 1734 | return prev; |
f1aa6320 | 1735 | } |
f9480ffc | 1736 | #endif /* !CONFIG_USER_ONLY */ |
f1aa6320 | 1737 | |
d9bea114 | 1738 | void helper_fork(target_ulong arg1, target_ulong arg2) |
f1aa6320 | 1739 | { |
d9bea114 AJ |
1740 | // arg1 = rt, arg2 = rs |
1741 | arg1 = 0; | |
f1aa6320 TS |
1742 | // TODO: store to TC register |
1743 | } | |
1744 | ||
895c2d04 | 1745 | target_ulong helper_yield(CPUMIPSState *env, target_ulong arg) |
f1aa6320 | 1746 | { |
1c7242da BS |
1747 | target_long arg1 = arg; |
1748 | ||
d9bea114 | 1749 | if (arg1 < 0) { |
f1aa6320 | 1750 | /* No scheduling policy implemented. */ |
d9bea114 | 1751 | if (arg1 != -2) { |
f1aa6320 | 1752 | if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) && |
b5dc7732 | 1753 | env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) { |
f1aa6320 TS |
1754 | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); |
1755 | env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT; | |
895c2d04 | 1756 | helper_raise_exception(env, EXCP_THREAD); |
f1aa6320 TS |
1757 | } |
1758 | } | |
d9bea114 | 1759 | } else if (arg1 == 0) { |
6958549d | 1760 | if (0 /* TODO: TC underflow */) { |
f1aa6320 | 1761 | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); |
895c2d04 | 1762 | helper_raise_exception(env, EXCP_THREAD); |
f1aa6320 TS |
1763 | } else { |
1764 | // TODO: Deallocate TC | |
1765 | } | |
d9bea114 | 1766 | } else if (arg1 > 0) { |
f1aa6320 TS |
1767 | /* Yield qualifier inputs not implemented. */ |
1768 | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); | |
1769 | env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT; | |
895c2d04 | 1770 | helper_raise_exception(env, EXCP_THREAD); |
f1aa6320 | 1771 | } |
be24bb4f | 1772 | return env->CP0_YQMask; |
f1aa6320 TS |
1773 | } |
1774 | ||
f1aa6320 | 1775 | #ifndef CONFIG_USER_ONLY |
6af0bf9c | 1776 | /* TLB management */ |
7db13fae | 1777 | static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global) |
814b9a47 TS |
1778 | { |
1779 | /* Flush qemu's TLB and discard all shadowed entries. */ | |
1780 | tlb_flush (env, flush_global); | |
ead9360e | 1781 | env->tlb->tlb_in_use = env->tlb->nb_tlb; |
814b9a47 TS |
1782 | } |
1783 | ||
7db13fae | 1784 | static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first) |
814b9a47 TS |
1785 | { |
1786 | /* Discard entries from env->tlb[first] onwards. */ | |
ead9360e TS |
1787 | while (env->tlb->tlb_in_use > first) { |
1788 | r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); | |
814b9a47 TS |
1789 | } |
1790 | } | |
1791 | ||
895c2d04 | 1792 | static void r4k_fill_tlb(CPUMIPSState *env, int idx) |
6af0bf9c | 1793 | { |
c227f099 | 1794 | r4k_tlb_t *tlb; |
6af0bf9c FB |
1795 | |
1796 | /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */ | |
ead9360e | 1797 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
f2e9ebef | 1798 | tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); |
d26bc211 | 1799 | #if defined(TARGET_MIPS64) |
e034e2c3 | 1800 | tlb->VPN &= env->SEGMask; |
100ce988 | 1801 | #endif |
98c1b82b | 1802 | tlb->ASID = env->CP0_EntryHi & 0xFF; |
3b1c8be4 | 1803 | tlb->PageMask = env->CP0_PageMask; |
6af0bf9c | 1804 | tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; |
98c1b82b PB |
1805 | tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
1806 | tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; | |
1807 | tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; | |
6af0bf9c | 1808 | tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
98c1b82b PB |
1809 | tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
1810 | tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; | |
1811 | tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; | |
6af0bf9c FB |
1812 | tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
1813 | } | |
1814 | ||
895c2d04 | 1815 | void r4k_helper_tlbwi(CPUMIPSState *env) |
6af0bf9c | 1816 | { |
286d52eb | 1817 | r4k_tlb_t *tlb; |
bbc0d79c | 1818 | int idx; |
286d52eb AJ |
1819 | target_ulong VPN; |
1820 | uint8_t ASID; | |
1821 | bool G, V0, D0, V1, D1; | |
bbc0d79c AJ |
1822 | |
1823 | idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; | |
286d52eb AJ |
1824 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
1825 | VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); | |
1826 | #if defined(TARGET_MIPS64) | |
1827 | VPN &= env->SEGMask; | |
1828 | #endif | |
1829 | ASID = env->CP0_EntryHi & 0xff; | |
1830 | G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; | |
1831 | V0 = (env->CP0_EntryLo0 & 2) != 0; | |
1832 | D0 = (env->CP0_EntryLo0 & 4) != 0; | |
1833 | V1 = (env->CP0_EntryLo1 & 2) != 0; | |
1834 | D1 = (env->CP0_EntryLo1 & 4) != 0; | |
1835 | ||
1836 | /* Discard cached TLB entries, unless tlbwi is just upgrading access | |
1837 | permissions on the current entry. */ | |
1838 | if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G || | |
1839 | (tlb->V0 && !V0) || (tlb->D0 && !D0) || | |
1840 | (tlb->V1 && !V1) || (tlb->D1 && !D1)) { | |
1841 | r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); | |
1842 | } | |
814b9a47 | 1843 | |
bbc0d79c | 1844 | r4k_invalidate_tlb(env, idx, 0); |
895c2d04 | 1845 | r4k_fill_tlb(env, idx); |
6af0bf9c FB |
1846 | } |
1847 | ||
895c2d04 | 1848 | void r4k_helper_tlbwr(CPUMIPSState *env) |
6af0bf9c FB |
1849 | { |
1850 | int r = cpu_mips_get_random(env); | |
1851 | ||
29929e34 | 1852 | r4k_invalidate_tlb(env, r, 1); |
895c2d04 | 1853 | r4k_fill_tlb(env, r); |
6af0bf9c FB |
1854 | } |
1855 | ||
895c2d04 | 1856 | void r4k_helper_tlbp(CPUMIPSState *env) |
6af0bf9c | 1857 | { |
c227f099 | 1858 | r4k_tlb_t *tlb; |
f2e9ebef | 1859 | target_ulong mask; |
6af0bf9c | 1860 | target_ulong tag; |
f2e9ebef | 1861 | target_ulong VPN; |
6af0bf9c FB |
1862 | uint8_t ASID; |
1863 | int i; | |
1864 | ||
3d9fb9fe | 1865 | ASID = env->CP0_EntryHi & 0xFF; |
ead9360e TS |
1866 | for (i = 0; i < env->tlb->nb_tlb; i++) { |
1867 | tlb = &env->tlb->mmu.r4k.tlb[i]; | |
f2e9ebef TS |
1868 | /* 1k pages are not supported. */ |
1869 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); | |
1870 | tag = env->CP0_EntryHi & ~mask; | |
1871 | VPN = tlb->VPN & ~mask; | |
bc3e45e1 AJ |
1872 | #if defined(TARGET_MIPS64) |
1873 | tag &= env->SEGMask; | |
1874 | #endif | |
6af0bf9c | 1875 | /* Check ASID, virtual page number & size */ |
f2e9ebef | 1876 | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
6af0bf9c | 1877 | /* TLB match */ |
9c2149c8 | 1878 | env->CP0_Index = i; |
6af0bf9c FB |
1879 | break; |
1880 | } | |
1881 | } | |
ead9360e | 1882 | if (i == env->tlb->nb_tlb) { |
814b9a47 | 1883 | /* No match. Discard any shadow entries, if any of them match. */ |
ead9360e | 1884 | for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) { |
6958549d AJ |
1885 | tlb = &env->tlb->mmu.r4k.tlb[i]; |
1886 | /* 1k pages are not supported. */ | |
1887 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); | |
1888 | tag = env->CP0_EntryHi & ~mask; | |
1889 | VPN = tlb->VPN & ~mask; | |
bc3e45e1 AJ |
1890 | #if defined(TARGET_MIPS64) |
1891 | tag &= env->SEGMask; | |
1892 | #endif | |
6958549d AJ |
1893 | /* Check ASID, virtual page number & size */ |
1894 | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { | |
29929e34 | 1895 | r4k_mips_tlb_flush_extra (env, i); |
6958549d AJ |
1896 | break; |
1897 | } | |
1898 | } | |
814b9a47 | 1899 | |
9c2149c8 | 1900 | env->CP0_Index |= 0x80000000; |
6af0bf9c FB |
1901 | } |
1902 | } | |
1903 | ||
895c2d04 | 1904 | void r4k_helper_tlbr(CPUMIPSState *env) |
6af0bf9c | 1905 | { |
c227f099 | 1906 | r4k_tlb_t *tlb; |
09c56b84 | 1907 | uint8_t ASID; |
bbc0d79c | 1908 | int idx; |
6af0bf9c | 1909 | |
09c56b84 | 1910 | ASID = env->CP0_EntryHi & 0xFF; |
bbc0d79c AJ |
1911 | idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; |
1912 | tlb = &env->tlb->mmu.r4k.tlb[idx]; | |
4ad40f36 FB |
1913 | |
1914 | /* If this will change the current ASID, flush qemu's TLB. */ | |
814b9a47 TS |
1915 | if (ASID != tlb->ASID) |
1916 | cpu_mips_tlb_flush (env, 1); | |
1917 | ||
ead9360e | 1918 | r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); |
4ad40f36 | 1919 | |
6af0bf9c | 1920 | env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
3b1c8be4 | 1921 | env->CP0_PageMask = tlb->PageMask; |
7495fd0f TS |
1922 | env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | |
1923 | (tlb->C0 << 3) | (tlb->PFN[0] >> 6); | |
1924 | env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | | |
1925 | (tlb->C1 << 3) | (tlb->PFN[1] >> 6); | |
6af0bf9c | 1926 | } |
6af0bf9c | 1927 | |
895c2d04 | 1928 | void helper_tlbwi(CPUMIPSState *env) |
a7812ae4 | 1929 | { |
895c2d04 | 1930 | env->tlb->helper_tlbwi(env); |
a7812ae4 PB |
1931 | } |
1932 | ||
895c2d04 | 1933 | void helper_tlbwr(CPUMIPSState *env) |
a7812ae4 | 1934 | { |
895c2d04 | 1935 | env->tlb->helper_tlbwr(env); |
a7812ae4 PB |
1936 | } |
1937 | ||
895c2d04 | 1938 | void helper_tlbp(CPUMIPSState *env) |
a7812ae4 | 1939 | { |
895c2d04 | 1940 | env->tlb->helper_tlbp(env); |
a7812ae4 PB |
1941 | } |
1942 | ||
895c2d04 | 1943 | void helper_tlbr(CPUMIPSState *env) |
a7812ae4 | 1944 | { |
895c2d04 | 1945 | env->tlb->helper_tlbr(env); |
a7812ae4 PB |
1946 | } |
1947 | ||
2b0233ab | 1948 | /* Specials */ |
895c2d04 | 1949 | target_ulong helper_di(CPUMIPSState *env) |
2b0233ab | 1950 | { |
2796188e TS |
1951 | target_ulong t0 = env->CP0_Status; |
1952 | ||
be24bb4f | 1953 | env->CP0_Status = t0 & ~(1 << CP0St_IE); |
be24bb4f | 1954 | return t0; |
2b0233ab TS |
1955 | } |
1956 | ||
895c2d04 | 1957 | target_ulong helper_ei(CPUMIPSState *env) |
2b0233ab | 1958 | { |
2796188e TS |
1959 | target_ulong t0 = env->CP0_Status; |
1960 | ||
be24bb4f | 1961 | env->CP0_Status = t0 | (1 << CP0St_IE); |
be24bb4f | 1962 | return t0; |
2b0233ab TS |
1963 | } |
1964 | ||
895c2d04 | 1965 | static void debug_pre_eret(CPUMIPSState *env) |
6af0bf9c | 1966 | { |
8fec2b8c | 1967 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { |
93fcfe39 AL |
1968 | qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
1969 | env->active_tc.PC, env->CP0_EPC); | |
1970 | if (env->CP0_Status & (1 << CP0St_ERL)) | |
1971 | qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); | |
1972 | if (env->hflags & MIPS_HFLAG_DM) | |
1973 | qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); | |
1974 | qemu_log("\n"); | |
1975 | } | |
f41c52f1 TS |
1976 | } |
1977 | ||
895c2d04 | 1978 | static void debug_post_eret(CPUMIPSState *env) |
f41c52f1 | 1979 | { |
8fec2b8c | 1980 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { |
93fcfe39 AL |
1981 | qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
1982 | env->active_tc.PC, env->CP0_EPC); | |
1983 | if (env->CP0_Status & (1 << CP0St_ERL)) | |
1984 | qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); | |
1985 | if (env->hflags & MIPS_HFLAG_DM) | |
1986 | qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); | |
1987 | switch (env->hflags & MIPS_HFLAG_KSU) { | |
1988 | case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; | |
1989 | case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; | |
1990 | case MIPS_HFLAG_KM: qemu_log("\n"); break; | |
1991 | default: cpu_abort(env, "Invalid MMU mode!\n"); break; | |
1992 | } | |
623a930e | 1993 | } |
6af0bf9c FB |
1994 | } |
1995 | ||
895c2d04 | 1996 | static void set_pc(CPUMIPSState *env, target_ulong error_pc) |
32188a03 NF |
1997 | { |
1998 | env->active_tc.PC = error_pc & ~(target_ulong)1; | |
1999 | if (error_pc & 1) { | |
2000 | env->hflags |= MIPS_HFLAG_M16; | |
2001 | } else { | |
2002 | env->hflags &= ~(MIPS_HFLAG_M16); | |
2003 | } | |
2004 | } | |
2005 | ||
895c2d04 | 2006 | void helper_eret(CPUMIPSState *env) |
2b0233ab | 2007 | { |
895c2d04 | 2008 | debug_pre_eret(env); |
2b0233ab | 2009 | if (env->CP0_Status & (1 << CP0St_ERL)) { |
895c2d04 | 2010 | set_pc(env, env->CP0_ErrorEPC); |
2b0233ab TS |
2011 | env->CP0_Status &= ~(1 << CP0St_ERL); |
2012 | } else { | |
895c2d04 | 2013 | set_pc(env, env->CP0_EPC); |
2b0233ab TS |
2014 | env->CP0_Status &= ~(1 << CP0St_EXL); |
2015 | } | |
2016 | compute_hflags(env); | |
895c2d04 | 2017 | debug_post_eret(env); |
5499b6ff | 2018 | env->lladdr = 1; |
2b0233ab TS |
2019 | } |
2020 | ||
895c2d04 | 2021 | void helper_deret(CPUMIPSState *env) |
2b0233ab | 2022 | { |
895c2d04 BS |
2023 | debug_pre_eret(env); |
2024 | set_pc(env, env->CP0_DEPC); | |
32188a03 | 2025 | |
2b0233ab TS |
2026 | env->hflags &= MIPS_HFLAG_DM; |
2027 | compute_hflags(env); | |
895c2d04 | 2028 | debug_post_eret(env); |
5499b6ff | 2029 | env->lladdr = 1; |
2b0233ab | 2030 | } |
0eaef5aa | 2031 | #endif /* !CONFIG_USER_ONLY */ |
2b0233ab | 2032 | |
895c2d04 | 2033 | target_ulong helper_rdhwr_cpunum(CPUMIPSState *env) |
2b0233ab TS |
2034 | { |
2035 | if ((env->hflags & MIPS_HFLAG_CP0) || | |
2036 | (env->CP0_HWREna & (1 << 0))) | |
2796188e | 2037 | return env->CP0_EBase & 0x3ff; |
2b0233ab | 2038 | else |
895c2d04 | 2039 | helper_raise_exception(env, EXCP_RI); |
be24bb4f | 2040 | |
2796188e | 2041 | return 0; |
2b0233ab TS |
2042 | } |
2043 | ||
895c2d04 | 2044 | target_ulong helper_rdhwr_synci_step(CPUMIPSState *env) |
2b0233ab TS |
2045 | { |
2046 | if ((env->hflags & MIPS_HFLAG_CP0) || | |
2047 | (env->CP0_HWREna & (1 << 1))) | |
2796188e | 2048 | return env->SYNCI_Step; |
2b0233ab | 2049 | else |
895c2d04 | 2050 | helper_raise_exception(env, EXCP_RI); |
be24bb4f | 2051 | |
2796188e | 2052 | return 0; |
2b0233ab TS |
2053 | } |
2054 | ||
895c2d04 | 2055 | target_ulong helper_rdhwr_cc(CPUMIPSState *env) |
2b0233ab TS |
2056 | { |
2057 | if ((env->hflags & MIPS_HFLAG_CP0) || | |
2058 | (env->CP0_HWREna & (1 << 2))) | |
2796188e | 2059 | return env->CP0_Count; |
2b0233ab | 2060 | else |
895c2d04 | 2061 | helper_raise_exception(env, EXCP_RI); |
be24bb4f | 2062 | |
2796188e | 2063 | return 0; |
2b0233ab TS |
2064 | } |
2065 | ||
895c2d04 | 2066 | target_ulong helper_rdhwr_ccres(CPUMIPSState *env) |
2b0233ab TS |
2067 | { |
2068 | if ((env->hflags & MIPS_HFLAG_CP0) || | |
2069 | (env->CP0_HWREna & (1 << 3))) | |
2796188e | 2070 | return env->CCRes; |
2b0233ab | 2071 | else |
895c2d04 | 2072 | helper_raise_exception(env, EXCP_RI); |
be24bb4f | 2073 | |
2796188e | 2074 | return 0; |
2b0233ab TS |
2075 | } |
2076 | ||
895c2d04 | 2077 | void helper_pmon(CPUMIPSState *env, int function) |
6af0bf9c FB |
2078 | { |
2079 | function /= 2; | |
2080 | switch (function) { | |
2081 | case 2: /* TODO: char inbyte(int waitflag); */ | |
b5dc7732 TS |
2082 | if (env->active_tc.gpr[4] == 0) |
2083 | env->active_tc.gpr[2] = -1; | |
6af0bf9c FB |
2084 | /* Fall through */ |
2085 | case 11: /* TODO: char inbyte (void); */ | |
b5dc7732 | 2086 | env->active_tc.gpr[2] = -1; |
6af0bf9c FB |
2087 | break; |
2088 | case 3: | |
2089 | case 12: | |
b5dc7732 | 2090 | printf("%c", (char)(env->active_tc.gpr[4] & 0xFF)); |
6af0bf9c FB |
2091 | break; |
2092 | case 17: | |
2093 | break; | |
2094 | case 158: | |
2095 | { | |
b69e48a8 | 2096 | unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4]; |
6af0bf9c FB |
2097 | printf("%s", fmt); |
2098 | } | |
2099 | break; | |
2100 | } | |
2101 | } | |
e37e863f | 2102 | |
895c2d04 | 2103 | void helper_wait(CPUMIPSState *env) |
08ba7963 TS |
2104 | { |
2105 | env->halted = 1; | |
f249412c | 2106 | cpu_reset_interrupt(env, CPU_INTERRUPT_WAKE); |
895c2d04 | 2107 | helper_raise_exception(env, EXCP_HLT); |
08ba7963 TS |
2108 | } |
2109 | ||
5fafdf24 | 2110 | #if !defined(CONFIG_USER_ONLY) |
e37e863f | 2111 | |
895c2d04 BS |
2112 | static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env, |
2113 | target_ulong addr, int is_write, | |
20503968 | 2114 | int is_user, uintptr_t retaddr); |
4ad40f36 | 2115 | |
e37e863f | 2116 | #define MMUSUFFIX _mmu |
4ad40f36 | 2117 | #define ALIGNED_ONLY |
e37e863f FB |
2118 | |
2119 | #define SHIFT 0 | |
022c62cb | 2120 | #include "exec/softmmu_template.h" |
e37e863f FB |
2121 | |
2122 | #define SHIFT 1 | |
022c62cb | 2123 | #include "exec/softmmu_template.h" |
e37e863f FB |
2124 | |
2125 | #define SHIFT 2 | |
022c62cb | 2126 | #include "exec/softmmu_template.h" |
e37e863f FB |
2127 | |
2128 | #define SHIFT 3 | |
022c62cb | 2129 | #include "exec/softmmu_template.h" |
e37e863f | 2130 | |
895c2d04 BS |
2131 | static void do_unaligned_access(CPUMIPSState *env, target_ulong addr, |
2132 | int is_write, int is_user, uintptr_t retaddr) | |
4ad40f36 FB |
2133 | { |
2134 | env->CP0_BadVAddr = addr; | |
5f7319cd | 2135 | do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr); |
4ad40f36 FB |
2136 | } |
2137 | ||
895c2d04 | 2138 | void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx, |
20503968 | 2139 | uintptr_t retaddr) |
e37e863f | 2140 | { |
e37e863f FB |
2141 | int ret; |
2142 | ||
97b348e7 | 2143 | ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx); |
e37e863f | 2144 | if (ret) { |
5f7319cd AJ |
2145 | do_raise_exception_err(env, env->exception_index, |
2146 | env->error_code, retaddr); | |
e37e863f | 2147 | } |
e37e863f FB |
2148 | } |
2149 | ||
a8170e5e | 2150 | void cpu_unassigned_access(CPUMIPSState *env, hwaddr addr, |
b14ef7c9 | 2151 | int is_write, int is_exec, int unused, int size) |
647de6ca TS |
2152 | { |
2153 | if (is_exec) | |
895c2d04 | 2154 | helper_raise_exception(env, EXCP_IBE); |
647de6ca | 2155 | else |
895c2d04 | 2156 | helper_raise_exception(env, EXCP_DBE); |
647de6ca | 2157 | } |
f1aa6320 | 2158 | #endif /* !CONFIG_USER_ONLY */ |
fd4a04eb TS |
2159 | |
2160 | /* Complex FPU operations which may need stack space. */ | |
2161 | ||
f090c9d4 PB |
2162 | #define FLOAT_TWO32 make_float32(1 << 30) |
2163 | #define FLOAT_TWO64 make_float64(1ULL << 62) | |
05993cd0 AJ |
2164 | #define FP_TO_INT32_OVERFLOW 0x7fffffff |
2165 | #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL | |
8dfdb87c | 2166 | |
fd4a04eb | 2167 | /* convert MIPS rounding mode in FCR31 to IEEE library */ |
6f4fc367 | 2168 | static unsigned int ieee_rm[] = { |
fd4a04eb TS |
2169 | float_round_nearest_even, |
2170 | float_round_to_zero, | |
2171 | float_round_up, | |
2172 | float_round_down | |
2173 | }; | |
2174 | ||
e320d05a SW |
2175 | static inline void restore_rounding_mode(CPUMIPSState *env) |
2176 | { | |
2177 | set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], | |
2178 | &env->active_fpu.fp_status); | |
2179 | } | |
fd4a04eb | 2180 | |
e320d05a SW |
2181 | static inline void restore_flush_mode(CPUMIPSState *env) |
2182 | { | |
2183 | set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, | |
2184 | &env->active_fpu.fp_status); | |
2185 | } | |
41e0c701 | 2186 | |
895c2d04 | 2187 | target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg) |
fd4a04eb | 2188 | { |
d9bea114 | 2189 | target_ulong arg1; |
6c5c1e20 | 2190 | |
ead9360e TS |
2191 | switch (reg) { |
2192 | case 0: | |
d9bea114 | 2193 | arg1 = (int32_t)env->active_fpu.fcr0; |
ead9360e TS |
2194 | break; |
2195 | case 25: | |
d9bea114 | 2196 | arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1); |
ead9360e TS |
2197 | break; |
2198 | case 26: | |
d9bea114 | 2199 | arg1 = env->active_fpu.fcr31 & 0x0003f07c; |
ead9360e TS |
2200 | break; |
2201 | case 28: | |
d9bea114 | 2202 | arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4); |
ead9360e TS |
2203 | break; |
2204 | default: | |
d9bea114 | 2205 | arg1 = (int32_t)env->active_fpu.fcr31; |
ead9360e TS |
2206 | break; |
2207 | } | |
be24bb4f | 2208 | |
d9bea114 | 2209 | return arg1; |
ead9360e TS |
2210 | } |
2211 | ||
895c2d04 | 2212 | void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t reg) |
ead9360e TS |
2213 | { |
2214 | switch(reg) { | |
fd4a04eb | 2215 | case 25: |
d9bea114 | 2216 | if (arg1 & 0xffffff00) |
fd4a04eb | 2217 | return; |
d9bea114 AJ |
2218 | env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) | |
2219 | ((arg1 & 0x1) << 23); | |
fd4a04eb TS |
2220 | break; |
2221 | case 26: | |
d9bea114 | 2222 | if (arg1 & 0x007c0000) |
fd4a04eb | 2223 | return; |
d9bea114 | 2224 | env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c); |
fd4a04eb TS |
2225 | break; |
2226 | case 28: | |
d9bea114 | 2227 | if (arg1 & 0x007c0000) |
fd4a04eb | 2228 | return; |
d9bea114 AJ |
2229 | env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) | |
2230 | ((arg1 & 0x4) << 22); | |
fd4a04eb TS |
2231 | break; |
2232 | case 31: | |
d9bea114 | 2233 | if (arg1 & 0x007c0000) |
fd4a04eb | 2234 | return; |
d9bea114 | 2235 | env->active_fpu.fcr31 = arg1; |
fd4a04eb TS |
2236 | break; |
2237 | default: | |
2238 | return; | |
2239 | } | |
2240 | /* set rounding mode */ | |
e320d05a | 2241 | restore_rounding_mode(env); |
41e0c701 | 2242 | /* set flush-to-zero mode */ |
e320d05a | 2243 | restore_flush_mode(env); |
f01be154 TS |
2244 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2245 | if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31)) | |
5f7319cd | 2246 | do_raise_exception(env, EXCP_FPE, GETPC()); |
fd4a04eb TS |
2247 | } |
2248 | ||
353ebb7a | 2249 | static inline int ieee_ex_to_mips(int xcpt) |
fd4a04eb | 2250 | { |
353ebb7a AJ |
2251 | int ret = 0; |
2252 | if (xcpt) { | |
2253 | if (xcpt & float_flag_invalid) { | |
2254 | ret |= FP_INVALID; | |
2255 | } | |
2256 | if (xcpt & float_flag_overflow) { | |
2257 | ret |= FP_OVERFLOW; | |
2258 | } | |
2259 | if (xcpt & float_flag_underflow) { | |
2260 | ret |= FP_UNDERFLOW; | |
2261 | } | |
2262 | if (xcpt & float_flag_divbyzero) { | |
2263 | ret |= FP_DIV0; | |
2264 | } | |
2265 | if (xcpt & float_flag_inexact) { | |
2266 | ret |= FP_INEXACT; | |
2267 | } | |
2268 | } | |
2269 | return ret; | |
fd4a04eb TS |
2270 | } |
2271 | ||
5f7319cd | 2272 | static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc) |
fd4a04eb | 2273 | { |
f01be154 | 2274 | int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status)); |
fd4a04eb | 2275 | |
f01be154 | 2276 | SET_FP_CAUSE(env->active_fpu.fcr31, tmp); |
4a587b2c AJ |
2277 | |
2278 | if (tmp) { | |
2279 | set_float_exception_flags(0, &env->active_fpu.fp_status); | |
2280 | ||
2281 | if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) { | |
5f7319cd | 2282 | do_raise_exception(env, EXCP_FPE, pc); |
4a587b2c AJ |
2283 | } else { |
2284 | UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp); | |
2285 | } | |
2286 | } | |
fd4a04eb TS |
2287 | } |
2288 | ||
a16336e4 TS |
2289 | /* Float support. |
2290 | Single precition routines have a "s" suffix, double precision a | |
2291 | "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps", | |
2292 | paired single lower "pl", paired single upper "pu". */ | |
2293 | ||
a16336e4 | 2294 | /* unary operations, modifying fp status */ |
895c2d04 | 2295 | uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0) |
b6d96bed | 2296 | { |
5dbe90bb | 2297 | fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status); |
5f7319cd | 2298 | update_fcr31(env, GETPC()); |
5dbe90bb | 2299 | return fdt0; |
b6d96bed TS |
2300 | } |
2301 | ||
895c2d04 | 2302 | uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0) |
b6d96bed | 2303 | { |
5dbe90bb | 2304 | fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status); |
5f7319cd | 2305 | update_fcr31(env, GETPC()); |
5dbe90bb | 2306 | return fst0; |
b6d96bed | 2307 | } |
a16336e4 | 2308 | |
895c2d04 | 2309 | uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0) |
fd4a04eb | 2310 | { |
b6d96bed TS |
2311 | uint64_t fdt2; |
2312 | ||
f01be154 | 2313 | fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status); |
5f7319cd | 2314 | update_fcr31(env, GETPC()); |
b6d96bed | 2315 | return fdt2; |
fd4a04eb | 2316 | } |
b6d96bed | 2317 | |
895c2d04 | 2318 | uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0) |
fd4a04eb | 2319 | { |
b6d96bed TS |
2320 | uint64_t fdt2; |
2321 | ||
f01be154 | 2322 | fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status); |
5f7319cd | 2323 | update_fcr31(env, GETPC()); |
b6d96bed | 2324 | return fdt2; |
fd4a04eb | 2325 | } |
b6d96bed | 2326 | |
895c2d04 | 2327 | uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0) |
fd4a04eb | 2328 | { |
b6d96bed TS |
2329 | uint64_t fdt2; |
2330 | ||
f01be154 | 2331 | fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status); |
5f7319cd | 2332 | update_fcr31(env, GETPC()); |
b6d96bed | 2333 | return fdt2; |
fd4a04eb | 2334 | } |
b6d96bed | 2335 | |
895c2d04 | 2336 | uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2337 | { |
b6d96bed TS |
2338 | uint64_t dt2; |
2339 | ||
f01be154 | 2340 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); |
4cc2e5f9 AJ |
2341 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2342 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2343 | dt2 = FP_TO_INT64_OVERFLOW; |
4cc2e5f9 | 2344 | } |
5f7319cd | 2345 | update_fcr31(env, GETPC()); |
b6d96bed | 2346 | return dt2; |
fd4a04eb | 2347 | } |
b6d96bed | 2348 | |
895c2d04 | 2349 | uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0) |
fd4a04eb | 2350 | { |
b6d96bed TS |
2351 | uint64_t dt2; |
2352 | ||
f01be154 | 2353 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); |
4cc2e5f9 AJ |
2354 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2355 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2356 | dt2 = FP_TO_INT64_OVERFLOW; |
4cc2e5f9 | 2357 | } |
5f7319cd | 2358 | update_fcr31(env, GETPC()); |
b6d96bed | 2359 | return dt2; |
fd4a04eb TS |
2360 | } |
2361 | ||
895c2d04 | 2362 | uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0) |
fd4a04eb | 2363 | { |
b6d96bed TS |
2364 | uint32_t fst2; |
2365 | uint32_t fsth2; | |
2366 | ||
f01be154 TS |
2367 | fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); |
2368 | fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status); | |
5f7319cd | 2369 | update_fcr31(env, GETPC()); |
b6d96bed | 2370 | return ((uint64_t)fsth2 << 32) | fst2; |
fd4a04eb | 2371 | } |
b6d96bed | 2372 | |
895c2d04 | 2373 | uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2374 | { |
b6d96bed TS |
2375 | uint32_t wt2; |
2376 | uint32_t wth2; | |
5dbe90bb | 2377 | int excp, excph; |
b6d96bed | 2378 | |
f01be154 | 2379 | wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); |
5dbe90bb AJ |
2380 | excp = get_float_exception_flags(&env->active_fpu.fp_status); |
2381 | if (excp & (float_flag_overflow | float_flag_invalid)) { | |
05993cd0 | 2382 | wt2 = FP_TO_INT32_OVERFLOW; |
5dbe90bb AJ |
2383 | } |
2384 | ||
2385 | set_float_exception_flags(0, &env->active_fpu.fp_status); | |
2386 | wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status); | |
2387 | excph = get_float_exception_flags(&env->active_fpu.fp_status); | |
2388 | if (excph & (float_flag_overflow | float_flag_invalid)) { | |
05993cd0 | 2389 | wth2 = FP_TO_INT32_OVERFLOW; |
b6d96bed | 2390 | } |
5dbe90bb AJ |
2391 | |
2392 | set_float_exception_flags(excp | excph, &env->active_fpu.fp_status); | |
5f7319cd | 2393 | update_fcr31(env, GETPC()); |
5dbe90bb | 2394 | |
b6d96bed | 2395 | return ((uint64_t)wth2 << 32) | wt2; |
fd4a04eb | 2396 | } |
b6d96bed | 2397 | |
895c2d04 | 2398 | uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2399 | { |
b6d96bed TS |
2400 | uint32_t fst2; |
2401 | ||
f01be154 | 2402 | fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status); |
5f7319cd | 2403 | update_fcr31(env, GETPC()); |
b6d96bed | 2404 | return fst2; |
fd4a04eb | 2405 | } |
b6d96bed | 2406 | |
895c2d04 | 2407 | uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0) |
fd4a04eb | 2408 | { |
b6d96bed TS |
2409 | uint32_t fst2; |
2410 | ||
f01be154 | 2411 | fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status); |
5f7319cd | 2412 | update_fcr31(env, GETPC()); |
b6d96bed | 2413 | return fst2; |
fd4a04eb | 2414 | } |
b6d96bed | 2415 | |
895c2d04 | 2416 | uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0) |
fd4a04eb | 2417 | { |
b6d96bed TS |
2418 | uint32_t fst2; |
2419 | ||
f01be154 | 2420 | fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status); |
5f7319cd | 2421 | update_fcr31(env, GETPC()); |
b6d96bed | 2422 | return fst2; |
fd4a04eb | 2423 | } |
b6d96bed | 2424 | |
895c2d04 | 2425 | uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0) |
fd4a04eb | 2426 | { |
b6d96bed TS |
2427 | uint32_t wt2; |
2428 | ||
b6d96bed | 2429 | wt2 = wt0; |
5f7319cd | 2430 | update_fcr31(env, GETPC()); |
b6d96bed | 2431 | return wt2; |
fd4a04eb | 2432 | } |
b6d96bed | 2433 | |
895c2d04 | 2434 | uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0) |
fd4a04eb | 2435 | { |
b6d96bed TS |
2436 | uint32_t wt2; |
2437 | ||
b6d96bed | 2438 | wt2 = wth0; |
5f7319cd | 2439 | update_fcr31(env, GETPC()); |
b6d96bed | 2440 | return wt2; |
fd4a04eb | 2441 | } |
b6d96bed | 2442 | |
895c2d04 | 2443 | uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0) |
fd4a04eb | 2444 | { |
b6d96bed TS |
2445 | uint32_t wt2; |
2446 | ||
f01be154 | 2447 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); |
5f7319cd | 2448 | update_fcr31(env, GETPC()); |
4cc2e5f9 AJ |
2449 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2450 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2451 | wt2 = FP_TO_INT32_OVERFLOW; |
4cc2e5f9 | 2452 | } |
b6d96bed | 2453 | return wt2; |
fd4a04eb | 2454 | } |
b6d96bed | 2455 | |
895c2d04 | 2456 | uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2457 | { |
b6d96bed TS |
2458 | uint32_t wt2; |
2459 | ||
f01be154 | 2460 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); |
4cc2e5f9 AJ |
2461 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2462 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2463 | wt2 = FP_TO_INT32_OVERFLOW; |
4cc2e5f9 | 2464 | } |
5f7319cd | 2465 | update_fcr31(env, GETPC()); |
b6d96bed | 2466 | return wt2; |
fd4a04eb TS |
2467 | } |
2468 | ||
895c2d04 | 2469 | uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2470 | { |
b6d96bed TS |
2471 | uint64_t dt2; |
2472 | ||
f01be154 TS |
2473 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2474 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); | |
e320d05a | 2475 | restore_rounding_mode(env); |
4cc2e5f9 AJ |
2476 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2477 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2478 | dt2 = FP_TO_INT64_OVERFLOW; |
4cc2e5f9 | 2479 | } |
5f7319cd | 2480 | update_fcr31(env, GETPC()); |
b6d96bed | 2481 | return dt2; |
fd4a04eb | 2482 | } |
b6d96bed | 2483 | |
895c2d04 | 2484 | uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0) |
fd4a04eb | 2485 | { |
b6d96bed TS |
2486 | uint64_t dt2; |
2487 | ||
f01be154 TS |
2488 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2489 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); | |
e320d05a | 2490 | restore_rounding_mode(env); |
4cc2e5f9 AJ |
2491 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2492 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2493 | dt2 = FP_TO_INT64_OVERFLOW; |
4cc2e5f9 | 2494 | } |
5f7319cd | 2495 | update_fcr31(env, GETPC()); |
b6d96bed | 2496 | return dt2; |
fd4a04eb | 2497 | } |
b6d96bed | 2498 | |
895c2d04 | 2499 | uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2500 | { |
b6d96bed TS |
2501 | uint32_t wt2; |
2502 | ||
f01be154 TS |
2503 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2504 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); | |
e320d05a | 2505 | restore_rounding_mode(env); |
4cc2e5f9 AJ |
2506 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2507 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2508 | wt2 = FP_TO_INT32_OVERFLOW; |
4cc2e5f9 | 2509 | } |
5f7319cd | 2510 | update_fcr31(env, GETPC()); |
b6d96bed | 2511 | return wt2; |
fd4a04eb | 2512 | } |
b6d96bed | 2513 | |
895c2d04 | 2514 | uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0) |
fd4a04eb | 2515 | { |
b6d96bed TS |
2516 | uint32_t wt2; |
2517 | ||
f01be154 TS |
2518 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2519 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); | |
e320d05a | 2520 | restore_rounding_mode(env); |
4cc2e5f9 AJ |
2521 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2522 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2523 | wt2 = FP_TO_INT32_OVERFLOW; |
4cc2e5f9 | 2524 | } |
5f7319cd | 2525 | update_fcr31(env, GETPC()); |
b6d96bed | 2526 | return wt2; |
fd4a04eb TS |
2527 | } |
2528 | ||
895c2d04 | 2529 | uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2530 | { |
b6d96bed TS |
2531 | uint64_t dt2; |
2532 | ||
f01be154 | 2533 | dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status); |
4cc2e5f9 AJ |
2534 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2535 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2536 | dt2 = FP_TO_INT64_OVERFLOW; |
4cc2e5f9 | 2537 | } |
5f7319cd | 2538 | update_fcr31(env, GETPC()); |
b6d96bed | 2539 | return dt2; |
fd4a04eb | 2540 | } |
b6d96bed | 2541 | |
895c2d04 | 2542 | uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0) |
fd4a04eb | 2543 | { |
b6d96bed TS |
2544 | uint64_t dt2; |
2545 | ||
f01be154 | 2546 | dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status); |
4cc2e5f9 AJ |
2547 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2548 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2549 | dt2 = FP_TO_INT64_OVERFLOW; |
4cc2e5f9 | 2550 | } |
5f7319cd | 2551 | update_fcr31(env, GETPC()); |
b6d96bed | 2552 | return dt2; |
fd4a04eb | 2553 | } |
b6d96bed | 2554 | |
895c2d04 | 2555 | uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2556 | { |
b6d96bed TS |
2557 | uint32_t wt2; |
2558 | ||
f01be154 | 2559 | wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status); |
4cc2e5f9 AJ |
2560 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2561 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2562 | wt2 = FP_TO_INT32_OVERFLOW; |
4cc2e5f9 | 2563 | } |
5f7319cd | 2564 | update_fcr31(env, GETPC()); |
b6d96bed | 2565 | return wt2; |
fd4a04eb | 2566 | } |
b6d96bed | 2567 | |
895c2d04 | 2568 | uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0) |
fd4a04eb | 2569 | { |
b6d96bed TS |
2570 | uint32_t wt2; |
2571 | ||
f01be154 | 2572 | wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status); |
4cc2e5f9 AJ |
2573 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2574 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2575 | wt2 = FP_TO_INT32_OVERFLOW; |
4cc2e5f9 | 2576 | } |
5f7319cd | 2577 | update_fcr31(env, GETPC()); |
b6d96bed | 2578 | return wt2; |
fd4a04eb TS |
2579 | } |
2580 | ||
895c2d04 | 2581 | uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2582 | { |
b6d96bed TS |
2583 | uint64_t dt2; |
2584 | ||
f01be154 TS |
2585 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2586 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); | |
e320d05a | 2587 | restore_rounding_mode(env); |
4cc2e5f9 AJ |
2588 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2589 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2590 | dt2 = FP_TO_INT64_OVERFLOW; |
4cc2e5f9 | 2591 | } |
5f7319cd | 2592 | update_fcr31(env, GETPC()); |
b6d96bed | 2593 | return dt2; |
fd4a04eb | 2594 | } |
b6d96bed | 2595 | |
895c2d04 | 2596 | uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0) |
fd4a04eb | 2597 | { |
b6d96bed TS |
2598 | uint64_t dt2; |
2599 | ||
f01be154 TS |
2600 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2601 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); | |
e320d05a | 2602 | restore_rounding_mode(env); |
4cc2e5f9 AJ |
2603 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2604 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2605 | dt2 = FP_TO_INT64_OVERFLOW; |
4cc2e5f9 | 2606 | } |
5f7319cd | 2607 | update_fcr31(env, GETPC()); |
b6d96bed | 2608 | return dt2; |
fd4a04eb | 2609 | } |
b6d96bed | 2610 | |
895c2d04 | 2611 | uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2612 | { |
b6d96bed TS |
2613 | uint32_t wt2; |
2614 | ||
f01be154 TS |
2615 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2616 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); | |
e320d05a | 2617 | restore_rounding_mode(env); |
4cc2e5f9 AJ |
2618 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2619 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2620 | wt2 = FP_TO_INT32_OVERFLOW; |
4cc2e5f9 | 2621 | } |
5f7319cd | 2622 | update_fcr31(env, GETPC()); |
b6d96bed | 2623 | return wt2; |
fd4a04eb | 2624 | } |
b6d96bed | 2625 | |
895c2d04 | 2626 | uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0) |
fd4a04eb | 2627 | { |
b6d96bed TS |
2628 | uint32_t wt2; |
2629 | ||
f01be154 TS |
2630 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2631 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); | |
e320d05a | 2632 | restore_rounding_mode(env); |
4cc2e5f9 AJ |
2633 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2634 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2635 | wt2 = FP_TO_INT32_OVERFLOW; |
4cc2e5f9 | 2636 | } |
5f7319cd | 2637 | update_fcr31(env, GETPC()); |
b6d96bed | 2638 | return wt2; |
fd4a04eb TS |
2639 | } |
2640 | ||
895c2d04 | 2641 | uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2642 | { |
b6d96bed TS |
2643 | uint64_t dt2; |
2644 | ||
f01be154 TS |
2645 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2646 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); | |
e320d05a | 2647 | restore_rounding_mode(env); |
4cc2e5f9 AJ |
2648 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2649 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2650 | dt2 = FP_TO_INT64_OVERFLOW; |
4cc2e5f9 | 2651 | } |
5f7319cd | 2652 | update_fcr31(env, GETPC()); |
b6d96bed | 2653 | return dt2; |
fd4a04eb | 2654 | } |
b6d96bed | 2655 | |
895c2d04 | 2656 | uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0) |
fd4a04eb | 2657 | { |
b6d96bed TS |
2658 | uint64_t dt2; |
2659 | ||
f01be154 TS |
2660 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2661 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); | |
e320d05a | 2662 | restore_rounding_mode(env); |
4cc2e5f9 AJ |
2663 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2664 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2665 | dt2 = FP_TO_INT64_OVERFLOW; |
4cc2e5f9 | 2666 | } |
5f7319cd | 2667 | update_fcr31(env, GETPC()); |
b6d96bed | 2668 | return dt2; |
fd4a04eb | 2669 | } |
b6d96bed | 2670 | |
895c2d04 | 2671 | uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0) |
fd4a04eb | 2672 | { |
b6d96bed TS |
2673 | uint32_t wt2; |
2674 | ||
f01be154 TS |
2675 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2676 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); | |
e320d05a | 2677 | restore_rounding_mode(env); |
4cc2e5f9 AJ |
2678 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2679 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2680 | wt2 = FP_TO_INT32_OVERFLOW; |
4cc2e5f9 | 2681 | } |
5f7319cd | 2682 | update_fcr31(env, GETPC()); |
b6d96bed | 2683 | return wt2; |
fd4a04eb | 2684 | } |
b6d96bed | 2685 | |
895c2d04 | 2686 | uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0) |
fd4a04eb | 2687 | { |
b6d96bed TS |
2688 | uint32_t wt2; |
2689 | ||
f01be154 TS |
2690 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2691 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); | |
e320d05a | 2692 | restore_rounding_mode(env); |
4cc2e5f9 AJ |
2693 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
2694 | & (float_flag_invalid | float_flag_overflow)) { | |
05993cd0 | 2695 | wt2 = FP_TO_INT32_OVERFLOW; |
4cc2e5f9 | 2696 | } |
5f7319cd | 2697 | update_fcr31(env, GETPC()); |
b6d96bed | 2698 | return wt2; |
fd4a04eb TS |
2699 | } |
2700 | ||
a16336e4 | 2701 | /* unary operations, not modifying fp status */ |
b6d96bed | 2702 | #define FLOAT_UNOP(name) \ |
c01fccd2 | 2703 | uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \ |
b6d96bed TS |
2704 | { \ |
2705 | return float64_ ## name(fdt0); \ | |
2706 | } \ | |
c01fccd2 | 2707 | uint32_t helper_float_ ## name ## _s(uint32_t fst0) \ |
b6d96bed TS |
2708 | { \ |
2709 | return float32_ ## name(fst0); \ | |
2710 | } \ | |
c01fccd2 | 2711 | uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \ |
b6d96bed TS |
2712 | { \ |
2713 | uint32_t wt0; \ | |
2714 | uint32_t wth0; \ | |
2715 | \ | |
2716 | wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \ | |
2717 | wth0 = float32_ ## name(fdt0 >> 32); \ | |
2718 | return ((uint64_t)wth0 << 32) | wt0; \ | |
a16336e4 TS |
2719 | } |
2720 | FLOAT_UNOP(abs) | |
2721 | FLOAT_UNOP(chs) | |
2722 | #undef FLOAT_UNOP | |
2723 | ||
8dfdb87c | 2724 | /* MIPS specific unary operations */ |
895c2d04 | 2725 | uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0) |
8dfdb87c | 2726 | { |
b6d96bed TS |
2727 | uint64_t fdt2; |
2728 | ||
05993cd0 | 2729 | fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status); |
5f7319cd | 2730 | update_fcr31(env, GETPC()); |
b6d96bed | 2731 | return fdt2; |
8dfdb87c | 2732 | } |
b6d96bed | 2733 | |
895c2d04 | 2734 | uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0) |
8dfdb87c | 2735 | { |
b6d96bed TS |
2736 | uint32_t fst2; |
2737 | ||
05993cd0 | 2738 | fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status); |
5f7319cd | 2739 | update_fcr31(env, GETPC()); |
b6d96bed | 2740 | return fst2; |
57fa1fb3 | 2741 | } |
57fa1fb3 | 2742 | |
895c2d04 | 2743 | uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0) |
8dfdb87c | 2744 | { |
b6d96bed TS |
2745 | uint64_t fdt2; |
2746 | ||
f01be154 | 2747 | fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); |
05993cd0 | 2748 | fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status); |
5f7319cd | 2749 | update_fcr31(env, GETPC()); |
b6d96bed | 2750 | return fdt2; |
8dfdb87c | 2751 | } |
b6d96bed | 2752 | |
895c2d04 | 2753 | uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0) |
8dfdb87c | 2754 | { |
b6d96bed TS |
2755 | uint32_t fst2; |
2756 | ||
f01be154 | 2757 | fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); |
05993cd0 | 2758 | fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status); |
5f7319cd | 2759 | update_fcr31(env, GETPC()); |
b6d96bed | 2760 | return fst2; |
8dfdb87c TS |
2761 | } |
2762 | ||
895c2d04 | 2763 | uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0) |
8dfdb87c | 2764 | { |
b6d96bed TS |
2765 | uint64_t fdt2; |
2766 | ||
05993cd0 | 2767 | fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status); |
5f7319cd | 2768 | update_fcr31(env, GETPC()); |
b6d96bed | 2769 | return fdt2; |
8dfdb87c | 2770 | } |
b6d96bed | 2771 | |
895c2d04 | 2772 | uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0) |
8dfdb87c | 2773 | { |
b6d96bed TS |
2774 | uint32_t fst2; |
2775 | ||
05993cd0 | 2776 | fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status); |
5f7319cd | 2777 | update_fcr31(env, GETPC()); |
b6d96bed | 2778 | return fst2; |
8dfdb87c | 2779 | } |
b6d96bed | 2780 | |
895c2d04 | 2781 | uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0) |
8dfdb87c | 2782 | { |
b6d96bed TS |
2783 | uint32_t fst2; |
2784 | uint32_t fsth2; | |
2785 | ||
05993cd0 AJ |
2786 | fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); |
2787 | fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status); | |
5f7319cd | 2788 | update_fcr31(env, GETPC()); |
b6d96bed | 2789 | return ((uint64_t)fsth2 << 32) | fst2; |
8dfdb87c TS |
2790 | } |
2791 | ||
895c2d04 | 2792 | uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0) |
8dfdb87c | 2793 | { |
b6d96bed TS |
2794 | uint64_t fdt2; |
2795 | ||
f01be154 | 2796 | fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); |
05993cd0 | 2797 | fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status); |
5f7319cd | 2798 | update_fcr31(env, GETPC()); |
b6d96bed | 2799 | return fdt2; |
8dfdb87c | 2800 | } |
b6d96bed | 2801 | |
895c2d04 | 2802 | uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0) |
8dfdb87c | 2803 | { |
b6d96bed TS |
2804 | uint32_t fst2; |
2805 | ||
f01be154 | 2806 | fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); |
05993cd0 | 2807 | fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status); |
5f7319cd | 2808 | update_fcr31(env, GETPC()); |
b6d96bed | 2809 | return fst2; |
8dfdb87c | 2810 | } |
b6d96bed | 2811 | |
895c2d04 | 2812 | uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0) |
8dfdb87c | 2813 | { |
b6d96bed TS |
2814 | uint32_t fst2; |
2815 | uint32_t fsth2; | |
2816 | ||
f01be154 TS |
2817 | fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); |
2818 | fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status); | |
05993cd0 AJ |
2819 | fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status); |
2820 | fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status); | |
5f7319cd | 2821 | update_fcr31(env, GETPC()); |
b6d96bed | 2822 | return ((uint64_t)fsth2 << 32) | fst2; |
57fa1fb3 | 2823 | } |
57fa1fb3 | 2824 | |
895c2d04 | 2825 | #define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env) |
b6d96bed | 2826 | |
fd4a04eb | 2827 | /* binary operations */ |
b6d96bed | 2828 | #define FLOAT_BINOP(name) \ |
895c2d04 BS |
2829 | uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ |
2830 | uint64_t fdt0, uint64_t fdt1) \ | |
b6d96bed TS |
2831 | { \ |
2832 | uint64_t dt2; \ | |
2833 | \ | |
f01be154 | 2834 | dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \ |
5f7319cd | 2835 | update_fcr31(env, GETPC()); \ |
b6d96bed TS |
2836 | return dt2; \ |
2837 | } \ | |
2838 | \ | |
895c2d04 BS |
2839 | uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ |
2840 | uint32_t fst0, uint32_t fst1) \ | |
b6d96bed TS |
2841 | { \ |
2842 | uint32_t wt2; \ | |
2843 | \ | |
f01be154 | 2844 | wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ |
5f7319cd | 2845 | update_fcr31(env, GETPC()); \ |
b6d96bed TS |
2846 | return wt2; \ |
2847 | } \ | |
2848 | \ | |
895c2d04 BS |
2849 | uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ |
2850 | uint64_t fdt0, \ | |
2851 | uint64_t fdt1) \ | |
b6d96bed TS |
2852 | { \ |
2853 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ | |
2854 | uint32_t fsth0 = fdt0 >> 32; \ | |
2855 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ | |
2856 | uint32_t fsth1 = fdt1 >> 32; \ | |
2857 | uint32_t wt2; \ | |
2858 | uint32_t wth2; \ | |
2859 | \ | |
f01be154 TS |
2860 | wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ |
2861 | wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \ | |
5f7319cd | 2862 | update_fcr31(env, GETPC()); \ |
b6d96bed | 2863 | return ((uint64_t)wth2 << 32) | wt2; \ |
fd4a04eb | 2864 | } |
b6d96bed | 2865 | |
fd4a04eb TS |
2866 | FLOAT_BINOP(add) |
2867 | FLOAT_BINOP(sub) | |
2868 | FLOAT_BINOP(mul) | |
2869 | FLOAT_BINOP(div) | |
2870 | #undef FLOAT_BINOP | |
2871 | ||
b3d6cd44 AJ |
2872 | /* FMA based operations */ |
2873 | #define FLOAT_FMA(name, type) \ | |
2874 | uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ | |
2875 | uint64_t fdt0, uint64_t fdt1, \ | |
2876 | uint64_t fdt2) \ | |
2877 | { \ | |
b3d6cd44 AJ |
2878 | fdt0 = float64_muladd(fdt0, fdt1, fdt2, type, \ |
2879 | &env->active_fpu.fp_status); \ | |
5f7319cd | 2880 | update_fcr31(env, GETPC()); \ |
b3d6cd44 AJ |
2881 | return fdt0; \ |
2882 | } \ | |
2883 | \ | |
2884 | uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ | |
2885 | uint32_t fst0, uint32_t fst1, \ | |
2886 | uint32_t fst2) \ | |
2887 | { \ | |
b3d6cd44 AJ |
2888 | fst0 = float32_muladd(fst0, fst1, fst2, type, \ |
2889 | &env->active_fpu.fp_status); \ | |
5f7319cd | 2890 | update_fcr31(env, GETPC()); \ |
b3d6cd44 AJ |
2891 | return fst0; \ |
2892 | } \ | |
2893 | \ | |
2894 | uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ | |
2895 | uint64_t fdt0, uint64_t fdt1, \ | |
2896 | uint64_t fdt2) \ | |
2897 | { \ | |
2898 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ | |
2899 | uint32_t fsth0 = fdt0 >> 32; \ | |
2900 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ | |
2901 | uint32_t fsth1 = fdt1 >> 32; \ | |
2902 | uint32_t fst2 = fdt2 & 0XFFFFFFFF; \ | |
2903 | uint32_t fsth2 = fdt2 >> 32; \ | |
2904 | \ | |
b3d6cd44 AJ |
2905 | fst0 = float32_muladd(fst0, fst1, fst2, type, \ |
2906 | &env->active_fpu.fp_status); \ | |
2907 | fsth0 = float32_muladd(fsth0, fsth1, fsth2, type, \ | |
2908 | &env->active_fpu.fp_status); \ | |
5f7319cd | 2909 | update_fcr31(env, GETPC()); \ |
b3d6cd44 AJ |
2910 | return ((uint64_t)fsth0 << 32) | fst0; \ |
2911 | } | |
2912 | FLOAT_FMA(madd, 0) | |
2913 | FLOAT_FMA(msub, float_muladd_negate_c) | |
2914 | FLOAT_FMA(nmadd, float_muladd_negate_result) | |
2915 | FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c) | |
2916 | #undef FLOAT_FMA | |
a16336e4 | 2917 | |
8dfdb87c | 2918 | /* MIPS specific binary operations */ |
895c2d04 | 2919 | uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) |
8dfdb87c | 2920 | { |
f01be154 | 2921 | fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); |
05993cd0 | 2922 | fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status)); |
5f7319cd | 2923 | update_fcr31(env, GETPC()); |
b6d96bed | 2924 | return fdt2; |
8dfdb87c | 2925 | } |
b6d96bed | 2926 | |
895c2d04 | 2927 | uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) |
8dfdb87c | 2928 | { |
f01be154 | 2929 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
05993cd0 | 2930 | fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status)); |
5f7319cd | 2931 | update_fcr31(env, GETPC()); |
b6d96bed | 2932 | return fst2; |
8dfdb87c | 2933 | } |
b6d96bed | 2934 | |
895c2d04 | 2935 | uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) |
8dfdb87c | 2936 | { |
b6d96bed TS |
2937 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
2938 | uint32_t fsth0 = fdt0 >> 32; | |
2939 | uint32_t fst2 = fdt2 & 0XFFFFFFFF; | |
2940 | uint32_t fsth2 = fdt2 >> 32; | |
2941 | ||
f01be154 TS |
2942 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
2943 | fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); | |
05993cd0 AJ |
2944 | fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status)); |
2945 | fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status)); | |
5f7319cd | 2946 | update_fcr31(env, GETPC()); |
b6d96bed | 2947 | return ((uint64_t)fsth2 << 32) | fst2; |
8dfdb87c TS |
2948 | } |
2949 | ||
895c2d04 | 2950 | uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) |
8dfdb87c | 2951 | { |
f01be154 | 2952 | fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); |
05993cd0 | 2953 | fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status); |
f01be154 | 2954 | fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status)); |
5f7319cd | 2955 | update_fcr31(env, GETPC()); |
b6d96bed | 2956 | return fdt2; |
8dfdb87c | 2957 | } |
b6d96bed | 2958 | |
895c2d04 | 2959 | uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) |
8dfdb87c | 2960 | { |
f01be154 | 2961 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
05993cd0 | 2962 | fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status); |
f01be154 | 2963 | fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); |
5f7319cd | 2964 | update_fcr31(env, GETPC()); |
b6d96bed | 2965 | return fst2; |
8dfdb87c | 2966 | } |
b6d96bed | 2967 | |
895c2d04 | 2968 | uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) |
8dfdb87c | 2969 | { |
b6d96bed TS |
2970 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
2971 | uint32_t fsth0 = fdt0 >> 32; | |
2972 | uint32_t fst2 = fdt2 & 0XFFFFFFFF; | |
2973 | uint32_t fsth2 = fdt2 >> 32; | |
2974 | ||
f01be154 TS |
2975 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
2976 | fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); | |
05993cd0 AJ |
2977 | fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status); |
2978 | fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status); | |
f01be154 TS |
2979 | fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); |
2980 | fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status)); | |
5f7319cd | 2981 | update_fcr31(env, GETPC()); |
b6d96bed | 2982 | return ((uint64_t)fsth2 << 32) | fst2; |
57fa1fb3 | 2983 | } |
57fa1fb3 | 2984 | |
895c2d04 | 2985 | uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) |
fd4a04eb | 2986 | { |
b6d96bed TS |
2987 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
2988 | uint32_t fsth0 = fdt0 >> 32; | |
2989 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; | |
2990 | uint32_t fsth1 = fdt1 >> 32; | |
2991 | uint32_t fst2; | |
2992 | uint32_t fsth2; | |
2993 | ||
f01be154 TS |
2994 | fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status); |
2995 | fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status); | |
5f7319cd | 2996 | update_fcr31(env, GETPC()); |
b6d96bed | 2997 | return ((uint64_t)fsth2 << 32) | fst2; |
fd4a04eb TS |
2998 | } |
2999 | ||
895c2d04 | 3000 | uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) |
57fa1fb3 | 3001 | { |
b6d96bed TS |
3002 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
3003 | uint32_t fsth0 = fdt0 >> 32; | |
3004 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; | |
3005 | uint32_t fsth1 = fdt1 >> 32; | |
3006 | uint32_t fst2; | |
3007 | uint32_t fsth2; | |
3008 | ||
f01be154 TS |
3009 | fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status); |
3010 | fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status); | |
5f7319cd | 3011 | update_fcr31(env, GETPC()); |
b6d96bed | 3012 | return ((uint64_t)fsth2 << 32) | fst2; |
57fa1fb3 TS |
3013 | } |
3014 | ||
8dfdb87c | 3015 | /* compare operations */ |
b6d96bed | 3016 | #define FOP_COND_D(op, cond) \ |
895c2d04 BS |
3017 | void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ |
3018 | uint64_t fdt1, int cc) \ | |
b6d96bed | 3019 | { \ |
6a385343 | 3020 | int c; \ |
6a385343 | 3021 | c = cond; \ |
5f7319cd | 3022 | update_fcr31(env, GETPC()); \ |
b6d96bed | 3023 | if (c) \ |
f01be154 | 3024 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 3025 | else \ |
f01be154 | 3026 | CLEAR_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 3027 | } \ |
895c2d04 BS |
3028 | void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ |
3029 | uint64_t fdt1, int cc) \ | |
b6d96bed TS |
3030 | { \ |
3031 | int c; \ | |
3032 | fdt0 = float64_abs(fdt0); \ | |
3033 | fdt1 = float64_abs(fdt1); \ | |
3034 | c = cond; \ | |
5f7319cd | 3035 | update_fcr31(env, GETPC()); \ |
b6d96bed | 3036 | if (c) \ |
f01be154 | 3037 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 3038 | else \ |
f01be154 | 3039 | CLEAR_FP_COND(cc, env->active_fpu); \ |
fd4a04eb TS |
3040 | } |
3041 | ||
fd4a04eb | 3042 | /* NOTE: the comma operator will make "cond" to eval to false, |
3a599383 AJ |
3043 | * but float64_unordered_quiet() is still called. */ |
3044 | FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0)) | |
3045 | FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)) | |
06a0e6b1 | 3046 | FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
211315fb | 3047 | FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
06a0e6b1 AJ |
3048 | FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
3049 | FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) | |
3050 | FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) | |
3051 | FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) | |
fd4a04eb | 3052 | /* NOTE: the comma operator will make "cond" to eval to false, |
3a599383 AJ |
3053 | * but float64_unordered() is still called. */ |
3054 | FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0)) | |
3055 | FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)) | |
06a0e6b1 AJ |
3056 | FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) |
3057 | FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) | |
3058 | FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) | |
3a599383 | 3059 | FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) |
06a0e6b1 | 3060 | FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) |
3a599383 | 3061 | FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) |
b6d96bed TS |
3062 | |
3063 | #define FOP_COND_S(op, cond) \ | |
895c2d04 BS |
3064 | void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ |
3065 | uint32_t fst1, int cc) \ | |
b6d96bed | 3066 | { \ |
6a385343 | 3067 | int c; \ |
6a385343 | 3068 | c = cond; \ |
5f7319cd | 3069 | update_fcr31(env, GETPC()); \ |
b6d96bed | 3070 | if (c) \ |
f01be154 | 3071 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 3072 | else \ |
f01be154 | 3073 | CLEAR_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 3074 | } \ |
895c2d04 BS |
3075 | void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ |
3076 | uint32_t fst1, int cc) \ | |
b6d96bed TS |
3077 | { \ |
3078 | int c; \ | |
3079 | fst0 = float32_abs(fst0); \ | |
3080 | fst1 = float32_abs(fst1); \ | |
3081 | c = cond; \ | |
5f7319cd | 3082 | update_fcr31(env, GETPC()); \ |
b6d96bed | 3083 | if (c) \ |
f01be154 | 3084 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 3085 | else \ |
f01be154 | 3086 | CLEAR_FP_COND(cc, env->active_fpu); \ |
fd4a04eb TS |
3087 | } |
3088 | ||
fd4a04eb | 3089 | /* NOTE: the comma operator will make "cond" to eval to false, |
3a599383 AJ |
3090 | * but float32_unordered_quiet() is still called. */ |
3091 | FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0)) | |
3092 | FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)) | |
06a0e6b1 | 3093 | FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
211315fb | 3094 | FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
06a0e6b1 AJ |
3095 | FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
3096 | FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)) | |
3097 | FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)) | |
3098 | FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)) | |
fd4a04eb | 3099 | /* NOTE: the comma operator will make "cond" to eval to false, |
3a599383 AJ |
3100 | * but float32_unordered() is still called. */ |
3101 | FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0)) | |
3102 | FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status)) | |
06a0e6b1 AJ |
3103 | FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status)) |
3104 | FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status)) | |
3105 | FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status)) | |
3a599383 | 3106 | FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status)) |
06a0e6b1 | 3107 | FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status)) |
3a599383 | 3108 | FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status)) |
b6d96bed TS |
3109 | |
3110 | #define FOP_COND_PS(op, condl, condh) \ | |
895c2d04 BS |
3111 | void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ |
3112 | uint64_t fdt1, int cc) \ | |
b6d96bed | 3113 | { \ |
6a385343 AJ |
3114 | uint32_t fst0, fsth0, fst1, fsth1; \ |
3115 | int ch, cl; \ | |
6a385343 AJ |
3116 | fst0 = fdt0 & 0XFFFFFFFF; \ |
3117 | fsth0 = fdt0 >> 32; \ | |
3118 | fst1 = fdt1 & 0XFFFFFFFF; \ | |
3119 | fsth1 = fdt1 >> 32; \ | |
3120 | cl = condl; \ | |
3121 | ch = condh; \ | |
5f7319cd | 3122 | update_fcr31(env, GETPC()); \ |
b6d96bed | 3123 | if (cl) \ |
f01be154 | 3124 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 3125 | else \ |
f01be154 | 3126 | CLEAR_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 3127 | if (ch) \ |
f01be154 | 3128 | SET_FP_COND(cc + 1, env->active_fpu); \ |
b6d96bed | 3129 | else \ |
f01be154 | 3130 | CLEAR_FP_COND(cc + 1, env->active_fpu); \ |
b6d96bed | 3131 | } \ |
895c2d04 BS |
3132 | void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ |
3133 | uint64_t fdt1, int cc) \ | |
b6d96bed | 3134 | { \ |
6a385343 AJ |
3135 | uint32_t fst0, fsth0, fst1, fsth1; \ |
3136 | int ch, cl; \ | |
3137 | fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \ | |
3138 | fsth0 = float32_abs(fdt0 >> 32); \ | |
3139 | fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \ | |
3140 | fsth1 = float32_abs(fdt1 >> 32); \ | |
3141 | cl = condl; \ | |
3142 | ch = condh; \ | |
5f7319cd | 3143 | update_fcr31(env, GETPC()); \ |
b6d96bed | 3144 | if (cl) \ |
f01be154 | 3145 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 3146 | else \ |
f01be154 | 3147 | CLEAR_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 3148 | if (ch) \ |
f01be154 | 3149 | SET_FP_COND(cc + 1, env->active_fpu); \ |
b6d96bed | 3150 | else \ |
f01be154 | 3151 | CLEAR_FP_COND(cc + 1, env->active_fpu); \ |
fd4a04eb TS |
3152 | } |
3153 | ||
3154 | /* NOTE: the comma operator will make "cond" to eval to false, | |
3a599383 AJ |
3155 | * but float32_unordered_quiet() is still called. */ |
3156 | FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0), | |
3157 | (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0)) | |
3158 | FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), | |
3159 | float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)) | |
06a0e6b1 AJ |
3160 | FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status), |
3161 | float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) | |
211315fb AJ |
3162 | FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status), |
3163 | float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) | |
06a0e6b1 AJ |
3164 | FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status), |
3165 | float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3166 | FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status), | |
3167 | float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3168 | FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status), | |
3169 | float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3170 | FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status), | |
3171 | float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) | |
fd4a04eb | 3172 | /* NOTE: the comma operator will make "cond" to eval to false, |
3a599383 AJ |
3173 | * but float32_unordered() is still called. */ |
3174 | FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0), | |
3175 | (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0)) | |
3176 | FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status), | |
3177 | float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)) | |
06a0e6b1 AJ |
3178 | FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status), |
3179 | float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3180 | FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status), | |
3181 | float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3182 | FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status), | |
3183 | float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3a599383 AJ |
3184 | FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status), |
3185 | float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) | |
06a0e6b1 AJ |
3186 | FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status), |
3187 | float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) | |
3a599383 AJ |
3188 | FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status), |
3189 | float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) |