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[qemu.git] / target-mips / op_helper.c
CommitLineData
6af0bf9c
FB		 1/*
2 * MIPS emulation helpers for qemu.
5fafdf24 3 *
6af0bf9c
FB		 4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
2d0e944d 20#include <stdlib.h>
6af0bf9c
FB		 21#include "exec.h"
22
05f778c8
TS		 23#include "host-utils.h"
24
6af0bf9c
FB		 25/*****************************************************************************/
26/* Exceptions processing helpers */
6af0bf9c 27
6af0bf9c
FB		 28void do_raise_exception_err (uint32_t exception, int error_code)
29{
30#if 1
31 if (logfile && exception < 0x100)
32 fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
33#endif
34 env->exception_index = exception;
35 env->error_code = error_code;
6af0bf9c
FB		 36 cpu_loop_exit();
37}
38
6af0bf9c
FB		 39void do_raise_exception (uint32_t exception)
40{
41 do_raise_exception_err(exception, 0);
42}
43
48d38ca5
TS		 44void do_interrupt_restart (void)
45{
46 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
47 !(env->CP0_Status & (1 << CP0St_ERL)) &&
48 !(env->hflags & MIPS_HFLAG_DM) &&
49 (env->CP0_Status & (1 << CP0St_IE)) &&
50 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
51 env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
52 do_raise_exception(EXCP_EXT_INTERRUPT);
53 }
54}
55
4ad40f36
FB		 56void do_restore_state (void *pc_ptr)
57{
a607922c
FB		 58 TranslationBlock *tb;
59 unsigned long pc = (unsigned long) pc_ptr;
60
61 tb = tb_find_pc (pc);
62 if (tb) {
63 cpu_restore_state (tb, env, pc, NULL);
64 }
4ad40f36
FB		 65}
66
be24bb4f 67target_ulong do_clo (target_ulong t0)
30898801 68{
be24bb4f 69 return clo32(t0);
30898801
TS		 70}
71
be24bb4f 72target_ulong do_clz (target_ulong t0)
30898801 73{
be24bb4f 74 return clz32(t0);
30898801
TS		 75}
76
d26bc211 77#if defined(TARGET_MIPS64)
be24bb4f 78target_ulong do_dclo (target_ulong t0)
05f778c8 79{
be24bb4f 80 return clo64(t0);
05f778c8
TS		 81}
82
be24bb4f 83target_ulong do_dclz (target_ulong t0)
05f778c8 84{
be24bb4f 85 return clz64(t0);
05f778c8 86}
d26bc211 87#endif /* TARGET_MIPS64 */
c570fd16 88
6af0bf9c 89/* 64 bits arithmetic for 32 bits hosts */
aa343735 90static always_inline uint64_t get_HILO (void)
6af0bf9c 91{
92af06d2 92 return ((uint64_t)(env->HI[env->current_tc][0]) << 32) | (uint32_t)env->LO[env->current_tc][0];
6af0bf9c
FB		 93}
94
aa343735 95static always_inline void set_HILO (uint64_t HILO)
6af0bf9c 96{
d0dc7dc3
TS		 97 env->LO[env->current_tc][0] = (int32_t)HILO;
98 env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
6af0bf9c
FB		 99}
100
be24bb4f 101static always_inline void set_HIT0_LO (target_ulong t0, uint64_t HILO)
e9c71dd1 102{
d0dc7dc3 103 env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);
be24bb4f 104 t0 = env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
e9c71dd1
TS		 105}
106
be24bb4f 107static always_inline void set_HI_LOT0 (target_ulong t0, uint64_t HILO)
e9c71dd1 108{
be24bb4f 109 t0 = env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);
d0dc7dc3 110 env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
e9c71dd1
TS		 111}
112
92af06d2 113#if TARGET_LONG_BITS > HOST_LONG_BITS
be24bb4f 114void do_madd (target_ulong t0, target_ulong t1)
6af0bf9c
FB		 115{
116 int64_t tmp;
117
be24bb4f 118 tmp = ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
6af0bf9c
FB		 119 set_HILO((int64_t)get_HILO() + tmp);
120}
121
be24bb4f 122void do_maddu (target_ulong t0, target_ulong t1)
6af0bf9c
FB		 123{
124 uint64_t tmp;
125
be24bb4f 126 tmp = ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
6af0bf9c
FB		 127 set_HILO(get_HILO() + tmp);
128}
129
be24bb4f 130void do_msub (target_ulong t0, target_ulong t1)
6af0bf9c
FB		 131{
132 int64_t tmp;
133
be24bb4f 134 tmp = ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
6af0bf9c
FB		 135 set_HILO((int64_t)get_HILO() - tmp);
136}
137
be24bb4f 138void do_msubu (target_ulong t0, target_ulong t1)
6af0bf9c
FB		 139{
140 uint64_t tmp;
141
be24bb4f 142 tmp = ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
6af0bf9c
FB		 143 set_HILO(get_HILO() - tmp);
144}
92af06d2 145#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
e9c71dd1
TS		 146
147/* Multiplication variants of the vr54xx. */
be24bb4f 148target_ulong do_muls (target_ulong t0, target_ulong t1)
e9c71dd1 149{
be24bb4f
TS		 150 set_HI_LOT0(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
151
152 return t0;
e9c71dd1
TS		 153}
154
be24bb4f 155target_ulong do_mulsu (target_ulong t0, target_ulong t1)
e9c71dd1 156{
be24bb4f
TS		 157 set_HI_LOT0(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
158
159 return t0;
e9c71dd1
TS		 160}
161
be24bb4f 162target_ulong do_macc (target_ulong t0, target_ulong t1)
e9c71dd1 163{
be24bb4f
TS		 164 set_HI_LOT0(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
165
166 return t0;
e9c71dd1
TS		 167}
168
be24bb4f 169target_ulong do_macchi (target_ulong t0, target_ulong t1)
e9c71dd1 170{
be24bb4f
TS		 171 set_HIT0_LO(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
172
173 return t0;
e9c71dd1
TS		 174}
175
be24bb4f 176target_ulong do_maccu (target_ulong t0, target_ulong t1)
e9c71dd1 177{
be24bb4f
TS		 178 set_HI_LOT0(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
179
180 return t0;
e9c71dd1
TS		 181}
182
be24bb4f 183target_ulong do_macchiu (target_ulong t0, target_ulong t1)
e9c71dd1 184{
be24bb4f
TS		 185 set_HIT0_LO(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
186
187 return t0;
e9c71dd1
TS		 188}
189
be24bb4f 190target_ulong do_msac (target_ulong t0, target_ulong t1)
e9c71dd1 191{
be24bb4f
TS		 192 set_HI_LOT0(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
193
194 return t0;
e9c71dd1
TS		 195}
196
be24bb4f 197target_ulong do_msachi (target_ulong t0, target_ulong t1)
e9c71dd1 198{
be24bb4f
TS		 199 set_HIT0_LO(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
200
201 return t0;
e9c71dd1
TS		 202}
203
be24bb4f 204target_ulong do_msacu (target_ulong t0, target_ulong t1)
e9c71dd1 205{
be24bb4f
TS		 206 set_HI_LOT0(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
207
208 return t0;
e9c71dd1
TS		 209}
210
be24bb4f 211target_ulong do_msachiu (target_ulong t0, target_ulong t1)
e9c71dd1 212{
be24bb4f
TS		 213 set_HIT0_LO(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
214
215 return t0;
e9c71dd1
TS		 216}
217
be24bb4f 218target_ulong do_mulhi (target_ulong t0, target_ulong t1)
e9c71dd1 219{
be24bb4f
TS		 220 set_HIT0_LO(t0, (int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
221
222 return t0;
e9c71dd1
TS		 223}
224
be24bb4f 225target_ulong do_mulhiu (target_ulong t0, target_ulong t1)
e9c71dd1 226{
be24bb4f
TS		 227 set_HIT0_LO(t0, (uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
228
229 return t0;
e9c71dd1
TS		 230}
231
be24bb4f 232target_ulong do_mulshi (target_ulong t0, target_ulong t1)
e9c71dd1 233{
be24bb4f
TS		 234 set_HIT0_LO(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
235
236 return t0;
e9c71dd1
TS		 237}
238
be24bb4f 239target_ulong do_mulshiu (target_ulong t0, target_ulong t1)
e9c71dd1 240{
be24bb4f
TS		 241 set_HIT0_LO(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
242
243 return t0;
e9c71dd1 244}
6af0bf9c 245
214c465f 246#ifdef TARGET_MIPS64
be24bb4f 247void do_dmult (target_ulong t0, target_ulong t1)
214c465f 248{
be24bb4f 249 muls64(&(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), t0, t1);
214c465f
TS		 250}
251
be24bb4f 252void do_dmultu (target_ulong t0, target_ulong t1)
214c465f 253{
be24bb4f 254 mulu64(&(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), t0, t1);
214c465f
TS		 255}
256#endif
257
c8c2227e
TS		 258#ifdef TARGET_WORDS_BIGENDIAN
259#define GET_LMASK(v) ((v) & 3)
260#define GET_OFFSET(addr, offset) (addr + (offset))
261#else
262#define GET_LMASK(v) (((v) & 3) ^ 3)
263#define GET_OFFSET(addr, offset) (addr - (offset))
264#endif
265
be24bb4f 266target_ulong do_lwl(target_ulong t0, target_ulong t1, int mem_idx)
c8c2227e
TS		 267{
268 target_ulong tmp;
269
270#ifdef CONFIG_USER_ONLY
271#define ldfun ldub_raw
272#else
273 int (*ldfun)(target_ulong);
274
275 switch (mem_idx)
276 {
277 case 0: ldfun = ldub_kernel; break;
278 case 1: ldfun = ldub_super; break;
279 default:
280 case 2: ldfun = ldub_user; break;
281 }
282#endif
be24bb4f
TS		 283 tmp = ldfun(t0);
284 t1 = (t1 & 0x00FFFFFF) | (tmp << 24);
c8c2227e 285
be24bb4f
TS		 286 if (GET_LMASK(t0) <= 2) {
287 tmp = ldfun(GET_OFFSET(t0, 1));
288 t1 = (t1 & 0xFF00FFFF) | (tmp << 16);
c8c2227e
TS		 289 }
290
be24bb4f
TS		 291 if (GET_LMASK(t0) <= 1) {
292 tmp = ldfun(GET_OFFSET(t0, 2));
293 t1 = (t1 & 0xFFFF00FF) | (tmp << 8);
c8c2227e
TS		 294 }
295
be24bb4f
TS		 296 if (GET_LMASK(t0) == 0) {
297 tmp = ldfun(GET_OFFSET(t0, 3));
298 t1 = (t1 & 0xFFFFFF00) | tmp;
c8c2227e 299 }
be24bb4f 300 return (int32_t)t1;
c8c2227e
TS		 301}
302
be24bb4f 303target_ulong do_lwr(target_ulong t0, target_ulong t1, int mem_idx)
c8c2227e
TS		 304{
305 target_ulong tmp;
306
307#ifdef CONFIG_USER_ONLY
308#define ldfun ldub_raw
309#else
310 int (*ldfun)(target_ulong);
311
312 switch (mem_idx)
313 {
314 case 0: ldfun = ldub_kernel; break;
315 case 1: ldfun = ldub_super; break;
316 default:
317 case 2: ldfun = ldub_user; break;
318 }
319#endif
be24bb4f
TS		 320 tmp = ldfun(t0);
321 t1 = (t1 & 0xFFFFFF00) | tmp;
c8c2227e 322
be24bb4f
TS		 323 if (GET_LMASK(t0) >= 1) {
324 tmp = ldfun(GET_OFFSET(t0, -1));
325 t1 = (t1 & 0xFFFF00FF) | (tmp << 8);
c8c2227e
TS		 326 }
327
be24bb4f
TS		 328 if (GET_LMASK(t0) >= 2) {
329 tmp = ldfun(GET_OFFSET(t0, -2));
330 t1 = (t1 & 0xFF00FFFF) | (tmp << 16);
c8c2227e
TS		 331 }
332
be24bb4f
TS		 333 if (GET_LMASK(t0) == 3) {
334 tmp = ldfun(GET_OFFSET(t0, -3));
335 t1 = (t1 & 0x00FFFFFF) | (tmp << 24);
c8c2227e 336 }
be24bb4f 337 return (int32_t)t1;
c8c2227e
TS		 338}
339
be24bb4f 340void do_swl(target_ulong t0, target_ulong t1, int mem_idx)
c8c2227e
TS		 341{
342#ifdef CONFIG_USER_ONLY
343#define stfun stb_raw
344#else
345 void (*stfun)(target_ulong, int);
346
347 switch (mem_idx)
348 {
349 case 0: stfun = stb_kernel; break;
350 case 1: stfun = stb_super; break;
351 default:
352 case 2: stfun = stb_user; break;
353 }
354#endif
be24bb4f 355 stfun(t0, (uint8_t)(t1 >> 24));
c8c2227e 356
be24bb4f
TS		 357 if (GET_LMASK(t0) <= 2)
358 stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 16));
c8c2227e 359
be24bb4f
TS		 360 if (GET_LMASK(t0) <= 1)
361 stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 8));
c8c2227e 362
be24bb4f
TS		 363 if (GET_LMASK(t0) == 0)
364 stfun(GET_OFFSET(t0, 3), (uint8_t)t1);
c8c2227e
TS		 365}
366
be24bb4f 367void do_swr(target_ulong t0, target_ulong t1, int mem_idx)
c8c2227e
TS		 368{
369#ifdef CONFIG_USER_ONLY
370#define stfun stb_raw
371#else
372 void (*stfun)(target_ulong, int);
373
374 switch (mem_idx)
375 {
376 case 0: stfun = stb_kernel; break;
377 case 1: stfun = stb_super; break;
378 default:
379 case 2: stfun = stb_user; break;
380 }
381#endif
be24bb4f 382 stfun(t0, (uint8_t)t1);
c8c2227e 383
be24bb4f
TS		 384 if (GET_LMASK(t0) >= 1)
385 stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));
c8c2227e 386
be24bb4f
TS		 387 if (GET_LMASK(t0) >= 2)
388 stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));
c8c2227e 389
be24bb4f
TS		 390 if (GET_LMASK(t0) == 3)
391 stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));
c8c2227e
TS		 392}
393
394#if defined(TARGET_MIPS64)
395/* "half" load and stores. We must do the memory access inline,
396 or fault handling won't work. */
397
398#ifdef TARGET_WORDS_BIGENDIAN
399#define GET_LMASK64(v) ((v) & 7)
400#else
401#define GET_LMASK64(v) (((v) & 7) ^ 7)
402#endif
403
be24bb4f 404target_ulong do_ldl(target_ulong t0, target_ulong t1, int mem_idx)
c8c2227e
TS		 405{
406 uint64_t tmp;
407
408#ifdef CONFIG_USER_ONLY
409#define ldfun ldub_raw
410#else
be24bb4f 411 int (*ldfun)(target_ulong);
c8c2227e
TS		 412
413 switch (mem_idx)
414 {
415 case 0: ldfun = ldub_kernel; break;
416 case 1: ldfun = ldub_super; break;
417 default:
418 case 2: ldfun = ldub_user; break;
419 }
420#endif
be24bb4f
TS		 421 tmp = ldfun(t0);
422 t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
c8c2227e 423
be24bb4f
TS		 424 if (GET_LMASK64(t0) <= 6) {
425 tmp = ldfun(GET_OFFSET(t0, 1));
426 t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
c8c2227e
TS		 427 }
428
be24bb4f
TS		 429 if (GET_LMASK64(t0) <= 5) {
430 tmp = ldfun(GET_OFFSET(t0, 2));
431 t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
c8c2227e
TS		 432 }
433
be24bb4f
TS		 434 if (GET_LMASK64(t0) <= 4) {
435 tmp = ldfun(GET_OFFSET(t0, 3));
436 t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
c8c2227e
TS		 437 }
438
be24bb4f
TS		 439 if (GET_LMASK64(t0) <= 3) {
440 tmp = ldfun(GET_OFFSET(t0, 4));
441 t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
c8c2227e
TS		 442 }
443
be24bb4f
TS		 444 if (GET_LMASK64(t0) <= 2) {
445 tmp = ldfun(GET_OFFSET(t0, 5));
446 t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
c8c2227e
TS		 447 }
448
be24bb4f
TS		 449 if (GET_LMASK64(t0) <= 1) {
450 tmp = ldfun(GET_OFFSET(t0, 6));
451 t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
c8c2227e
TS		 452 }
453
be24bb4f
TS		 454 if (GET_LMASK64(t0) == 0) {
455 tmp = ldfun(GET_OFFSET(t0, 7));
456 t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
c8c2227e 457 }
be24bb4f
TS		 458
459 return t1;
c8c2227e
TS		 460}
461
be24bb4f 462target_ulong do_ldr(target_ulong t0, target_ulong t1, int mem_idx)
c8c2227e
TS		 463{
464 uint64_t tmp;
465
466#ifdef CONFIG_USER_ONLY
467#define ldfun ldub_raw
468#else
be24bb4f 469 int (*ldfun)(target_ulong);
c8c2227e
TS		 470
471 switch (mem_idx)
472 {
473 case 0: ldfun = ldub_kernel; break;
474 case 1: ldfun = ldub_super; break;
475 default:
476 case 2: ldfun = ldub_user; break;
477 }
478#endif
be24bb4f
TS		 479 tmp = ldfun(t0);
480 t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
c8c2227e 481
be24bb4f
TS		 482 if (GET_LMASK64(t0) >= 1) {
483 tmp = ldfun(GET_OFFSET(t0, -1));
484 t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
c8c2227e
TS		 485 }
486
be24bb4f
TS		 487 if (GET_LMASK64(t0) >= 2) {
488 tmp = ldfun(GET_OFFSET(t0, -2));
489 t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
c8c2227e
TS		 490 }
491
be24bb4f
TS		 492 if (GET_LMASK64(t0) >= 3) {
493 tmp = ldfun(GET_OFFSET(t0, -3));
494 t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
c8c2227e
TS		 495 }
496
be24bb4f
TS		 497 if (GET_LMASK64(t0) >= 4) {
498 tmp = ldfun(GET_OFFSET(t0, -4));
499 t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
c8c2227e
TS		 500 }
501
be24bb4f
TS		 502 if (GET_LMASK64(t0) >= 5) {
503 tmp = ldfun(GET_OFFSET(t0, -5));
504 t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
c8c2227e
TS		 505 }
506
be24bb4f
TS		 507 if (GET_LMASK64(t0) >= 6) {
508 tmp = ldfun(GET_OFFSET(t0, -6));
509 t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
c8c2227e
TS		 510 }
511
be24bb4f
TS		 512 if (GET_LMASK64(t0) == 7) {
513 tmp = ldfun(GET_OFFSET(t0, -7));
514 t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
c8c2227e 515 }
be24bb4f
TS		 516
517 return t1;
c8c2227e
TS		 518}
519
be24bb4f 520void do_sdl(target_ulong t0, target_ulong t1, int mem_idx)
c8c2227e
TS		 521{
522#ifdef CONFIG_USER_ONLY
523#define stfun stb_raw
524#else
525 void (*stfun)(target_ulong, int);
526
527 switch (mem_idx)
528 {
529 case 0: stfun = stb_kernel; break;
530 case 1: stfun = stb_super; break;
531 default:
532 case 2: stfun = stb_user; break;
533 }
534#endif
be24bb4f 535 stfun(t0, (uint8_t)(t1 >> 56));
c8c2227e 536
be24bb4f
TS		 537 if (GET_LMASK64(t0) <= 6)
538 stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 48));
c8c2227e 539
be24bb4f
TS		 540 if (GET_LMASK64(t0) <= 5)
541 stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 40));
c8c2227e 542
be24bb4f
TS		 543 if (GET_LMASK64(t0) <= 4)
544 stfun(GET_OFFSET(t0, 3), (uint8_t)(t1 >> 32));
c8c2227e 545
be24bb4f
TS		 546 if (GET_LMASK64(t0) <= 3)
547 stfun(GET_OFFSET(t0, 4), (uint8_t)(t1 >> 24));
c8c2227e 548
be24bb4f
TS		 549 if (GET_LMASK64(t0) <= 2)
550 stfun(GET_OFFSET(t0, 5), (uint8_t)(t1 >> 16));
c8c2227e 551
be24bb4f
TS		 552 if (GET_LMASK64(t0) <= 1)
553 stfun(GET_OFFSET(t0, 6), (uint8_t)(t1 >> 8));
c8c2227e 554
be24bb4f
TS		 555 if (GET_LMASK64(t0) <= 0)
556 stfun(GET_OFFSET(t0, 7), (uint8_t)t1);
c8c2227e
TS		 557}
558
be24bb4f 559void do_sdr(target_ulong t0, target_ulong t1, int mem_idx)
c8c2227e
TS		 560{
561#ifdef CONFIG_USER_ONLY
562#define stfun stb_raw
563#else
564 void (*stfun)(target_ulong, int);
565
566 switch (mem_idx)
567 {
568 case 0: stfun = stb_kernel; break;
569 case 1: stfun = stb_super; break;
570 default:
571 case 2: stfun = stb_user; break;
572 }
573#endif
be24bb4f 574 stfun(t0, (uint8_t)t1);
c8c2227e 575
be24bb4f
TS		 576 if (GET_LMASK64(t0) >= 1)
577 stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));
c8c2227e 578
be24bb4f
TS		 579 if (GET_LMASK64(t0) >= 2)
580 stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));
c8c2227e 581
be24bb4f
TS		 582 if (GET_LMASK64(t0) >= 3)
583 stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));
c8c2227e 584
be24bb4f
TS		 585 if (GET_LMASK64(t0) >= 4)
586 stfun(GET_OFFSET(t0, -4), (uint8_t)(t1 >> 32));
c8c2227e 587
be24bb4f
TS		 588 if (GET_LMASK64(t0) >= 5)
589 stfun(GET_OFFSET(t0, -5), (uint8_t)(t1 >> 40));
c8c2227e 590
be24bb4f
TS		 591 if (GET_LMASK64(t0) >= 6)
592 stfun(GET_OFFSET(t0, -6), (uint8_t)(t1 >> 48));
c8c2227e 593
be24bb4f
TS		 594 if (GET_LMASK64(t0) == 7)
595 stfun(GET_OFFSET(t0, -7), (uint8_t)(t1 >> 56));
c8c2227e
TS		 596}
597#endif /* TARGET_MIPS64 */
598
f1aa6320 599#ifdef CONFIG_USER_ONLY
873eb012 600void do_mfc0_random (void)
048f6b4d 601{
873eb012 602 cpu_abort(env, "mfc0 random\n");
048f6b4d 603}
873eb012
TS		 604
605void do_mfc0_count (void)
606{
607 cpu_abort(env, "mfc0 count\n");
608}
609
8c0fdd85 610void cpu_mips_store_count(CPUState *env, uint32_t value)
048f6b4d 611{
8c0fdd85
TS		 612 cpu_abort(env, "mtc0 count\n");
613}
614
615void cpu_mips_store_compare(CPUState *env, uint32_t value)
616{
617 cpu_abort(env, "mtc0 compare\n");
618}
619
42532189
TS		 620void cpu_mips_start_count(CPUState *env)
621{
622 cpu_abort(env, "start count\n");
623}
624
625void cpu_mips_stop_count(CPUState *env)
626{
627 cpu_abort(env, "stop count\n");
628}
629
4de9b249
TS		 630void cpu_mips_update_irq(CPUState *env)
631{
632 cpu_abort(env, "mtc0 status / mtc0 cause\n");
633}
634
8c0fdd85
TS		 635void do_mtc0_status_debug(uint32_t old, uint32_t val)
636{
7a387fff 637 cpu_abort(env, "mtc0 status debug\n");
8c0fdd85
TS		 638}
639
7a387fff 640void do_mtc0_status_irqraise_debug (void)
8c0fdd85 641{
7a387fff 642 cpu_abort(env, "mtc0 status irqraise debug\n");
048f6b4d
FB		 643}
644
8c0fdd85
TS		 645void cpu_mips_tlb_flush (CPUState *env, int flush_global)
646{
647 cpu_abort(env, "mips_tlb_flush\n");
648}
649
048f6b4d
FB		 650#else
651
6af0bf9c 652/* CP0 helpers */
be24bb4f 653target_ulong do_mfc0_mvpcontrol (target_ulong t0)
f1aa6320 654{
be24bb4f 655 return env->mvp->CP0_MVPControl;
f1aa6320
TS		 656}
657
be24bb4f 658target_ulong do_mfc0_mvpconf0 (target_ulong t0)
f1aa6320 659{
be24bb4f 660 return env->mvp->CP0_MVPConf0;
f1aa6320
TS		 661}
662
be24bb4f 663target_ulong do_mfc0_mvpconf1 (target_ulong t0)
f1aa6320 664{
be24bb4f 665 return env->mvp->CP0_MVPConf1;
f1aa6320
TS		 666}
667
be24bb4f 668target_ulong do_mfc0_random (target_ulong t0)
6af0bf9c 669{
be24bb4f 670 return (int32_t)cpu_mips_get_random(env);
873eb012 671}
6af0bf9c 672
be24bb4f 673target_ulong do_mfc0_tcstatus (target_ulong t0)
f1aa6320 674{
be24bb4f 675 return env->CP0_TCStatus[env->current_tc];
f1aa6320
TS		 676}
677
be24bb4f 678target_ulong do_mftc0_tcstatus(target_ulong t0)
f1aa6320
TS		 679{
680 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
681
be24bb4f 682 return env->CP0_TCStatus[other_tc];
f1aa6320
TS		 683}
684
be24bb4f 685target_ulong do_mfc0_tcbind (target_ulong t0)
f1aa6320 686{
be24bb4f 687 return env->CP0_TCBind[env->current_tc];
f1aa6320
TS		 688}
689
be24bb4f 690target_ulong do_mftc0_tcbind(target_ulong t0)
f1aa6320
TS		 691{
692 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
693
be24bb4f 694 return env->CP0_TCBind[other_tc];
f1aa6320
TS		 695}
696
be24bb4f 697target_ulong do_mfc0_tcrestart (target_ulong t0)
f1aa6320 698{
be24bb4f 699 return env->PC[env->current_tc];
f1aa6320
TS		 700}
701
be24bb4f 702target_ulong do_mftc0_tcrestart(target_ulong t0)
f1aa6320
TS		 703{
704 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
705
be24bb4f 706 return env->PC[other_tc];
f1aa6320
TS		 707}
708
be24bb4f 709target_ulong do_mfc0_tchalt (target_ulong t0)
f1aa6320 710{
be24bb4f 711 return env->CP0_TCHalt[env->current_tc];
f1aa6320
TS		 712}
713
be24bb4f 714target_ulong do_mftc0_tchalt(target_ulong t0)
f1aa6320
TS		 715{
716 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
717
be24bb4f 718 return env->CP0_TCHalt[other_tc];
f1aa6320
TS		 719}
720
be24bb4f 721target_ulong do_mfc0_tccontext (target_ulong t0)
f1aa6320 722{
be24bb4f 723 return env->CP0_TCContext[env->current_tc];
f1aa6320
TS		 724}
725
be24bb4f 726target_ulong do_mftc0_tccontext(target_ulong t0)
f1aa6320
TS		 727{
728 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
729
be24bb4f 730 return env->CP0_TCContext[other_tc];
f1aa6320
TS		 731}
732
be24bb4f 733target_ulong do_mfc0_tcschedule (target_ulong t0)
f1aa6320 734{
be24bb4f 735 return env->CP0_TCSchedule[env->current_tc];
f1aa6320
TS		 736}
737
be24bb4f 738target_ulong do_mftc0_tcschedule(target_ulong t0)
f1aa6320
TS		 739{
740 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
741
be24bb4f 742 return env->CP0_TCSchedule[other_tc];
f1aa6320
TS		 743}
744
be24bb4f 745target_ulong do_mfc0_tcschefback (target_ulong t0)
f1aa6320 746{
be24bb4f 747 return env->CP0_TCScheFBack[env->current_tc];
f1aa6320
TS		 748}
749
be24bb4f 750target_ulong do_mftc0_tcschefback(target_ulong t0)
f1aa6320
TS		 751{
752 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
753
be24bb4f 754 return env->CP0_TCScheFBack[other_tc];
f1aa6320
TS		 755}
756
be24bb4f 757target_ulong do_mfc0_count (target_ulong t0)
873eb012 758{
be24bb4f 759 return (int32_t)cpu_mips_get_count(env);
6af0bf9c
FB		 760}
761
be24bb4f 762target_ulong do_mftc0_entryhi(target_ulong t0)
f1aa6320
TS		 763{
764 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
765
be24bb4f 766 return (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff);
f1aa6320
TS		 767}
768
be24bb4f 769target_ulong do_mftc0_status(target_ulong t0)
f1aa6320
TS		 770{
771 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
772 uint32_t tcstatus = env->CP0_TCStatus[other_tc];
773
be24bb4f
TS		 774 t0 = env->CP0_Status & ~0xf1000018;
775 t0 |= tcstatus & (0xf << CP0TCSt_TCU0);
776 t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
777 t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
778
779 return t0;
f1aa6320
TS		 780}
781
be24bb4f 782target_ulong do_mfc0_lladdr (target_ulong t0)
f1aa6320 783{
be24bb4f 784 return (int32_t)env->CP0_LLAddr >> 4;
f1aa6320
TS		 785}
786
be24bb4f 787target_ulong do_mfc0_watchlo (target_ulong t0, uint32_t sel)
f1aa6320 788{
be24bb4f 789 return (int32_t)env->CP0_WatchLo[sel];
f1aa6320
TS		 790}
791
be24bb4f 792target_ulong do_mfc0_watchhi (target_ulong t0, uint32_t sel)
f1aa6320 793{
be24bb4f 794 return env->CP0_WatchHi[sel];
f1aa6320
TS		 795}
796
be24bb4f 797target_ulong do_mfc0_debug (target_ulong t0)
f1aa6320 798{
be24bb4f 799 t0 = env->CP0_Debug;
f1aa6320 800 if (env->hflags & MIPS_HFLAG_DM)
be24bb4f
TS		 801 t0 |= 1 << CP0DB_DM;
802
803 return t0;
f1aa6320
TS		 804}
805
be24bb4f 806target_ulong do_mftc0_debug(target_ulong t0)
f1aa6320
TS		 807{
808 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
809
810 /* XXX: Might be wrong, check with EJTAG spec. */
be24bb4f
TS		 811 return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
812 (env->CP0_Debug_tcstatus[other_tc] &
813 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
f1aa6320
TS		 814}
815
816#if defined(TARGET_MIPS64)
be24bb4f 817target_ulong do_dmfc0_tcrestart (target_ulong t0)
f1aa6320 818{
be24bb4f 819 return env->PC[env->current_tc];
f1aa6320
TS		 820}
821
be24bb4f 822target_ulong do_dmfc0_tchalt (target_ulong t0)
f1aa6320 823{
be24bb4f 824 return env->CP0_TCHalt[env->current_tc];
f1aa6320
TS		 825}
826
be24bb4f 827target_ulong do_dmfc0_tccontext (target_ulong t0)
f1aa6320 828{
be24bb4f 829 return env->CP0_TCContext[env->current_tc];
f1aa6320
TS		 830}
831
be24bb4f 832target_ulong do_dmfc0_tcschedule (target_ulong t0)
f1aa6320 833{
be24bb4f 834 return env->CP0_TCSchedule[env->current_tc];
f1aa6320
TS		 835}
836
be24bb4f 837target_ulong do_dmfc0_tcschefback (target_ulong t0)
f1aa6320 838{
be24bb4f 839 return env->CP0_TCScheFBack[env->current_tc];
f1aa6320
TS		 840}
841
be24bb4f 842target_ulong do_dmfc0_lladdr (target_ulong t0)
f1aa6320 843{
be24bb4f 844 return env->CP0_LLAddr >> 4;
f1aa6320
TS		 845}
846
be24bb4f 847target_ulong do_dmfc0_watchlo (target_ulong t0, uint32_t sel)
f1aa6320 848{
be24bb4f 849 return env->CP0_WatchLo[sel];
f1aa6320
TS		 850}
851#endif /* TARGET_MIPS64 */
852
be24bb4f 853void do_mtc0_index (target_ulong t0)
f1aa6320
TS		 854{
855 int num = 1;
856 unsigned int tmp = env->tlb->nb_tlb;
857
858 do {
859 tmp >>= 1;
860 num <<= 1;
861 } while (tmp);
be24bb4f 862 env->CP0_Index = (env->CP0_Index & 0x80000000) | (t0 & (num - 1));
f1aa6320
TS		 863}
864
be24bb4f 865void do_mtc0_mvpcontrol (target_ulong t0)
f1aa6320
TS		 866{
867 uint32_t mask = 0;
868 uint32_t newval;
869
870 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
871 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
872 (1 << CP0MVPCo_EVP);
873 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
874 mask |= (1 << CP0MVPCo_STLB);
be24bb4f 875 newval = (env->mvp->CP0_MVPControl & ~mask) | (t0 & mask);
f1aa6320
TS		 876
877 // TODO: Enable/disable shared TLB, enable/disable VPEs.
878
879 env->mvp->CP0_MVPControl = newval;
880}
881
be24bb4f 882void do_mtc0_vpecontrol (target_ulong t0)
f1aa6320
TS		 883{
884 uint32_t mask;
885 uint32_t newval;
886
887 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
888 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
be24bb4f 889 newval = (env->CP0_VPEControl & ~mask) | (t0 & mask);
f1aa6320
TS		 890
891 /* Yield scheduler intercept not implemented. */
892 /* Gating storage scheduler intercept not implemented. */
893
894 // TODO: Enable/disable TCs.
895
896 env->CP0_VPEControl = newval;
897}
898
be24bb4f 899void do_mtc0_vpeconf0 (target_ulong t0)
f1aa6320
TS		 900{
901 uint32_t mask = 0;
902 uint32_t newval;
903
904 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
905 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
906 mask |= (0xff << CP0VPEC0_XTC);
907 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
908 }
be24bb4f 909 newval = (env->CP0_VPEConf0 & ~mask) | (t0 & mask);
f1aa6320
TS		 910
911 // TODO: TC exclusive handling due to ERL/EXL.
912
913 env->CP0_VPEConf0 = newval;
914}
915
be24bb4f 916void do_mtc0_vpeconf1 (target_ulong t0)
f1aa6320
TS		 917{
918 uint32_t mask = 0;
919 uint32_t newval;
920
921 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
922 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
923 (0xff << CP0VPEC1_NCP1);
be24bb4f 924 newval = (env->CP0_VPEConf1 & ~mask) | (t0 & mask);
f1aa6320
TS		 925
926 /* UDI not implemented. */
927 /* CP2 not implemented. */
928
929 // TODO: Handle FPU (CP1) binding.
930
931 env->CP0_VPEConf1 = newval;
932}
933
be24bb4f 934void do_mtc0_yqmask (target_ulong t0)
f1aa6320
TS		 935{
936 /* Yield qualifier inputs not implemented. */
937 env->CP0_YQMask = 0x00000000;
938}
939
be24bb4f 940void do_mtc0_vpeopt (target_ulong t0)
f1aa6320 941{
be24bb4f 942 env->CP0_VPEOpt = t0 & 0x0000ffff;
f1aa6320
TS		 943}
944
be24bb4f 945void do_mtc0_entrylo0 (target_ulong t0)
f1aa6320
TS		 946{
947 /* Large physaddr (PABITS) not implemented */
948 /* 1k pages not implemented */
be24bb4f 949 env->CP0_EntryLo0 = t0 & 0x3FFFFFFF;
f1aa6320
TS		 950}
951
be24bb4f 952void do_mtc0_tcstatus (target_ulong t0)
f1aa6320
TS		 953{
954 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
955 uint32_t newval;
956
be24bb4f 957 newval = (env->CP0_TCStatus[env->current_tc] & ~mask) | (t0 & mask);
f1aa6320
TS		 958
959 // TODO: Sync with CP0_Status.
960
961 env->CP0_TCStatus[env->current_tc] = newval;
962}
963
be24bb4f 964void do_mttc0_tcstatus (target_ulong t0)
f1aa6320
TS		 965{
966 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
967
968 // TODO: Sync with CP0_Status.
969
be24bb4f 970 env->CP0_TCStatus[other_tc] = t0;
f1aa6320
TS		 971}
972
be24bb4f 973void do_mtc0_tcbind (target_ulong t0)
f1aa6320
TS		 974{
975 uint32_t mask = (1 << CP0TCBd_TBE);
976 uint32_t newval;
977
978 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
979 mask |= (1 << CP0TCBd_CurVPE);
be24bb4f 980 newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (t0 & mask);
f1aa6320
TS		 981 env->CP0_TCBind[env->current_tc] = newval;
982}
983
be24bb4f 984void do_mttc0_tcbind (target_ulong t0)
f1aa6320
TS		 985{
986 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
987 uint32_t mask = (1 << CP0TCBd_TBE);
988 uint32_t newval;
989
990 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
991 mask |= (1 << CP0TCBd_CurVPE);
be24bb4f 992 newval = (env->CP0_TCBind[other_tc] & ~mask) | (t0 & mask);
f1aa6320
TS		 993 env->CP0_TCBind[other_tc] = newval;
994}
995
be24bb4f 996void do_mtc0_tcrestart (target_ulong t0)
f1aa6320 997{
be24bb4f 998 env->PC[env->current_tc] = t0;
f1aa6320
TS		 999 env->CP0_TCStatus[env->current_tc] &= ~(1 << CP0TCSt_TDS);
1000 env->CP0_LLAddr = 0ULL;
1001 /* MIPS16 not implemented. */
1002}
1003
be24bb4f 1004void do_mttc0_tcrestart (target_ulong t0)
f1aa6320
TS		 1005{
1006 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1007
be24bb4f 1008 env->PC[other_tc] = t0;
f1aa6320
TS		 1009 env->CP0_TCStatus[other_tc] &= ~(1 << CP0TCSt_TDS);
1010 env->CP0_LLAddr = 0ULL;
1011 /* MIPS16 not implemented. */
1012}
1013
be24bb4f 1014void do_mtc0_tchalt (target_ulong t0)
f1aa6320 1015{
be24bb4f 1016 env->CP0_TCHalt[env->current_tc] = t0 & 0x1;
f1aa6320
TS		 1017
1018 // TODO: Halt TC / Restart (if allocated+active) TC.
1019}
1020
be24bb4f 1021void do_mttc0_tchalt (target_ulong t0)
f1aa6320
TS		 1022{
1023 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1024
1025 // TODO: Halt TC / Restart (if allocated+active) TC.
1026
be24bb4f 1027 env->CP0_TCHalt[other_tc] = t0;
f1aa6320
TS		 1028}
1029
be24bb4f 1030void do_mtc0_tccontext (target_ulong t0)
f1aa6320 1031{
be24bb4f 1032 env->CP0_TCContext[env->current_tc] = t0;
f1aa6320
TS		 1033}
1034
be24bb4f 1035void do_mttc0_tccontext (target_ulong t0)
f1aa6320
TS		 1036{
1037 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1038
be24bb4f 1039 env->CP0_TCContext[other_tc] = t0;
f1aa6320
TS		 1040}
1041
be24bb4f 1042void do_mtc0_tcschedule (target_ulong t0)
f1aa6320 1043{
be24bb4f 1044 env->CP0_TCSchedule[env->current_tc] = t0;
f1aa6320
TS		 1045}
1046
be24bb4f 1047void do_mttc0_tcschedule (target_ulong t0)
f1aa6320
TS		 1048{
1049 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1050
be24bb4f 1051 env->CP0_TCSchedule[other_tc] = t0;
f1aa6320
TS		 1052}
1053
be24bb4f 1054void do_mtc0_tcschefback (target_ulong t0)
f1aa6320 1055{
be24bb4f 1056 env->CP0_TCScheFBack[env->current_tc] = t0;
f1aa6320
TS		 1057}
1058
be24bb4f 1059void do_mttc0_tcschefback (target_ulong t0)
f1aa6320
TS		 1060{
1061 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1062
be24bb4f 1063 env->CP0_TCScheFBack[other_tc] = t0;
f1aa6320
TS		 1064}
1065
be24bb4f 1066void do_mtc0_entrylo1 (target_ulong t0)
f1aa6320
TS		 1067{
1068 /* Large physaddr (PABITS) not implemented */
1069 /* 1k pages not implemented */
be24bb4f 1070 env->CP0_EntryLo1 = t0 & 0x3FFFFFFF;
f1aa6320
TS		 1071}
1072
be24bb4f 1073void do_mtc0_context (target_ulong t0)
f1aa6320 1074{
be24bb4f 1075 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (t0 & ~0x007FFFFF);
f1aa6320
TS		 1076}
1077
be24bb4f 1078void do_mtc0_pagemask (target_ulong t0)
f1aa6320
TS		 1079{
1080 /* 1k pages not implemented */
be24bb4f 1081 env->CP0_PageMask = t0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
f1aa6320
TS		 1082}
1083
be24bb4f 1084void do_mtc0_pagegrain (target_ulong t0)
f1aa6320
TS		 1085{
1086 /* SmartMIPS not implemented */
1087 /* Large physaddr (PABITS) not implemented */
1088 /* 1k pages not implemented */
1089 env->CP0_PageGrain = 0;
1090}
1091
be24bb4f 1092void do_mtc0_wired (target_ulong t0)
f1aa6320 1093{
be24bb4f 1094 env->CP0_Wired = t0 % env->tlb->nb_tlb;
f1aa6320
TS		 1095}
1096
be24bb4f 1097void do_mtc0_srsconf0 (target_ulong t0)
f1aa6320 1098{
be24bb4f 1099 env->CP0_SRSConf0 |= t0 & env->CP0_SRSConf0_rw_bitmask;
f1aa6320
TS		 1100}
1101
be24bb4f 1102void do_mtc0_srsconf1 (target_ulong t0)
f1aa6320 1103{
be24bb4f 1104 env->CP0_SRSConf1 |= t0 & env->CP0_SRSConf1_rw_bitmask;
f1aa6320
TS		 1105}
1106
be24bb4f 1107void do_mtc0_srsconf2 (target_ulong t0)
f1aa6320 1108{
be24bb4f 1109 env->CP0_SRSConf2 |= t0 & env->CP0_SRSConf2_rw_bitmask;
f1aa6320
TS		 1110}
1111
be24bb4f 1112void do_mtc0_srsconf3 (target_ulong t0)
f1aa6320 1113{
be24bb4f 1114 env->CP0_SRSConf3 |= t0 & env->CP0_SRSConf3_rw_bitmask;
f1aa6320
TS		 1115}
1116
be24bb4f 1117void do_mtc0_srsconf4 (target_ulong t0)
f1aa6320 1118{
be24bb4f 1119 env->CP0_SRSConf4 |= t0 & env->CP0_SRSConf4_rw_bitmask;
f1aa6320
TS		 1120}
1121
be24bb4f 1122void do_mtc0_hwrena (target_ulong t0)
f1aa6320 1123{
be24bb4f 1124 env->CP0_HWREna = t0 & 0x0000000F;
f1aa6320
TS		 1125}
1126
be24bb4f 1127void do_mtc0_count (target_ulong t0)
f1aa6320 1128{
be24bb4f 1129 cpu_mips_store_count(env, t0);
f1aa6320
TS		 1130}
1131
be24bb4f 1132void do_mtc0_entryhi (target_ulong t0)
f1aa6320
TS		 1133{
1134 target_ulong old, val;
1135
1136 /* 1k pages not implemented */
be24bb4f 1137 val = t0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
f1aa6320
TS		 1138#if defined(TARGET_MIPS64)
1139 val &= env->SEGMask;
1140#endif
1141 old = env->CP0_EntryHi;
1142 env->CP0_EntryHi = val;
1143 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1144 uint32_t tcst = env->CP0_TCStatus[env->current_tc] & ~0xff;
1145 env->CP0_TCStatus[env->current_tc] = tcst | (val & 0xff);
1146 }
1147 /* If the ASID changes, flush qemu's TLB. */
1148 if ((old & 0xFF) != (val & 0xFF))
1149 cpu_mips_tlb_flush(env, 1);
1150}
1151
be24bb4f 1152void do_mttc0_entryhi(target_ulong t0)
f1aa6320
TS		 1153{
1154 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1155
be24bb4f
TS		 1156 env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (t0 & ~0xff);
1157 env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (t0 & 0xff);
f1aa6320
TS		 1158}
1159
be24bb4f 1160void do_mtc0_compare (target_ulong t0)
f1aa6320 1161{
be24bb4f 1162 cpu_mips_store_compare(env, t0);
f1aa6320
TS		 1163}
1164
be24bb4f 1165void do_mtc0_status (target_ulong t0)
f1aa6320
TS		 1166{
1167 uint32_t val, old;
1168 uint32_t mask = env->CP0_Status_rw_bitmask;
1169
be24bb4f 1170 val = t0 & mask;
f1aa6320
TS		 1171 old = env->CP0_Status;
1172 env->CP0_Status = (env->CP0_Status & ~mask) | val;
1173 compute_hflags(env);
1174 if (loglevel & CPU_LOG_EXEC)
1175 do_mtc0_status_debug(old, val);
1176 cpu_mips_update_irq(env);
1177}
1178
be24bb4f 1179void do_mttc0_status(target_ulong t0)
f1aa6320
TS		 1180{
1181 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1182 uint32_t tcstatus = env->CP0_TCStatus[other_tc];
1183
be24bb4f
TS		 1184 env->CP0_Status = t0 & ~0xf1000018;
1185 tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (t0 & (0xf << CP0St_CU0));
1186 tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((t0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
1187 tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((t0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
f1aa6320
TS		 1188 env->CP0_TCStatus[other_tc] = tcstatus;
1189}
1190
be24bb4f 1191void do_mtc0_intctl (target_ulong t0)
f1aa6320
TS		 1192{
1193 /* vectored interrupts not implemented, no performance counters. */
be24bb4f 1194 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (t0 & 0x000002e0);
f1aa6320
TS		 1195}
1196
be24bb4f 1197void do_mtc0_srsctl (target_ulong t0)
f1aa6320
TS		 1198{
1199 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
be24bb4f 1200 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (t0 & mask);
f1aa6320
TS		 1201}
1202
be24bb4f 1203void do_mtc0_cause (target_ulong t0)
f1aa6320
TS		 1204{
1205 uint32_t mask = 0x00C00300;
1206 uint32_t old = env->CP0_Cause;
1207
1208 if (env->insn_flags & ISA_MIPS32R2)
1209 mask |= 1 << CP0Ca_DC;
1210
be24bb4f 1211 env->CP0_Cause = (env->CP0_Cause & ~mask) | (t0 & mask);
f1aa6320
TS		 1212
1213 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
1214 if (env->CP0_Cause & (1 << CP0Ca_DC))
1215 cpu_mips_stop_count(env);
1216 else
1217 cpu_mips_start_count(env);
1218 }
1219
1220 /* Handle the software interrupt as an hardware one, as they
1221 are very similar */
be24bb4f 1222 if (t0 & CP0Ca_IP_mask) {
f1aa6320
TS		 1223 cpu_mips_update_irq(env);
1224 }
1225}
1226
be24bb4f 1227void do_mtc0_ebase (target_ulong t0)
f1aa6320
TS		 1228{
1229 /* vectored interrupts not implemented */
1230 /* Multi-CPU not implemented */
be24bb4f 1231 env->CP0_EBase = 0x80000000 | (t0 & 0x3FFFF000);
f1aa6320
TS		 1232}
1233
be24bb4f 1234void do_mtc0_config0 (target_ulong t0)
f1aa6320 1235{
be24bb4f 1236 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (t0 & 0x00000007);
f1aa6320
TS		 1237}
1238
be24bb4f 1239void do_mtc0_config2 (target_ulong t0)
f1aa6320
TS		 1240{
1241 /* tertiary/secondary caches not implemented */
1242 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1243}
1244
be24bb4f 1245void do_mtc0_watchlo (target_ulong t0, uint32_t sel)
f1aa6320
TS		 1246{
1247 /* Watch exceptions for instructions, data loads, data stores
1248 not implemented. */
be24bb4f 1249 env->CP0_WatchLo[sel] = (t0 & ~0x7);
f1aa6320
TS		 1250}
1251
be24bb4f 1252void do_mtc0_watchhi (target_ulong t0, uint32_t sel)
f1aa6320 1253{
be24bb4f
TS		 1254 env->CP0_WatchHi[sel] = (t0 & 0x40FF0FF8);
1255 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & t0 & 0x7);
f1aa6320
TS		 1256}
1257
be24bb4f 1258void do_mtc0_xcontext (target_ulong t0)
f1aa6320
TS		 1259{
1260 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
be24bb4f 1261 env->CP0_XContext = (env->CP0_XContext & mask) | (t0 & ~mask);
f1aa6320
TS		 1262}
1263
be24bb4f 1264void do_mtc0_framemask (target_ulong t0)
f1aa6320 1265{
be24bb4f 1266 env->CP0_Framemask = t0; /* XXX */
f1aa6320
TS		 1267}
1268
be24bb4f 1269void do_mtc0_debug (target_ulong t0)
f1aa6320 1270{
be24bb4f
TS		 1271 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (t0 & 0x13300120);
1272 if (t0 & (1 << CP0DB_DM))
f1aa6320
TS		 1273 env->hflags |= MIPS_HFLAG_DM;
1274 else
1275 env->hflags &= ~MIPS_HFLAG_DM;
1276}
1277
be24bb4f 1278void do_mttc0_debug(target_ulong t0)
f1aa6320
TS		 1279{
1280 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1281
1282 /* XXX: Might be wrong, check with EJTAG spec. */
be24bb4f 1283 env->CP0_Debug_tcstatus[other_tc] = t0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
f1aa6320 1284 env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
be24bb4f 1285 (t0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
f1aa6320
TS		 1286}
1287
be24bb4f 1288void do_mtc0_performance0 (target_ulong t0)
f1aa6320 1289{
be24bb4f 1290 env->CP0_Performance0 = t0 & 0x000007ff;
f1aa6320
TS		 1291}
1292
be24bb4f 1293void do_mtc0_taglo (target_ulong t0)
f1aa6320 1294{
be24bb4f 1295 env->CP0_TagLo = t0 & 0xFFFFFCF6;
f1aa6320
TS		 1296}
1297
be24bb4f 1298void do_mtc0_datalo (target_ulong t0)
f1aa6320 1299{
be24bb4f 1300 env->CP0_DataLo = t0; /* XXX */
f1aa6320
TS		 1301}
1302
be24bb4f 1303void do_mtc0_taghi (target_ulong t0)
f1aa6320 1304{
be24bb4f 1305 env->CP0_TagHi = t0; /* XXX */
f1aa6320
TS		 1306}
1307
be24bb4f 1308void do_mtc0_datahi (target_ulong t0)
f1aa6320 1309{
be24bb4f 1310 env->CP0_DataHi = t0; /* XXX */
f1aa6320
TS		 1311}
1312
8c0fdd85 1313void do_mtc0_status_debug(uint32_t old, uint32_t val)
6af0bf9c 1314{
f41c52f1
TS		 1315 fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
1316 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1317 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1318 env->CP0_Cause);
623a930e
TS		 1319 switch (env->hflags & MIPS_HFLAG_KSU) {
1320 case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break;
1321 case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break;
1322 case MIPS_HFLAG_KM: fputs("\n", logfile); break;
1323 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1324 }
8c0fdd85
TS		 1325}
1326
1327void do_mtc0_status_irqraise_debug(void)
1328{
1329 fprintf(logfile, "Raise pending IRQs\n");
6af0bf9c 1330}
f1aa6320
TS		 1331#endif /* !CONFIG_USER_ONLY */
1332
1333/* MIPS MT functions */
be24bb4f 1334target_ulong do_mftgpr(target_ulong t0, uint32_t sel)
f1aa6320
TS		 1335{
1336 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1337
be24bb4f 1338 return env->gpr[other_tc][sel];
f1aa6320
TS		 1339}
1340
be24bb4f 1341target_ulong do_mftlo(target_ulong t0, uint32_t sel)
f1aa6320
TS		 1342{
1343 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1344
be24bb4f 1345 return env->LO[other_tc][sel];
f1aa6320
TS		 1346}
1347
be24bb4f 1348target_ulong do_mfthi(target_ulong t0, uint32_t sel)
f1aa6320
TS		 1349{
1350 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1351
be24bb4f 1352 return env->HI[other_tc][sel];
f1aa6320
TS		 1353}
1354
be24bb4f 1355target_ulong do_mftacx(target_ulong t0, uint32_t sel)
f1aa6320
TS		 1356{
1357 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1358
be24bb4f 1359 return env->ACX[other_tc][sel];
f1aa6320
TS		 1360}
1361
be24bb4f 1362target_ulong do_mftdsp(target_ulong t0)
f1aa6320
TS		 1363{
1364 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1365
be24bb4f 1366 return env->DSPControl[other_tc];
f1aa6320 1367}
6af0bf9c 1368
be24bb4f 1369void do_mttgpr(target_ulong t0, uint32_t sel)
f1aa6320
TS		 1370{
1371 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1372
be24bb4f 1373 env->gpr[other_tc][sel] = t0;
f1aa6320
TS		 1374}
1375
be24bb4f 1376void do_mttlo(target_ulong t0, uint32_t sel)
f1aa6320
TS		 1377{
1378 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1379
be24bb4f 1380 env->LO[other_tc][sel] = t0;
f1aa6320
TS		 1381}
1382
be24bb4f 1383void do_mtthi(target_ulong t0, uint32_t sel)
f1aa6320
TS		 1384{
1385 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1386
be24bb4f 1387 env->HI[other_tc][sel] = t0;
f1aa6320
TS		 1388}
1389
be24bb4f 1390void do_mttacx(target_ulong t0, uint32_t sel)
f1aa6320
TS		 1391{
1392 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1393
be24bb4f 1394 env->ACX[other_tc][sel] = t0;
f1aa6320
TS		 1395}
1396
be24bb4f 1397void do_mttdsp(target_ulong t0)
f1aa6320
TS		 1398{
1399 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1400
be24bb4f 1401 env->DSPControl[other_tc] = t0;
f1aa6320
TS		 1402}
1403
1404/* MIPS MT functions */
be24bb4f 1405target_ulong do_dmt(target_ulong t0)
f1aa6320
TS		 1406{
1407 // TODO
be24bb4f
TS		 1408 t0 = 0;
1409 // rt = t0
1410
1411 return t0;
f1aa6320
TS		 1412}
1413
be24bb4f 1414target_ulong do_emt(target_ulong t0)
f1aa6320
TS		 1415{
1416 // TODO
be24bb4f
TS		 1417 t0 = 0;
1418 // rt = t0
1419
1420 return t0;
f1aa6320
TS		 1421}
1422
be24bb4f 1423target_ulong do_dvpe(target_ulong t0)
f1aa6320
TS		 1424{
1425 // TODO
be24bb4f
TS		 1426 t0 = 0;
1427 // rt = t0
1428
1429 return t0;
f1aa6320
TS		 1430}
1431
be24bb4f 1432target_ulong do_evpe(target_ulong t0)
f1aa6320
TS		 1433{
1434 // TODO
be24bb4f
TS		 1435 t0 = 0;
1436 // rt = t0
1437
1438 return t0;
f1aa6320
TS		 1439}
1440
6c5c1e20 1441void do_fork(target_ulong t0, target_ulong t1)
f1aa6320 1442{
be24bb4f
TS		 1443 // t0 = rt, t1 = rs
1444 t0 = 0;
f1aa6320
TS		 1445 // TODO: store to TC register
1446}
1447
be24bb4f 1448target_ulong do_yield(target_ulong t0)
f1aa6320 1449{
be24bb4f 1450 if (t0 < 0) {
f1aa6320 1451 /* No scheduling policy implemented. */
be24bb4f 1452 if (t0 != -2) {
f1aa6320
TS		 1453 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1454 env->CP0_TCStatus[env->current_tc] & (1 << CP0TCSt_DT)) {
1455 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1456 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1457 do_raise_exception(EXCP_THREAD);
1458 }
1459 }
be24bb4f 1460 } else if (t0 == 0) {
f1aa6320
TS		 1461 if (0 /* TODO: TC underflow */) {
1462 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1463 do_raise_exception(EXCP_THREAD);
1464 } else {
1465 // TODO: Deallocate TC
1466 }
be24bb4f 1467 } else if (t0 > 0) {
f1aa6320
TS		 1468 /* Yield qualifier inputs not implemented. */
1469 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1470 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1471 do_raise_exception(EXCP_THREAD);
1472 }
be24bb4f 1473 return env->CP0_YQMask;
f1aa6320
TS		 1474}
1475
1476/* CP1 functions */
6ea83fed
FB		 1477void fpu_handle_exception(void)
1478{
1479#ifdef CONFIG_SOFTFLOAT
ead9360e 1480 int flags = get_float_exception_flags(&env->fpu->fp_status);
6ea83fed
FB		 1481 unsigned int cpuflags = 0, enable, cause = 0;
1482
ead9360e 1483 enable = GET_FP_ENABLE(env->fpu->fcr31);
6ea83fed 1484
3b46e624 1485 /* determine current flags */
6ea83fed
FB		 1486 if (flags & float_flag_invalid) {
1487 cpuflags |= FP_INVALID;
1488 cause |= FP_INVALID & enable;
1489 }
1490 if (flags & float_flag_divbyzero) {
3b46e624 1491 cpuflags |= FP_DIV0;
6ea83fed
FB		 1492 cause |= FP_DIV0 & enable;
1493 }
1494 if (flags & float_flag_overflow) {
3b46e624 1495 cpuflags |= FP_OVERFLOW;
6ea83fed
FB		 1496 cause |= FP_OVERFLOW & enable;
1497 }
1498 if (flags & float_flag_underflow) {
3b46e624 1499 cpuflags |= FP_UNDERFLOW;
6ea83fed
FB		 1500 cause |= FP_UNDERFLOW & enable;
1501 }
1502 if (flags & float_flag_inexact) {
5fafdf24 1503 cpuflags |= FP_INEXACT;
6ea83fed
FB		 1504 cause |= FP_INEXACT & enable;
1505 }
ead9360e
TS		 1506 SET_FP_FLAGS(env->fpu->fcr31, cpuflags);
1507 SET_FP_CAUSE(env->fpu->fcr31, cause);
6ea83fed 1508#else
ead9360e
TS		 1509 SET_FP_FLAGS(env->fpu->fcr31, 0);
1510 SET_FP_CAUSE(env->fpu->fcr31, 0);
6ea83fed
FB		 1511#endif
1512}
6ea83fed 1513
f1aa6320 1514#ifndef CONFIG_USER_ONLY
6af0bf9c 1515/* TLB management */
814b9a47
TS		 1516void cpu_mips_tlb_flush (CPUState *env, int flush_global)
1517{
1518 /* Flush qemu's TLB and discard all shadowed entries. */
1519 tlb_flush (env, flush_global);
ead9360e 1520 env->tlb->tlb_in_use = env->tlb->nb_tlb;
814b9a47
TS		 1521}
1522
29929e34 1523static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
814b9a47
TS		 1524{
1525 /* Discard entries from env->tlb[first] onwards. */
ead9360e
TS		 1526 while (env->tlb->tlb_in_use > first) {
1527 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
814b9a47
TS		 1528 }
1529}
1530
29929e34 1531static void r4k_fill_tlb (int idx)
6af0bf9c 1532{
29929e34 1533 r4k_tlb_t *tlb;
6af0bf9c
FB		 1534
1535 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
ead9360e 1536 tlb = &env->tlb->mmu.r4k.tlb[idx];
f2e9ebef 1537 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
d26bc211 1538#if defined(TARGET_MIPS64)
e034e2c3 1539 tlb->VPN &= env->SEGMask;
100ce988 1540#endif
98c1b82b 1541 tlb->ASID = env->CP0_EntryHi & 0xFF;
3b1c8be4 1542 tlb->PageMask = env->CP0_PageMask;
6af0bf9c 1543 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
98c1b82b
PB		 1544 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1545 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1546 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
6af0bf9c 1547 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
98c1b82b
PB		 1548 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1549 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1550 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
6af0bf9c
FB		 1551 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1552}
1553
29929e34 1554void r4k_do_tlbwi (void)
6af0bf9c 1555{
814b9a47
TS		 1556 /* Discard cached TLB entries. We could avoid doing this if the
1557 tlbwi is just upgrading access permissions on the current entry;
1558 that might be a further win. */
ead9360e 1559 r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
814b9a47 1560
ead9360e
TS		 1561 r4k_invalidate_tlb(env, env->CP0_Index % env->tlb->nb_tlb, 0);
1562 r4k_fill_tlb(env->CP0_Index % env->tlb->nb_tlb);
6af0bf9c
FB		 1563}
1564
29929e34 1565void r4k_do_tlbwr (void)
6af0bf9c
FB		 1566{
1567 int r = cpu_mips_get_random(env);
1568
29929e34
TS		 1569 r4k_invalidate_tlb(env, r, 1);
1570 r4k_fill_tlb(r);
6af0bf9c
FB		 1571}
1572
29929e34 1573void r4k_do_tlbp (void)
6af0bf9c 1574{
29929e34 1575 r4k_tlb_t *tlb;
f2e9ebef 1576 target_ulong mask;
6af0bf9c 1577 target_ulong tag;
f2e9ebef 1578 target_ulong VPN;
6af0bf9c
FB		 1579 uint8_t ASID;
1580 int i;
1581
3d9fb9fe 1582 ASID = env->CP0_EntryHi & 0xFF;
ead9360e
TS		 1583 for (i = 0; i < env->tlb->nb_tlb; i++) {
1584 tlb = &env->tlb->mmu.r4k.tlb[i];
f2e9ebef
TS		 1585 /* 1k pages are not supported. */
1586 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1587 tag = env->CP0_EntryHi & ~mask;
1588 VPN = tlb->VPN & ~mask;
6af0bf9c 1589 /* Check ASID, virtual page number & size */
f2e9ebef 1590 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
6af0bf9c 1591 /* TLB match */
9c2149c8 1592 env->CP0_Index = i;
6af0bf9c
FB		 1593 break;
1594 }
1595 }
ead9360e 1596 if (i == env->tlb->nb_tlb) {
814b9a47 1597 /* No match. Discard any shadow entries, if any of them match. */
ead9360e
TS		 1598 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1599 tlb = &env->tlb->mmu.r4k.tlb[i];
f2e9ebef
TS		 1600 /* 1k pages are not supported. */
1601 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1602 tag = env->CP0_EntryHi & ~mask;
1603 VPN = tlb->VPN & ~mask;
814b9a47 1604 /* Check ASID, virtual page number & size */
f2e9ebef 1605 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
29929e34 1606 r4k_mips_tlb_flush_extra (env, i);
814b9a47
TS		 1607 break;
1608 }
1609 }
1610
9c2149c8 1611 env->CP0_Index |= 0x80000000;
6af0bf9c
FB		 1612 }
1613}
1614
29929e34 1615void r4k_do_tlbr (void)
6af0bf9c 1616{
29929e34 1617 r4k_tlb_t *tlb;
09c56b84 1618 uint8_t ASID;
6af0bf9c 1619
09c56b84 1620 ASID = env->CP0_EntryHi & 0xFF;
ead9360e 1621 tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb];
4ad40f36
FB		 1622
1623 /* If this will change the current ASID, flush qemu's TLB. */
814b9a47
TS		 1624 if (ASID != tlb->ASID)
1625 cpu_mips_tlb_flush (env, 1);
1626
ead9360e 1627 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
4ad40f36 1628
6af0bf9c 1629 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
3b1c8be4 1630 env->CP0_PageMask = tlb->PageMask;
7495fd0f
TS		 1631 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1632 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1633 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1634 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
6af0bf9c 1635}
6af0bf9c 1636
048f6b4d
FB		 1637#endif /* !CONFIG_USER_ONLY */
1638
2b0233ab 1639/* Specials */
be24bb4f 1640target_ulong do_di (target_ulong t0)
2b0233ab 1641{
be24bb4f
TS		 1642 t0 = env->CP0_Status;
1643 env->CP0_Status = t0 & ~(1 << CP0St_IE);
2b0233ab 1644 cpu_mips_update_irq(env);
be24bb4f
TS		 1645
1646 return t0;
2b0233ab
TS		 1647}
1648
be24bb4f 1649target_ulong do_ei (target_ulong t0)
2b0233ab 1650{
be24bb4f
TS		 1651 t0 = env->CP0_Status;
1652 env->CP0_Status = t0 | (1 << CP0St_IE);
2b0233ab 1653 cpu_mips_update_irq(env);
be24bb4f
TS		 1654
1655 return t0;
2b0233ab
TS		 1656}
1657
f41c52f1 1658void debug_pre_eret (void)
6af0bf9c 1659{
f41c52f1 1660 fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
ead9360e 1661 env->PC[env->current_tc], env->CP0_EPC);
f41c52f1
TS		 1662 if (env->CP0_Status & (1 << CP0St_ERL))
1663 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1664 if (env->hflags & MIPS_HFLAG_DM)
1665 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1666 fputs("\n", logfile);
1667}
1668
1669void debug_post_eret (void)
1670{
744e0915 1671 fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
ead9360e 1672 env->PC[env->current_tc], env->CP0_EPC);
f41c52f1
TS		 1673 if (env->CP0_Status & (1 << CP0St_ERL))
1674 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1675 if (env->hflags & MIPS_HFLAG_DM)
1676 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
623a930e
TS		 1677 switch (env->hflags & MIPS_HFLAG_KSU) {
1678 case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break;
1679 case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break;
1680 case MIPS_HFLAG_KM: fputs("\n", logfile); break;
1681 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1682 }
6af0bf9c
FB		 1683}
1684
6c5c1e20 1685void do_eret (void)
2b0233ab
TS		 1686{
1687 if (loglevel & CPU_LOG_EXEC)
1688 debug_pre_eret();
1689 if (env->CP0_Status & (1 << CP0St_ERL)) {
1690 env->PC[env->current_tc] = env->CP0_ErrorEPC;
1691 env->CP0_Status &= ~(1 << CP0St_ERL);
1692 } else {
1693 env->PC[env->current_tc] = env->CP0_EPC;
1694 env->CP0_Status &= ~(1 << CP0St_EXL);
1695 }
1696 compute_hflags(env);
1697 if (loglevel & CPU_LOG_EXEC)
1698 debug_post_eret();
1699 env->CP0_LLAddr = 1;
1700}
1701
6c5c1e20 1702void do_deret (void)
2b0233ab
TS		 1703{
1704 if (loglevel & CPU_LOG_EXEC)
1705 debug_pre_eret();
1706 env->PC[env->current_tc] = env->CP0_DEPC;
1707 env->hflags &= MIPS_HFLAG_DM;
1708 compute_hflags(env);
1709 if (loglevel & CPU_LOG_EXEC)
1710 debug_post_eret();
1711 env->CP0_LLAddr = 1;
1712}
1713
be24bb4f 1714target_ulong do_rdhwr_cpunum(target_ulong t0)
2b0233ab
TS		 1715{
1716 if ((env->hflags & MIPS_HFLAG_CP0) ||
1717 (env->CP0_HWREna & (1 << 0)))
be24bb4f 1718 t0 = env->CP0_EBase & 0x3ff;
2b0233ab
TS		 1719 else
1720 do_raise_exception(EXCP_RI);
be24bb4f
TS		 1721
1722 return t0;
2b0233ab
TS		 1723}
1724
be24bb4f 1725target_ulong do_rdhwr_synci_step(target_ulong t0)
2b0233ab
TS		 1726{
1727 if ((env->hflags & MIPS_HFLAG_CP0) ||
1728 (env->CP0_HWREna & (1 << 1)))
be24bb4f 1729 t0 = env->SYNCI_Step;
2b0233ab
TS		 1730 else
1731 do_raise_exception(EXCP_RI);
be24bb4f
TS		 1732
1733 return t0;
2b0233ab
TS		 1734}
1735
be24bb4f 1736target_ulong do_rdhwr_cc(target_ulong t0)
2b0233ab
TS		 1737{
1738 if ((env->hflags & MIPS_HFLAG_CP0) ||
1739 (env->CP0_HWREna & (1 << 2)))
be24bb4f 1740 t0 = env->CP0_Count;
2b0233ab
TS		 1741 else
1742 do_raise_exception(EXCP_RI);
be24bb4f
TS		 1743
1744 return t0;
2b0233ab
TS		 1745}
1746
be24bb4f 1747target_ulong do_rdhwr_ccres(target_ulong t0)
2b0233ab
TS		 1748{
1749 if ((env->hflags & MIPS_HFLAG_CP0) ||
1750 (env->CP0_HWREna & (1 << 3)))
be24bb4f 1751 t0 = env->CCRes;
2b0233ab
TS		 1752 else
1753 do_raise_exception(EXCP_RI);
be24bb4f
TS		 1754
1755 return t0;
2b0233ab
TS		 1756}
1757
1758/* Bitfield operations. */
be24bb4f 1759target_ulong do_ext(target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size)
2b0233ab 1760{
be24bb4f 1761 return (int32_t)((t1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0));
2b0233ab
TS		 1762}
1763
be24bb4f 1764target_ulong do_ins(target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size)
2b0233ab
TS		 1765{
1766 target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
1767
be24bb4f 1768 return (int32_t)((t0 & ~mask) | ((t1 << pos) & mask));
2b0233ab
TS		 1769}
1770
be24bb4f 1771target_ulong do_wsbh(target_ulong t0, target_ulong t1)
2b0233ab 1772{
be24bb4f 1773 return (int32_t)(((t1 << 8) & ~0x00FF00FF) | ((t1 >> 8) & 0x00FF00FF));
2b0233ab
TS		 1774}
1775
1776#if defined(TARGET_MIPS64)
be24bb4f 1777target_ulong do_dext(target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size)
2b0233ab 1778{
be24bb4f 1779 return (t1 >> pos) & ((size < 64) ? ((1ULL << size) - 1) : ~0ULL);
2b0233ab
TS		 1780}
1781
be24bb4f 1782target_ulong do_dins(target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size)
2b0233ab
TS		 1783{
1784 target_ulong mask = ((size < 64) ? ((1ULL << size) - 1) : ~0ULL) << pos;
1785
be24bb4f 1786 return (t0 & ~mask) | ((t1 << pos) & mask);
2b0233ab
TS		 1787}
1788
be24bb4f 1789target_ulong do_dsbh(target_ulong t0, target_ulong t1)
2b0233ab 1790{
be24bb4f 1791 return ((t1 << 8) & ~0x00FF00FF00FF00FFULL) | ((t1 >> 8) & 0x00FF00FF00FF00FFULL);
2b0233ab
TS		 1792}
1793
be24bb4f 1794target_ulong do_dshd(target_ulong t0, target_ulong t1)
2b0233ab 1795{
be24bb4f
TS		 1796 t1 = ((t1 << 16) & ~0x0000FFFF0000FFFFULL) | ((t1 >> 16) & 0x0000FFFF0000FFFFULL);
1797 return (t1 << 32) | (t1 >> 32);
2b0233ab
TS		 1798}
1799#endif
1800
6af0bf9c
FB		 1801void do_pmon (int function)
1802{
1803 function /= 2;
1804 switch (function) {
1805 case 2: /* TODO: char inbyte(int waitflag); */
d0dc7dc3
TS		 1806 if (env->gpr[env->current_tc][4] == 0)
1807 env->gpr[env->current_tc][2] = -1;
6af0bf9c
FB		 1808 /* Fall through */
1809 case 11: /* TODO: char inbyte (void); */
d0dc7dc3 1810 env->gpr[env->current_tc][2] = -1;
6af0bf9c
FB		 1811 break;
1812 case 3:
1813 case 12:
d0dc7dc3 1814 printf("%c", (char)(env->gpr[env->current_tc][4] & 0xFF));
6af0bf9c
FB		 1815 break;
1816 case 17:
1817 break;
1818 case 158:
1819 {
d0dc7dc3 1820 unsigned char *fmt = (void *)(unsigned long)env->gpr[env->current_tc][4];
6af0bf9c
FB		 1821 printf("%s", fmt);
1822 }
1823 break;
1824 }
1825}
e37e863f 1826
08ba7963
TS		 1827void do_wait (void)
1828{
1829 env->halted = 1;
1830 do_raise_exception(EXCP_HLT);
1831}
1832
5fafdf24 1833#if !defined(CONFIG_USER_ONLY)
e37e863f 1834
4ad40f36
FB		 1835static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
1836
e37e863f 1837#define MMUSUFFIX _mmu
4ad40f36 1838#define ALIGNED_ONLY
e37e863f
FB		 1839
1840#define SHIFT 0
1841#include "softmmu_template.h"
1842
1843#define SHIFT 1
1844#include "softmmu_template.h"
1845
1846#define SHIFT 2
1847#include "softmmu_template.h"
1848
1849#define SHIFT 3
1850#include "softmmu_template.h"
1851
4ad40f36
FB		 1852static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
1853{
1854 env->CP0_BadVAddr = addr;
1855 do_restore_state (retaddr);
1856 do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
1857}
1858
6ebbf390 1859void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
e37e863f
FB		 1860{
1861 TranslationBlock *tb;
1862 CPUState *saved_env;
1863 unsigned long pc;
1864 int ret;
1865
1866 /* XXX: hack to restore env in all cases, even if not called from
1867 generated code */
1868 saved_env = env;
1869 env = cpu_single_env;
6ebbf390 1870 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
e37e863f
FB		 1871 if (ret) {
1872 if (retaddr) {
1873 /* now we have a real cpu fault */
1874 pc = (unsigned long)retaddr;
1875 tb = tb_find_pc(pc);
1876 if (tb) {
1877 /* the PC is inside the translated code. It means that we have
1878 a virtual CPU fault */
1879 cpu_restore_state(tb, env, pc, NULL);
1880 }
1881 }
1882 do_raise_exception_err(env->exception_index, env->error_code);
1883 }
1884 env = saved_env;
1885}
1886
647de6ca
TS		 1887void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1888 int unused)
1889{
1890 if (is_exec)
1891 do_raise_exception(EXCP_IBE);
1892 else
1893 do_raise_exception(EXCP_DBE);
1894}
f1aa6320 1895#endif /* !CONFIG_USER_ONLY */
fd4a04eb
TS		 1896
1897/* Complex FPU operations which may need stack space. */
1898
f090c9d4
PB		 1899#define FLOAT_ONE32 make_float32(0x3f8 << 20)
1900#define FLOAT_ONE64 make_float64(0x3ffULL << 52)
1901#define FLOAT_TWO32 make_float32(1 << 30)
1902#define FLOAT_TWO64 make_float64(1ULL << 62)
54454097
TS		 1903#define FLOAT_QNAN32 0x7fbfffff
1904#define FLOAT_QNAN64 0x7ff7ffffffffffffULL
1905#define FLOAT_SNAN32 0x7fffffff
1906#define FLOAT_SNAN64 0x7fffffffffffffffULL
8dfdb87c 1907
fd4a04eb
TS		 1908/* convert MIPS rounding mode in FCR31 to IEEE library */
1909unsigned int ieee_rm[] = {
1910 float_round_nearest_even,
1911 float_round_to_zero,
1912 float_round_up,
1913 float_round_down
1914};
1915
1916#define RESTORE_ROUNDING_MODE \
ead9360e 1917 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
fd4a04eb 1918
6c5c1e20 1919target_ulong do_cfc1 (uint32_t reg)
fd4a04eb 1920{
6c5c1e20
TS		 1921 target_ulong t0;
1922
ead9360e
TS		 1923 switch (reg) {
1924 case 0:
be24bb4f 1925 t0 = (int32_t)env->fpu->fcr0;
ead9360e
TS		 1926 break;
1927 case 25:
be24bb4f 1928 t0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1);
ead9360e
TS		 1929 break;
1930 case 26:
be24bb4f 1931 t0 = env->fpu->fcr31 & 0x0003f07c;
ead9360e
TS		 1932 break;
1933 case 28:
be24bb4f 1934 t0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4);
ead9360e
TS		 1935 break;
1936 default:
be24bb4f 1937 t0 = (int32_t)env->fpu->fcr31;
ead9360e
TS		 1938 break;
1939 }
be24bb4f
TS		 1940
1941 return t0;
ead9360e
TS		 1942}
1943
be24bb4f 1944void do_ctc1 (target_ulong t0, uint32_t reg)
ead9360e
TS		 1945{
1946 switch(reg) {
fd4a04eb 1947 case 25:
be24bb4f 1948 if (t0 & 0xffffff00)
fd4a04eb 1949 return;
be24bb4f
TS		 1950 env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((t0 & 0xfe) << 24) |
1951 ((t0 & 0x1) << 23);
fd4a04eb
TS		 1952 break;
1953 case 26:
be24bb4f 1954 if (t0 & 0x007c0000)
fd4a04eb 1955 return;
be24bb4f 1956 env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (t0 & 0x0003f07c);
fd4a04eb
TS		 1957 break;
1958 case 28:
be24bb4f 1959 if (t0 & 0x007c0000)
fd4a04eb 1960 return;
be24bb4f
TS		 1961 env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (t0 & 0x00000f83) |
1962 ((t0 & 0x4) << 22);
fd4a04eb
TS		 1963 break;
1964 case 31:
be24bb4f 1965 if (t0 & 0x007c0000)
fd4a04eb 1966 return;
be24bb4f 1967 env->fpu->fcr31 = t0;
fd4a04eb
TS		 1968 break;
1969 default:
1970 return;
1971 }
1972 /* set rounding mode */
1973 RESTORE_ROUNDING_MODE;
ead9360e
TS		 1974 set_float_exception_flags(0, &env->fpu->fp_status);
1975 if ((GET_FP_ENABLE(env->fpu->fcr31) | 0x20) & GET_FP_CAUSE(env->fpu->fcr31))
fd4a04eb
TS		 1976 do_raise_exception(EXCP_FPE);
1977}
1978
aa343735 1979static always_inline char ieee_ex_to_mips(char xcpt)
fd4a04eb
TS		 1980{
1981 return (xcpt & float_flag_inexact) >> 5 |
1982 (xcpt & float_flag_underflow) >> 3 |
1983 (xcpt & float_flag_overflow) >> 1 |
1984 (xcpt & float_flag_divbyzero) << 1 |
1985 (xcpt & float_flag_invalid) << 4;
1986}
1987
aa343735 1988static always_inline char mips_ex_to_ieee(char xcpt)
fd4a04eb
TS		 1989{
1990 return (xcpt & FP_INEXACT) << 5 |
1991 (xcpt & FP_UNDERFLOW) << 3 |
1992 (xcpt & FP_OVERFLOW) << 1 |
1993 (xcpt & FP_DIV0) >> 1 |
1994 (xcpt & FP_INVALID) >> 4;
1995}
1996
aa343735 1997static always_inline void update_fcr31(void)
fd4a04eb 1998{
ead9360e 1999 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status));
fd4a04eb 2000
ead9360e
TS		 2001 SET_FP_CAUSE(env->fpu->fcr31, tmp);
2002 if (GET_FP_ENABLE(env->fpu->fcr31) & tmp)
fd4a04eb
TS		 2003 do_raise_exception(EXCP_FPE);
2004 else
ead9360e 2005 UPDATE_FP_FLAGS(env->fpu->fcr31, tmp);
fd4a04eb
TS		 2006}
2007
a16336e4
TS		 2008/* Float support.
2009 Single precition routines have a "s" suffix, double precision a
2010 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2011 paired single lower "pl", paired single upper "pu". */
2012
fd4a04eb
TS		 2013#define FLOAT_OP(name, p) void do_float_##name##_##p(void)
2014
a16336e4
TS		 2015/* unary operations, modifying fp status */
2016#define FLOAT_UNOP(name) \
2017FLOAT_OP(name, d) \
2018{ \
2019 FDT2 = float64_ ## name(FDT0, &env->fpu->fp_status); \
2020} \
2021FLOAT_OP(name, s) \
2022{ \
2023 FST2 = float32_ ## name(FST0, &env->fpu->fp_status); \
2024}
2025FLOAT_UNOP(sqrt)
2026#undef FLOAT_UNOP
2027
fd4a04eb
TS		 2028FLOAT_OP(cvtd, s)
2029{
ead9360e
TS		 2030 set_float_exception_flags(0, &env->fpu->fp_status);
2031 FDT2 = float32_to_float64(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 2032 update_fcr31();
2033}
2034FLOAT_OP(cvtd, w)
2035{
ead9360e
TS		 2036 set_float_exception_flags(0, &env->fpu->fp_status);
2037 FDT2 = int32_to_float64(WT0, &env->fpu->fp_status);
fd4a04eb
TS		 2038 update_fcr31();
2039}
2040FLOAT_OP(cvtd, l)
2041{
ead9360e
TS		 2042 set_float_exception_flags(0, &env->fpu->fp_status);
2043 FDT2 = int64_to_float64(DT0, &env->fpu->fp_status);
fd4a04eb
TS		 2044 update_fcr31();
2045}
2046FLOAT_OP(cvtl, d)
2047{
ead9360e
TS		 2048 set_float_exception_flags(0, &env->fpu->fp_status);
2049 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
fd4a04eb 2050 update_fcr31();
ead9360e 2051 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 2052 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 2053}
2054FLOAT_OP(cvtl, s)
2055{
ead9360e
TS		 2056 set_float_exception_flags(0, &env->fpu->fp_status);
2057 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
fd4a04eb 2058 update_fcr31();
ead9360e 2059 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 2060 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 2061}
2062
2063FLOAT_OP(cvtps, pw)
2064{
ead9360e
TS		 2065 set_float_exception_flags(0, &env->fpu->fp_status);
2066 FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
2067 FSTH2 = int32_to_float32(WTH0, &env->fpu->fp_status);
fd4a04eb
TS		 2068 update_fcr31();
2069}
2070FLOAT_OP(cvtpw, ps)
2071{
ead9360e
TS		 2072 set_float_exception_flags(0, &env->fpu->fp_status);
2073 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
2074 WTH2 = float32_to_int32(FSTH0, &env->fpu->fp_status);
fd4a04eb 2075 update_fcr31();
ead9360e 2076 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 2077 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 2078}
2079FLOAT_OP(cvts, d)
2080{
ead9360e
TS		 2081 set_float_exception_flags(0, &env->fpu->fp_status);
2082 FST2 = float64_to_float32(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 2083 update_fcr31();
2084}
2085FLOAT_OP(cvts, w)
2086{
ead9360e
TS		 2087 set_float_exception_flags(0, &env->fpu->fp_status);
2088 FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
fd4a04eb
TS		 2089 update_fcr31();
2090}
2091FLOAT_OP(cvts, l)
2092{
ead9360e
TS		 2093 set_float_exception_flags(0, &env->fpu->fp_status);
2094 FST2 = int64_to_float32(DT0, &env->fpu->fp_status);
fd4a04eb
TS		 2095 update_fcr31();
2096}
2097FLOAT_OP(cvts, pl)
2098{
ead9360e 2099 set_float_exception_flags(0, &env->fpu->fp_status);
fd4a04eb
TS		 2100 WT2 = WT0;
2101 update_fcr31();
2102}
2103FLOAT_OP(cvts, pu)
2104{
ead9360e 2105 set_float_exception_flags(0, &env->fpu->fp_status);
fd4a04eb
TS		 2106 WT2 = WTH0;
2107 update_fcr31();
2108}
2109FLOAT_OP(cvtw, s)
2110{
ead9360e
TS		 2111 set_float_exception_flags(0, &env->fpu->fp_status);
2112 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
fd4a04eb 2113 update_fcr31();
ead9360e 2114 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 2115 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 2116}
2117FLOAT_OP(cvtw, d)
2118{
ead9360e
TS		 2119 set_float_exception_flags(0, &env->fpu->fp_status);
2120 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
fd4a04eb 2121 update_fcr31();
ead9360e 2122 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 2123 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 2124}
2125
2126FLOAT_OP(roundl, d)
2127{
ead9360e
TS		 2128 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
2129 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 2130 RESTORE_ROUNDING_MODE;
2131 update_fcr31();
ead9360e 2132 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 2133 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 2134}
2135FLOAT_OP(roundl, s)
2136{
ead9360e
TS		 2137 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
2138 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 2139 RESTORE_ROUNDING_MODE;
2140 update_fcr31();
ead9360e 2141 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 2142 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 2143}
2144FLOAT_OP(roundw, d)
2145{
ead9360e
TS		 2146 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
2147 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 2148 RESTORE_ROUNDING_MODE;
2149 update_fcr31();
ead9360e 2150 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 2151 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 2152}
2153FLOAT_OP(roundw, s)
2154{
ead9360e
TS		 2155 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
2156 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 2157 RESTORE_ROUNDING_MODE;
2158 update_fcr31();
ead9360e 2159 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 2160 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 2161}
2162
2163FLOAT_OP(truncl, d)
2164{
ead9360e 2165 DT2 = float64_to_int64_round_to_zero(FDT0, &env->fpu->fp_status);
fd4a04eb 2166 update_fcr31();
ead9360e 2167 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 2168 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 2169}
2170FLOAT_OP(truncl, s)
2171{
ead9360e 2172 DT2 = float32_to_int64_round_to_zero(FST0, &env->fpu->fp_status);
fd4a04eb 2173 update_fcr31();
ead9360e 2174 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 2175 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 2176}
2177FLOAT_OP(truncw, d)
2178{
ead9360e 2179 WT2 = float64_to_int32_round_to_zero(FDT0, &env->fpu->fp_status);
fd4a04eb 2180 update_fcr31();
ead9360e 2181 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 2182 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 2183}
2184FLOAT_OP(truncw, s)
2185{
ead9360e 2186 WT2 = float32_to_int32_round_to_zero(FST0, &env->fpu->fp_status);
fd4a04eb 2187 update_fcr31();
ead9360e 2188 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 2189 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 2190}
2191
2192FLOAT_OP(ceill, d)
2193{
ead9360e
TS		 2194 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
2195 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 2196 RESTORE_ROUNDING_MODE;
2197 update_fcr31();
ead9360e 2198 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 2199 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 2200}
2201FLOAT_OP(ceill, s)
2202{
ead9360e
TS		 2203 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
2204 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 2205 RESTORE_ROUNDING_MODE;
2206 update_fcr31();
ead9360e 2207 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 2208 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 2209}
2210FLOAT_OP(ceilw, d)
2211{
ead9360e
TS		 2212 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
2213 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 2214 RESTORE_ROUNDING_MODE;
2215 update_fcr31();
ead9360e 2216 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 2217 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 2218}
2219FLOAT_OP(ceilw, s)
2220{
ead9360e
TS		 2221 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
2222 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 2223 RESTORE_ROUNDING_MODE;
2224 update_fcr31();
ead9360e 2225 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 2226 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 2227}
2228
2229FLOAT_OP(floorl, d)
2230{
ead9360e
TS		 2231 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
2232 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 2233 RESTORE_ROUNDING_MODE;
2234 update_fcr31();
ead9360e 2235 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 2236 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 2237}
2238FLOAT_OP(floorl, s)
2239{
ead9360e
TS		 2240 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
2241 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 2242 RESTORE_ROUNDING_MODE;
2243 update_fcr31();
ead9360e 2244 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 2245 DT2 = FLOAT_SNAN64;
fd4a04eb
TS		 2246}
2247FLOAT_OP(floorw, d)
2248{
ead9360e
TS		 2249 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
2250 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
fd4a04eb
TS		 2251 RESTORE_ROUNDING_MODE;
2252 update_fcr31();
ead9360e 2253 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 2254 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 2255}
2256FLOAT_OP(floorw, s)
2257{
ead9360e
TS		 2258 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
2259 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
fd4a04eb
TS		 2260 RESTORE_ROUNDING_MODE;
2261 update_fcr31();
ead9360e 2262 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
54454097 2263 WT2 = FLOAT_SNAN32;
fd4a04eb
TS		 2264}
2265
a16336e4
TS		 2266/* unary operations, not modifying fp status */
2267#define FLOAT_UNOP(name) \
2268FLOAT_OP(name, d) \
2269{ \
2270 FDT2 = float64_ ## name(FDT0); \
2271} \
2272FLOAT_OP(name, s) \
2273{ \
2274 FST2 = float32_ ## name(FST0); \
2275} \
2276FLOAT_OP(name, ps) \
2277{ \
2278 FST2 = float32_ ## name(FST0); \
2279 FSTH2 = float32_ ## name(FSTH0); \
2280}
2281FLOAT_UNOP(abs)
2282FLOAT_UNOP(chs)
2283#undef FLOAT_UNOP
2284
8dfdb87c
TS		 2285/* MIPS specific unary operations */
2286FLOAT_OP(recip, d)
2287{
ead9360e
TS		 2288 set_float_exception_flags(0, &env->fpu->fp_status);
2289 FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
8dfdb87c
TS		 2290 update_fcr31();
2291}
2292FLOAT_OP(recip, s)
2293{
ead9360e
TS		 2294 set_float_exception_flags(0, &env->fpu->fp_status);
2295 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
8dfdb87c 2296 update_fcr31();
57fa1fb3 2297}
57fa1fb3 2298
8dfdb87c
TS		 2299FLOAT_OP(rsqrt, d)
2300{
ead9360e
TS		 2301 set_float_exception_flags(0, &env->fpu->fp_status);
2302 FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
2303 FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
8dfdb87c
TS		 2304 update_fcr31();
2305}
2306FLOAT_OP(rsqrt, s)
2307{
ead9360e
TS		 2308 set_float_exception_flags(0, &env->fpu->fp_status);
2309 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
2310 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
8dfdb87c
TS		 2311 update_fcr31();
2312}
2313
2314FLOAT_OP(recip1, d)
2315{
ead9360e
TS		 2316 set_float_exception_flags(0, &env->fpu->fp_status);
2317 FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
8dfdb87c
TS		 2318 update_fcr31();
2319}
2320FLOAT_OP(recip1, s)
2321{
ead9360e
TS		 2322 set_float_exception_flags(0, &env->fpu->fp_status);
2323 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
8dfdb87c
TS		 2324 update_fcr31();
2325}
2326FLOAT_OP(recip1, ps)
2327{
ead9360e
TS		 2328 set_float_exception_flags(0, &env->fpu->fp_status);
2329 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
2330 FSTH2 = float32_div(FLOAT_ONE32, FSTH0, &env->fpu->fp_status);
8dfdb87c
TS		 2331 update_fcr31();
2332}
2333
2334FLOAT_OP(rsqrt1, d)
2335{
ead9360e
TS		 2336 set_float_exception_flags(0, &env->fpu->fp_status);
2337 FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
2338 FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
8dfdb87c
TS		 2339 update_fcr31();
2340}
2341FLOAT_OP(rsqrt1, s)
2342{
ead9360e
TS		 2343 set_float_exception_flags(0, &env->fpu->fp_status);
2344 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
2345 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
8dfdb87c
TS		 2346 update_fcr31();
2347}
2348FLOAT_OP(rsqrt1, ps)
2349{
ead9360e
TS		 2350 set_float_exception_flags(0, &env->fpu->fp_status);
2351 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
2352 FSTH2 = float32_sqrt(FSTH0, &env->fpu->fp_status);
2353 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
2354 FSTH2 = float32_div(FLOAT_ONE32, FSTH2, &env->fpu->fp_status);
8dfdb87c 2355 update_fcr31();
57fa1fb3 2356}
57fa1fb3 2357
fd4a04eb
TS		 2358/* binary operations */
2359#define FLOAT_BINOP(name) \
2360FLOAT_OP(name, d) \
2361{ \
ead9360e
TS		 2362 set_float_exception_flags(0, &env->fpu->fp_status); \
2363 FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \
2364 update_fcr31(); \
2365 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
5747c073 2366 DT2 = FLOAT_QNAN64; \
fd4a04eb
TS		 2367} \
2368FLOAT_OP(name, s) \
2369{ \
ead9360e
TS		 2370 set_float_exception_flags(0, &env->fpu->fp_status); \
2371 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
2372 update_fcr31(); \
2373 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
5747c073 2374 WT2 = FLOAT_QNAN32; \
fd4a04eb
TS		 2375} \
2376FLOAT_OP(name, ps) \
2377{ \
ead9360e
TS		 2378 set_float_exception_flags(0, &env->fpu->fp_status); \
2379 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
2380 FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \
fd4a04eb 2381 update_fcr31(); \
ead9360e 2382 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
5747c073
PB		 2383 WT2 = FLOAT_QNAN32; \
2384 WTH2 = FLOAT_QNAN32; \
3a5b360d 2385 } \
fd4a04eb
TS		 2386}
2387FLOAT_BINOP(add)
2388FLOAT_BINOP(sub)
2389FLOAT_BINOP(mul)
2390FLOAT_BINOP(div)
2391#undef FLOAT_BINOP
2392
a16336e4
TS		 2393/* ternary operations */
2394#define FLOAT_TERNOP(name1, name2) \
2395FLOAT_OP(name1 ## name2, d) \
2396{ \
2397 FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status); \
2398 FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status); \
2399} \
2400FLOAT_OP(name1 ## name2, s) \
2401{ \
2402 FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
2403 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
2404} \
2405FLOAT_OP(name1 ## name2, ps) \
2406{ \
2407 FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
2408 FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \
2409 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
2410 FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \
2411}
2412FLOAT_TERNOP(mul, add)
2413FLOAT_TERNOP(mul, sub)
2414#undef FLOAT_TERNOP
2415
2416/* negated ternary operations */
2417#define FLOAT_NTERNOP(name1, name2) \
2418FLOAT_OP(n ## name1 ## name2, d) \
2419{ \
2420 FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status); \
2421 FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status); \
2422 FDT2 = float64_chs(FDT2); \
2423} \
2424FLOAT_OP(n ## name1 ## name2, s) \
2425{ \
2426 FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
2427 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
2428 FST2 = float32_chs(FST2); \
2429} \
2430FLOAT_OP(n ## name1 ## name2, ps) \
2431{ \
2432 FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
2433 FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \
2434 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
2435 FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \
2436 FST2 = float32_chs(FST2); \
2437 FSTH2 = float32_chs(FSTH2); \
2438}
2439FLOAT_NTERNOP(mul, add)
2440FLOAT_NTERNOP(mul, sub)
2441#undef FLOAT_NTERNOP
2442
8dfdb87c
TS		 2443/* MIPS specific binary operations */
2444FLOAT_OP(recip2, d)
2445{
ead9360e
TS		 2446 set_float_exception_flags(0, &env->fpu->fp_status);
2447 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
5747c073 2448 FDT2 = float64_chs(float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status));
8dfdb87c
TS		 2449 update_fcr31();
2450}
2451FLOAT_OP(recip2, s)
2452{
ead9360e
TS		 2453 set_float_exception_flags(0, &env->fpu->fp_status);
2454 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
5747c073 2455 FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
8dfdb87c
TS		 2456 update_fcr31();
2457}
2458FLOAT_OP(recip2, ps)
2459{
ead9360e
TS		 2460 set_float_exception_flags(0, &env->fpu->fp_status);
2461 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
2462 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
5747c073
PB		 2463 FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
2464 FSTH2 = float32_chs(float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status));
8dfdb87c
TS		 2465 update_fcr31();
2466}
2467
2468FLOAT_OP(rsqrt2, d)
2469{
ead9360e
TS		 2470 set_float_exception_flags(0, &env->fpu->fp_status);
2471 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
2472 FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status);
5747c073 2473 FDT2 = float64_chs(float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status));
8dfdb87c
TS		 2474 update_fcr31();
2475}
2476FLOAT_OP(rsqrt2, s)
2477{
ead9360e
TS		 2478 set_float_exception_flags(0, &env->fpu->fp_status);
2479 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
2480 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
5747c073 2481 FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
8dfdb87c
TS		 2482 update_fcr31();
2483}
2484FLOAT_OP(rsqrt2, ps)
2485{
ead9360e
TS		 2486 set_float_exception_flags(0, &env->fpu->fp_status);
2487 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
2488 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
2489 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
2490 FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status);
5747c073
PB		 2491 FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
2492 FSTH2 = float32_chs(float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status));
8dfdb87c 2493 update_fcr31();
57fa1fb3 2494}
57fa1fb3 2495
fd4a04eb
TS		 2496FLOAT_OP(addr, ps)
2497{
ead9360e
TS		 2498 set_float_exception_flags(0, &env->fpu->fp_status);
2499 FST2 = float32_add (FST0, FSTH0, &env->fpu->fp_status);
2500 FSTH2 = float32_add (FST1, FSTH1, &env->fpu->fp_status);
fd4a04eb
TS		 2501 update_fcr31();
2502}
2503
57fa1fb3
TS		 2504FLOAT_OP(mulr, ps)
2505{
ead9360e
TS		 2506 set_float_exception_flags(0, &env->fpu->fp_status);
2507 FST2 = float32_mul (FST0, FSTH0, &env->fpu->fp_status);
2508 FSTH2 = float32_mul (FST1, FSTH1, &env->fpu->fp_status);
57fa1fb3
TS		 2509 update_fcr31();
2510}
2511
8dfdb87c 2512/* compare operations */
fd4a04eb
TS		 2513#define FOP_COND_D(op, cond) \
2514void do_cmp_d_ ## op (long cc) \
2515{ \
2516 int c = cond; \
2517 update_fcr31(); \
2518 if (c) \
ead9360e 2519 SET_FP_COND(cc, env->fpu); \
fd4a04eb 2520 else \
ead9360e 2521 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb
TS		 2522} \
2523void do_cmpabs_d_ ## op (long cc) \
2524{ \
2525 int c; \
6b5435d7
TS		 2526 FDT0 = float64_abs(FDT0); \
2527 FDT1 = float64_abs(FDT1); \
fd4a04eb
TS		 2528 c = cond; \
2529 update_fcr31(); \
2530 if (c) \
ead9360e 2531 SET_FP_COND(cc, env->fpu); \
fd4a04eb 2532 else \
ead9360e 2533 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb
TS		 2534}
2535
2536int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
2537{
2538 if (float64_is_signaling_nan(a) ||
2539 float64_is_signaling_nan(b) ||
2540 (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
2541 float_raise(float_flag_invalid, status);
2542 return 1;
2543 } else if (float64_is_nan(a) || float64_is_nan(b)) {
2544 return 1;
2545 } else {
2546 return 0;
2547 }
2548}
2549
2550/* NOTE: the comma operator will make "cond" to eval to false,
2551 * but float*_is_unordered() is still called. */
ead9360e
TS		 2552FOP_COND_D(f, (float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status), 0))
2553FOP_COND_D(un, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status))
2554FOP_COND_D(eq, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
2555FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
2556FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
2557FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
2558FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
2559FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
fd4a04eb
TS		 2560/* NOTE: the comma operator will make "cond" to eval to false,
2561 * but float*_is_unordered() is still called. */
ead9360e
TS		 2562FOP_COND_D(sf, (float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status), 0))
2563FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status))
2564FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
2565FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
2566FOP_COND_D(lt, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
2567FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
2568FOP_COND_D(le, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
2569FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
fd4a04eb
TS		 2570
2571#define FOP_COND_S(op, cond) \
2572void do_cmp_s_ ## op (long cc) \
2573{ \
2574 int c = cond; \
2575 update_fcr31(); \
2576 if (c) \
ead9360e 2577 SET_FP_COND(cc, env->fpu); \
fd4a04eb 2578 else \
ead9360e 2579 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb
TS		 2580} \
2581void do_cmpabs_s_ ## op (long cc) \
2582{ \
2583 int c; \
5747c073
PB		 2584 FST0 = float32_abs(FST0); \
2585 FST1 = float32_abs(FST1); \
fd4a04eb
TS		 2586 c = cond; \
2587 update_fcr31(); \
2588 if (c) \
ead9360e 2589 SET_FP_COND(cc, env->fpu); \
fd4a04eb 2590 else \
ead9360e 2591 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb
TS		 2592}
2593
2594flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
2595{
fd4a04eb
TS		 2596 if (float32_is_signaling_nan(a) ||
2597 float32_is_signaling_nan(b) ||
2598 (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
2599 float_raise(float_flag_invalid, status);
2600 return 1;
2601 } else if (float32_is_nan(a) || float32_is_nan(b)) {
2602 return 1;
2603 } else {
2604 return 0;
2605 }
2606}
2607
2608/* NOTE: the comma operator will make "cond" to eval to false,
2609 * but float*_is_unordered() is still called. */
ead9360e
TS		 2610FOP_COND_S(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0))
2611FOP_COND_S(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status))
2612FOP_COND_S(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
2613FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
2614FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
2615FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
2616FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
2617FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
fd4a04eb
TS		 2618/* NOTE: the comma operator will make "cond" to eval to false,
2619 * but float*_is_unordered() is still called. */
ead9360e
TS		 2620FOP_COND_S(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0))
2621FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status))
2622FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
2623FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
2624FOP_COND_S(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
2625FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
2626FOP_COND_S(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
2627FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
fd4a04eb
TS		 2628
2629#define FOP_COND_PS(op, condl, condh) \
2630void do_cmp_ps_ ## op (long cc) \
2631{ \
2632 int cl = condl; \
2633 int ch = condh; \
2634 update_fcr31(); \
2635 if (cl) \
ead9360e 2636 SET_FP_COND(cc, env->fpu); \
fd4a04eb 2637 else \
ead9360e 2638 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb 2639 if (ch) \
ead9360e 2640 SET_FP_COND(cc + 1, env->fpu); \
fd4a04eb 2641 else \
ead9360e 2642 CLEAR_FP_COND(cc + 1, env->fpu); \
fd4a04eb
TS		 2643} \
2644void do_cmpabs_ps_ ## op (long cc) \
2645{ \
2646 int cl, ch; \
5747c073
PB		 2647 FST0 = float32_abs(FST0); \
2648 FSTH0 = float32_abs(FSTH0); \
2649 FST1 = float32_abs(FST1); \
2650 FSTH1 = float32_abs(FSTH1); \
fd4a04eb
TS		 2651 cl = condl; \
2652 ch = condh; \
2653 update_fcr31(); \
2654 if (cl) \
ead9360e 2655 SET_FP_COND(cc, env->fpu); \
fd4a04eb 2656 else \
ead9360e 2657 CLEAR_FP_COND(cc, env->fpu); \
fd4a04eb 2658 if (ch) \
ead9360e 2659 SET_FP_COND(cc + 1, env->fpu); \
fd4a04eb 2660 else \
ead9360e 2661 CLEAR_FP_COND(cc + 1, env->fpu); \
fd4a04eb
TS		 2662}
2663
2664/* NOTE: the comma operator will make "cond" to eval to false,
2665 * but float*_is_unordered() is still called. */
ead9360e
TS		 2666FOP_COND_PS(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0),
2667 (float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status), 0))
2668FOP_COND_PS(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status),
2669 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status))
2670FOP_COND_PS(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
2671 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
2672FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
2673 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
2674FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
2675 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
2676FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
2677 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
2678FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
2679 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
2680FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
2681 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
fd4a04eb
TS		 2682/* NOTE: the comma operator will make "cond" to eval to false,
2683 * but float*_is_unordered() is still called. */
ead9360e
TS		 2684FOP_COND_PS(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0),
2685 (float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status), 0))
2686FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status),
2687 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status))
2688FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
2689 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
2690FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
2691 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
2692FOP_COND_PS(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
2693 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
2694FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
2695 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
2696FOP_COND_PS(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
2697 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
2698FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
2699 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
Qemu copy for testing