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6af0bf9c FB |
1 | /* |
2 | * MIPS32 emulation for qemu: main translation routines. | |
3 | * | |
4 | * Copyright (c) 2004-2005 Jocelyn Mayer | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | #include <stdarg.h> | |
22 | #include <stdlib.h> | |
23 | #include <stdio.h> | |
24 | #include <string.h> | |
25 | #include <inttypes.h> | |
26 | ||
27 | #include "cpu.h" | |
28 | #include "exec-all.h" | |
29 | #include "disas.h" | |
30 | ||
eeef26cd | 31 | //#define MIPS_DEBUG_DISAS |
6af0bf9c FB |
32 | //#define MIPS_SINGLE_STEP |
33 | ||
c53be334 FB |
34 | #ifdef USE_DIRECT_JUMP |
35 | #define TBPARAM(x) | |
36 | #else | |
37 | #define TBPARAM(x) (long)(x) | |
38 | #endif | |
39 | ||
6af0bf9c FB |
40 | enum { |
41 | #define DEF(s, n, copy_size) INDEX_op_ ## s, | |
42 | #include "opc.h" | |
43 | #undef DEF | |
44 | NB_OPS, | |
45 | }; | |
46 | ||
47 | static uint16_t *gen_opc_ptr; | |
48 | static uint32_t *gen_opparam_ptr; | |
49 | ||
50 | #include "gen-op.h" | |
51 | ||
e37e863f FB |
52 | /* MIPS opcodes */ |
53 | #define EXT_SPECIAL 0x100 | |
54 | #define EXT_SPECIAL2 0x200 | |
55 | #define EXT_REGIMM 0x300 | |
56 | #define EXT_CP0 0x400 | |
57 | #define EXT_CP1 0x500 | |
58 | #define EXT_CP2 0x600 | |
59 | #define EXT_CP3 0x700 | |
60 | ||
61 | enum { | |
62 | /* indirect opcode tables */ | |
63 | OPC_SPECIAL = 0x00, | |
64 | OPC_BREGIMM = 0x01, | |
65 | OPC_CP0 = 0x10, | |
66 | OPC_CP1 = 0x11, | |
67 | OPC_CP2 = 0x12, | |
68 | OPC_CP3 = 0x13, | |
69 | OPC_SPECIAL2 = 0x1C, | |
70 | /* arithmetic with immediate */ | |
71 | OPC_ADDI = 0x08, | |
72 | OPC_ADDIU = 0x09, | |
73 | OPC_SLTI = 0x0A, | |
74 | OPC_SLTIU = 0x0B, | |
75 | OPC_ANDI = 0x0C, | |
76 | OPC_ORI = 0x0D, | |
77 | OPC_XORI = 0x0E, | |
78 | OPC_LUI = 0x0F, | |
79 | /* Jump and branches */ | |
80 | OPC_J = 0x02, | |
81 | OPC_JAL = 0x03, | |
82 | OPC_BEQ = 0x04, /* Unconditional if rs = rt = 0 (B) */ | |
83 | OPC_BEQL = 0x14, | |
84 | OPC_BNE = 0x05, | |
85 | OPC_BNEL = 0x15, | |
86 | OPC_BLEZ = 0x06, | |
87 | OPC_BLEZL = 0x16, | |
88 | OPC_BGTZ = 0x07, | |
89 | OPC_BGTZL = 0x17, | |
90 | OPC_JALX = 0x1D, /* MIPS 16 only */ | |
91 | /* Load and stores */ | |
92 | OPC_LB = 0x20, | |
93 | OPC_LH = 0x21, | |
94 | OPC_LWL = 0x22, | |
95 | OPC_LW = 0x23, | |
96 | OPC_LBU = 0x24, | |
97 | OPC_LHU = 0x25, | |
98 | OPC_LWR = 0x26, | |
99 | OPC_SB = 0x28, | |
100 | OPC_SH = 0x29, | |
101 | OPC_SWL = 0x2A, | |
102 | OPC_SW = 0x2B, | |
103 | OPC_SWR = 0x2E, | |
104 | OPC_LL = 0x30, | |
105 | OPC_SC = 0x38, | |
106 | /* Floating point load/store */ | |
107 | OPC_LWC1 = 0x31, | |
108 | OPC_LWC2 = 0x32, | |
109 | OPC_LDC1 = 0x35, | |
110 | OPC_LDC2 = 0x36, | |
111 | OPC_SWC1 = 0x39, | |
112 | OPC_SWC2 = 0x3A, | |
113 | OPC_SDC1 = 0x3D, | |
114 | OPC_SDC2 = 0x3E, | |
115 | /* Cache and prefetch */ | |
116 | OPC_CACHE = 0x2F, | |
117 | OPC_PREF = 0x33, | |
118 | }; | |
119 | ||
120 | /* MIPS special opcodes */ | |
121 | enum { | |
122 | /* Shifts */ | |
123 | OPC_SLL = 0x00 | EXT_SPECIAL, | |
124 | /* NOP is SLL r0, r0, 0 */ | |
125 | /* SSNOP is SLL r0, r0, 1 */ | |
126 | OPC_SRL = 0x02 | EXT_SPECIAL, | |
127 | OPC_SRA = 0x03 | EXT_SPECIAL, | |
128 | OPC_SLLV = 0x04 | EXT_SPECIAL, | |
129 | OPC_SRLV = 0x06 | EXT_SPECIAL, | |
130 | OPC_SRAV = 0x07 | EXT_SPECIAL, | |
131 | /* Multiplication / division */ | |
132 | OPC_MULT = 0x18 | EXT_SPECIAL, | |
133 | OPC_MULTU = 0x19 | EXT_SPECIAL, | |
134 | OPC_DIV = 0x1A | EXT_SPECIAL, | |
135 | OPC_DIVU = 0x1B | EXT_SPECIAL, | |
136 | /* 2 registers arithmetic / logic */ | |
137 | OPC_ADD = 0x20 | EXT_SPECIAL, | |
138 | OPC_ADDU = 0x21 | EXT_SPECIAL, | |
139 | OPC_SUB = 0x22 | EXT_SPECIAL, | |
140 | OPC_SUBU = 0x23 | EXT_SPECIAL, | |
141 | OPC_AND = 0x24 | EXT_SPECIAL, | |
142 | OPC_OR = 0x25 | EXT_SPECIAL, | |
143 | OPC_XOR = 0x26 | EXT_SPECIAL, | |
144 | OPC_NOR = 0x27 | EXT_SPECIAL, | |
145 | OPC_SLT = 0x2A | EXT_SPECIAL, | |
146 | OPC_SLTU = 0x2B | EXT_SPECIAL, | |
147 | /* Jumps */ | |
148 | OPC_JR = 0x08 | EXT_SPECIAL, | |
149 | OPC_JALR = 0x09 | EXT_SPECIAL, | |
150 | /* Traps */ | |
151 | OPC_TGE = 0x30 | EXT_SPECIAL, | |
152 | OPC_TGEU = 0x31 | EXT_SPECIAL, | |
153 | OPC_TLT = 0x32 | EXT_SPECIAL, | |
154 | OPC_TLTU = 0x33 | EXT_SPECIAL, | |
155 | OPC_TEQ = 0x34 | EXT_SPECIAL, | |
156 | OPC_TNE = 0x36 | EXT_SPECIAL, | |
157 | /* HI / LO registers load & stores */ | |
158 | OPC_MFHI = 0x10 | EXT_SPECIAL, | |
159 | OPC_MTHI = 0x11 | EXT_SPECIAL, | |
160 | OPC_MFLO = 0x12 | EXT_SPECIAL, | |
161 | OPC_MTLO = 0x13 | EXT_SPECIAL, | |
162 | /* Conditional moves */ | |
163 | OPC_MOVZ = 0x0A | EXT_SPECIAL, | |
164 | OPC_MOVN = 0x0B | EXT_SPECIAL, | |
165 | ||
166 | OPC_MOVCI = 0x01 | EXT_SPECIAL, | |
167 | ||
168 | /* Special */ | |
169 | OPC_PMON = 0x05 | EXT_SPECIAL, | |
170 | OPC_SYSCALL = 0x0C | EXT_SPECIAL, | |
171 | OPC_BREAK = 0x0D | EXT_SPECIAL, | |
172 | OPC_SYNC = 0x0F | EXT_SPECIAL, | |
173 | }; | |
174 | ||
175 | enum { | |
176 | /* Mutiply & xxx operations */ | |
177 | OPC_MADD = 0x00 | EXT_SPECIAL2, | |
178 | OPC_MADDU = 0x01 | EXT_SPECIAL2, | |
179 | OPC_MUL = 0x02 | EXT_SPECIAL2, | |
180 | OPC_MSUB = 0x04 | EXT_SPECIAL2, | |
181 | OPC_MSUBU = 0x05 | EXT_SPECIAL2, | |
182 | /* Misc */ | |
183 | OPC_CLZ = 0x20 | EXT_SPECIAL2, | |
184 | OPC_CLO = 0x21 | EXT_SPECIAL2, | |
185 | /* Special */ | |
186 | OPC_SDBBP = 0x3F | EXT_SPECIAL2, | |
187 | }; | |
188 | ||
189 | /* Branch REGIMM */ | |
190 | enum { | |
191 | OPC_BLTZ = 0x00 | EXT_REGIMM, | |
192 | OPC_BLTZL = 0x02 | EXT_REGIMM, | |
193 | OPC_BGEZ = 0x01 | EXT_REGIMM, | |
194 | OPC_BGEZL = 0x03 | EXT_REGIMM, | |
195 | OPC_BLTZAL = 0x10 | EXT_REGIMM, | |
196 | OPC_BLTZALL = 0x12 | EXT_REGIMM, | |
197 | OPC_BGEZAL = 0x11 | EXT_REGIMM, | |
198 | OPC_BGEZALL = 0x13 | EXT_REGIMM, | |
199 | OPC_TGEI = 0x08 | EXT_REGIMM, | |
200 | OPC_TGEIU = 0x09 | EXT_REGIMM, | |
201 | OPC_TLTI = 0x0A | EXT_REGIMM, | |
202 | OPC_TLTIU = 0x0B | EXT_REGIMM, | |
203 | OPC_TEQI = 0x0C | EXT_REGIMM, | |
204 | OPC_TNEI = 0x0E | EXT_REGIMM, | |
205 | }; | |
206 | ||
207 | enum { | |
208 | /* Coprocessor 0 (MMU) */ | |
209 | OPC_MFC0 = 0x00 | EXT_CP0, | |
210 | OPC_MTC0 = 0x04 | EXT_CP0, | |
211 | OPC_TLBR = 0x01 | EXT_CP0, | |
212 | OPC_TLBWI = 0x02 | EXT_CP0, | |
213 | OPC_TLBWR = 0x06 | EXT_CP0, | |
214 | OPC_TLBP = 0x08 | EXT_CP0, | |
215 | OPC_ERET = 0x18 | EXT_CP0, | |
216 | OPC_DERET = 0x1F | EXT_CP0, | |
217 | OPC_WAIT = 0x20 | EXT_CP0, | |
218 | }; | |
219 | ||
6af0bf9c FB |
220 | const unsigned char *regnames[] = |
221 | { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
222 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
223 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
224 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", }; | |
225 | ||
226 | /* Warning: no function for r0 register (hard wired to zero) */ | |
227 | #define GEN32(func, NAME) \ | |
228 | static GenOpFunc *NAME ## _table [32] = { \ | |
229 | NULL, NAME ## 1, NAME ## 2, NAME ## 3, \ | |
230 | NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ | |
231 | NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ | |
232 | NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ | |
233 | NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \ | |
234 | NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ | |
235 | NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ | |
236 | NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ | |
237 | }; \ | |
238 | static inline void func(int n) \ | |
239 | { \ | |
240 | NAME ## _table[n](); \ | |
241 | } | |
242 | ||
243 | /* General purpose registers moves */ | |
244 | GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr); | |
245 | GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr); | |
246 | GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr); | |
247 | ||
248 | GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr); | |
249 | GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr); | |
250 | ||
251 | typedef struct DisasContext { | |
252 | struct TranslationBlock *tb; | |
253 | target_ulong pc, saved_pc; | |
254 | uint32_t opcode; | |
255 | /* Routine used to access memory */ | |
256 | int mem_idx; | |
257 | uint32_t hflags, saved_hflags; | |
258 | uint32_t CP0_Status; | |
259 | int bstate; | |
260 | target_ulong btarget; | |
261 | } DisasContext; | |
262 | ||
263 | enum { | |
264 | BS_NONE = 0, /* We go out of the TB without reaching a branch or an | |
265 | * exception condition | |
266 | */ | |
267 | BS_STOP = 1, /* We want to stop translation for any reason */ | |
268 | BS_BRANCH = 2, /* We reached a branch condition */ | |
269 | BS_EXCP = 3, /* We reached an exception condition */ | |
270 | }; | |
271 | ||
272 | #if defined MIPS_DEBUG_DISAS | |
273 | #define MIPS_DEBUG(fmt, args...) \ | |
274 | do { \ | |
275 | if (loglevel & CPU_LOG_TB_IN_ASM) { \ | |
276 | fprintf(logfile, "%08x: %08x " fmt "\n", \ | |
277 | ctx->pc, ctx->opcode , ##args); \ | |
278 | } \ | |
279 | } while (0) | |
280 | #else | |
281 | #define MIPS_DEBUG(fmt, args...) do { } while(0) | |
282 | #endif | |
283 | ||
284 | #define MIPS_INVAL(op) \ | |
285 | do { \ | |
286 | MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \ | |
287 | ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \ | |
288 | } while (0) | |
289 | ||
290 | #define GEN_LOAD_REG_TN(Tn, Rn) \ | |
291 | do { \ | |
292 | if (Rn == 0) { \ | |
293 | glue(gen_op_reset_, Tn)(); \ | |
294 | } else { \ | |
295 | glue(gen_op_load_gpr_, Tn)(Rn); \ | |
296 | } \ | |
297 | } while (0) | |
298 | ||
299 | #define GEN_LOAD_IMM_TN(Tn, Imm) \ | |
300 | do { \ | |
301 | if (Imm == 0) { \ | |
302 | glue(gen_op_reset_, Tn)(); \ | |
303 | } else { \ | |
304 | glue(gen_op_set_, Tn)(Imm); \ | |
305 | } \ | |
306 | } while (0) | |
307 | ||
308 | #define GEN_STORE_TN_REG(Rn, Tn) \ | |
309 | do { \ | |
310 | if (Rn != 0) { \ | |
311 | glue(glue(gen_op_store_, Tn),_gpr)(Rn); \ | |
312 | } \ | |
313 | } while (0) | |
314 | ||
315 | static inline void save_cpu_state (DisasContext *ctx, int do_save_pc) | |
316 | { | |
317 | #if defined MIPS_DEBUG_DISAS | |
318 | if (loglevel & CPU_LOG_TB_IN_ASM) { | |
319 | fprintf(logfile, "hflags %08x saved %08x\n", | |
320 | ctx->hflags, ctx->saved_hflags); | |
321 | } | |
322 | #endif | |
323 | if (do_save_pc && ctx->pc != ctx->saved_pc) { | |
324 | gen_op_save_pc(ctx->pc); | |
325 | ctx->saved_pc = ctx->pc; | |
326 | } | |
327 | if (ctx->hflags != ctx->saved_hflags) { | |
328 | gen_op_save_state(ctx->hflags); | |
329 | ctx->saved_hflags = ctx->hflags; | |
330 | if (ctx->hflags & MIPS_HFLAG_BR) { | |
331 | gen_op_save_breg_target(); | |
332 | } else if (ctx->hflags & MIPS_HFLAG_B) { | |
333 | gen_op_save_btarget(ctx->btarget); | |
334 | } else if (ctx->hflags & MIPS_HFLAG_BMASK) { | |
335 | gen_op_save_bcond(); | |
336 | gen_op_save_btarget(ctx->btarget); | |
337 | } | |
338 | } | |
339 | } | |
340 | ||
341 | static inline void generate_exception (DisasContext *ctx, int excp) | |
342 | { | |
343 | #if defined MIPS_DEBUG_DISAS | |
344 | if (loglevel & CPU_LOG_TB_IN_ASM) | |
345 | fprintf(logfile, "%s: raise exception %d\n", __func__, excp); | |
346 | #endif | |
347 | save_cpu_state(ctx, 1); | |
348 | gen_op_raise_exception(excp); | |
349 | ctx->bstate = BS_EXCP; | |
350 | } | |
351 | ||
352 | #if defined(CONFIG_USER_ONLY) | |
353 | #define op_ldst(name) gen_op_##name##_raw() | |
354 | #define OP_LD_TABLE(width) | |
355 | #define OP_ST_TABLE(width) | |
356 | #else | |
357 | #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])() | |
358 | #define OP_LD_TABLE(width) \ | |
359 | static GenOpFunc *gen_op_l##width[] = { \ | |
360 | &gen_op_l##width##_user, \ | |
361 | &gen_op_l##width##_kernel, \ | |
362 | } | |
363 | #define OP_ST_TABLE(width) \ | |
364 | static GenOpFunc *gen_op_s##width[] = { \ | |
365 | &gen_op_s##width##_user, \ | |
366 | &gen_op_s##width##_kernel, \ | |
367 | } | |
368 | #endif | |
369 | ||
370 | #ifdef TARGET_MIPS64 | |
371 | OP_LD_TABLE(d); | |
372 | OP_LD_TABLE(dl); | |
373 | OP_LD_TABLE(dr); | |
374 | OP_ST_TABLE(d); | |
375 | OP_ST_TABLE(dl); | |
376 | OP_ST_TABLE(dr); | |
377 | #endif | |
378 | OP_LD_TABLE(w); | |
379 | OP_LD_TABLE(wl); | |
380 | OP_LD_TABLE(wr); | |
381 | OP_ST_TABLE(w); | |
382 | OP_ST_TABLE(wl); | |
383 | OP_ST_TABLE(wr); | |
384 | OP_LD_TABLE(h); | |
385 | OP_LD_TABLE(hu); | |
386 | OP_ST_TABLE(h); | |
387 | OP_LD_TABLE(b); | |
388 | OP_LD_TABLE(bu); | |
389 | OP_ST_TABLE(b); | |
390 | OP_LD_TABLE(l); | |
391 | OP_ST_TABLE(c); | |
392 | ||
393 | /* Load and store */ | |
394 | static void gen_ldst (DisasContext *ctx, uint16_t opc, int rt, | |
395 | int base, int16_t offset) | |
396 | { | |
397 | const unsigned char *opn = "unk"; | |
398 | ||
399 | if (base == 0) { | |
400 | GEN_LOAD_IMM_TN(T0, offset); | |
401 | } else if (offset == 0) { | |
402 | gen_op_load_gpr_T0(base); | |
403 | } else { | |
404 | gen_op_load_gpr_T0(base); | |
405 | gen_op_set_T1(offset); | |
406 | gen_op_add(); | |
407 | } | |
408 | /* Don't do NOP if destination is zero: we must perform the actual | |
409 | * memory access | |
410 | */ | |
411 | switch (opc) { | |
412 | #if defined(TARGET_MIPS64) | |
413 | case OPC_LD: | |
414 | #if defined (MIPS_HAS_UNALIGNED_LS) | |
415 | case OPC_ULD: | |
416 | #endif | |
417 | op_ldst(ld); | |
418 | GEN_STORE_TN_REG(rt, T0); | |
419 | opn = "ld"; | |
420 | break; | |
421 | case OPC_SD: | |
422 | #if defined (MIPS_HAS_UNALIGNED_LS) | |
423 | case OPC_USD: | |
424 | #endif | |
425 | GEN_LOAD_REG_TN(T1, rt); | |
426 | op_ldst(sd); | |
427 | opn = "sd"; | |
428 | break; | |
429 | case OPC_LDL: | |
430 | op_ldst(ldl); | |
431 | GEN_STORE_TN_REG(rt, T0); | |
432 | opn = "ldl"; | |
433 | break; | |
434 | case OPC_SDL: | |
435 | GEN_LOAD_REG_TN(T1, rt); | |
436 | op_ldst(sdl); | |
437 | opn = "sdl"; | |
438 | break; | |
439 | case OPC_LDR: | |
440 | op_ldst(ldr); | |
441 | GEN_STORE_TN_REG(rt, T0); | |
442 | opn = "ldr"; | |
443 | break; | |
444 | case OPC_SDR: | |
445 | GEN_LOAD_REG_TN(T1, rt); | |
446 | op_ldst(sdr); | |
447 | opn = "sdr"; | |
448 | break; | |
449 | #endif | |
450 | case OPC_LW: | |
451 | #if defined (MIPS_HAS_UNALIGNED_LS) | |
452 | case OPC_ULW: | |
453 | #endif | |
454 | op_ldst(lw); | |
455 | GEN_STORE_TN_REG(rt, T0); | |
456 | opn = "lw"; | |
457 | break; | |
458 | case OPC_SW: | |
459 | #if defined (MIPS_HAS_UNALIGNED_LS) | |
460 | case OPC_USW: | |
461 | #endif | |
462 | GEN_LOAD_REG_TN(T1, rt); | |
463 | op_ldst(sw); | |
464 | opn = "sw"; | |
465 | break; | |
466 | case OPC_LH: | |
467 | #if defined (MIPS_HAS_UNALIGNED_LS) | |
468 | case OPC_ULH: | |
469 | #endif | |
470 | op_ldst(lh); | |
471 | GEN_STORE_TN_REG(rt, T0); | |
472 | opn = "lh"; | |
473 | break; | |
474 | case OPC_SH: | |
475 | #if defined (MIPS_HAS_UNALIGNED_LS) | |
476 | case OPC_USH: | |
477 | #endif | |
478 | GEN_LOAD_REG_TN(T1, rt); | |
479 | op_ldst(sh); | |
480 | opn = "sh"; | |
481 | break; | |
482 | case OPC_LHU: | |
483 | #if defined (MIPS_HAS_UNALIGNED_LS) | |
484 | case OPC_ULHU: | |
485 | #endif | |
486 | op_ldst(lhu); | |
487 | GEN_STORE_TN_REG(rt, T0); | |
488 | opn = "lhu"; | |
489 | break; | |
490 | case OPC_LB: | |
491 | op_ldst(lb); | |
492 | GEN_STORE_TN_REG(rt, T0); | |
493 | opn = "lb"; | |
494 | break; | |
495 | case OPC_SB: | |
496 | GEN_LOAD_REG_TN(T1, rt); | |
497 | op_ldst(sb); | |
498 | opn = "sb"; | |
499 | break; | |
500 | case OPC_LBU: | |
501 | op_ldst(lbu); | |
502 | GEN_STORE_TN_REG(rt, T0); | |
503 | opn = "lbu"; | |
504 | break; | |
505 | case OPC_LWL: | |
9d1d106a | 506 | GEN_LOAD_REG_TN(T1, rt); |
6af0bf9c FB |
507 | op_ldst(lwl); |
508 | GEN_STORE_TN_REG(rt, T0); | |
509 | opn = "lwl"; | |
510 | break; | |
511 | case OPC_SWL: | |
512 | GEN_LOAD_REG_TN(T1, rt); | |
513 | op_ldst(swl); | |
514 | opn = "swr"; | |
515 | break; | |
516 | case OPC_LWR: | |
9d1d106a | 517 | GEN_LOAD_REG_TN(T1, rt); |
6af0bf9c FB |
518 | op_ldst(lwr); |
519 | GEN_STORE_TN_REG(rt, T0); | |
520 | opn = "lwr"; | |
521 | break; | |
522 | case OPC_SWR: | |
523 | GEN_LOAD_REG_TN(T1, rt); | |
524 | op_ldst(swr); | |
525 | opn = "swr"; | |
526 | break; | |
527 | case OPC_LL: | |
528 | op_ldst(ll); | |
529 | GEN_STORE_TN_REG(rt, T0); | |
530 | opn = "ll"; | |
531 | break; | |
532 | case OPC_SC: | |
533 | GEN_LOAD_REG_TN(T1, rt); | |
534 | op_ldst(sc); | |
535 | GEN_STORE_TN_REG(rt, T0); | |
536 | opn = "sc"; | |
537 | break; | |
538 | default: | |
539 | MIPS_INVAL("load/store"); | |
540 | generate_exception(ctx, EXCP_RI); | |
541 | return; | |
542 | } | |
543 | MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]); | |
544 | } | |
545 | ||
546 | /* Arithmetic with immediate operand */ | |
547 | static void gen_arith_imm (DisasContext *ctx, uint16_t opc, int rt, | |
548 | int rs, int16_t imm) | |
549 | { | |
550 | uint32_t uimm; | |
551 | const unsigned char *opn = "unk"; | |
552 | ||
553 | if (rt == 0 && opc != OPC_ADDI) { | |
554 | /* if no destination, treat it as a NOP | |
555 | * For addi, we must generate the overflow exception when needed. | |
556 | */ | |
557 | MIPS_DEBUG("NOP"); | |
558 | return; | |
559 | } | |
560 | if (opc == OPC_ADDI || opc == OPC_ADDIU || | |
561 | opc == OPC_SLTI || opc == OPC_SLTIU) | |
562 | uimm = (int32_t)imm; /* Sign extent to 32 bits */ | |
563 | else | |
564 | uimm = (uint16_t)imm; | |
565 | if (opc != OPC_LUI) { | |
566 | GEN_LOAD_REG_TN(T0, rs); | |
567 | GEN_LOAD_IMM_TN(T1, uimm); | |
568 | } else { | |
569 | uimm = uimm << 16; | |
570 | GEN_LOAD_IMM_TN(T0, uimm); | |
571 | } | |
572 | switch (opc) { | |
573 | case OPC_ADDI: | |
574 | save_cpu_state(ctx, 1); | |
575 | gen_op_addo(); | |
576 | opn = "addi"; | |
577 | break; | |
578 | case OPC_ADDIU: | |
579 | gen_op_add(); | |
580 | opn = "addiu"; | |
581 | break; | |
582 | case OPC_SLTI: | |
583 | gen_op_lt(); | |
584 | opn = "slti"; | |
585 | break; | |
586 | case OPC_SLTIU: | |
587 | gen_op_ltu(); | |
588 | opn = "sltiu"; | |
589 | break; | |
590 | case OPC_ANDI: | |
591 | gen_op_and(); | |
592 | opn = "andi"; | |
593 | break; | |
594 | case OPC_ORI: | |
595 | gen_op_or(); | |
596 | opn = "ori"; | |
597 | break; | |
598 | case OPC_XORI: | |
599 | gen_op_xor(); | |
600 | opn = "xori"; | |
601 | break; | |
602 | case OPC_LUI: | |
603 | opn = "lui"; | |
604 | break; | |
605 | case OPC_SLL: | |
606 | gen_op_sll(); | |
607 | opn = "sll"; | |
608 | break; | |
609 | case OPC_SRA: | |
610 | gen_op_sra(); | |
611 | opn = "sra"; | |
612 | break; | |
613 | case OPC_SRL: | |
614 | gen_op_srl(); | |
615 | opn = "srl"; | |
616 | break; | |
617 | default: | |
618 | MIPS_INVAL("imm arith"); | |
619 | generate_exception(ctx, EXCP_RI); | |
620 | return; | |
621 | } | |
622 | GEN_STORE_TN_REG(rt, T0); | |
623 | MIPS_DEBUG("%s %s, %s, %x", opn, regnames[rt], regnames[rs], uimm); | |
624 | } | |
625 | ||
626 | /* Arithmetic */ | |
627 | static void gen_arith (DisasContext *ctx, uint16_t opc, | |
628 | int rd, int rs, int rt) | |
629 | { | |
630 | const unsigned char *opn = "unk"; | |
631 | ||
632 | if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB) { | |
633 | /* if no destination, treat it as a NOP | |
634 | * For add & sub, we must generate the overflow exception when needed. | |
635 | */ | |
636 | MIPS_DEBUG("NOP"); | |
637 | return; | |
638 | } | |
639 | GEN_LOAD_REG_TN(T0, rs); | |
640 | GEN_LOAD_REG_TN(T1, rt); | |
641 | switch (opc) { | |
642 | case OPC_ADD: | |
643 | save_cpu_state(ctx, 1); | |
644 | gen_op_addo(); | |
645 | opn = "add"; | |
646 | break; | |
647 | case OPC_ADDU: | |
648 | gen_op_add(); | |
649 | opn = "addu"; | |
650 | break; | |
651 | case OPC_SUB: | |
652 | save_cpu_state(ctx, 1); | |
653 | gen_op_subo(); | |
654 | opn = "sub"; | |
655 | break; | |
656 | case OPC_SUBU: | |
657 | gen_op_sub(); | |
658 | opn = "subu"; | |
659 | break; | |
660 | case OPC_SLT: | |
661 | gen_op_lt(); | |
662 | opn = "slt"; | |
663 | break; | |
664 | case OPC_SLTU: | |
665 | gen_op_ltu(); | |
666 | opn = "sltu"; | |
667 | break; | |
668 | case OPC_AND: | |
669 | gen_op_and(); | |
670 | opn = "and"; | |
671 | break; | |
672 | case OPC_NOR: | |
673 | gen_op_nor(); | |
674 | opn = "nor"; | |
675 | break; | |
676 | case OPC_OR: | |
677 | gen_op_or(); | |
678 | opn = "or"; | |
679 | break; | |
680 | case OPC_XOR: | |
681 | gen_op_xor(); | |
682 | opn = "xor"; | |
683 | break; | |
684 | case OPC_MUL: | |
685 | gen_op_mul(); | |
686 | opn = "mul"; | |
687 | break; | |
688 | case OPC_MOVN: | |
689 | gen_op_movn(rd); | |
690 | opn = "movn"; | |
691 | goto print; | |
692 | case OPC_MOVZ: | |
693 | gen_op_movz(rd); | |
694 | opn = "movz"; | |
695 | goto print; | |
696 | case OPC_SLLV: | |
697 | gen_op_sllv(); | |
698 | opn = "sllv"; | |
699 | break; | |
700 | case OPC_SRAV: | |
701 | gen_op_srav(); | |
702 | opn = "srav"; | |
703 | break; | |
704 | case OPC_SRLV: | |
705 | gen_op_srlv(); | |
706 | opn = "srlv"; | |
707 | break; | |
708 | default: | |
709 | MIPS_INVAL("arith"); | |
710 | generate_exception(ctx, EXCP_RI); | |
711 | return; | |
712 | } | |
713 | GEN_STORE_TN_REG(rd, T0); | |
714 | print: | |
715 | MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); | |
716 | } | |
717 | ||
718 | /* Arithmetic on HI/LO registers */ | |
719 | static void gen_HILO (DisasContext *ctx, uint16_t opc, int reg) | |
720 | { | |
721 | const unsigned char *opn = "unk"; | |
722 | ||
723 | if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) { | |
724 | /* Treat as a NOP */ | |
725 | MIPS_DEBUG("NOP"); | |
726 | return; | |
727 | } | |
728 | switch (opc) { | |
729 | case OPC_MFHI: | |
730 | gen_op_load_HI(); | |
731 | GEN_STORE_TN_REG(reg, T0); | |
732 | opn = "mfhi"; | |
733 | break; | |
734 | case OPC_MFLO: | |
735 | gen_op_load_LO(); | |
736 | GEN_STORE_TN_REG(reg, T0); | |
737 | opn = "mflo"; | |
738 | break; | |
739 | case OPC_MTHI: | |
740 | GEN_LOAD_REG_TN(T0, reg); | |
741 | gen_op_store_HI(); | |
742 | opn = "mthi"; | |
743 | break; | |
744 | case OPC_MTLO: | |
745 | GEN_LOAD_REG_TN(T0, reg); | |
746 | gen_op_store_LO(); | |
747 | opn = "mtlo"; | |
748 | break; | |
749 | default: | |
750 | MIPS_INVAL("HILO"); | |
751 | generate_exception(ctx, EXCP_RI); | |
752 | return; | |
753 | } | |
754 | MIPS_DEBUG("%s %s", opn, regnames[reg]); | |
755 | } | |
756 | ||
757 | static void gen_muldiv (DisasContext *ctx, uint16_t opc, | |
758 | int rs, int rt) | |
759 | { | |
760 | const unsigned char *opn = "unk"; | |
761 | ||
762 | GEN_LOAD_REG_TN(T0, rs); | |
763 | GEN_LOAD_REG_TN(T1, rt); | |
764 | switch (opc) { | |
765 | case OPC_DIV: | |
766 | gen_op_div(); | |
767 | opn = "div"; | |
768 | break; | |
769 | case OPC_DIVU: | |
770 | gen_op_divu(); | |
771 | opn = "divu"; | |
772 | break; | |
773 | case OPC_MULT: | |
774 | gen_op_mult(); | |
775 | opn = "mult"; | |
776 | break; | |
777 | case OPC_MULTU: | |
778 | gen_op_multu(); | |
779 | opn = "multu"; | |
780 | break; | |
781 | case OPC_MADD: | |
782 | gen_op_madd(); | |
783 | opn = "madd"; | |
784 | break; | |
785 | case OPC_MADDU: | |
786 | gen_op_maddu(); | |
787 | opn = "maddu"; | |
788 | break; | |
789 | case OPC_MSUB: | |
790 | gen_op_msub(); | |
791 | opn = "msub"; | |
792 | break; | |
793 | case OPC_MSUBU: | |
794 | gen_op_msubu(); | |
795 | opn = "msubu"; | |
796 | break; | |
797 | default: | |
798 | MIPS_INVAL("mul/div"); | |
799 | generate_exception(ctx, EXCP_RI); | |
800 | return; | |
801 | } | |
802 | MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]); | |
803 | } | |
804 | ||
805 | static void gen_cl (DisasContext *ctx, uint16_t opc, | |
806 | int rd, int rs) | |
807 | { | |
808 | const unsigned char *opn = "unk"; | |
809 | if (rd == 0) { | |
810 | /* Treat as a NOP */ | |
811 | MIPS_DEBUG("NOP"); | |
812 | return; | |
813 | } | |
814 | GEN_LOAD_REG_TN(T0, rs); | |
815 | switch (opc) { | |
816 | case OPC_CLO: | |
817 | /* CLO */ | |
818 | gen_op_clo(); | |
819 | opn = "clo"; | |
820 | break; | |
821 | case OPC_CLZ: | |
822 | /* CLZ */ | |
823 | gen_op_clz(); | |
824 | opn = "clz"; | |
825 | break; | |
826 | default: | |
827 | MIPS_INVAL("CLx"); | |
828 | generate_exception(ctx, EXCP_RI); | |
829 | return; | |
830 | } | |
831 | gen_op_store_T0_gpr(rd); | |
832 | MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]); | |
833 | } | |
834 | ||
835 | /* Traps */ | |
836 | static void gen_trap (DisasContext *ctx, uint16_t opc, | |
837 | int rs, int rt, int16_t imm) | |
838 | { | |
839 | int cond; | |
840 | ||
841 | cond = 0; | |
842 | /* Load needed operands */ | |
843 | switch (opc) { | |
844 | case OPC_TEQ: | |
845 | case OPC_TGE: | |
846 | case OPC_TGEU: | |
847 | case OPC_TLT: | |
848 | case OPC_TLTU: | |
849 | case OPC_TNE: | |
850 | /* Compare two registers */ | |
851 | if (rs != rt) { | |
852 | GEN_LOAD_REG_TN(T0, rs); | |
853 | GEN_LOAD_REG_TN(T1, rt); | |
854 | cond = 1; | |
855 | } | |
856 | case OPC_TEQI: | |
857 | case OPC_TGEI: | |
858 | case OPC_TGEIU: | |
859 | case OPC_TLTI: | |
860 | case OPC_TLTIU: | |
861 | case OPC_TNEI: | |
862 | /* Compare register to immediate */ | |
863 | if (rs != 0 || imm != 0) { | |
864 | GEN_LOAD_REG_TN(T0, rs); | |
865 | GEN_LOAD_IMM_TN(T1, (int32_t)imm); | |
866 | cond = 1; | |
867 | } | |
868 | break; | |
869 | } | |
870 | if (cond == 0) { | |
871 | switch (opc) { | |
872 | case OPC_TEQ: /* rs == rs */ | |
873 | case OPC_TEQI: /* r0 == 0 */ | |
874 | case OPC_TGE: /* rs >= rs */ | |
875 | case OPC_TGEI: /* r0 >= 0 */ | |
876 | case OPC_TGEU: /* rs >= rs unsigned */ | |
877 | case OPC_TGEIU: /* r0 >= 0 unsigned */ | |
878 | /* Always trap */ | |
879 | gen_op_set_T0(1); | |
880 | break; | |
881 | case OPC_TLT: /* rs < rs */ | |
882 | case OPC_TLTI: /* r0 < 0 */ | |
883 | case OPC_TLTU: /* rs < rs unsigned */ | |
884 | case OPC_TLTIU: /* r0 < 0 unsigned */ | |
885 | case OPC_TNE: /* rs != rs */ | |
886 | case OPC_TNEI: /* r0 != 0 */ | |
887 | /* Never trap: treat as NOP */ | |
888 | return; | |
889 | default: | |
890 | MIPS_INVAL("TRAP"); | |
891 | generate_exception(ctx, EXCP_RI); | |
892 | return; | |
893 | } | |
894 | } else { | |
895 | switch (opc) { | |
896 | case OPC_TEQ: | |
897 | case OPC_TEQI: | |
898 | gen_op_eq(); | |
899 | break; | |
900 | case OPC_TGE: | |
901 | case OPC_TGEI: | |
902 | gen_op_ge(); | |
903 | break; | |
904 | case OPC_TGEU: | |
905 | case OPC_TGEIU: | |
906 | gen_op_geu(); | |
907 | break; | |
908 | case OPC_TLT: | |
909 | case OPC_TLTI: | |
910 | gen_op_lt(); | |
911 | break; | |
912 | case OPC_TLTU: | |
913 | case OPC_TLTIU: | |
914 | gen_op_ltu(); | |
915 | break; | |
916 | case OPC_TNE: | |
917 | case OPC_TNEI: | |
918 | gen_op_ne(); | |
919 | break; | |
920 | default: | |
921 | MIPS_INVAL("TRAP"); | |
922 | generate_exception(ctx, EXCP_RI); | |
923 | return; | |
924 | } | |
925 | } | |
926 | save_cpu_state(ctx, 1); | |
927 | gen_op_trap(); | |
928 | ctx->bstate = BS_STOP; | |
929 | } | |
930 | ||
6e256c93 | 931 | static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
c53be334 | 932 | { |
6e256c93 FB |
933 | TranslationBlock *tb; |
934 | tb = ctx->tb; | |
935 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) { | |
936 | if (n == 0) | |
937 | gen_op_goto_tb0(TBPARAM(tb)); | |
938 | else | |
939 | gen_op_goto_tb1(TBPARAM(tb)); | |
940 | gen_op_save_pc(dest); | |
941 | gen_op_set_T0((long)tb + n); | |
942 | gen_op_exit_tb(); | |
943 | } else { | |
944 | gen_op_save_pc(dest); | |
945 | gen_op_set_T0(0); | |
946 | gen_op_exit_tb(); | |
947 | } | |
c53be334 FB |
948 | } |
949 | ||
6af0bf9c FB |
950 | /* Branches (before delay slot) */ |
951 | static void gen_compute_branch (DisasContext *ctx, uint16_t opc, | |
952 | int rs, int rt, int32_t offset) | |
953 | { | |
954 | target_ulong btarget; | |
955 | int blink, bcond; | |
956 | ||
957 | btarget = -1; | |
958 | blink = 0; | |
959 | bcond = 0; | |
960 | /* Load needed operands */ | |
961 | switch (opc) { | |
962 | case OPC_BEQ: | |
963 | case OPC_BEQL: | |
964 | case OPC_BNE: | |
965 | case OPC_BNEL: | |
966 | /* Compare two registers */ | |
967 | if (rs != rt) { | |
968 | GEN_LOAD_REG_TN(T0, rs); | |
969 | GEN_LOAD_REG_TN(T1, rt); | |
970 | bcond = 1; | |
971 | } | |
972 | btarget = ctx->pc + 4 + offset; | |
973 | break; | |
974 | case OPC_BGEZ: | |
975 | case OPC_BGEZAL: | |
976 | case OPC_BGEZALL: | |
977 | case OPC_BGEZL: | |
978 | case OPC_BGTZ: | |
979 | case OPC_BGTZL: | |
980 | case OPC_BLEZ: | |
981 | case OPC_BLEZL: | |
982 | case OPC_BLTZ: | |
983 | case OPC_BLTZAL: | |
984 | case OPC_BLTZALL: | |
985 | case OPC_BLTZL: | |
986 | /* Compare to zero */ | |
987 | if (rs != 0) { | |
988 | gen_op_load_gpr_T0(rs); | |
989 | bcond = 1; | |
990 | } | |
991 | btarget = ctx->pc + 4 + offset; | |
992 | break; | |
993 | case OPC_J: | |
994 | case OPC_JAL: | |
995 | /* Jump to immediate */ | |
bc9ed47b | 996 | btarget = ((ctx->pc + 4) & 0xF0000000) | offset; |
6af0bf9c FB |
997 | break; |
998 | case OPC_JR: | |
999 | case OPC_JALR: | |
1000 | /* Jump to register */ | |
1001 | if (offset != 0) { | |
1002 | /* Only hint = 0 is valid */ | |
1003 | generate_exception(ctx, EXCP_RI); | |
1004 | return; | |
1005 | } | |
1006 | GEN_LOAD_REG_TN(T2, rs); | |
1007 | break; | |
1008 | default: | |
1009 | MIPS_INVAL("branch/jump"); | |
1010 | generate_exception(ctx, EXCP_RI); | |
1011 | return; | |
1012 | } | |
1013 | if (bcond == 0) { | |
1014 | /* No condition to be computed */ | |
1015 | switch (opc) { | |
1016 | case OPC_BEQ: /* rx == rx */ | |
1017 | case OPC_BEQL: /* rx == rx likely */ | |
1018 | case OPC_BGEZ: /* 0 >= 0 */ | |
1019 | case OPC_BGEZL: /* 0 >= 0 likely */ | |
1020 | case OPC_BLEZ: /* 0 <= 0 */ | |
1021 | case OPC_BLEZL: /* 0 <= 0 likely */ | |
1022 | /* Always take */ | |
1023 | ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B; | |
1024 | MIPS_DEBUG("balways"); | |
1025 | break; | |
1026 | case OPC_BGEZAL: /* 0 >= 0 */ | |
1027 | case OPC_BGEZALL: /* 0 >= 0 likely */ | |
1028 | /* Always take and link */ | |
1029 | blink = 31; | |
1030 | ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B; | |
1031 | MIPS_DEBUG("balways and link"); | |
1032 | break; | |
1033 | case OPC_BNE: /* rx != rx */ | |
1034 | case OPC_BGTZ: /* 0 > 0 */ | |
1035 | case OPC_BLTZ: /* 0 < 0 */ | |
6af0bf9c FB |
1036 | /* Treated as NOP */ |
1037 | MIPS_DEBUG("bnever (NOP)"); | |
1038 | return; | |
eeef26cd FB |
1039 | case OPC_BLTZAL: /* 0 < 0 */ |
1040 | gen_op_set_T0(ctx->pc + 8); | |
1041 | gen_op_store_T0_gpr(31); | |
1042 | return; | |
1043 | case OPC_BLTZALL: /* 0 < 0 likely */ | |
1044 | gen_op_set_T0(ctx->pc + 8); | |
1045 | gen_op_store_T0_gpr(31); | |
1046 | gen_goto_tb(ctx, 0, ctx->pc + 4); | |
1047 | return; | |
6af0bf9c FB |
1048 | case OPC_BNEL: /* rx != rx likely */ |
1049 | case OPC_BGTZL: /* 0 > 0 likely */ | |
6af0bf9c FB |
1050 | case OPC_BLTZL: /* 0 < 0 likely */ |
1051 | /* Skip the instruction in the delay slot */ | |
1052 | MIPS_DEBUG("bnever and skip"); | |
6e256c93 | 1053 | gen_goto_tb(ctx, 0, ctx->pc + 4); |
6af0bf9c FB |
1054 | return; |
1055 | case OPC_J: | |
1056 | ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B; | |
1057 | MIPS_DEBUG("j %08x", btarget); | |
1058 | break; | |
1059 | case OPC_JAL: | |
1060 | blink = 31; | |
1061 | ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B; | |
1062 | MIPS_DEBUG("jal %08x", btarget); | |
1063 | break; | |
1064 | case OPC_JR: | |
1065 | ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BR; | |
1066 | MIPS_DEBUG("jr %s", regnames[rs]); | |
1067 | break; | |
1068 | case OPC_JALR: | |
1069 | blink = rt; | |
1070 | ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BR; | |
1071 | MIPS_DEBUG("jalr %s, %s", regnames[rt], regnames[rs]); | |
1072 | break; | |
1073 | default: | |
1074 | MIPS_INVAL("branch/jump"); | |
1075 | generate_exception(ctx, EXCP_RI); | |
1076 | return; | |
1077 | } | |
1078 | } else { | |
1079 | switch (opc) { | |
1080 | case OPC_BEQ: | |
1081 | gen_op_eq(); | |
1082 | MIPS_DEBUG("beq %s, %s, %08x", | |
1083 | regnames[rs], regnames[rt], btarget); | |
1084 | goto not_likely; | |
1085 | case OPC_BEQL: | |
1086 | gen_op_eq(); | |
1087 | MIPS_DEBUG("beql %s, %s, %08x", | |
1088 | regnames[rs], regnames[rt], btarget); | |
1089 | goto likely; | |
1090 | case OPC_BNE: | |
1091 | gen_op_ne(); | |
1092 | MIPS_DEBUG("bne %s, %s, %08x", | |
1093 | regnames[rs], regnames[rt], btarget); | |
1094 | goto not_likely; | |
1095 | case OPC_BNEL: | |
1096 | gen_op_ne(); | |
1097 | MIPS_DEBUG("bnel %s, %s, %08x", | |
1098 | regnames[rs], regnames[rt], btarget); | |
1099 | goto likely; | |
1100 | case OPC_BGEZ: | |
1101 | gen_op_gez(); | |
1102 | MIPS_DEBUG("bgez %s, %08x", regnames[rs], btarget); | |
1103 | goto not_likely; | |
1104 | case OPC_BGEZL: | |
1105 | gen_op_gez(); | |
1106 | MIPS_DEBUG("bgezl %s, %08x", regnames[rs], btarget); | |
1107 | goto likely; | |
1108 | case OPC_BGEZAL: | |
1109 | gen_op_gez(); | |
1110 | MIPS_DEBUG("bgezal %s, %08x", regnames[rs], btarget); | |
1111 | blink = 31; | |
1112 | goto not_likely; | |
1113 | case OPC_BGEZALL: | |
1114 | gen_op_gez(); | |
1115 | blink = 31; | |
1116 | MIPS_DEBUG("bgezall %s, %08x", regnames[rs], btarget); | |
1117 | goto likely; | |
1118 | case OPC_BGTZ: | |
1119 | gen_op_gtz(); | |
1120 | MIPS_DEBUG("bgtz %s, %08x", regnames[rs], btarget); | |
1121 | goto not_likely; | |
1122 | case OPC_BGTZL: | |
1123 | gen_op_gtz(); | |
1124 | MIPS_DEBUG("bgtzl %s, %08x", regnames[rs], btarget); | |
1125 | goto likely; | |
1126 | case OPC_BLEZ: | |
1127 | gen_op_lez(); | |
1128 | MIPS_DEBUG("blez %s, %08x", regnames[rs], btarget); | |
1129 | goto not_likely; | |
1130 | case OPC_BLEZL: | |
1131 | gen_op_lez(); | |
1132 | MIPS_DEBUG("blezl %s, %08x", regnames[rs], btarget); | |
1133 | goto likely; | |
1134 | case OPC_BLTZ: | |
1135 | gen_op_ltz(); | |
1136 | MIPS_DEBUG("bltz %s, %08x", regnames[rs], btarget); | |
1137 | goto not_likely; | |
1138 | case OPC_BLTZL: | |
1139 | gen_op_ltz(); | |
1140 | MIPS_DEBUG("bltzl %s, %08x", regnames[rs], btarget); | |
1141 | goto likely; | |
1142 | case OPC_BLTZAL: | |
1143 | gen_op_ltz(); | |
1144 | blink = 31; | |
1145 | MIPS_DEBUG("bltzal %s, %08x", regnames[rs], btarget); | |
1146 | not_likely: | |
1147 | ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BC; | |
1148 | break; | |
1149 | case OPC_BLTZALL: | |
1150 | gen_op_ltz(); | |
1151 | blink = 31; | |
1152 | MIPS_DEBUG("bltzall %s, %08x", regnames[rs], btarget); | |
1153 | likely: | |
1154 | ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BL; | |
1155 | break; | |
1156 | } | |
1157 | gen_op_set_bcond(); | |
1158 | } | |
1159 | MIPS_DEBUG("enter ds: link %d cond %02x target %08x", | |
1160 | blink, ctx->hflags, btarget); | |
1161 | ctx->btarget = btarget; | |
1162 | if (blink > 0) { | |
1163 | gen_op_set_T0(ctx->pc + 8); | |
1164 | gen_op_store_T0_gpr(blink); | |
1165 | } | |
1166 | return; | |
1167 | } | |
1168 | ||
1169 | /* CP0 (MMU and control) */ | |
1170 | static void gen_cp0 (DisasContext *ctx, uint16_t opc, int rt, int rd) | |
1171 | { | |
1172 | const unsigned char *opn = "unk"; | |
1173 | ||
bc2c3909 FB |
1174 | if (!(ctx->CP0_Status & (1 << CP0St_CU0)) && |
1175 | !(ctx->hflags & MIPS_HFLAG_UM) && | |
1176 | !(ctx->hflags & MIPS_HFLAG_ERL) && | |
1177 | !(ctx->hflags & MIPS_HFLAG_EXL)) { | |
6af0bf9c FB |
1178 | if (loglevel & CPU_LOG_TB_IN_ASM) { |
1179 | fprintf(logfile, "CP0 is not usable\n"); | |
1180 | } | |
1181 | gen_op_raise_exception_err(EXCP_CpU, 0); | |
1182 | return; | |
1183 | } | |
1184 | switch (opc) { | |
1185 | case OPC_MFC0: | |
1186 | if (rt == 0) { | |
1187 | /* Treat as NOP */ | |
1188 | return; | |
1189 | } | |
1190 | gen_op_mfc0(rd, ctx->opcode & 0x7); | |
1191 | gen_op_store_T0_gpr(rt); | |
1192 | opn = "mfc0"; | |
1193 | break; | |
1194 | case OPC_MTC0: | |
1195 | /* If we get an exception, we want to restart at next instruction */ | |
1196 | ctx->pc += 4; | |
1197 | save_cpu_state(ctx, 1); | |
1198 | ctx->pc -= 4; | |
1199 | GEN_LOAD_REG_TN(T0, rt); | |
1200 | gen_op_mtc0(rd, ctx->opcode & 0x7); | |
1201 | /* Stop translation as we may have switched the execution mode */ | |
1202 | ctx->bstate = BS_STOP; | |
1203 | opn = "mtc0"; | |
1204 | break; | |
1205 | #if defined(MIPS_USES_R4K_TLB) | |
1206 | case OPC_TLBWI: | |
1207 | gen_op_tlbwi(); | |
1208 | opn = "tlbwi"; | |
1209 | break; | |
1210 | case OPC_TLBWR: | |
1211 | gen_op_tlbwr(); | |
1212 | opn = "tlbwr"; | |
1213 | break; | |
1214 | case OPC_TLBP: | |
1215 | gen_op_tlbp(); | |
1216 | opn = "tlbp"; | |
1217 | break; | |
1218 | case OPC_TLBR: | |
1219 | gen_op_tlbr(); | |
1220 | opn = "tlbr"; | |
1221 | break; | |
1222 | #endif | |
1223 | case OPC_ERET: | |
1224 | opn = "eret"; | |
1225 | save_cpu_state(ctx, 0); | |
1226 | gen_op_eret(); | |
1227 | ctx->bstate = BS_EXCP; | |
1228 | break; | |
1229 | case OPC_DERET: | |
1230 | opn = "deret"; | |
1231 | if (!(ctx->hflags & MIPS_HFLAG_DM)) { | |
1232 | generate_exception(ctx, EXCP_RI); | |
1233 | } else { | |
1234 | save_cpu_state(ctx, 0); | |
1235 | gen_op_deret(); | |
1236 | ctx->bstate = BS_EXCP; | |
1237 | } | |
1238 | break; | |
1239 | /* XXX: TODO: WAIT */ | |
1240 | default: | |
1241 | if (loglevel & CPU_LOG_TB_IN_ASM) { | |
1242 | fprintf(logfile, "Invalid CP0 opcode: %08x %03x %03x %03x\n", | |
1243 | ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F, | |
1244 | ((ctx->opcode >> 16) & 0x1F)); | |
1245 | } | |
1246 | generate_exception(ctx, EXCP_RI); | |
1247 | return; | |
1248 | } | |
1249 | MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd); | |
1250 | } | |
1251 | ||
1252 | /* Coprocessor 1 (FPU) */ | |
1253 | ||
1254 | /* ISA extensions */ | |
1255 | /* MIPS16 extension to MIPS32 */ | |
1256 | /* SmartMIPS extension to MIPS32 */ | |
1257 | ||
1258 | #ifdef TARGET_MIPS64 | |
1259 | static void gen_arith64 (DisasContext *ctx, uint16_t opc) | |
1260 | { | |
1261 | if (func == 0x02 && rd == 0) { | |
1262 | /* NOP */ | |
1263 | return; | |
1264 | } | |
1265 | if (rs == 0 || rt == 0) { | |
1266 | gen_op_reset_T0(); | |
1267 | gen_op_save64(); | |
1268 | } else { | |
1269 | gen_op_load_gpr_T0(rs); | |
1270 | gen_op_load_gpr_T1(rt); | |
1271 | gen_op_save64(); | |
1272 | if (func & 0x01) | |
1273 | gen_op_mul64u(); | |
1274 | else | |
1275 | gen_op_mul64s(); | |
1276 | } | |
1277 | if (func & 0x02) | |
1278 | gen_op_add64(); | |
1279 | else | |
1280 | gen_op_sub64(); | |
1281 | } | |
1282 | ||
1283 | /* Coprocessor 3 (FPU) */ | |
1284 | ||
1285 | /* MDMX extension to MIPS64 */ | |
1286 | /* MIPS-3D extension to MIPS64 */ | |
1287 | ||
1288 | #endif | |
1289 | ||
c53be334 FB |
1290 | static void gen_blikely(DisasContext *ctx) |
1291 | { | |
eeef26cd FB |
1292 | int l1; |
1293 | l1 = gen_new_label(); | |
1294 | gen_op_jnz_T2(l1); | |
1295 | gen_op_save_state(ctx->hflags & ~(MIPS_HFLAG_BMASK | MIPS_HFLAG_DS)); | |
1296 | gen_goto_tb(ctx, 1, ctx->pc + 4); | |
1297 | gen_set_label(l1); | |
c53be334 FB |
1298 | } |
1299 | ||
6af0bf9c FB |
1300 | static void decode_opc (DisasContext *ctx) |
1301 | { | |
1302 | int32_t offset; | |
1303 | int rs, rt, rd, sa; | |
1304 | uint16_t op, op1; | |
1305 | int16_t imm; | |
1306 | ||
1307 | if ((ctx->hflags & MIPS_HFLAG_DS) && | |
1308 | (ctx->hflags & MIPS_HFLAG_BL)) { | |
1309 | /* Handle blikely not taken case */ | |
1310 | MIPS_DEBUG("blikely condition (%08x)", ctx->pc + 4); | |
c53be334 | 1311 | gen_blikely(ctx); |
6af0bf9c FB |
1312 | } |
1313 | op = ctx->opcode >> 26; | |
1314 | rs = ((ctx->opcode >> 21) & 0x1F); | |
1315 | rt = ((ctx->opcode >> 16) & 0x1F); | |
1316 | rd = ((ctx->opcode >> 11) & 0x1F); | |
1317 | sa = ((ctx->opcode >> 6) & 0x1F); | |
1318 | imm = (int16_t)ctx->opcode; | |
1319 | switch (op) { | |
1320 | case 0x00: /* Special opcode */ | |
1321 | op1 = ctx->opcode & 0x3F; | |
1322 | switch (op1) { | |
1323 | case 0x00: /* Arithmetic with immediate */ | |
1324 | case 0x02 ... 0x03: | |
1325 | gen_arith_imm(ctx, op1 | EXT_SPECIAL, rd, rt, sa); | |
1326 | break; | |
1327 | case 0x04: /* Arithmetic */ | |
1328 | case 0x06 ... 0x07: | |
1329 | case 0x0A ... 0x0B: | |
1330 | case 0x20 ... 0x27: | |
1331 | case 0x2A ... 0x2B: | |
1332 | gen_arith(ctx, op1 | EXT_SPECIAL, rd, rs, rt); | |
1333 | break; | |
1334 | case 0x18 ... 0x1B: /* MULT / DIV */ | |
1335 | gen_muldiv(ctx, op1 | EXT_SPECIAL, rs, rt); | |
1336 | break; | |
1337 | case 0x08 ... 0x09: /* Jumps */ | |
1338 | gen_compute_branch(ctx, op1 | EXT_SPECIAL, rs, rd, sa); | |
1339 | return; | |
1340 | case 0x30 ... 0x34: /* Traps */ | |
1341 | case 0x36: | |
1342 | gen_trap(ctx, op1 | EXT_SPECIAL, rs, rt, -1); | |
1343 | break; | |
1344 | case 0x10: /* Move from HI/LO */ | |
1345 | case 0x12: | |
1346 | gen_HILO(ctx, op1 | EXT_SPECIAL, rd); | |
1347 | break; | |
1348 | case 0x11: | |
1349 | case 0x13: /* Move to HI/LO */ | |
1350 | gen_HILO(ctx, op1 | EXT_SPECIAL, rs); | |
1351 | break; | |
1352 | case 0x0C: /* SYSCALL */ | |
1353 | generate_exception(ctx, EXCP_SYSCALL); | |
1354 | break; | |
1355 | case 0x0D: /* BREAK */ | |
1356 | generate_exception(ctx, EXCP_BREAK); | |
1357 | break; | |
1358 | case 0x0F: /* SYNC */ | |
1359 | /* Treat as a noop */ | |
1360 | break; | |
1361 | case 0x05: /* Pmon entry point */ | |
1362 | gen_op_pmon((ctx->opcode >> 6) & 0x1F); | |
1363 | break; | |
1364 | #if defined (MIPS_HAS_MOVCI) | |
1365 | case 0x01: /* MOVCI */ | |
1366 | #endif | |
1367 | #if defined (TARGET_MIPS64) | |
1368 | case 0x14: /* MIPS64 specific opcodes */ | |
1369 | case 0x16: | |
1370 | case 0x17: | |
1371 | case 0x1C ... 0x1F: | |
1372 | case 0x2C ... 0x2F: | |
1373 | case 0x37: | |
1374 | case 0x39 ... 0x3B: | |
1375 | case 0x3E ... 0x3F: | |
1376 | #endif | |
1377 | default: /* Invalid */ | |
1378 | MIPS_INVAL("special"); | |
1379 | generate_exception(ctx, EXCP_RI); | |
1380 | break; | |
1381 | } | |
1382 | break; | |
1383 | case 0x1C: /* Special2 opcode */ | |
1384 | op1 = ctx->opcode & 0x3F; | |
1385 | switch (op1) { | |
1386 | #if defined (MIPS_USES_R4K_EXT) | |
1387 | /* Those instructions are not part of MIPS32 core */ | |
1388 | case 0x00 ... 0x01: /* Multiply and add/sub */ | |
1389 | case 0x04 ... 0x05: | |
1390 | gen_muldiv(ctx, op1 | EXT_SPECIAL2, rs, rt); | |
1391 | break; | |
1392 | case 0x02: /* MUL */ | |
1393 | gen_arith(ctx, op1 | EXT_SPECIAL2, rd, rs, rt); | |
1394 | break; | |
1395 | case 0x20 ... 0x21: /* CLO / CLZ */ | |
1396 | gen_cl(ctx, op1 | EXT_SPECIAL2, rd, rs); | |
1397 | break; | |
1398 | #endif | |
1399 | case 0x3F: /* SDBBP */ | |
1400 | /* XXX: not clear which exception should be raised | |
1401 | * when in debug mode... | |
1402 | */ | |
1403 | if (!(ctx->hflags & MIPS_HFLAG_DM)) { | |
1404 | generate_exception(ctx, EXCP_DBp); | |
1405 | } else { | |
1406 | generate_exception(ctx, EXCP_DBp); | |
1407 | } | |
1408 | /* Treat as a noop */ | |
1409 | break; | |
1410 | default: /* Invalid */ | |
1411 | MIPS_INVAL("special2"); | |
1412 | generate_exception(ctx, EXCP_RI); | |
1413 | break; | |
1414 | } | |
1415 | break; | |
1416 | case 0x01: /* B REGIMM opcode */ | |
1417 | op1 = ((ctx->opcode >> 16) & 0x1F); | |
1418 | switch (op1) { | |
1419 | case 0x00 ... 0x03: /* REGIMM branches */ | |
1420 | case 0x10 ... 0x13: | |
1421 | gen_compute_branch(ctx, op1 | EXT_REGIMM, rs, -1, imm << 2); | |
1422 | return; | |
1423 | case 0x08 ... 0x0C: /* Traps */ | |
1424 | case 0x0E: | |
1425 | gen_trap(ctx, op1 | EXT_REGIMM, rs, -1, imm); | |
1426 | break; | |
1427 | default: /* Invalid */ | |
1428 | MIPS_INVAL("REGIMM"); | |
1429 | generate_exception(ctx, EXCP_RI); | |
1430 | break; | |
1431 | } | |
1432 | break; | |
1433 | case 0x10: /* CP0 opcode */ | |
1434 | op1 = ((ctx->opcode >> 21) & 0x1F); | |
1435 | switch (op1) { | |
1436 | case 0x00: | |
1437 | case 0x04: | |
1438 | gen_cp0(ctx, op1 | EXT_CP0, rt, rd); | |
1439 | break; | |
1440 | default: | |
1441 | gen_cp0(ctx, (ctx->opcode & 0x1F) | EXT_CP0, rt, rd); | |
1442 | break; | |
1443 | } | |
1444 | break; | |
1445 | case 0x08 ... 0x0F: /* Arithmetic with immediate opcode */ | |
1446 | gen_arith_imm(ctx, op, rt, rs, imm); | |
1447 | break; | |
1448 | case 0x02 ... 0x03: /* Jump */ | |
1449 | offset = (int32_t)(ctx->opcode & 0x03FFFFFF) << 2; | |
1450 | gen_compute_branch(ctx, op, rs, rt, offset); | |
1451 | return; | |
1452 | case 0x04 ... 0x07: /* Branch */ | |
1453 | case 0x14 ... 0x17: | |
1454 | gen_compute_branch(ctx, op, rs, rt, imm << 2); | |
1455 | return; | |
1456 | case 0x20 ... 0x26: /* Load and stores */ | |
1457 | case 0x28 ... 0x2E: | |
1458 | case 0x30: | |
1459 | case 0x38: | |
1460 | gen_ldst(ctx, op, rt, rs, imm); | |
1461 | break; | |
1462 | case 0x2F: /* Cache operation */ | |
1463 | /* Treat as a noop */ | |
1464 | break; | |
1465 | case 0x33: /* Prefetch */ | |
1466 | /* Treat as a noop */ | |
1467 | break; | |
1468 | case 0x3F: /* HACK */ | |
1469 | break; | |
1470 | #if defined(MIPS_USES_FPU) | |
1471 | case 0x31 ... 0x32: /* Floating point load/store */ | |
1472 | case 0x35 ... 0x36: | |
1473 | case 0x3A ... 0x3B: | |
1474 | case 0x3D ... 0x3E: | |
1475 | /* Not implemented */ | |
1476 | /* XXX: not correct */ | |
1477 | #endif | |
1478 | case 0x11: /* CP1 opcode */ | |
1479 | /* Not implemented */ | |
1480 | /* XXX: not correct */ | |
1481 | case 0x12: /* CP2 opcode */ | |
1482 | /* Not implemented */ | |
1483 | /* XXX: not correct */ | |
1484 | case 0x13: /* CP3 opcode */ | |
1485 | /* Not implemented */ | |
1486 | /* XXX: not correct */ | |
1487 | #if defined (TARGET_MIPS64) | |
1488 | case 0x18 ... 0x1B: | |
1489 | case 0x27: | |
1490 | case 0x34: | |
1491 | case 0x37: | |
1492 | /* MIPS64 opcodes */ | |
1493 | #endif | |
1494 | #if defined (MIPS_HAS_JALX) | |
1495 | case 0x1D: | |
1496 | /* JALX: not implemented */ | |
1497 | #endif | |
1498 | case 0x1E: | |
1499 | /* ASE specific */ | |
1500 | #if defined (MIPS_HAS_LSC) | |
1501 | case 0x31: /* LWC1 */ | |
1502 | case 0x32: /* LWC2 */ | |
1503 | case 0x35: /* SDC1 */ | |
1504 | case 0x36: /* SDC2 */ | |
1505 | #endif | |
1506 | default: /* Invalid */ | |
1507 | MIPS_INVAL(""); | |
1508 | generate_exception(ctx, EXCP_RI); | |
1509 | break; | |
1510 | } | |
1511 | if (ctx->hflags & MIPS_HFLAG_DS) { | |
1512 | int hflags = ctx->hflags; | |
1513 | /* Branches completion */ | |
1514 | ctx->hflags &= ~(MIPS_HFLAG_BMASK | MIPS_HFLAG_DS); | |
1515 | ctx->bstate = BS_BRANCH; | |
1516 | save_cpu_state(ctx, 0); | |
1517 | switch (hflags & MIPS_HFLAG_BMASK) { | |
1518 | case MIPS_HFLAG_B: | |
1519 | /* unconditional branch */ | |
1520 | MIPS_DEBUG("unconditional branch"); | |
6e256c93 | 1521 | gen_goto_tb(ctx, 0, ctx->btarget); |
6af0bf9c FB |
1522 | break; |
1523 | case MIPS_HFLAG_BL: | |
1524 | /* blikely taken case */ | |
1525 | MIPS_DEBUG("blikely branch taken"); | |
6e256c93 | 1526 | gen_goto_tb(ctx, 0, ctx->btarget); |
6af0bf9c FB |
1527 | break; |
1528 | case MIPS_HFLAG_BC: | |
1529 | /* Conditional branch */ | |
1530 | MIPS_DEBUG("conditional branch"); | |
c53be334 FB |
1531 | { |
1532 | int l1; | |
1533 | l1 = gen_new_label(); | |
1534 | gen_op_jnz_T2(l1); | |
6e256c93 | 1535 | gen_goto_tb(ctx, 1, ctx->pc + 4); |
eeef26cd FB |
1536 | gen_set_label(l1); |
1537 | gen_goto_tb(ctx, 0, ctx->btarget); | |
c53be334 | 1538 | } |
6af0bf9c FB |
1539 | break; |
1540 | case MIPS_HFLAG_BR: | |
1541 | /* unconditional branch to register */ | |
1542 | MIPS_DEBUG("branch to register"); | |
1543 | gen_op_breg(); | |
1544 | break; | |
1545 | default: | |
1546 | MIPS_DEBUG("unknown branch"); | |
1547 | break; | |
1548 | } | |
1549 | } | |
1550 | } | |
1551 | ||
1552 | int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, | |
1553 | int search_pc) | |
1554 | { | |
1555 | DisasContext ctx, *ctxp = &ctx; | |
1556 | target_ulong pc_start; | |
1557 | uint16_t *gen_opc_end; | |
1558 | int j, lj = -1; | |
1559 | ||
1560 | pc_start = tb->pc; | |
1561 | gen_opc_ptr = gen_opc_buf; | |
1562 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; | |
1563 | gen_opparam_ptr = gen_opparam_buf; | |
c53be334 | 1564 | nb_gen_labels = 0; |
6af0bf9c FB |
1565 | ctx.pc = pc_start; |
1566 | ctx.tb = tb; | |
1567 | ctx.bstate = BS_NONE; | |
1568 | /* Restore delay slot state */ | |
1569 | ctx.hflags = env->hflags; | |
1570 | ctx.saved_hflags = ctx.hflags; | |
1571 | if (ctx.hflags & MIPS_HFLAG_BR) { | |
1572 | gen_op_restore_breg_target(); | |
1573 | } else if (ctx.hflags & MIPS_HFLAG_B) { | |
1574 | ctx.btarget = env->btarget; | |
1575 | } else if (ctx.hflags & MIPS_HFLAG_BMASK) { | |
1576 | /* If we are in the delay slot of a conditional branch, | |
1577 | * restore the branch condition from env->bcond to T2 | |
1578 | */ | |
1579 | ctx.btarget = env->btarget; | |
1580 | gen_op_restore_bcond(); | |
1581 | } | |
1582 | #if defined(CONFIG_USER_ONLY) | |
1583 | ctx.mem_idx = 0; | |
1584 | #else | |
1585 | ctx.mem_idx = (ctx.hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM ? 0 : 1; | |
1586 | #endif | |
1587 | ctx.CP0_Status = env->CP0_Status; | |
1588 | #ifdef DEBUG_DISAS | |
1589 | if (loglevel & CPU_LOG_TB_CPU) { | |
1590 | fprintf(logfile, "------------------------------------------------\n"); | |
1591 | cpu_dump_state(env, logfile, fprintf, 0); | |
1592 | } | |
1593 | #endif | |
1594 | #if defined MIPS_DEBUG_DISAS | |
1595 | if (loglevel & CPU_LOG_TB_IN_ASM) | |
1596 | fprintf(logfile, "\ntb %p super %d cond %04x %04x\n", | |
1597 | tb, ctx.mem_idx, ctx.hflags, env->hflags); | |
1598 | #endif | |
1599 | while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) { | |
1600 | if (search_pc) { | |
1601 | j = gen_opc_ptr - gen_opc_buf; | |
1602 | save_cpu_state(ctxp, 1); | |
1603 | if (lj < j) { | |
1604 | lj++; | |
1605 | while (lj < j) | |
1606 | gen_opc_instr_start[lj++] = 0; | |
1607 | gen_opc_pc[lj] = ctx.pc; | |
1608 | gen_opc_instr_start[lj] = 1; | |
1609 | } | |
1610 | } | |
1611 | ctx.opcode = ldl_code(ctx.pc); | |
1612 | decode_opc(&ctx); | |
1613 | ctx.pc += 4; | |
1614 | if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) | |
1615 | break; | |
1616 | #if defined (MIPS_SINGLE_STEP) | |
1617 | break; | |
1618 | #endif | |
1619 | } | |
1620 | if (ctx.bstate != BS_BRANCH && ctx.bstate != BS_EXCP) { | |
1621 | save_cpu_state(ctxp, 0); | |
6e256c93 | 1622 | gen_goto_tb(&ctx, 0, ctx.pc); |
6af0bf9c FB |
1623 | } |
1624 | gen_op_reset_T0(); | |
1625 | /* Generate the return instruction */ | |
1626 | gen_op_exit_tb(); | |
1627 | *gen_opc_ptr = INDEX_op_end; | |
1628 | if (search_pc) { | |
1629 | j = gen_opc_ptr - gen_opc_buf; | |
1630 | lj++; | |
1631 | while (lj <= j) | |
1632 | gen_opc_instr_start[lj++] = 0; | |
1633 | tb->size = 0; | |
1634 | } else { | |
1635 | tb->size = ctx.pc - pc_start; | |
1636 | } | |
1637 | #ifdef DEBUG_DISAS | |
1638 | #if defined MIPS_DEBUG_DISAS | |
1639 | if (loglevel & CPU_LOG_TB_IN_ASM) | |
1640 | fprintf(logfile, "\n"); | |
1641 | #endif | |
1642 | if (loglevel & CPU_LOG_TB_IN_ASM) { | |
1643 | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start)); | |
1644 | target_disas(logfile, pc_start, ctx.pc - pc_start, 0); | |
1645 | fprintf(logfile, "\n"); | |
1646 | } | |
1647 | if (loglevel & CPU_LOG_TB_OP) { | |
1648 | fprintf(logfile, "OP:\n"); | |
1649 | dump_ops(gen_opc_buf, gen_opparam_buf); | |
1650 | fprintf(logfile, "\n"); | |
1651 | } | |
1652 | if (loglevel & CPU_LOG_TB_CPU) { | |
1653 | fprintf(logfile, "---------------- %d %08x\n", ctx.bstate, ctx.hflags); | |
1654 | } | |
1655 | #endif | |
1656 | ||
1657 | return 0; | |
1658 | } | |
1659 | ||
1660 | int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) | |
1661 | { | |
1662 | return gen_intermediate_code_internal(env, tb, 0); | |
1663 | } | |
1664 | ||
1665 | int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) | |
1666 | { | |
1667 | return gen_intermediate_code_internal(env, tb, 1); | |
1668 | } | |
1669 | ||
1670 | void cpu_dump_state (CPUState *env, FILE *f, | |
1671 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), | |
1672 | int flags) | |
1673 | { | |
568b600d | 1674 | uint32_t c0_status; |
6af0bf9c FB |
1675 | int i; |
1676 | ||
1677 | cpu_fprintf(f, "pc=0x%08x HI=0x%08x LO=0x%08x ds %04x %08x %d\n", | |
1678 | env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond); | |
1679 | for (i = 0; i < 32; i++) { | |
1680 | if ((i & 3) == 0) | |
1681 | cpu_fprintf(f, "GPR%02d:", i); | |
1682 | cpu_fprintf(f, " %s %08x", regnames[i], env->gpr[i]); | |
1683 | if ((i & 3) == 3) | |
1684 | cpu_fprintf(f, "\n"); | |
1685 | } | |
568b600d FB |
1686 | |
1687 | c0_status = env->CP0_Status; | |
1688 | if (env->hflags & MIPS_HFLAG_UM) | |
1689 | c0_status |= (1 << CP0St_UM); | |
1690 | if (env->hflags & MIPS_HFLAG_ERL) | |
1691 | c0_status |= (1 << CP0St_ERL); | |
1692 | if (env->hflags & MIPS_HFLAG_EXL) | |
1693 | c0_status |= (1 << CP0St_EXL); | |
1694 | ||
6af0bf9c | 1695 | cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x%08x\n", |
568b600d | 1696 | c0_status, env->CP0_Cause, env->CP0_EPC); |
6af0bf9c FB |
1697 | cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%08x\n", |
1698 | env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); | |
1699 | } | |
1700 | ||
1701 | CPUMIPSState *cpu_mips_init (void) | |
1702 | { | |
1703 | CPUMIPSState *env; | |
1704 | ||
6af0bf9c FB |
1705 | env = qemu_mallocz(sizeof(CPUMIPSState)); |
1706 | if (!env) | |
1707 | return NULL; | |
173d6cfe | 1708 | cpu_exec_init(env); |
6af0bf9c FB |
1709 | tlb_flush(env, 1); |
1710 | /* Minimal init */ | |
1711 | env->PC = 0xBFC00000; | |
1712 | #if defined (MIPS_USES_R4K_TLB) | |
1713 | env->CP0_random = MIPS_TLB_NB - 1; | |
1714 | #endif | |
1715 | env->CP0_Wired = 0; | |
1716 | env->CP0_Config0 = MIPS_CONFIG0; | |
1717 | #if defined (MIPS_CONFIG1) | |
1718 | env->CP0_Config1 = MIPS_CONFIG1; | |
1719 | #endif | |
1720 | #if defined (MIPS_CONFIG2) | |
1721 | env->CP0_Config2 = MIPS_CONFIG2; | |
1722 | #endif | |
1723 | #if defined (MIPS_CONFIG3) | |
1724 | env->CP0_Config3 = MIPS_CONFIG3; | |
1725 | #endif | |
1726 | env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV); | |
1727 | env->CP0_WatchLo = 0; | |
1728 | env->hflags = MIPS_HFLAG_ERL; | |
1729 | /* Count register increments in debug mode, EJTAG version 1 */ | |
1730 | env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); | |
1731 | env->CP0_PRid = MIPS_CPU; | |
1732 | env->exception_index = EXCP_NONE; | |
eeef26cd FB |
1733 | #if defined(CONFIG_USER_ONLY) |
1734 | env->hflags |= MIPS_HFLAG_UM; | |
1735 | #endif | |
6af0bf9c FB |
1736 | return env; |
1737 | } |