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MIPS target (Jocelyn Mayer)
[qemu.git] / target-mips / translate.c
CommitLineData
6af0bf9c
FB		 1/*
2 * MIPS32 emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <stdarg.h>
22#include <stdlib.h>
23#include <stdio.h>
24#include <string.h>
25#include <inttypes.h>
26
27#include "cpu.h"
28#include "exec-all.h"
29#include "disas.h"
30
31#define MIPS_DEBUG_DISAS
32//#define MIPS_SINGLE_STEP
33
34enum {
35#define DEF(s, n, copy_size) INDEX_op_ ## s,
36#include "opc.h"
37#undef DEF
38 NB_OPS,
39};
40
41static uint16_t *gen_opc_ptr;
42static uint32_t *gen_opparam_ptr;
43
44#include "gen-op.h"
45
46const unsigned char *regnames[] =
47 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
48 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
49 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
50 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
51
52/* Warning: no function for r0 register (hard wired to zero) */
53#define GEN32(func, NAME) \
54static GenOpFunc *NAME ## _table [32] = { \
55NULL, NAME ## 1, NAME ## 2, NAME ## 3, \
56NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
57NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
58NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
59NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
60NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
61NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
62NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
63}; \
64static inline void func(int n) \
65{ \
66 NAME ## _table[n](); \
67}
68
69/* General purpose registers moves */
70GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
71GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
72GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
73
74GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
75GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
76
77typedef struct DisasContext {
78 struct TranslationBlock *tb;
79 target_ulong pc, saved_pc;
80 uint32_t opcode;
81 /* Routine used to access memory */
82 int mem_idx;
83 uint32_t hflags, saved_hflags;
84 uint32_t CP0_Status;
85 int bstate;
86 target_ulong btarget;
87} DisasContext;
88
89enum {
90 BS_NONE = 0, /* We go out of the TB without reaching a branch or an
91 * exception condition
92 */
93 BS_STOP = 1, /* We want to stop translation for any reason */
94 BS_BRANCH = 2, /* We reached a branch condition */
95 BS_EXCP = 3, /* We reached an exception condition */
96};
97
98#if defined MIPS_DEBUG_DISAS
99#define MIPS_DEBUG(fmt, args...) \
100do { \
101 if (loglevel & CPU_LOG_TB_IN_ASM) { \
102 fprintf(logfile, "%08x: %08x " fmt "\n", \
103 ctx->pc, ctx->opcode , ##args); \
104 } \
105} while (0)
106#else
107#define MIPS_DEBUG(fmt, args...) do { } while(0)
108#endif
109
110#define MIPS_INVAL(op) \
111do { \
112 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
113 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
114} while (0)
115
116#define GEN_LOAD_REG_TN(Tn, Rn) \
117do { \
118 if (Rn == 0) { \
119 glue(gen_op_reset_, Tn)(); \
120 } else { \
121 glue(gen_op_load_gpr_, Tn)(Rn); \
122 } \
123} while (0)
124
125#define GEN_LOAD_IMM_TN(Tn, Imm) \
126do { \
127 if (Imm == 0) { \
128 glue(gen_op_reset_, Tn)(); \
129 } else { \
130 glue(gen_op_set_, Tn)(Imm); \
131 } \
132} while (0)
133
134#define GEN_STORE_TN_REG(Rn, Tn) \
135do { \
136 if (Rn != 0) { \
137 glue(glue(gen_op_store_, Tn),_gpr)(Rn); \
138 } \
139} while (0)
140
141static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
142{
143#if defined MIPS_DEBUG_DISAS
144 if (loglevel & CPU_LOG_TB_IN_ASM) {
145 fprintf(logfile, "hflags %08x saved %08x\n",
146 ctx->hflags, ctx->saved_hflags);
147 }
148#endif
149 if (do_save_pc && ctx->pc != ctx->saved_pc) {
150 gen_op_save_pc(ctx->pc);
151 ctx->saved_pc = ctx->pc;
152 }
153 if (ctx->hflags != ctx->saved_hflags) {
154 gen_op_save_state(ctx->hflags);
155 ctx->saved_hflags = ctx->hflags;
156 if (ctx->hflags & MIPS_HFLAG_BR) {
157 gen_op_save_breg_target();
158 } else if (ctx->hflags & MIPS_HFLAG_B) {
159 gen_op_save_btarget(ctx->btarget);
160 } else if (ctx->hflags & MIPS_HFLAG_BMASK) {
161 gen_op_save_bcond();
162 gen_op_save_btarget(ctx->btarget);
163 }
164 }
165}
166
167static inline void generate_exception (DisasContext *ctx, int excp)
168{
169#if defined MIPS_DEBUG_DISAS
170 if (loglevel & CPU_LOG_TB_IN_ASM)
171 fprintf(logfile, "%s: raise exception %d\n", __func__, excp);
172#endif
173 save_cpu_state(ctx, 1);
174 gen_op_raise_exception(excp);
175 ctx->bstate = BS_EXCP;
176}
177
178#if defined(CONFIG_USER_ONLY)
179#define op_ldst(name) gen_op_##name##_raw()
180#define OP_LD_TABLE(width)
181#define OP_ST_TABLE(width)
182#else
183#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
184#define OP_LD_TABLE(width) \
185static GenOpFunc *gen_op_l##width[] = { \
186 &gen_op_l##width##_user, \
187 &gen_op_l##width##_kernel, \
188}
189#define OP_ST_TABLE(width) \
190static GenOpFunc *gen_op_s##width[] = { \
191 &gen_op_s##width##_user, \
192 &gen_op_s##width##_kernel, \
193}
194#endif
195
196#ifdef TARGET_MIPS64
197OP_LD_TABLE(d);
198OP_LD_TABLE(dl);
199OP_LD_TABLE(dr);
200OP_ST_TABLE(d);
201OP_ST_TABLE(dl);
202OP_ST_TABLE(dr);
203#endif
204OP_LD_TABLE(w);
205OP_LD_TABLE(wl);
206OP_LD_TABLE(wr);
207OP_ST_TABLE(w);
208OP_ST_TABLE(wl);
209OP_ST_TABLE(wr);
210OP_LD_TABLE(h);
211OP_LD_TABLE(hu);
212OP_ST_TABLE(h);
213OP_LD_TABLE(b);
214OP_LD_TABLE(bu);
215OP_ST_TABLE(b);
216OP_LD_TABLE(l);
217OP_ST_TABLE(c);
218
219/* Load and store */
220static void gen_ldst (DisasContext *ctx, uint16_t opc, int rt,
221 int base, int16_t offset)
222{
223 const unsigned char *opn = "unk";
224
225 if (base == 0) {
226 GEN_LOAD_IMM_TN(T0, offset);
227 } else if (offset == 0) {
228 gen_op_load_gpr_T0(base);
229 } else {
230 gen_op_load_gpr_T0(base);
231 gen_op_set_T1(offset);
232 gen_op_add();
233 }
234 /* Don't do NOP if destination is zero: we must perform the actual
235 * memory access
236 */
237 switch (opc) {
238#if defined(TARGET_MIPS64)
239 case OPC_LD:
240#if defined (MIPS_HAS_UNALIGNED_LS)
241 case OPC_ULD:
242#endif
243 op_ldst(ld);
244 GEN_STORE_TN_REG(rt, T0);
245 opn = "ld";
246 break;
247 case OPC_SD:
248#if defined (MIPS_HAS_UNALIGNED_LS)
249 case OPC_USD:
250#endif
251 GEN_LOAD_REG_TN(T1, rt);
252 op_ldst(sd);
253 opn = "sd";
254 break;
255 case OPC_LDL:
256 op_ldst(ldl);
257 GEN_STORE_TN_REG(rt, T0);
258 opn = "ldl";
259 break;
260 case OPC_SDL:
261 GEN_LOAD_REG_TN(T1, rt);
262 op_ldst(sdl);
263 opn = "sdl";
264 break;
265 case OPC_LDR:
266 op_ldst(ldr);
267 GEN_STORE_TN_REG(rt, T0);
268 opn = "ldr";
269 break;
270 case OPC_SDR:
271 GEN_LOAD_REG_TN(T1, rt);
272 op_ldst(sdr);
273 opn = "sdr";
274 break;
275#endif
276 case OPC_LW:
277#if defined (MIPS_HAS_UNALIGNED_LS)
278 case OPC_ULW:
279#endif
280 op_ldst(lw);
281 GEN_STORE_TN_REG(rt, T0);
282 opn = "lw";
283 break;
284 case OPC_SW:
285#if defined (MIPS_HAS_UNALIGNED_LS)
286 case OPC_USW:
287#endif
288 GEN_LOAD_REG_TN(T1, rt);
289 op_ldst(sw);
290 opn = "sw";
291 break;
292 case OPC_LH:
293#if defined (MIPS_HAS_UNALIGNED_LS)
294 case OPC_ULH:
295#endif
296 op_ldst(lh);
297 GEN_STORE_TN_REG(rt, T0);
298 opn = "lh";
299 break;
300 case OPC_SH:
301#if defined (MIPS_HAS_UNALIGNED_LS)
302 case OPC_USH:
303#endif
304 GEN_LOAD_REG_TN(T1, rt);
305 op_ldst(sh);
306 opn = "sh";
307 break;
308 case OPC_LHU:
309#if defined (MIPS_HAS_UNALIGNED_LS)
310 case OPC_ULHU:
311#endif
312 op_ldst(lhu);
313 GEN_STORE_TN_REG(rt, T0);
314 opn = "lhu";
315 break;
316 case OPC_LB:
317 op_ldst(lb);
318 GEN_STORE_TN_REG(rt, T0);
319 opn = "lb";
320 break;
321 case OPC_SB:
322 GEN_LOAD_REG_TN(T1, rt);
323 op_ldst(sb);
324 opn = "sb";
325 break;
326 case OPC_LBU:
327 op_ldst(lbu);
328 GEN_STORE_TN_REG(rt, T0);
329 opn = "lbu";
330 break;
331 case OPC_LWL:
332 op_ldst(lwl);
333 GEN_STORE_TN_REG(rt, T0);
334 opn = "lwl";
335 break;
336 case OPC_SWL:
337 GEN_LOAD_REG_TN(T1, rt);
338 op_ldst(swl);
339 opn = "swr";
340 break;
341 case OPC_LWR:
342 op_ldst(lwr);
343 GEN_STORE_TN_REG(rt, T0);
344 opn = "lwr";
345 break;
346 case OPC_SWR:
347 GEN_LOAD_REG_TN(T1, rt);
348 op_ldst(swr);
349 opn = "swr";
350 break;
351 case OPC_LL:
352 op_ldst(ll);
353 GEN_STORE_TN_REG(rt, T0);
354 opn = "ll";
355 break;
356 case OPC_SC:
357 GEN_LOAD_REG_TN(T1, rt);
358 op_ldst(sc);
359 GEN_STORE_TN_REG(rt, T0);
360 opn = "sc";
361 break;
362 default:
363 MIPS_INVAL("load/store");
364 generate_exception(ctx, EXCP_RI);
365 return;
366 }
367 MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
368}
369
370/* Arithmetic with immediate operand */
371static void gen_arith_imm (DisasContext *ctx, uint16_t opc, int rt,
372 int rs, int16_t imm)
373{
374 uint32_t uimm;
375 const unsigned char *opn = "unk";
376
377 if (rt == 0 && opc != OPC_ADDI) {
378 /* if no destination, treat it as a NOP
379 * For addi, we must generate the overflow exception when needed.
380 */
381 MIPS_DEBUG("NOP");
382 return;
383 }
384 if (opc == OPC_ADDI || opc == OPC_ADDIU ||
385 opc == OPC_SLTI || opc == OPC_SLTIU)
386 uimm = (int32_t)imm; /* Sign extent to 32 bits */
387 else
388 uimm = (uint16_t)imm;
389 if (opc != OPC_LUI) {
390 GEN_LOAD_REG_TN(T0, rs);
391 GEN_LOAD_IMM_TN(T1, uimm);
392 } else {
393 uimm = uimm << 16;
394 GEN_LOAD_IMM_TN(T0, uimm);
395 }
396 switch (opc) {
397 case OPC_ADDI:
398 save_cpu_state(ctx, 1);
399 gen_op_addo();
400 opn = "addi";
401 break;
402 case OPC_ADDIU:
403 gen_op_add();
404 opn = "addiu";
405 break;
406 case OPC_SLTI:
407 gen_op_lt();
408 opn = "slti";
409 break;
410 case OPC_SLTIU:
411 gen_op_ltu();
412 opn = "sltiu";
413 break;
414 case OPC_ANDI:
415 gen_op_and();
416 opn = "andi";
417 break;
418 case OPC_ORI:
419 gen_op_or();
420 opn = "ori";
421 break;
422 case OPC_XORI:
423 gen_op_xor();
424 opn = "xori";
425 break;
426 case OPC_LUI:
427 opn = "lui";
428 break;
429 case OPC_SLL:
430 gen_op_sll();
431 opn = "sll";
432 break;
433 case OPC_SRA:
434 gen_op_sra();
435 opn = "sra";
436 break;
437 case OPC_SRL:
438 gen_op_srl();
439 opn = "srl";
440 break;
441 default:
442 MIPS_INVAL("imm arith");
443 generate_exception(ctx, EXCP_RI);
444 return;
445 }
446 GEN_STORE_TN_REG(rt, T0);
447 MIPS_DEBUG("%s %s, %s, %x", opn, regnames[rt], regnames[rs], uimm);
448}
449
450/* Arithmetic */
451static void gen_arith (DisasContext *ctx, uint16_t opc,
452 int rd, int rs, int rt)
453{
454 const unsigned char *opn = "unk";
455
456 if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB) {
457 /* if no destination, treat it as a NOP
458 * For add & sub, we must generate the overflow exception when needed.
459 */
460 MIPS_DEBUG("NOP");
461 return;
462 }
463 GEN_LOAD_REG_TN(T0, rs);
464 GEN_LOAD_REG_TN(T1, rt);
465 switch (opc) {
466 case OPC_ADD:
467 save_cpu_state(ctx, 1);
468 gen_op_addo();
469 opn = "add";
470 break;
471 case OPC_ADDU:
472 gen_op_add();
473 opn = "addu";
474 break;
475 case OPC_SUB:
476 save_cpu_state(ctx, 1);
477 gen_op_subo();
478 opn = "sub";
479 break;
480 case OPC_SUBU:
481 gen_op_sub();
482 opn = "subu";
483 break;
484 case OPC_SLT:
485 gen_op_lt();
486 opn = "slt";
487 break;
488 case OPC_SLTU:
489 gen_op_ltu();
490 opn = "sltu";
491 break;
492 case OPC_AND:
493 gen_op_and();
494 opn = "and";
495 break;
496 case OPC_NOR:
497 gen_op_nor();
498 opn = "nor";
499 break;
500 case OPC_OR:
501 gen_op_or();
502 opn = "or";
503 break;
504 case OPC_XOR:
505 gen_op_xor();
506 opn = "xor";
507 break;
508 case OPC_MUL:
509 gen_op_mul();
510 opn = "mul";
511 break;
512 case OPC_MOVN:
513 gen_op_movn(rd);
514 opn = "movn";
515 goto print;
516 case OPC_MOVZ:
517 gen_op_movz(rd);
518 opn = "movz";
519 goto print;
520 case OPC_SLLV:
521 gen_op_sllv();
522 opn = "sllv";
523 break;
524 case OPC_SRAV:
525 gen_op_srav();
526 opn = "srav";
527 break;
528 case OPC_SRLV:
529 gen_op_srlv();
530 opn = "srlv";
531 break;
532 default:
533 MIPS_INVAL("arith");
534 generate_exception(ctx, EXCP_RI);
535 return;
536 }
537 GEN_STORE_TN_REG(rd, T0);
538 print:
539 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
540}
541
542/* Arithmetic on HI/LO registers */
543static void gen_HILO (DisasContext *ctx, uint16_t opc, int reg)
544{
545 const unsigned char *opn = "unk";
546
547 if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
548 /* Treat as a NOP */
549 MIPS_DEBUG("NOP");
550 return;
551 }
552 switch (opc) {
553 case OPC_MFHI:
554 gen_op_load_HI();
555 GEN_STORE_TN_REG(reg, T0);
556 opn = "mfhi";
557 break;
558 case OPC_MFLO:
559 gen_op_load_LO();
560 GEN_STORE_TN_REG(reg, T0);
561 opn = "mflo";
562 break;
563 case OPC_MTHI:
564 GEN_LOAD_REG_TN(T0, reg);
565 gen_op_store_HI();
566 opn = "mthi";
567 break;
568 case OPC_MTLO:
569 GEN_LOAD_REG_TN(T0, reg);
570 gen_op_store_LO();
571 opn = "mtlo";
572 break;
573 default:
574 MIPS_INVAL("HILO");
575 generate_exception(ctx, EXCP_RI);
576 return;
577 }
578 MIPS_DEBUG("%s %s", opn, regnames[reg]);
579}
580
581static void gen_muldiv (DisasContext *ctx, uint16_t opc,
582 int rs, int rt)
583{
584 const unsigned char *opn = "unk";
585
586 GEN_LOAD_REG_TN(T0, rs);
587 GEN_LOAD_REG_TN(T1, rt);
588 switch (opc) {
589 case OPC_DIV:
590 gen_op_div();
591 opn = "div";
592 break;
593 case OPC_DIVU:
594 gen_op_divu();
595 opn = "divu";
596 break;
597 case OPC_MULT:
598 gen_op_mult();
599 opn = "mult";
600 break;
601 case OPC_MULTU:
602 gen_op_multu();
603 opn = "multu";
604 break;
605 case OPC_MADD:
606 gen_op_madd();
607 opn = "madd";
608 break;
609 case OPC_MADDU:
610 gen_op_maddu();
611 opn = "maddu";
612 break;
613 case OPC_MSUB:
614 gen_op_msub();
615 opn = "msub";
616 break;
617 case OPC_MSUBU:
618 gen_op_msubu();
619 opn = "msubu";
620 break;
621 default:
622 MIPS_INVAL("mul/div");
623 generate_exception(ctx, EXCP_RI);
624 return;
625 }
626 MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]);
627}
628
629static void gen_cl (DisasContext *ctx, uint16_t opc,
630 int rd, int rs)
631{
632 const unsigned char *opn = "unk";
633 if (rd == 0) {
634 /* Treat as a NOP */
635 MIPS_DEBUG("NOP");
636 return;
637 }
638 GEN_LOAD_REG_TN(T0, rs);
639 switch (opc) {
640 case OPC_CLO:
641 /* CLO */
642 gen_op_clo();
643 opn = "clo";
644 break;
645 case OPC_CLZ:
646 /* CLZ */
647 gen_op_clz();
648 opn = "clz";
649 break;
650 default:
651 MIPS_INVAL("CLx");
652 generate_exception(ctx, EXCP_RI);
653 return;
654 }
655 gen_op_store_T0_gpr(rd);
656 MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]);
657}
658
659/* Traps */
660static void gen_trap (DisasContext *ctx, uint16_t opc,
661 int rs, int rt, int16_t imm)
662{
663 int cond;
664
665 cond = 0;
666 /* Load needed operands */
667 switch (opc) {
668 case OPC_TEQ:
669 case OPC_TGE:
670 case OPC_TGEU:
671 case OPC_TLT:
672 case OPC_TLTU:
673 case OPC_TNE:
674 /* Compare two registers */
675 if (rs != rt) {
676 GEN_LOAD_REG_TN(T0, rs);
677 GEN_LOAD_REG_TN(T1, rt);
678 cond = 1;
679 }
680 case OPC_TEQI:
681 case OPC_TGEI:
682 case OPC_TGEIU:
683 case OPC_TLTI:
684 case OPC_TLTIU:
685 case OPC_TNEI:
686 /* Compare register to immediate */
687 if (rs != 0 || imm != 0) {
688 GEN_LOAD_REG_TN(T0, rs);
689 GEN_LOAD_IMM_TN(T1, (int32_t)imm);
690 cond = 1;
691 }
692 break;
693 }
694 if (cond == 0) {
695 switch (opc) {
696 case OPC_TEQ: /* rs == rs */
697 case OPC_TEQI: /* r0 == 0 */
698 case OPC_TGE: /* rs >= rs */
699 case OPC_TGEI: /* r0 >= 0 */
700 case OPC_TGEU: /* rs >= rs unsigned */
701 case OPC_TGEIU: /* r0 >= 0 unsigned */
702 /* Always trap */
703 gen_op_set_T0(1);
704 break;
705 case OPC_TLT: /* rs < rs */
706 case OPC_TLTI: /* r0 < 0 */
707 case OPC_TLTU: /* rs < rs unsigned */
708 case OPC_TLTIU: /* r0 < 0 unsigned */
709 case OPC_TNE: /* rs != rs */
710 case OPC_TNEI: /* r0 != 0 */
711 /* Never trap: treat as NOP */
712 return;
713 default:
714 MIPS_INVAL("TRAP");
715 generate_exception(ctx, EXCP_RI);
716 return;
717 }
718 } else {
719 switch (opc) {
720 case OPC_TEQ:
721 case OPC_TEQI:
722 gen_op_eq();
723 break;
724 case OPC_TGE:
725 case OPC_TGEI:
726 gen_op_ge();
727 break;
728 case OPC_TGEU:
729 case OPC_TGEIU:
730 gen_op_geu();
731 break;
732 case OPC_TLT:
733 case OPC_TLTI:
734 gen_op_lt();
735 break;
736 case OPC_TLTU:
737 case OPC_TLTIU:
738 gen_op_ltu();
739 break;
740 case OPC_TNE:
741 case OPC_TNEI:
742 gen_op_ne();
743 break;
744 default:
745 MIPS_INVAL("TRAP");
746 generate_exception(ctx, EXCP_RI);
747 return;
748 }
749 }
750 save_cpu_state(ctx, 1);
751 gen_op_trap();
752 ctx->bstate = BS_STOP;
753}
754
755/* Branches (before delay slot) */
756static void gen_compute_branch (DisasContext *ctx, uint16_t opc,
757 int rs, int rt, int32_t offset)
758{
759 target_ulong btarget;
760 int blink, bcond;
761
762 btarget = -1;
763 blink = 0;
764 bcond = 0;
765 /* Load needed operands */
766 switch (opc) {
767 case OPC_BEQ:
768 case OPC_BEQL:
769 case OPC_BNE:
770 case OPC_BNEL:
771 /* Compare two registers */
772 if (rs != rt) {
773 GEN_LOAD_REG_TN(T0, rs);
774 GEN_LOAD_REG_TN(T1, rt);
775 bcond = 1;
776 }
777 btarget = ctx->pc + 4 + offset;
778 break;
779 case OPC_BGEZ:
780 case OPC_BGEZAL:
781 case OPC_BGEZALL:
782 case OPC_BGEZL:
783 case OPC_BGTZ:
784 case OPC_BGTZL:
785 case OPC_BLEZ:
786 case OPC_BLEZL:
787 case OPC_BLTZ:
788 case OPC_BLTZAL:
789 case OPC_BLTZALL:
790 case OPC_BLTZL:
791 /* Compare to zero */
792 if (rs != 0) {
793 gen_op_load_gpr_T0(rs);
794 bcond = 1;
795 }
796 btarget = ctx->pc + 4 + offset;
797 break;
798 case OPC_J:
799 case OPC_JAL:
800 /* Jump to immediate */
801 btarget = ((ctx->pc + 4) & 0xFF000000) | offset;
802 break;
803 case OPC_JR:
804 case OPC_JALR:
805 /* Jump to register */
806 if (offset != 0) {
807 /* Only hint = 0 is valid */
808 generate_exception(ctx, EXCP_RI);
809 return;
810 }
811 GEN_LOAD_REG_TN(T2, rs);
812 break;
813 default:
814 MIPS_INVAL("branch/jump");
815 generate_exception(ctx, EXCP_RI);
816 return;
817 }
818 if (bcond == 0) {
819 /* No condition to be computed */
820 switch (opc) {
821 case OPC_BEQ: /* rx == rx */
822 case OPC_BEQL: /* rx == rx likely */
823 case OPC_BGEZ: /* 0 >= 0 */
824 case OPC_BGEZL: /* 0 >= 0 likely */
825 case OPC_BLEZ: /* 0 <= 0 */
826 case OPC_BLEZL: /* 0 <= 0 likely */
827 /* Always take */
828 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
829 MIPS_DEBUG("balways");
830 break;
831 case OPC_BGEZAL: /* 0 >= 0 */
832 case OPC_BGEZALL: /* 0 >= 0 likely */
833 /* Always take and link */
834 blink = 31;
835 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
836 MIPS_DEBUG("balways and link");
837 break;
838 case OPC_BNE: /* rx != rx */
839 case OPC_BGTZ: /* 0 > 0 */
840 case OPC_BLTZ: /* 0 < 0 */
841 case OPC_BLTZAL: /* 0 < 0 */
842 /* Treated as NOP */
843 MIPS_DEBUG("bnever (NOP)");
844 return;
845 case OPC_BNEL: /* rx != rx likely */
846 case OPC_BGTZL: /* 0 > 0 likely */
847 case OPC_BLTZALL: /* 0 < 0 likely */
848 case OPC_BLTZL: /* 0 < 0 likely */
849 /* Skip the instruction in the delay slot */
850 MIPS_DEBUG("bnever and skip");
851 gen_op_branch((long)ctx->tb, ctx->pc + 4);
852 return;
853 case OPC_J:
854 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
855 MIPS_DEBUG("j %08x", btarget);
856 break;
857 case OPC_JAL:
858 blink = 31;
859 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
860 MIPS_DEBUG("jal %08x", btarget);
861 break;
862 case OPC_JR:
863 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BR;
864 MIPS_DEBUG("jr %s", regnames[rs]);
865 break;
866 case OPC_JALR:
867 blink = rt;
868 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BR;
869 MIPS_DEBUG("jalr %s, %s", regnames[rt], regnames[rs]);
870 break;
871 default:
872 MIPS_INVAL("branch/jump");
873 generate_exception(ctx, EXCP_RI);
874 return;
875 }
876 } else {
877 switch (opc) {
878 case OPC_BEQ:
879 gen_op_eq();
880 MIPS_DEBUG("beq %s, %s, %08x",
881 regnames[rs], regnames[rt], btarget);
882 goto not_likely;
883 case OPC_BEQL:
884 gen_op_eq();
885 MIPS_DEBUG("beql %s, %s, %08x",
886 regnames[rs], regnames[rt], btarget);
887 goto likely;
888 case OPC_BNE:
889 gen_op_ne();
890 MIPS_DEBUG("bne %s, %s, %08x",
891 regnames[rs], regnames[rt], btarget);
892 goto not_likely;
893 case OPC_BNEL:
894 gen_op_ne();
895 MIPS_DEBUG("bnel %s, %s, %08x",
896 regnames[rs], regnames[rt], btarget);
897 goto likely;
898 case OPC_BGEZ:
899 gen_op_gez();
900 MIPS_DEBUG("bgez %s, %08x", regnames[rs], btarget);
901 goto not_likely;
902 case OPC_BGEZL:
903 gen_op_gez();
904 MIPS_DEBUG("bgezl %s, %08x", regnames[rs], btarget);
905 goto likely;
906 case OPC_BGEZAL:
907 gen_op_gez();
908 MIPS_DEBUG("bgezal %s, %08x", regnames[rs], btarget);
909 blink = 31;
910 goto not_likely;
911 case OPC_BGEZALL:
912 gen_op_gez();
913 blink = 31;
914 MIPS_DEBUG("bgezall %s, %08x", regnames[rs], btarget);
915 goto likely;
916 case OPC_BGTZ:
917 gen_op_gtz();
918 MIPS_DEBUG("bgtz %s, %08x", regnames[rs], btarget);
919 goto not_likely;
920 case OPC_BGTZL:
921 gen_op_gtz();
922 MIPS_DEBUG("bgtzl %s, %08x", regnames[rs], btarget);
923 goto likely;
924 case OPC_BLEZ:
925 gen_op_lez();
926 MIPS_DEBUG("blez %s, %08x", regnames[rs], btarget);
927 goto not_likely;
928 case OPC_BLEZL:
929 gen_op_lez();
930 MIPS_DEBUG("blezl %s, %08x", regnames[rs], btarget);
931 goto likely;
932 case OPC_BLTZ:
933 gen_op_ltz();
934 MIPS_DEBUG("bltz %s, %08x", regnames[rs], btarget);
935 goto not_likely;
936 case OPC_BLTZL:
937 gen_op_ltz();
938 MIPS_DEBUG("bltzl %s, %08x", regnames[rs], btarget);
939 goto likely;
940 case OPC_BLTZAL:
941 gen_op_ltz();
942 blink = 31;
943 MIPS_DEBUG("bltzal %s, %08x", regnames[rs], btarget);
944 not_likely:
945 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BC;
946 break;
947 case OPC_BLTZALL:
948 gen_op_ltz();
949 blink = 31;
950 MIPS_DEBUG("bltzall %s, %08x", regnames[rs], btarget);
951 likely:
952 ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BL;
953 break;
954 }
955 gen_op_set_bcond();
956 }
957 MIPS_DEBUG("enter ds: link %d cond %02x target %08x",
958 blink, ctx->hflags, btarget);
959 ctx->btarget = btarget;
960 if (blink > 0) {
961 gen_op_set_T0(ctx->pc + 8);
962 gen_op_store_T0_gpr(blink);
963 }
964 return;
965}
966
967/* CP0 (MMU and control) */
968static void gen_cp0 (DisasContext *ctx, uint16_t opc, int rt, int rd)
969{
970 const unsigned char *opn = "unk";
971
972 if (!(ctx->CP0_Status & (1 << CP0St_CU0))) {
973 if (loglevel & CPU_LOG_TB_IN_ASM) {
974 fprintf(logfile, "CP0 is not usable\n");
975 }
976 gen_op_raise_exception_err(EXCP_CpU, 0);
977 return;
978 }
979 switch (opc) {
980 case OPC_MFC0:
981 if (rt == 0) {
982 /* Treat as NOP */
983 return;
984 }
985 gen_op_mfc0(rd, ctx->opcode & 0x7);
986 gen_op_store_T0_gpr(rt);
987 opn = "mfc0";
988 break;
989 case OPC_MTC0:
990 /* If we get an exception, we want to restart at next instruction */
991 ctx->pc += 4;
992 save_cpu_state(ctx, 1);
993 ctx->pc -= 4;
994 GEN_LOAD_REG_TN(T0, rt);
995 gen_op_mtc0(rd, ctx->opcode & 0x7);
996 /* Stop translation as we may have switched the execution mode */
997 ctx->bstate = BS_STOP;
998 opn = "mtc0";
999 break;
1000#if defined(MIPS_USES_R4K_TLB)
1001 case OPC_TLBWI:
1002 gen_op_tlbwi();
1003 opn = "tlbwi";
1004 break;
1005 case OPC_TLBWR:
1006 gen_op_tlbwr();
1007 opn = "tlbwr";
1008 break;
1009 case OPC_TLBP:
1010 gen_op_tlbp();
1011 opn = "tlbp";
1012 break;
1013 case OPC_TLBR:
1014 gen_op_tlbr();
1015 opn = "tlbr";
1016 break;
1017#endif
1018 case OPC_ERET:
1019 opn = "eret";
1020 save_cpu_state(ctx, 0);
1021 gen_op_eret();
1022 ctx->bstate = BS_EXCP;
1023 break;
1024 case OPC_DERET:
1025 opn = "deret";
1026 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
1027 generate_exception(ctx, EXCP_RI);
1028 } else {
1029 save_cpu_state(ctx, 0);
1030 gen_op_deret();
1031 ctx->bstate = BS_EXCP;
1032 }
1033 break;
1034 /* XXX: TODO: WAIT */
1035 default:
1036 if (loglevel & CPU_LOG_TB_IN_ASM) {
1037 fprintf(logfile, "Invalid CP0 opcode: %08x %03x %03x %03x\n",
1038 ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
1039 ((ctx->opcode >> 16) & 0x1F));
1040 }
1041 generate_exception(ctx, EXCP_RI);
1042 return;
1043 }
1044 MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd);
1045}
1046
1047/* Coprocessor 1 (FPU) */
1048
1049/* ISA extensions */
1050/* MIPS16 extension to MIPS32 */
1051/* SmartMIPS extension to MIPS32 */
1052
1053#ifdef TARGET_MIPS64
1054static void gen_arith64 (DisasContext *ctx, uint16_t opc)
1055{
1056 if (func == 0x02 && rd == 0) {
1057 /* NOP */
1058 return;
1059 }
1060 if (rs == 0 || rt == 0) {
1061 gen_op_reset_T0();
1062 gen_op_save64();
1063 } else {
1064 gen_op_load_gpr_T0(rs);
1065 gen_op_load_gpr_T1(rt);
1066 gen_op_save64();
1067 if (func & 0x01)
1068 gen_op_mul64u();
1069 else
1070 gen_op_mul64s();
1071 }
1072 if (func & 0x02)
1073 gen_op_add64();
1074 else
1075 gen_op_sub64();
1076}
1077
1078/* Coprocessor 3 (FPU) */
1079
1080/* MDMX extension to MIPS64 */
1081/* MIPS-3D extension to MIPS64 */
1082
1083#endif
1084
1085static void decode_opc (DisasContext *ctx)
1086{
1087 int32_t offset;
1088 int rs, rt, rd, sa;
1089 uint16_t op, op1;
1090 int16_t imm;
1091
1092 if ((ctx->hflags & MIPS_HFLAG_DS) &&
1093 (ctx->hflags & MIPS_HFLAG_BL)) {
1094 /* Handle blikely not taken case */
1095 MIPS_DEBUG("blikely condition (%08x)", ctx->pc + 4);
1096 gen_op_blikely((long)ctx->tb, ctx->pc + 4,
1097 ctx->hflags & ~(MIPS_HFLAG_BMASK | MIPS_HFLAG_DS));
1098 }
1099 op = ctx->opcode >> 26;
1100 rs = ((ctx->opcode >> 21) & 0x1F);
1101 rt = ((ctx->opcode >> 16) & 0x1F);
1102 rd = ((ctx->opcode >> 11) & 0x1F);
1103 sa = ((ctx->opcode >> 6) & 0x1F);
1104 imm = (int16_t)ctx->opcode;
1105 switch (op) {
1106 case 0x00: /* Special opcode */
1107 op1 = ctx->opcode & 0x3F;
1108 switch (op1) {
1109 case 0x00: /* Arithmetic with immediate */
1110 case 0x02 ... 0x03:
1111 gen_arith_imm(ctx, op1 | EXT_SPECIAL, rd, rt, sa);
1112 break;
1113 case 0x04: /* Arithmetic */
1114 case 0x06 ... 0x07:
1115 case 0x0A ... 0x0B:
1116 case 0x20 ... 0x27:
1117 case 0x2A ... 0x2B:
1118 gen_arith(ctx, op1 | EXT_SPECIAL, rd, rs, rt);
1119 break;
1120 case 0x18 ... 0x1B: /* MULT / DIV */
1121 gen_muldiv(ctx, op1 | EXT_SPECIAL, rs, rt);
1122 break;
1123 case 0x08 ... 0x09: /* Jumps */
1124 gen_compute_branch(ctx, op1 | EXT_SPECIAL, rs, rd, sa);
1125 return;
1126 case 0x30 ... 0x34: /* Traps */
1127 case 0x36:
1128 gen_trap(ctx, op1 | EXT_SPECIAL, rs, rt, -1);
1129 break;
1130 case 0x10: /* Move from HI/LO */
1131 case 0x12:
1132 gen_HILO(ctx, op1 | EXT_SPECIAL, rd);
1133 break;
1134 case 0x11:
1135 case 0x13: /* Move to HI/LO */
1136 gen_HILO(ctx, op1 | EXT_SPECIAL, rs);
1137 break;
1138 case 0x0C: /* SYSCALL */
1139 generate_exception(ctx, EXCP_SYSCALL);
1140 break;
1141 case 0x0D: /* BREAK */
1142 generate_exception(ctx, EXCP_BREAK);
1143 break;
1144 case 0x0F: /* SYNC */
1145 /* Treat as a noop */
1146 break;
1147 case 0x05: /* Pmon entry point */
1148 gen_op_pmon((ctx->opcode >> 6) & 0x1F);
1149 break;
1150#if defined (MIPS_HAS_MOVCI)
1151 case 0x01: /* MOVCI */
1152#endif
1153#if defined (TARGET_MIPS64)
1154 case 0x14: /* MIPS64 specific opcodes */
1155 case 0x16:
1156 case 0x17:
1157 case 0x1C ... 0x1F:
1158 case 0x2C ... 0x2F:
1159 case 0x37:
1160 case 0x39 ... 0x3B:
1161 case 0x3E ... 0x3F:
1162#endif
1163 default: /* Invalid */
1164 MIPS_INVAL("special");
1165 generate_exception(ctx, EXCP_RI);
1166 break;
1167 }
1168 break;
1169 case 0x1C: /* Special2 opcode */
1170 op1 = ctx->opcode & 0x3F;
1171 switch (op1) {
1172#if defined (MIPS_USES_R4K_EXT)
1173 /* Those instructions are not part of MIPS32 core */
1174 case 0x00 ... 0x01: /* Multiply and add/sub */
1175 case 0x04 ... 0x05:
1176 gen_muldiv(ctx, op1 | EXT_SPECIAL2, rs, rt);
1177 break;
1178 case 0x02: /* MUL */
1179 gen_arith(ctx, op1 | EXT_SPECIAL2, rd, rs, rt);
1180 break;
1181 case 0x20 ... 0x21: /* CLO / CLZ */
1182 gen_cl(ctx, op1 | EXT_SPECIAL2, rd, rs);
1183 break;
1184#endif
1185 case 0x3F: /* SDBBP */
1186 /* XXX: not clear which exception should be raised
1187 * when in debug mode...
1188 */
1189 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
1190 generate_exception(ctx, EXCP_DBp);
1191 } else {
1192 generate_exception(ctx, EXCP_DBp);
1193 }
1194 /* Treat as a noop */
1195 break;
1196 default: /* Invalid */
1197 MIPS_INVAL("special2");
1198 generate_exception(ctx, EXCP_RI);
1199 break;
1200 }
1201 break;
1202 case 0x01: /* B REGIMM opcode */
1203 op1 = ((ctx->opcode >> 16) & 0x1F);
1204 switch (op1) {
1205 case 0x00 ... 0x03: /* REGIMM branches */
1206 case 0x10 ... 0x13:
1207 gen_compute_branch(ctx, op1 | EXT_REGIMM, rs, -1, imm << 2);
1208 return;
1209 case 0x08 ... 0x0C: /* Traps */
1210 case 0x0E:
1211 gen_trap(ctx, op1 | EXT_REGIMM, rs, -1, imm);
1212 break;
1213 default: /* Invalid */
1214 MIPS_INVAL("REGIMM");
1215 generate_exception(ctx, EXCP_RI);
1216 break;
1217 }
1218 break;
1219 case 0x10: /* CP0 opcode */
1220 op1 = ((ctx->opcode >> 21) & 0x1F);
1221 switch (op1) {
1222 case 0x00:
1223 case 0x04:
1224 gen_cp0(ctx, op1 | EXT_CP0, rt, rd);
1225 break;
1226 default:
1227 gen_cp0(ctx, (ctx->opcode & 0x1F) | EXT_CP0, rt, rd);
1228 break;
1229 }
1230 break;
1231 case 0x08 ... 0x0F: /* Arithmetic with immediate opcode */
1232 gen_arith_imm(ctx, op, rt, rs, imm);
1233 break;
1234 case 0x02 ... 0x03: /* Jump */
1235 offset = (int32_t)(ctx->opcode & 0x03FFFFFF) << 2;
1236 gen_compute_branch(ctx, op, rs, rt, offset);
1237 return;
1238 case 0x04 ... 0x07: /* Branch */
1239 case 0x14 ... 0x17:
1240 gen_compute_branch(ctx, op, rs, rt, imm << 2);
1241 return;
1242 case 0x20 ... 0x26: /* Load and stores */
1243 case 0x28 ... 0x2E:
1244 case 0x30:
1245 case 0x38:
1246 gen_ldst(ctx, op, rt, rs, imm);
1247 break;
1248 case 0x2F: /* Cache operation */
1249 /* Treat as a noop */
1250 break;
1251 case 0x33: /* Prefetch */
1252 /* Treat as a noop */
1253 break;
1254 case 0x3F: /* HACK */
1255 break;
1256#if defined(MIPS_USES_FPU)
1257 case 0x31 ... 0x32: /* Floating point load/store */
1258 case 0x35 ... 0x36:
1259 case 0x3A ... 0x3B:
1260 case 0x3D ... 0x3E:
1261 /* Not implemented */
1262 /* XXX: not correct */
1263#endif
1264 case 0x11: /* CP1 opcode */
1265 /* Not implemented */
1266 /* XXX: not correct */
1267 case 0x12: /* CP2 opcode */
1268 /* Not implemented */
1269 /* XXX: not correct */
1270 case 0x13: /* CP3 opcode */
1271 /* Not implemented */
1272 /* XXX: not correct */
1273#if defined (TARGET_MIPS64)
1274 case 0x18 ... 0x1B:
1275 case 0x27:
1276 case 0x34:
1277 case 0x37:
1278 /* MIPS64 opcodes */
1279#endif
1280#if defined (MIPS_HAS_JALX)
1281 case 0x1D:
1282 /* JALX: not implemented */
1283#endif
1284 case 0x1E:
1285 /* ASE specific */
1286#if defined (MIPS_HAS_LSC)
1287 case 0x31: /* LWC1 */
1288 case 0x32: /* LWC2 */
1289 case 0x35: /* SDC1 */
1290 case 0x36: /* SDC2 */
1291#endif
1292 default: /* Invalid */
1293 MIPS_INVAL("");
1294 generate_exception(ctx, EXCP_RI);
1295 break;
1296 }
1297 if (ctx->hflags & MIPS_HFLAG_DS) {
1298 int hflags = ctx->hflags;
1299 /* Branches completion */
1300 ctx->hflags &= ~(MIPS_HFLAG_BMASK | MIPS_HFLAG_DS);
1301 ctx->bstate = BS_BRANCH;
1302 save_cpu_state(ctx, 0);
1303 switch (hflags & MIPS_HFLAG_BMASK) {
1304 case MIPS_HFLAG_B:
1305 /* unconditional branch */
1306 MIPS_DEBUG("unconditional branch");
1307 gen_op_branch((long)ctx->tb, ctx->btarget);
1308 break;
1309 case MIPS_HFLAG_BL:
1310 /* blikely taken case */
1311 MIPS_DEBUG("blikely branch taken");
1312 gen_op_branch((long)ctx->tb, ctx->btarget);
1313 break;
1314 case MIPS_HFLAG_BC:
1315 /* Conditional branch */
1316 MIPS_DEBUG("conditional branch");
1317 gen_op_bcond((long)ctx->tb, ctx->btarget, ctx->pc + 4);
1318 break;
1319 case MIPS_HFLAG_BR:
1320 /* unconditional branch to register */
1321 MIPS_DEBUG("branch to register");
1322 gen_op_breg();
1323 break;
1324 default:
1325 MIPS_DEBUG("unknown branch");
1326 break;
1327 }
1328 }
1329}
1330
1331int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
1332 int search_pc)
1333{
1334 DisasContext ctx, *ctxp = &ctx;
1335 target_ulong pc_start;
1336 uint16_t *gen_opc_end;
1337 int j, lj = -1;
1338
1339 pc_start = tb->pc;
1340 gen_opc_ptr = gen_opc_buf;
1341 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1342 gen_opparam_ptr = gen_opparam_buf;
1343 ctx.pc = pc_start;
1344 ctx.tb = tb;
1345 ctx.bstate = BS_NONE;
1346 /* Restore delay slot state */
1347 ctx.hflags = env->hflags;
1348 ctx.saved_hflags = ctx.hflags;
1349 if (ctx.hflags & MIPS_HFLAG_BR) {
1350 gen_op_restore_breg_target();
1351 } else if (ctx.hflags & MIPS_HFLAG_B) {
1352 ctx.btarget = env->btarget;
1353 } else if (ctx.hflags & MIPS_HFLAG_BMASK) {
1354 /* If we are in the delay slot of a conditional branch,
1355 * restore the branch condition from env->bcond to T2
1356 */
1357 ctx.btarget = env->btarget;
1358 gen_op_restore_bcond();
1359 }
1360#if defined(CONFIG_USER_ONLY)
1361 ctx.mem_idx = 0;
1362#else
1363 ctx.mem_idx = (ctx.hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM ? 0 : 1;
1364#endif
1365 ctx.CP0_Status = env->CP0_Status;
1366#ifdef DEBUG_DISAS
1367 if (loglevel & CPU_LOG_TB_CPU) {
1368 fprintf(logfile, "------------------------------------------------\n");
1369 cpu_dump_state(env, logfile, fprintf, 0);
1370 }
1371#endif
1372#if defined MIPS_DEBUG_DISAS
1373 if (loglevel & CPU_LOG_TB_IN_ASM)
1374 fprintf(logfile, "\ntb %p super %d cond %04x %04x\n",
1375 tb, ctx.mem_idx, ctx.hflags, env->hflags);
1376#endif
1377 while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
1378 if (search_pc) {
1379 j = gen_opc_ptr - gen_opc_buf;
1380 save_cpu_state(ctxp, 1);
1381 if (lj < j) {
1382 lj++;
1383 while (lj < j)
1384 gen_opc_instr_start[lj++] = 0;
1385 gen_opc_pc[lj] = ctx.pc;
1386 gen_opc_instr_start[lj] = 1;
1387 }
1388 }
1389 ctx.opcode = ldl_code(ctx.pc);
1390 decode_opc(&ctx);
1391 ctx.pc += 4;
1392 if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
1393 break;
1394#if defined (MIPS_SINGLE_STEP)
1395 break;
1396#endif
1397 }
1398 if (ctx.bstate != BS_BRANCH && ctx.bstate != BS_EXCP) {
1399 save_cpu_state(ctxp, 0);
1400 gen_op_branch((long)ctx.tb, ctx.pc);
1401 }
1402 gen_op_reset_T0();
1403 /* Generate the return instruction */
1404 gen_op_exit_tb();
1405 *gen_opc_ptr = INDEX_op_end;
1406 if (search_pc) {
1407 j = gen_opc_ptr - gen_opc_buf;
1408 lj++;
1409 while (lj <= j)
1410 gen_opc_instr_start[lj++] = 0;
1411 tb->size = 0;
1412 } else {
1413 tb->size = ctx.pc - pc_start;
1414 }
1415#ifdef DEBUG_DISAS
1416#if defined MIPS_DEBUG_DISAS
1417 if (loglevel & CPU_LOG_TB_IN_ASM)
1418 fprintf(logfile, "\n");
1419#endif
1420 if (loglevel & CPU_LOG_TB_IN_ASM) {
1421 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
1422 target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
1423 fprintf(logfile, "\n");
1424 }
1425 if (loglevel & CPU_LOG_TB_OP) {
1426 fprintf(logfile, "OP:\n");
1427 dump_ops(gen_opc_buf, gen_opparam_buf);
1428 fprintf(logfile, "\n");
1429 }
1430 if (loglevel & CPU_LOG_TB_CPU) {
1431 fprintf(logfile, "---------------- %d %08x\n", ctx.bstate, ctx.hflags);
1432 }
1433#endif
1434
1435 return 0;
1436}
1437
1438int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
1439{
1440 return gen_intermediate_code_internal(env, tb, 0);
1441}
1442
1443int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
1444{
1445 return gen_intermediate_code_internal(env, tb, 1);
1446}
1447
1448void cpu_dump_state (CPUState *env, FILE *f,
1449 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1450 int flags)
1451{
1452 int i;
1453
1454 cpu_fprintf(f, "pc=0x%08x HI=0x%08x LO=0x%08x ds %04x %08x %d\n",
1455 env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond);
1456 for (i = 0; i < 32; i++) {
1457 if ((i & 3) == 0)
1458 cpu_fprintf(f, "GPR%02d:", i);
1459 cpu_fprintf(f, " %s %08x", regnames[i], env->gpr[i]);
1460 if ((i & 3) == 3)
1461 cpu_fprintf(f, "\n");
1462 }
1463 cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x%08x\n",
1464 env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
1465 cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%08x\n",
1466 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
1467}
1468
1469CPUMIPSState *cpu_mips_init (void)
1470{
1471 CPUMIPSState *env;
1472
1473 cpu_exec_init();
1474 env = qemu_mallocz(sizeof(CPUMIPSState));
1475 if (!env)
1476 return NULL;
1477 tlb_flush(env, 1);
1478 /* Minimal init */
1479 env->PC = 0xBFC00000;
1480#if defined (MIPS_USES_R4K_TLB)
1481 env->CP0_random = MIPS_TLB_NB - 1;
1482#endif
1483 env->CP0_Wired = 0;
1484 env->CP0_Config0 = MIPS_CONFIG0;
1485#if defined (MIPS_CONFIG1)
1486 env->CP0_Config1 = MIPS_CONFIG1;
1487#endif
1488#if defined (MIPS_CONFIG2)
1489 env->CP0_Config2 = MIPS_CONFIG2;
1490#endif
1491#if defined (MIPS_CONFIG3)
1492 env->CP0_Config3 = MIPS_CONFIG3;
1493#endif
1494 env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV);
1495 env->CP0_WatchLo = 0;
1496 env->hflags = MIPS_HFLAG_ERL;
1497 /* Count register increments in debug mode, EJTAG version 1 */
1498 env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
1499 env->CP0_PRid = MIPS_CPU;
1500 env->exception_index = EXCP_NONE;
1501
1502 cpu_single_env = env;
1503
1504 return env;
1505}
Qemu copy for testing