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e67db06e JL |
1 | /* |
2 | * QEMU OpenRISC CPU | |
3 | * | |
4 | * Copyright (c) 2012 Jia Liu <proljc@gmail.com> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "cpu.h" | |
21 | #include "qemu-common.h" | |
22 | ||
23 | /* CPUClass::reset() */ | |
24 | static void openrisc_cpu_reset(CPUState *s) | |
25 | { | |
26 | OpenRISCCPU *cpu = OPENRISC_CPU(s); | |
27 | OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu); | |
28 | ||
29 | if (qemu_loglevel_mask(CPU_LOG_RESET)) { | |
30 | qemu_log("CPU Reset (CPU %d)\n", cpu->env.cpu_index); | |
31 | log_cpu_state(&cpu->env, 0); | |
32 | } | |
33 | ||
34 | occ->parent_reset(s); | |
35 | ||
36 | memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints)); | |
37 | ||
38 | tlb_flush(&cpu->env, 1); | |
39 | /*tb_flush(&cpu->env); FIXME: Do we need it? */ | |
40 | ||
41 | cpu->env.pc = 0x100; | |
42 | cpu->env.sr = SR_FO | SR_SM; | |
43 | cpu->env.exception_index = -1; | |
44 | ||
45 | cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; | |
46 | cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S; | |
47 | cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2)); | |
48 | cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2)); | |
49 | ||
50 | #ifndef CONFIG_USER_ONLY | |
51 | cpu->env.picmr = 0x00000000; | |
52 | cpu->env.picsr = 0x00000000; | |
53 | ||
54 | cpu->env.ttmr = 0x00000000; | |
55 | cpu->env.ttcr = 0x00000000; | |
56 | #endif | |
57 | } | |
58 | ||
59 | static inline void set_feature(OpenRISCCPU *cpu, int feature) | |
60 | { | |
61 | cpu->feature |= feature; | |
62 | cpu->env.cpucfgr = cpu->feature; | |
63 | } | |
64 | ||
65 | void openrisc_cpu_realize(Object *obj, Error **errp) | |
66 | { | |
67 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); | |
68 | ||
69 | qemu_init_vcpu(&cpu->env); | |
70 | cpu_reset(CPU(cpu)); | |
71 | } | |
72 | ||
73 | static void openrisc_cpu_initfn(Object *obj) | |
74 | { | |
75 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); | |
76 | static int inited; | |
77 | ||
78 | cpu_exec_init(&cpu->env); | |
79 | ||
80 | #ifndef CONFIG_USER_ONLY | |
81 | cpu_openrisc_mmu_init(cpu); | |
82 | #endif | |
83 | ||
84 | if (tcg_enabled() && !inited) { | |
85 | inited = 1; | |
86 | openrisc_translate_init(); | |
87 | } | |
88 | } | |
89 | ||
90 | /* CPU models */ | |
91 | static void or1200_initfn(Object *obj) | |
92 | { | |
93 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); | |
94 | ||
95 | set_feature(cpu, OPENRISC_FEATURE_OB32S); | |
96 | set_feature(cpu, OPENRISC_FEATURE_OF32S); | |
97 | } | |
98 | ||
99 | static void openrisc_any_initfn(Object *obj) | |
100 | { | |
101 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); | |
102 | ||
103 | set_feature(cpu, OPENRISC_FEATURE_OB32S); | |
104 | } | |
105 | ||
106 | typedef struct OpenRISCCPUInfo { | |
107 | const char *name; | |
108 | void (*initfn)(Object *obj); | |
109 | } OpenRISCCPUInfo; | |
110 | ||
111 | static const OpenRISCCPUInfo openrisc_cpus[] = { | |
112 | { .name = "or1200", .initfn = or1200_initfn }, | |
113 | { .name = "any", .initfn = openrisc_any_initfn }, | |
114 | }; | |
115 | ||
116 | static void openrisc_cpu_class_init(ObjectClass *oc, void *data) | |
117 | { | |
118 | OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); | |
119 | CPUClass *cc = CPU_CLASS(occ); | |
120 | ||
121 | occ->parent_reset = cc->reset; | |
122 | cc->reset = openrisc_cpu_reset; | |
123 | } | |
124 | ||
125 | static void cpu_register(const OpenRISCCPUInfo *info) | |
126 | { | |
127 | TypeInfo type_info = { | |
128 | .name = info->name, | |
129 | .parent = TYPE_OPENRISC_CPU, | |
130 | .instance_size = sizeof(OpenRISCCPU), | |
131 | .instance_init = info->initfn, | |
132 | .class_size = sizeof(OpenRISCCPUClass), | |
133 | }; | |
134 | ||
135 | type_register_static(&type_info); | |
136 | } | |
137 | ||
138 | static const TypeInfo openrisc_cpu_type_info = { | |
139 | .name = TYPE_OPENRISC_CPU, | |
140 | .parent = TYPE_CPU, | |
141 | .instance_size = sizeof(OpenRISCCPU), | |
142 | .instance_init = openrisc_cpu_initfn, | |
143 | .abstract = false, | |
144 | .class_size = sizeof(OpenRISCCPUClass), | |
145 | .class_init = openrisc_cpu_class_init, | |
146 | }; | |
147 | ||
148 | static void openrisc_cpu_register_types(void) | |
149 | { | |
150 | int i; | |
151 | ||
152 | type_register_static(&openrisc_cpu_type_info); | |
153 | for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) { | |
154 | cpu_register(&openrisc_cpus[i]); | |
155 | } | |
156 | } | |
157 | ||
158 | OpenRISCCPU *cpu_openrisc_init(const char *cpu_model) | |
159 | { | |
160 | OpenRISCCPU *cpu; | |
161 | ||
162 | if (!object_class_by_name(cpu_model)) { | |
163 | return NULL; | |
164 | } | |
165 | cpu = OPENRISC_CPU(object_new(cpu_model)); | |
166 | cpu->env.cpu_model_str = cpu_model; | |
167 | ||
168 | openrisc_cpu_realize(OBJECT(cpu), NULL); | |
169 | ||
170 | return cpu; | |
171 | } | |
172 | ||
173 | typedef struct OpenRISCCPUList { | |
174 | fprintf_function cpu_fprintf; | |
175 | FILE *file; | |
176 | } OpenRISCCPUList; | |
177 | ||
178 | /* Sort alphabetically by type name, except for "any". */ | |
179 | static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b) | |
180 | { | |
181 | ObjectClass *class_a = (ObjectClass *)a; | |
182 | ObjectClass *class_b = (ObjectClass *)b; | |
183 | const char *name_a, *name_b; | |
184 | ||
185 | name_a = object_class_get_name(class_a); | |
186 | name_b = object_class_get_name(class_b); | |
187 | if (strcmp(name_a, "any") == 0) { | |
188 | return 1; | |
189 | } else if (strcmp(name_b, "any") == 0) { | |
190 | return -1; | |
191 | } else { | |
192 | return strcmp(name_a, name_b); | |
193 | } | |
194 | } | |
195 | ||
196 | static void openrisc_cpu_list_entry(gpointer data, gpointer user_data) | |
197 | { | |
198 | ObjectClass *oc = data; | |
199 | OpenRISCCPUList *s = user_data; | |
200 | ||
201 | (*s->cpu_fprintf)(s->file, " %s\n", | |
202 | object_class_get_name(oc)); | |
203 | } | |
204 | ||
205 | void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf) | |
206 | { | |
207 | OpenRISCCPUList s = { | |
208 | .file = f, | |
209 | .cpu_fprintf = cpu_fprintf, | |
210 | }; | |
211 | GSList *list; | |
212 | ||
213 | list = object_class_get_list(TYPE_OPENRISC_CPU, false); | |
214 | list = g_slist_sort(list, openrisc_cpu_list_compare); | |
215 | (*cpu_fprintf)(f, "Available CPUs:\n"); | |
216 | g_slist_foreach(list, openrisc_cpu_list_entry, &s); | |
217 | g_slist_free(list); | |
218 | } | |
219 | ||
220 | type_init(openrisc_cpu_register_types) |