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target-i386: Update X86CPU to QOM realizefn
[qemu.git] / target-openrisc / cpu.c
CommitLineData
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1/*
2 * QEMU OpenRISC CPU
3 *
4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "cpu.h"
21#include "qemu-common.h"
22
23/* CPUClass::reset() */
24static void openrisc_cpu_reset(CPUState *s)
25{
26 OpenRISCCPU *cpu = OPENRISC_CPU(s);
27 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
28
29 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
55e5c285 30 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
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31 log_cpu_state(&cpu->env, 0);
32 }
33
34 occ->parent_reset(s);
35
36 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints));
37
38 tlb_flush(&cpu->env, 1);
39 /*tb_flush(&cpu->env); FIXME: Do we need it? */
40
41 cpu->env.pc = 0x100;
42 cpu->env.sr = SR_FO | SR_SM;
43 cpu->env.exception_index = -1;
44
45 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
46 cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S;
47 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
48 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
49
50#ifndef CONFIG_USER_ONLY
51 cpu->env.picmr = 0x00000000;
52 cpu->env.picsr = 0x00000000;
53
54 cpu->env.ttmr = 0x00000000;
55 cpu->env.ttcr = 0x00000000;
56#endif
57}
58
59static inline void set_feature(OpenRISCCPU *cpu, int feature)
60{
61 cpu->feature |= feature;
62 cpu->env.cpucfgr = cpu->feature;
63}
64
65void openrisc_cpu_realize(Object *obj, Error **errp)
66{
67 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
68
69 qemu_init_vcpu(&cpu->env);
70 cpu_reset(CPU(cpu));
71}
72
73static void openrisc_cpu_initfn(Object *obj)
74{
75 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
76 static int inited;
77
78 cpu_exec_init(&cpu->env);
79
80#ifndef CONFIG_USER_ONLY
81 cpu_openrisc_mmu_init(cpu);
82#endif
83
84 if (tcg_enabled() && !inited) {
85 inited = 1;
86 openrisc_translate_init();
87 }
88}
89
90/* CPU models */
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91
92static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
93{
94 ObjectClass *oc;
95
96 if (cpu_model == NULL) {
97 return NULL;
98 }
99
100 oc = object_class_by_name(cpu_model);
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101 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
102 object_class_is_abstract(oc))) {
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103 return NULL;
104 }
105 return oc;
106}
107
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108static void or1200_initfn(Object *obj)
109{
110 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
111
112 set_feature(cpu, OPENRISC_FEATURE_OB32S);
113 set_feature(cpu, OPENRISC_FEATURE_OF32S);
114}
115
116static void openrisc_any_initfn(Object *obj)
117{
118 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
119
120 set_feature(cpu, OPENRISC_FEATURE_OB32S);
121}
122
123typedef struct OpenRISCCPUInfo {
124 const char *name;
125 void (*initfn)(Object *obj);
126} OpenRISCCPUInfo;
127
128static const OpenRISCCPUInfo openrisc_cpus[] = {
129 { .name = "or1200", .initfn = or1200_initfn },
130 { .name = "any", .initfn = openrisc_any_initfn },
131};
132
133static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
134{
135 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
136 CPUClass *cc = CPU_CLASS(occ);
137
138 occ->parent_reset = cc->reset;
139 cc->reset = openrisc_cpu_reset;
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140
141 cc->class_by_name = openrisc_cpu_class_by_name;
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142}
143
144static void cpu_register(const OpenRISCCPUInfo *info)
145{
146 TypeInfo type_info = {
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147 .parent = TYPE_OPENRISC_CPU,
148 .instance_size = sizeof(OpenRISCCPU),
149 .instance_init = info->initfn,
150 .class_size = sizeof(OpenRISCCPUClass),
151 };
152
478032a9 153 type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name);
a1ebd6ce 154 type_register(&type_info);
478032a9 155 g_free((void *)type_info.name);
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156}
157
158static const TypeInfo openrisc_cpu_type_info = {
159 .name = TYPE_OPENRISC_CPU,
160 .parent = TYPE_CPU,
161 .instance_size = sizeof(OpenRISCCPU),
162 .instance_init = openrisc_cpu_initfn,
bc755a00 163 .abstract = true,
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164 .class_size = sizeof(OpenRISCCPUClass),
165 .class_init = openrisc_cpu_class_init,
166};
167
168static void openrisc_cpu_register_types(void)
169{
170 int i;
171
172 type_register_static(&openrisc_cpu_type_info);
173 for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) {
174 cpu_register(&openrisc_cpus[i]);
175 }
176}
177
178OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
179{
180 OpenRISCCPU *cpu;
bd039ce0 181 ObjectClass *oc;
e67db06e 182
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183 oc = openrisc_cpu_class_by_name(cpu_model);
184 if (oc == NULL) {
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185 return NULL;
186 }
bd039ce0 187 cpu = OPENRISC_CPU(object_new(object_class_get_name(oc)));
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188 cpu->env.cpu_model_str = cpu_model;
189
190 openrisc_cpu_realize(OBJECT(cpu), NULL);
191
192 return cpu;
193}
194
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195/* Sort alphabetically by type name, except for "any". */
196static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
197{
198 ObjectClass *class_a = (ObjectClass *)a;
199 ObjectClass *class_b = (ObjectClass *)b;
200 const char *name_a, *name_b;
201
202 name_a = object_class_get_name(class_a);
203 name_b = object_class_get_name(class_b);
478032a9 204 if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
e67db06e 205 return 1;
478032a9 206 } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
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207 return -1;
208 } else {
209 return strcmp(name_a, name_b);
210 }
211}
212
213static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
214{
215 ObjectClass *oc = data;
8486af93 216 CPUListState *s = user_data;
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217 const char *typename;
218 char *name;
e67db06e 219
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220 typename = object_class_get_name(oc);
221 name = g_strndup(typename,
222 strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
e67db06e 223 (*s->cpu_fprintf)(s->file, " %s\n",
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224 name);
225 g_free(name);
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226}
227
228void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf)
229{
8486af93 230 CPUListState s = {
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231 .file = f,
232 .cpu_fprintf = cpu_fprintf,
233 };
234 GSList *list;
235
236 list = object_class_get_list(TYPE_OPENRISC_CPU, false);
237 list = g_slist_sort(list, openrisc_cpu_list_compare);
238 (*cpu_fprintf)(f, "Available CPUs:\n");
239 g_slist_foreach(list, openrisc_cpu_list_entry, &s);
240 g_slist_free(list);
241}
242
243type_init(openrisc_cpu_register_types)