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1/*
2 * QEMU OpenRISC CPU
3 *
4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "cpu.h"
21#include "qemu-common.h"
22
23/* CPUClass::reset() */
24static void openrisc_cpu_reset(CPUState *s)
25{
26 OpenRISCCPU *cpu = OPENRISC_CPU(s);
27 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
28
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29 occ->parent_reset(s);
30
31 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints));
32
33 tlb_flush(&cpu->env, 1);
34 /*tb_flush(&cpu->env); FIXME: Do we need it? */
35
36 cpu->env.pc = 0x100;
37 cpu->env.sr = SR_FO | SR_SM;
38 cpu->env.exception_index = -1;
39
40 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
41 cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S;
42 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
43 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
44
45#ifndef CONFIG_USER_ONLY
46 cpu->env.picmr = 0x00000000;
47 cpu->env.picsr = 0x00000000;
48
49 cpu->env.ttmr = 0x00000000;
50 cpu->env.ttcr = 0x00000000;
51#endif
52}
53
54static inline void set_feature(OpenRISCCPU *cpu, int feature)
55{
56 cpu->feature |= feature;
57 cpu->env.cpucfgr = cpu->feature;
58}
59
c296262b 60static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
e67db06e 61{
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62 OpenRISCCPU *cpu = OPENRISC_CPU(dev);
63 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
e67db06e 64
e67db06e 65 cpu_reset(CPU(cpu));
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66
67 occ->parent_realize(dev, errp);
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68}
69
70static void openrisc_cpu_initfn(Object *obj)
71{
c05efcb1 72 CPUState *cs = CPU(obj);
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73 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
74 static int inited;
75
c05efcb1 76 cs->env_ptr = &cpu->env;
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77 cpu_exec_init(&cpu->env);
78
79#ifndef CONFIG_USER_ONLY
80 cpu_openrisc_mmu_init(cpu);
81#endif
82
83 if (tcg_enabled() && !inited) {
84 inited = 1;
85 openrisc_translate_init();
86 }
87}
88
89/* CPU models */
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90
91static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
92{
93 ObjectClass *oc;
071b3364 94 char *typename;
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95
96 if (cpu_model == NULL) {
97 return NULL;
98 }
99
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100 typename = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, cpu_model);
101 oc = object_class_by_name(typename);
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102 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
103 object_class_is_abstract(oc))) {
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104 return NULL;
105 }
106 return oc;
107}
108
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109static void or1200_initfn(Object *obj)
110{
111 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
112
113 set_feature(cpu, OPENRISC_FEATURE_OB32S);
114 set_feature(cpu, OPENRISC_FEATURE_OF32S);
115}
116
117static void openrisc_any_initfn(Object *obj)
118{
119 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
120
121 set_feature(cpu, OPENRISC_FEATURE_OB32S);
122}
123
124typedef struct OpenRISCCPUInfo {
125 const char *name;
126 void (*initfn)(Object *obj);
127} OpenRISCCPUInfo;
128
129static const OpenRISCCPUInfo openrisc_cpus[] = {
130 { .name = "or1200", .initfn = or1200_initfn },
131 { .name = "any", .initfn = openrisc_any_initfn },
132};
133
134static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
135{
136 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
137 CPUClass *cc = CPU_CLASS(occ);
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138 DeviceClass *dc = DEVICE_CLASS(oc);
139
140 occ->parent_realize = dc->realize;
141 dc->realize = openrisc_cpu_realizefn;
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142
143 occ->parent_reset = cc->reset;
144 cc->reset = openrisc_cpu_reset;
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145
146 cc->class_by_name = openrisc_cpu_class_by_name;
97a8ea5a 147 cc->do_interrupt = openrisc_cpu_do_interrupt;
878096ee 148 cc->dump_state = openrisc_cpu_dump_state;
da697214 149 device_class_set_vmsd(dc, &vmstate_openrisc_cpu);
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150}
151
152static void cpu_register(const OpenRISCCPUInfo *info)
153{
154 TypeInfo type_info = {
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155 .parent = TYPE_OPENRISC_CPU,
156 .instance_size = sizeof(OpenRISCCPU),
157 .instance_init = info->initfn,
158 .class_size = sizeof(OpenRISCCPUClass),
159 };
160
478032a9 161 type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name);
a1ebd6ce 162 type_register(&type_info);
478032a9 163 g_free((void *)type_info.name);
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164}
165
166static const TypeInfo openrisc_cpu_type_info = {
167 .name = TYPE_OPENRISC_CPU,
168 .parent = TYPE_CPU,
169 .instance_size = sizeof(OpenRISCCPU),
170 .instance_init = openrisc_cpu_initfn,
bc755a00 171 .abstract = true,
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172 .class_size = sizeof(OpenRISCCPUClass),
173 .class_init = openrisc_cpu_class_init,
174};
175
176static void openrisc_cpu_register_types(void)
177{
178 int i;
179
180 type_register_static(&openrisc_cpu_type_info);
181 for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) {
182 cpu_register(&openrisc_cpus[i]);
183 }
184}
185
186OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
187{
188 OpenRISCCPU *cpu;
bd039ce0 189 ObjectClass *oc;
e67db06e 190
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191 oc = openrisc_cpu_class_by_name(cpu_model);
192 if (oc == NULL) {
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193 return NULL;
194 }
bd039ce0 195 cpu = OPENRISC_CPU(object_new(object_class_get_name(oc)));
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196 cpu->env.cpu_model_str = cpu_model;
197
c296262b 198 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
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199
200 return cpu;
201}
202
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203/* Sort alphabetically by type name, except for "any". */
204static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
205{
206 ObjectClass *class_a = (ObjectClass *)a;
207 ObjectClass *class_b = (ObjectClass *)b;
208 const char *name_a, *name_b;
209
210 name_a = object_class_get_name(class_a);
211 name_b = object_class_get_name(class_b);
478032a9 212 if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
e67db06e 213 return 1;
478032a9 214 } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
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215 return -1;
216 } else {
217 return strcmp(name_a, name_b);
218 }
219}
220
221static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
222{
223 ObjectClass *oc = data;
8486af93 224 CPUListState *s = user_data;
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225 const char *typename;
226 char *name;
e67db06e 227
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228 typename = object_class_get_name(oc);
229 name = g_strndup(typename,
230 strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
e67db06e 231 (*s->cpu_fprintf)(s->file, " %s\n",
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232 name);
233 g_free(name);
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234}
235
236void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf)
237{
8486af93 238 CPUListState s = {
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239 .file = f,
240 .cpu_fprintf = cpu_fprintf,
241 };
242 GSList *list;
243
244 list = object_class_get_list(TYPE_OPENRISC_CPU, false);
245 list = g_slist_sort(list, openrisc_cpu_list_compare);
246 (*cpu_fprintf)(f, "Available CPUs:\n");
247 g_slist_foreach(list, openrisc_cpu_list_entry, &s);
248 g_slist_free(list);
249}
250
251type_init(openrisc_cpu_register_types)