[qemu.git] / target-openrisc / cpu.h

/*
 * OpenRISC virtual CPU header.
 *
 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef CPU_OPENRISC_H
#define CPU_OPENRISC_H

#define TARGET_LONG_BITS 32
#define ELF_MACHINE    EM_OPENRISC

#define CPUArchState struct CPUOpenRISCState

/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl.  */
struct OpenRISCCPU;

#include "config.h"
#include "qemu-common.h"
#include "cpu-defs.h"
#include "softfloat.h"
#include "qemu/cpu.h"
#include "error.h"

#define TYPE_OPENRISC_CPU "or32-cpu"

#define OPENRISC_CPU_CLASS(klass) \
    OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
#define OPENRISC_CPU(obj) \
    OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
#define OPENRISC_CPU_GET_CLASS(obj) \
    OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)

/**
 * OpenRISCCPUClass:
 * @parent_reset: The parent class' reset handler.
 *
 * A OpenRISC CPU model.
 */
typedef struct OpenRISCCPUClass {
    /*< private >*/
    CPUClass parent_class;
    /*< public >*/

    void (*parent_reset)(CPUState *cpu);
} OpenRISCCPUClass;

#define NB_MMU_MODES    3

enum {
    MMU_NOMMU_IDX = 0,
    MMU_SUPERVISOR_IDX = 1,
    MMU_USER_IDX = 2,
};

#define TARGET_PAGE_BITS 13

#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32

#define SET_FP_CAUSE(reg, v)    do {\
                                    (reg) = ((reg) & ~(0x3f << 12)) | \
                                            ((v & 0x3f) << 12);\
                                } while (0)
#define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
#define UPDATE_FP_FLAGS(reg, v)   do {\
                                      (reg) |= ((v & 0x1f) << 2);\
                                  } while (0)

/* Internal flags, delay slot flag */
#define D_FLAG    1

/* Interrupt */
#define NR_IRQS  32

/* Registers */
enum {
    R0 = 0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10,
    R11, R12, R13, R14, R15, R16, R17, R18, R19, R20,
    R21, R22, R23, R24, R25, R26, R27, R28, R29, R30,
    R31
};

/* Register aliases */
enum {
    R_ZERO = R0,
    R_SP = R1,
    R_FP = R2,
    R_LR = R9,
    R_RV = R11,
    R_RVH = R12
};

/* Unit presece register */
enum {
    UPR_UP = (1 << 0),
    UPR_DCP = (1 << 1),
    UPR_ICP = (1 << 2),
    UPR_DMP = (1 << 3),
    UPR_IMP = (1 << 4),
    UPR_MP = (1 << 5),
    UPR_DUP = (1 << 6),
    UPR_PCUR = (1 << 7),
    UPR_PMP = (1 << 8),
    UPR_PICP = (1 << 9),
    UPR_TTP = (1 << 10),
    UPR_CUP = (255 << 24),
};

/* CPU configure register */
enum {
    CPUCFGR_NSGF = (15 << 0),
    CPUCFGR_CGF = (1 << 4),
    CPUCFGR_OB32S = (1 << 5),
    CPUCFGR_OB64S = (1 << 6),
    CPUCFGR_OF32S = (1 << 7),
    CPUCFGR_OF64S = (1 << 8),
    CPUCFGR_OV64S = (1 << 9),
};

/* DMMU configure register */
enum {
    DMMUCFGR_NTW = (3 << 0),
    DMMUCFGR_NTS = (7 << 2),
    DMMUCFGR_NAE = (7 << 5),
    DMMUCFGR_CRI = (1 << 8),
    DMMUCFGR_PRI = (1 << 9),
    DMMUCFGR_TEIRI = (1 << 10),
    DMMUCFGR_HTR = (1 << 11),
};

/* IMMU configure register */
enum {
    IMMUCFGR_NTW = (3 << 0),
    IMMUCFGR_NTS = (7 << 2),
    IMMUCFGR_NAE = (7 << 5),
    IMMUCFGR_CRI = (1 << 8),
    IMMUCFGR_PRI = (1 << 9),
    IMMUCFGR_TEIRI = (1 << 10),
    IMMUCFGR_HTR = (1 << 11),
};

/* Float point control status register */
enum {
    FPCSR_FPEE = 1,
    FPCSR_RM = (3 << 1),
    FPCSR_OVF = (1 << 3),
    FPCSR_UNF = (1 << 4),
    FPCSR_SNF = (1 << 5),
    FPCSR_QNF = (1 << 6),
    FPCSR_ZF = (1 << 7),
    FPCSR_IXF = (1 << 8),
    FPCSR_IVF = (1 << 9),
    FPCSR_INF = (1 << 10),
    FPCSR_DZF = (1 << 11),
};

/* Exceptions indices */
enum {
    EXCP_RESET    = 0x1,
    EXCP_BUSERR   = 0x2,
    EXCP_DPF      = 0x3,
    EXCP_IPF      = 0x4,
    EXCP_TICK     = 0x5,
    EXCP_ALIGN    = 0x6,
    EXCP_ILLEGAL  = 0x7,
    EXCP_INT      = 0x8,
    EXCP_DTLBMISS = 0x9,
    EXCP_ITLBMISS = 0xa,
    EXCP_RANGE    = 0xb,
    EXCP_SYSCALL  = 0xc,
    EXCP_FPE      = 0xd,
    EXCP_TRAP     = 0xe,
    EXCP_NR,
};

/* Supervisor register */
enum {
    SR_SM = (1 << 0),
    SR_TEE = (1 << 1),
    SR_IEE = (1 << 2),
    SR_DCE = (1 << 3),
    SR_ICE = (1 << 4),
    SR_DME = (1 << 5),
    SR_IME = (1 << 6),
    SR_LEE = (1 << 7),
    SR_CE  = (1 << 8),
    SR_F   = (1 << 9),
    SR_CY  = (1 << 10),
    SR_OV  = (1 << 11),
    SR_OVE = (1 << 12),
    SR_DSX = (1 << 13),
    SR_EPH = (1 << 14),
    SR_FO  = (1 << 15),
    SR_SUMRA = (1 << 16),
    SR_SCE = (1 << 17),
};

/* OpenRISC Hardware Capabilities */
enum {
    OPENRISC_FEATURE_NSGF = (15 << 0),
    OPENRISC_FEATURE_CGF = (1 << 4),
    OPENRISC_FEATURE_OB32S = (1 << 5),
    OPENRISC_FEATURE_OB64S = (1 << 6),
    OPENRISC_FEATURE_OF32S = (1 << 7),
    OPENRISC_FEATURE_OF64S = (1 << 8),
    OPENRISC_FEATURE_OV64S = (1 << 9),
};

/* TLB size */
enum {
    DTLB_WAYS = 1,
    DTLB_SIZE = 64,
    DTLB_MASK = (DTLB_SIZE-1),
    ITLB_WAYS = 1,
    ITLB_SIZE = 64,
    ITLB_MASK = (ITLB_SIZE-1),
};

/* TLB prot */
enum {
    URE = (1 << 6),
    UWE = (1 << 7),
    SRE = (1 << 8),
    SWE = (1 << 9),

    SXE = (1 << 6),
    UXE = (1 << 7),
};

/* check if tlb available */
enum {
    TLBRET_INVALID = -3,
    TLBRET_NOMATCH = -2,
    TLBRET_BADADDR = -1,
    TLBRET_MATCH = 0
};

typedef struct OpenRISCTLBEntry {
    uint32_t mr;
    uint32_t tr;
} OpenRISCTLBEntry;

#ifndef CONFIG_USER_ONLY
typedef struct CPUOpenRISCTLBContext {
    OpenRISCTLBEntry itlb[ITLB_WAYS][ITLB_SIZE];
    OpenRISCTLBEntry dtlb[DTLB_WAYS][DTLB_SIZE];

    int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu,
                                         target_phys_addr_t *physical,
                                         int *prot,
                                         target_ulong address, int rw);
    int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu,
                                         target_phys_addr_t *physical,
                                         int *prot,
                                         target_ulong address, int rw);
} CPUOpenRISCTLBContext;
#endif

typedef struct CPUOpenRISCState {
    target_ulong gpr[32];     /* General registers */
    target_ulong pc;          /* Program counter */
    target_ulong npc;         /* Next PC */
    target_ulong ppc;         /* Prev PC */
    target_ulong jmp_pc;      /* Jump PC */

    target_ulong machi;       /* Multiply register MACHI */
    target_ulong maclo;       /* Multiply register MACLO */

    target_ulong fpmaddhi;    /* Multiply and add float register FPMADDHI */
    target_ulong fpmaddlo;    /* Multiply and add float register FPMADDLO */

    target_ulong epcr;        /* Exception PC register */
    target_ulong eear;        /* Exception EA register */

    uint32_t sr;              /* Supervisor register */
    uint32_t vr;              /* Version register */
    uint32_t upr;             /* Unit presence register */
    uint32_t cpucfgr;         /* CPU configure register */
    uint32_t dmmucfgr;        /* DMMU configure register */
    uint32_t immucfgr;        /* IMMU configure register */
    uint32_t esr;             /* Exception supervisor register */
    uint32_t fpcsr;           /* Float register */
    float_status fp_status;

    uint32_t flags;           /* cpu_flags, we only use it for exception
                                 in solt so far.  */
    uint32_t btaken;          /* the SR_F bit */

    CPU_COMMON

#ifndef CONFIG_USER_ONLY
    CPUOpenRISCTLBContext * tlb;

    struct QEMUTimer *timer;
    uint32_t ttmr;          /* Timer tick mode register */
    uint32_t ttcr;          /* Timer tick count register */

    uint32_t picmr;         /* Interrupt mask register */
    uint32_t picsr;         /* Interrupt contrl register*/
#endif
    void *irq[32];          /* Interrupt irq input */
} CPUOpenRISCState;

/**
 * OpenRISCCPU:
 * @env: #CPUOpenRISCState
 *
 * A OpenRISC CPU.
 */
typedef struct OpenRISCCPU {
    /*< private >*/
    CPUState parent_obj;
    /*< public >*/

    CPUOpenRISCState env;

    uint32_t feature;       /* CPU Capabilities */
} OpenRISCCPU;

static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env)
{
    return OPENRISC_CPU(container_of(env, OpenRISCCPU, env));
}

#define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))

OpenRISCCPU *cpu_openrisc_init(const char *cpu_model);
void openrisc_cpu_realize(Object *obj, Error **errp);

void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
int cpu_openrisc_exec(CPUOpenRISCState *s);
void do_interrupt(CPUOpenRISCState *env);
void openrisc_translate_init(void);
int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
                                  target_ulong address,
                                  int rw, int mmu_idx);

#define cpu_list cpu_openrisc_list
#define cpu_exec cpu_openrisc_exec
#define cpu_gen_code cpu_openrisc_gen_code
#define cpu_handle_mmu_fault cpu_openrisc_handle_mmu_fault

#ifndef CONFIG_USER_ONLY
void cpu_openrisc_mmu_init(OpenRISCCPU *cpu);
int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
                                target_phys_addr_t *physical,
                                int *prot, target_ulong address, int rw);
int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
                               target_phys_addr_t *physical,
                               int *prot, target_ulong address, int rw);
int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
                               target_phys_addr_t *physical,
                               int *prot, target_ulong address, int rw);
#endif

static inline CPUOpenRISCState *cpu_init(const char *cpu_model)
{
    OpenRISCCPU *cpu = cpu_openrisc_init(cpu_model);
    if (cpu) {
        return &cpu->env;
    }
    return NULL;
}

#include "cpu-all.h"

static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
                                        target_ulong *pc,
                                        target_ulong *cs_base, int *flags)
{
    *pc = env->pc;
    *cs_base = 0;
    /* D_FLAG -- branch instruction exception */
    *flags = (env->flags & D_FLAG);
}

static inline int cpu_mmu_index(CPUOpenRISCState *env)
{
    if (!(env->sr & SR_IME)) {
        return MMU_NOMMU_IDX;
    }
    return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX;
}

#define CPU_INTERRUPT_TIMER   CPU_INTERRUPT_TGT_INT_0
static inline bool cpu_has_work(CPUOpenRISCState *env)
{
    return env->interrupt_request & (CPU_INTERRUPT_HARD |
                                     CPU_INTERRUPT_TIMER);
}

#include "exec-all.h"

static inline target_ulong cpu_get_pc(CPUOpenRISCState *env)
{
    return env->pc;
}

static inline void cpu_pc_from_tb(CPUOpenRISCState *env, TranslationBlock *tb)
{
    env->pc = tb->pc;
}

#endif /* CPU_OPENRISC_H */
Commit	Line	Data
e67db06e JL	1	/*
	2	* OpenRISC virtual CPU header.
	3	*
	4	* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#ifndef CPU_OPENRISC_H
	21	#define CPU_OPENRISC_H
	22
	23	#define TARGET_LONG_BITS 32
	24	#define ELF_MACHINE EM_OPENRISC
	25
	26	#define CPUArchState struct CPUOpenRISCState
	27
726fe045 JL	28	/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
	29	struct OpenRISCCPU;
	30
e67db06e JL	31	#include "config.h"
	32	#include "qemu-common.h"
	33	#include "cpu-defs.h"
	34	#include "softfloat.h"
	35	#include "qemu/cpu.h"
	36	#include "error.h"
	37
	38	#define TYPE_OPENRISC_CPU "or32-cpu"
	39
	40	#define OPENRISC_CPU_CLASS(klass) \
	41	OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
	42	#define OPENRISC_CPU(obj) \
	43	OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
	44	#define OPENRISC_CPU_GET_CLASS(obj) \
	45	OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)
	46
	47	/**
	48	* OpenRISCCPUClass:
	49	* @parent_reset: The parent class' reset handler.
	50	*
	51	* A OpenRISC CPU model.
	52	*/
	53	typedef struct OpenRISCCPUClass {
	54	/< private >/
	55	CPUClass parent_class;
	56	/< public >/
	57
	58	void (parent_reset)(CPUState cpu);
	59	} OpenRISCCPUClass;
	60
	61	#define NB_MMU_MODES 3
	62
726fe045 JL	63	enum {
	64	MMU_NOMMU_IDX = 0,
	65	MMU_SUPERVISOR_IDX = 1,
	66	MMU_USER_IDX = 2,
	67	};
	68
e67db06e JL	69	#define TARGET_PAGE_BITS 13
	70
	71	#define TARGET_PHYS_ADDR_SPACE_BITS 32
	72	#define TARGET_VIRT_ADDR_SPACE_BITS 32
	73
	74	#define SET_FP_CAUSE(reg, v) do {\
	75	(reg) = ((reg) & ~(0x3f << 12)) \| \
	76	((v & 0x3f) << 12);\
	77	} while (0)
	78	#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
	79	#define UPDATE_FP_FLAGS(reg, v) do {\
	80	(reg) \|= ((v & 0x1f) << 2);\
	81	} while (0)
	82
	83	/* Internal flags, delay slot flag */
	84	#define D_FLAG 1
	85
b6a71ef7 JL	86	/* Interrupt */
	87	#define NR_IRQS 32
	88
e67db06e JL	89	/* Registers */
	90	enum {
	91	R0 = 0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10,
	92	R11, R12, R13, R14, R15, R16, R17, R18, R19, R20,
	93	R21, R22, R23, R24, R25, R26, R27, R28, R29, R30,
	94	R31
	95	};
	96
	97	/* Register aliases */
	98	enum {
	99	R_ZERO = R0,
	100	R_SP = R1,
	101	R_FP = R2,
	102	R_LR = R9,
	103	R_RV = R11,
	104	R_RVH = R12
	105	};
	106
	107	/* Unit presece register */
	108	enum {
	109	UPR_UP = (1 << 0),
	110	UPR_DCP = (1 << 1),
	111	UPR_ICP = (1 << 2),
	112	UPR_DMP = (1 << 3),
	113	UPR_IMP = (1 << 4),
	114	UPR_MP = (1 << 5),
	115	UPR_DUP = (1 << 6),
	116	UPR_PCUR = (1 << 7),
	117	UPR_PMP = (1 << 8),
	118	UPR_PICP = (1 << 9),
	119	UPR_TTP = (1 << 10),
	120	UPR_CUP = (255 << 24),
	121	};
	122
	123	/* CPU configure register */
	124	enum {
	125	CPUCFGR_NSGF = (15 << 0),
	126	CPUCFGR_CGF = (1 << 4),
	127	CPUCFGR_OB32S = (1 << 5),
	128	CPUCFGR_OB64S = (1 << 6),
	129	CPUCFGR_OF32S = (1 << 7),
	130	CPUCFGR_OF64S = (1 << 8),
	131	CPUCFGR_OV64S = (1 << 9),
	132	};
	133
	134	/* DMMU configure register */
	135	enum {
	136	DMMUCFGR_NTW = (3 << 0),
	137	DMMUCFGR_NTS = (7 << 2),
	138	DMMUCFGR_NAE = (7 << 5),
	139	DMMUCFGR_CRI = (1 << 8),
	140	DMMUCFGR_PRI = (1 << 9),
	141	DMMUCFGR_TEIRI = (1 << 10),
	142	DMMUCFGR_HTR = (1 << 11),
	143	};
	144
	145	/* IMMU configure register */
	146	enum {
	147	IMMUCFGR_NTW = (3 << 0),
	148	IMMUCFGR_NTS = (7 << 2),
	149	IMMUCFGR_NAE = (7 << 5),
	150	IMMUCFGR_CRI = (1 << 8),
	151	IMMUCFGR_PRI = (1 << 9),
	152	IMMUCFGR_TEIRI = (1 << 10),
153	IMMUCFGR_HTR = (1 << 11),
154	};
155
156	/* Float point control status register */
157	enum {
158	FPCSR_FPEE = 1,
159	FPCSR_RM = (3 << 1),
160	FPCSR_OVF = (1 << 3),
161	FPCSR_UNF = (1 << 4),
162	FPCSR_SNF = (1 << 5),
163	FPCSR_QNF = (1 << 6),
164	FPCSR_ZF = (1 << 7),
165	FPCSR_IXF = (1 << 8),
166	FPCSR_IVF = (1 << 9),
167	FPCSR_INF = (1 << 10),
168	FPCSR_DZF = (1 << 11),
169	};
170
171	/* Exceptions indices */
172	enum {
173	EXCP_RESET = 0x1,
174	EXCP_BUSERR = 0x2,
175	EXCP_DPF = 0x3,
176	EXCP_IPF = 0x4,
177	EXCP_TICK = 0x5,
178	EXCP_ALIGN = 0x6,
179	EXCP_ILLEGAL = 0x7,
180	EXCP_INT = 0x8,
181	EXCP_DTLBMISS = 0x9,
182	EXCP_ITLBMISS = 0xa,
183	EXCP_RANGE = 0xb,
184	EXCP_SYSCALL = 0xc,
185	EXCP_FPE = 0xd,
186	EXCP_TRAP = 0xe,
187	EXCP_NR,
188	};
189
190	/* Supervisor register */
191	enum {
192	SR_SM = (1 << 0),
193	SR_TEE = (1 << 1),
194	SR_IEE = (1 << 2),
195	SR_DCE = (1 << 3),
196	SR_ICE = (1 << 4),
197	SR_DME = (1 << 5),
198	SR_IME = (1 << 6),
199	SR_LEE = (1 << 7),
200	SR_CE = (1 << 8),
201	SR_F = (1 << 9),
202	SR_CY = (1 << 10),
203	SR_OV = (1 << 11),
204	SR_OVE = (1 << 12),
205	SR_DSX = (1 << 13),
206	SR_EPH = (1 << 14),
207	SR_FO = (1 << 15),
208	SR_SUMRA = (1 << 16),
209	SR_SCE = (1 << 17),
210	};
211
212	/* OpenRISC Hardware Capabilities */
213	enum {
214	OPENRISC_FEATURE_NSGF = (15 << 0),
215	OPENRISC_FEATURE_CGF = (1 << 4),
216	OPENRISC_FEATURE_OB32S = (1 << 5),
217	OPENRISC_FEATURE_OB64S = (1 << 6),
218	OPENRISC_FEATURE_OF32S = (1 << 7),
219	OPENRISC_FEATURE_OF64S = (1 << 8),
220	OPENRISC_FEATURE_OV64S = (1 << 9),
221	};
222
726fe045 JL	223	/* TLB size */
	224	enum {
	225	DTLB_WAYS = 1,
	226	DTLB_SIZE = 64,
	227	DTLB_MASK = (DTLB_SIZE-1),
	228	ITLB_WAYS = 1,
	229	ITLB_SIZE = 64,
	230	ITLB_MASK = (ITLB_SIZE-1),
	231	};
	232
	233	/* TLB prot */
	234	enum {
	235	URE = (1 << 6),
	236	UWE = (1 << 7),
	237	SRE = (1 << 8),
	238	SWE = (1 << 9),
	239
	240	SXE = (1 << 6),
	241	UXE = (1 << 7),
	242	};
	243
	244	/* check if tlb available */
	245	enum {
	246	TLBRET_INVALID = -3,
	247	TLBRET_NOMATCH = -2,
	248	TLBRET_BADADDR = -1,
	249	TLBRET_MATCH = 0
	250	};
	251
	252	typedef struct OpenRISCTLBEntry {
	253	uint32_t mr;
	254	uint32_t tr;
	255	} OpenRISCTLBEntry;
	256
	257	#ifndef CONFIG_USER_ONLY
	258	typedef struct CPUOpenRISCTLBContext {
	259	OpenRISCTLBEntry itlb[ITLB_WAYS][ITLB_SIZE];
	260	OpenRISCTLBEntry dtlb[DTLB_WAYS][DTLB_SIZE];
	261
	262	int (cpu_openrisc_map_address_code)(struct OpenRISCCPU cpu,
	263	target_phys_addr_t *physical,
	264	int *prot,
	265	target_ulong address, int rw);
	266	int (cpu_openrisc_map_address_data)(struct OpenRISCCPU cpu,
	267	target_phys_addr_t *physical,
	268	int *prot,
	269	target_ulong address, int rw);
	270	} CPUOpenRISCTLBContext;
	271	#endif
	272
e67db06e JL	273	typedef struct CPUOpenRISCState {
	274	target_ulong gpr[32]; /* General registers */
	275	target_ulong pc; /* Program counter */
	276	target_ulong npc; /* Next PC */
	277	target_ulong ppc; /* Prev PC */
	278	target_ulong jmp_pc; /* Jump PC */
	279
	280	target_ulong machi; /* Multiply register MACHI */
	281	target_ulong maclo; /* Multiply register MACLO */
	282
	283	target_ulong fpmaddhi; /* Multiply and add float register FPMADDHI */
	284	target_ulong fpmaddlo; /* Multiply and add float register FPMADDLO */
	285
	286	target_ulong epcr; /* Exception PC register */
	287	target_ulong eear; /* Exception EA register */
	288
	289	uint32_t sr; /* Supervisor register */
	290	uint32_t vr; /* Version register */
	291	uint32_t upr; /* Unit presence register */
	292	uint32_t cpucfgr; /* CPU configure register */
	293	uint32_t dmmucfgr; /* DMMU configure register */
	294	uint32_t immucfgr; /* IMMU configure register */
	295	uint32_t esr; /* Exception supervisor register */
	296	uint32_t fpcsr; /* Float register */
	297	float_status fp_status;
	298
	299	uint32_t flags; /* cpu_flags, we only use it for exception
	300	in solt so far. */
	301	uint32_t btaken; /* the SR_F bit */
	302
	303	CPU_COMMON
	304
	305	#ifndef CONFIG_USER_ONLY
726fe045 JL	306	CPUOpenRISCTLBContext * tlb;
726fe045 JL	307
e67db06e JL	308	struct QEMUTimer *timer;
	309	uint32_t ttmr; /* Timer tick mode register */
	310	uint32_t ttcr; /* Timer tick count register */
	311
	312	uint32_t picmr; /* Interrupt mask register */
	313	uint32_t picsr; /* Interrupt contrl register*/
	314	#endif
b6a71ef7	315	void irq[32]; / Interrupt irq input */
e67db06e JL	316	} CPUOpenRISCState;
	317
	318	/**
	319	* OpenRISCCPU:
	320	* @env: #CPUOpenRISCState
	321	*
	322	* A OpenRISC CPU.
	323	*/
	324	typedef struct OpenRISCCPU {
	325	/< private >/
	326	CPUState parent_obj;
	327	/< public >/
	328
	329	CPUOpenRISCState env;
	330
	331	uint32_t feature; /* CPU Capabilities */
	332	} OpenRISCCPU;
	333
	334	static inline OpenRISCCPU openrisc_env_get_cpu(CPUOpenRISCState env)
	335	{
	336	return OPENRISC_CPU(container_of(env, OpenRISCCPU, env));
	337	}
	338
	339	#define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))
	340
	341	OpenRISCCPU cpu_openrisc_init(const char cpu_model);
	342	void openrisc_cpu_realize(Object obj, Error *errp);
	343
	344	void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
	345	int cpu_openrisc_exec(CPUOpenRISCState *s);
	346	void do_interrupt(CPUOpenRISCState *env);
	347	void openrisc_translate_init(void);
726fe045 JL	348	int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
	349	target_ulong address,
	350	int rw, int mmu_idx);
e67db06e JL	351
	352	#define cpu_list cpu_openrisc_list
	353	#define cpu_exec cpu_openrisc_exec
	354	#define cpu_gen_code cpu_openrisc_gen_code
726fe045	355	#define cpu_handle_mmu_fault cpu_openrisc_handle_mmu_fault
e67db06e JL	356
	357	#ifndef CONFIG_USER_ONLY
	358	void cpu_openrisc_mmu_init(OpenRISCCPU *cpu);
726fe045 JL	359	int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
	360	target_phys_addr_t *physical,
	361	int *prot, target_ulong address, int rw);
	362	int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
	363	target_phys_addr_t *physical,
	364	int *prot, target_ulong address, int rw);
	365	int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
	366	target_phys_addr_t *physical,
	367	int *prot, target_ulong address, int rw);
e67db06e JL	368	#endif
	369
	370	static inline CPUOpenRISCState cpu_init(const char cpu_model)
	371	{
	372	OpenRISCCPU *cpu = cpu_openrisc_init(cpu_model);
	373	if (cpu) {
	374	return &cpu->env;
	375	}
	376	return NULL;
	377	}
	378
	379	#include "cpu-all.h"
	380
	381	static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
	382	target_ulong *pc,
	383	target_ulong cs_base, int flags)
	384	{
	385	*pc = env->pc;
	386	*cs_base = 0;
	387	/* D_FLAG -- branch instruction exception */
	388	*flags = (env->flags & D_FLAG);
	389	}
	390
	391	static inline int cpu_mmu_index(CPUOpenRISCState *env)
	392	{
726fe045 JL	393	if (!(env->sr & SR_IME)) {
	394	return MMU_NOMMU_IDX;
	395	}
	396	return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX;
e67db06e JL	397	}
e67db06e JL	398
b6a71ef7	399	#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
e67db06e JL	400	static inline bool cpu_has_work(CPUOpenRISCState *env)
e67db06e JL	401	{
b6a71ef7 JL	402	return env->interrupt_request & (CPU_INTERRUPT_HARD \|
b6a71ef7 JL	403	CPU_INTERRUPT_TIMER);
e67db06e JL	404	}
	405
	406	#include "exec-all.h"
	407
	408	static inline target_ulong cpu_get_pc(CPUOpenRISCState *env)
	409	{
	410	return env->pc;
	411	}
	412
	413	static inline void cpu_pc_from_tb(CPUOpenRISCState env, TranslationBlock tb)
	414	{
	415	env->pc = tb->pc;
	416	}
	417
	418	#endif /* CPU_OPENRISC_H */