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exec.h: fix coding style and change cpu_has_work to return bool
[qemu.git] / target-ppc / cpu.h
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation cpu definitions for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
79aceca5
FB		 18 */
19#if !defined (__CPU_PPC_H__)
20#define __CPU_PPC_H__
21
3fc6c082 22#include "config.h"
9a78eead 23#include "qemu-common.h"
3fc6c082 24
a4f30719
JM		 25//#define PPC_EMULATE_32BITS_HYPV
26
76a66253 27#if defined (TARGET_PPC64)
3cd7d1dd 28/* PowerPC 64 definitions */
d9d7210c 29#define TARGET_LONG_BITS 64
35cdaad6 30#define TARGET_PAGE_BITS 12
3cd7d1dd 31
52705890
RH		 32/* Note that the official physical address space bits is 62-M where M
33 is implementation dependent. I've not looked up M for the set of
34 cpus we emulate at the system level. */
35#define TARGET_PHYS_ADDR_SPACE_BITS 62
36
37/* Note that the PPC environment architecture talks about 80 bit virtual
38 addresses, with segmentation. Obviously that's not all visible to a
39 single process, which is all we're concerned with here. */
40#ifdef TARGET_ABI32
41# define TARGET_VIRT_ADDR_SPACE_BITS 32
42#else
43# define TARGET_VIRT_ADDR_SPACE_BITS 64
44#endif
45
81762d6d
DG		 46#define TARGET_PAGE_BITS_16M 24
47
3cd7d1dd
JM		 48#else /* defined (TARGET_PPC64) */
49/* PowerPC 32 definitions */
d9d7210c 50#define TARGET_LONG_BITS 32
3cd7d1dd
JM		 51
52#if defined(TARGET_PPCEMB)
53/* Specific definitions for PowerPC embedded */
54/* BookE have 36 bits physical address space */
3cd7d1dd
JM		 55#if defined(CONFIG_USER_ONLY)
56/* It looks like a lot of Linux programs assume page size
57 * is 4kB long. This is evil, but we have to deal with it...
58 */
35cdaad6 59#define TARGET_PAGE_BITS 12
3cd7d1dd
JM		 60#else /* defined(CONFIG_USER_ONLY) */
61/* Pages can be 1 kB small */
62#define TARGET_PAGE_BITS 10
63#endif /* defined(CONFIG_USER_ONLY) */
64#else /* defined(TARGET_PPCEMB) */
65/* "standard" PowerPC 32 definitions */
66#define TARGET_PAGE_BITS 12
67#endif /* defined(TARGET_PPCEMB) */
68
52705890
RH		 69#define TARGET_PHYS_ADDR_SPACE_BITS 32
70#define TARGET_VIRT_ADDR_SPACE_BITS 32
71
3cd7d1dd 72#endif /* defined (TARGET_PPC64) */
3cf1e035 73
c2764719
PB		 74#define CPUState struct CPUPPCState
75
79aceca5
FB		 76#include "cpu-defs.h"
77
79aceca5
FB		 78#include <setjmp.h>
79
4ecc3190
FB		 80#include "softfloat.h"
81
1fddef4b
FB		 82#define TARGET_HAS_ICE 1
83
7f70c937 84#if defined (TARGET_PPC64)
76a66253
JM		 85#define ELF_MACHINE EM_PPC64
86#else
87#define ELF_MACHINE EM_PPC
88#endif
9042c0e2 89
3fc6c082 90/*****************************************************************************/
a750fc0b 91/* MMU model */
c227f099
AL		 92typedef enum powerpc_mmu_t powerpc_mmu_t;
93enum powerpc_mmu_t {
add78955 94 POWERPC_MMU_UNKNOWN = 0x00000000,
a750fc0b 95 /* Standard 32 bits PowerPC MMU */
add78955 96 POWERPC_MMU_32B = 0x00000001,
a750fc0b 97 /* PowerPC 6xx MMU with software TLB */
add78955 98 POWERPC_MMU_SOFT_6xx = 0x00000002,
a750fc0b 99 /* PowerPC 74xx MMU with software TLB */
add78955 100 POWERPC_MMU_SOFT_74xx = 0x00000003,
a750fc0b 101 /* PowerPC 4xx MMU with software TLB */
add78955 102 POWERPC_MMU_SOFT_4xx = 0x00000004,
a750fc0b 103 /* PowerPC 4xx MMU with software TLB and zones protections */
add78955 104 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
b4095fed 105 /* PowerPC MMU in real mode only */
add78955 106 POWERPC_MMU_REAL = 0x00000006,
b4095fed 107 /* Freescale MPC8xx MMU model */
add78955 108 POWERPC_MMU_MPC8xx = 0x00000007,
a750fc0b 109 /* BookE MMU model */
add78955 110 POWERPC_MMU_BOOKE = 0x00000008,
01662f3e
AG		 111 /* BookE 2.06 MMU model */
112 POWERPC_MMU_BOOKE206 = 0x00000009,
faadf50e 113 /* PowerPC 601 MMU model (specific BATs format) */
add78955 114 POWERPC_MMU_601 = 0x0000000A,
00af685f 115#if defined(TARGET_PPC64)
add78955 116#define POWERPC_MMU_64 0x00010000
cdaee006 117#define POWERPC_MMU_1TSEG 0x00020000
12de9a39 118 /* 64 bits PowerPC MMU */
add78955
JM		 119 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
120 /* 620 variant (no segment exceptions) */
121 POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002,
9d52e907
DG		 122 /* Architecture 2.06 variant */
123 POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | 0x00000003,
00af685f 124#endif /* defined(TARGET_PPC64) */
3fc6c082
FB		 125};
126
127/*****************************************************************************/
a750fc0b 128/* Exception model */
c227f099
AL		 129typedef enum powerpc_excp_t powerpc_excp_t;
130enum powerpc_excp_t {
a750fc0b 131 POWERPC_EXCP_UNKNOWN = 0,
3fc6c082 132 /* Standard PowerPC exception model */
a750fc0b 133 POWERPC_EXCP_STD,
2662a059 134 /* PowerPC 40x exception model */
a750fc0b 135 POWERPC_EXCP_40x,
2662a059 136 /* PowerPC 601 exception model */
a750fc0b 137 POWERPC_EXCP_601,
2662a059 138 /* PowerPC 602 exception model */
a750fc0b 139 POWERPC_EXCP_602,
2662a059 140 /* PowerPC 603 exception model */
a750fc0b
JM		 141 POWERPC_EXCP_603,
142 /* PowerPC 603e exception model */
143 POWERPC_EXCP_603E,
144 /* PowerPC G2 exception model */
145 POWERPC_EXCP_G2,
2662a059 146 /* PowerPC 604 exception model */
a750fc0b 147 POWERPC_EXCP_604,
2662a059 148 /* PowerPC 7x0 exception model */
a750fc0b 149 POWERPC_EXCP_7x0,
2662a059 150 /* PowerPC 7x5 exception model */
a750fc0b 151 POWERPC_EXCP_7x5,
2662a059 152 /* PowerPC 74xx exception model */
a750fc0b 153 POWERPC_EXCP_74xx,
2662a059 154 /* BookE exception model */
a750fc0b 155 POWERPC_EXCP_BOOKE,
00af685f
JM		 156#if defined(TARGET_PPC64)
157 /* PowerPC 970 exception model */
158 POWERPC_EXCP_970,
9d52e907
DG		 159 /* POWER7 exception model */
160 POWERPC_EXCP_POWER7,
00af685f 161#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 162};
163
e1833e1f
JM		 164/*****************************************************************************/
165/* Exception vectors definitions */
166enum {
167 POWERPC_EXCP_NONE = -1,
168 /* The 64 first entries are used by the PowerPC embedded specification */
169 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
170 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
171 POWERPC_EXCP_DSI = 2, /* Data storage exception */
172 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
173 POWERPC_EXCP_EXTERNAL = 4, /* External input */
174 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
175 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
176 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
177 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
178 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
179 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
180 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
181 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
b4095fed
JM		 182 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
183 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
e1833e1f
JM		 184 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
185 /* Vectors 16 to 31 are reserved */
e1833e1f
JM		 186 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
187 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
188 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
189 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
190 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
191 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
e1833e1f
JM		 192 /* Vectors 38 to 63 are reserved */
193 /* Exceptions defined in the PowerPC server specification */
194 POWERPC_EXCP_RESET = 64, /* System reset exception */
e1833e1f
JM		 195 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
196 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
e1833e1f 197 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
e1833e1f 198 POWERPC_EXCP_TRACE = 68, /* Trace exception */
e1833e1f
JM		 199 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
200 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
201 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
202 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
e1833e1f
JM		 203 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
204 /* 40x specific exceptions */
205 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
206 /* 601 specific exceptions */
207 POWERPC_EXCP_IO = 75, /* IO error exception */
208 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
209 /* 602 specific exceptions */
210 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
211 /* 602/603 specific exceptions */
b4095fed 212 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
e1833e1f
JM		 213 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
214 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
215 /* Exceptions available on most PowerPC */
216 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
b4095fed
JM		 217 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
218 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
219 POWERPC_EXCP_SMI = 84, /* System management interrupt */
220 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
e1833e1f 221 /* 7xx/74xx specific exceptions */
b4095fed 222 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
e1833e1f 223 /* 74xx specific exceptions */
b4095fed 224 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
e1833e1f 225 /* 970FX specific exceptions */
b4095fed
JM		 226 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
227 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
5b46d07d 228 /* Freescale embedded cores specific exceptions */
b4095fed
JM		 229 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
230 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
231 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
232 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
e1833e1f
JM		 233 /* EOL */
234 POWERPC_EXCP_NB = 96,
235 /* Qemu exceptions: used internally during code translation */
236 POWERPC_EXCP_STOP = 0x200, /* stop translation */
237 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
238 /* Qemu exceptions: special cases we want to stop translation */
239 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
240 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
4425265b 241 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
e1833e1f
JM		 242};
243
e1833e1f
JM		 244/* Exceptions error codes */
245enum {
246 /* Exception subtypes for POWERPC_EXCP_ALIGN */
247 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
248 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
249 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
250 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
251 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
252 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
253 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
254 /* FP exceptions */
255 POWERPC_EXCP_FP = 0x10,
256 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
257 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
258 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
259 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
7c58044c 260 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
e1833e1f
JM		 261 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
262 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
263 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
264 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
265 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
266 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
267 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
268 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
269 /* Invalid instruction */
270 POWERPC_EXCP_INVAL = 0x20,
271 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
272 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
273 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
274 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
275 /* Privileged instruction */
276 POWERPC_EXCP_PRIV = 0x30,
277 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
278 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
279 /* Trap */
280 POWERPC_EXCP_TRAP = 0x40,
281};
282
a750fc0b
JM		 283/*****************************************************************************/
284/* Input pins model */
c227f099
AL		 285typedef enum powerpc_input_t powerpc_input_t;
286enum powerpc_input_t {
a750fc0b 287 PPC_FLAGS_INPUT_UNKNOWN = 0,
2662a059 288 /* PowerPC 6xx bus */
a750fc0b 289 PPC_FLAGS_INPUT_6xx,
2662a059 290 /* BookE bus */
a750fc0b
JM		 291 PPC_FLAGS_INPUT_BookE,
292 /* PowerPC 405 bus */
293 PPC_FLAGS_INPUT_405,
2662a059 294 /* PowerPC 970 bus */
a750fc0b 295 PPC_FLAGS_INPUT_970,
9d52e907
DG		 296 /* PowerPC POWER7 bus */
297 PPC_FLAGS_INPUT_POWER7,
a750fc0b
JM		 298 /* PowerPC 401 bus */
299 PPC_FLAGS_INPUT_401,
b4095fed
JM		 300 /* Freescale RCPU bus */
301 PPC_FLAGS_INPUT_RCPU,
3fc6c082
FB		 302};
303
a750fc0b 304#define PPC_INPUT(env) (env->bus_model)
3fc6c082 305
be147d08 306/*****************************************************************************/
c227f099
AL		 307typedef struct ppc_def_t ppc_def_t;
308typedef struct opc_handler_t opc_handler_t;
79aceca5 309
3fc6c082
FB		 310/*****************************************************************************/
311/* Types used to describe some PowerPC registers */
312typedef struct CPUPPCState CPUPPCState;
c227f099
AL		 313typedef struct ppc_tb_t ppc_tb_t;
314typedef struct ppc_spr_t ppc_spr_t;
315typedef struct ppc_dcr_t ppc_dcr_t;
316typedef union ppc_avr_t ppc_avr_t;
317typedef union ppc_tlb_t ppc_tlb_t;
76a66253 318
3fc6c082 319/* SPR access micro-ops generations callbacks */
c227f099 320struct ppc_spr_t {
45d827d2
AJ		 321 void (*uea_read)(void *opaque, int gpr_num, int spr_num);
322 void (*uea_write)(void *opaque, int spr_num, int gpr_num);
76a66253 323#if !defined(CONFIG_USER_ONLY)
45d827d2
AJ		 324 void (*oea_read)(void *opaque, int gpr_num, int spr_num);
325 void (*oea_write)(void *opaque, int spr_num, int gpr_num);
326 void (*hea_read)(void *opaque, int gpr_num, int spr_num);
327 void (*hea_write)(void *opaque, int spr_num, int gpr_num);
76a66253 328#endif
b55266b5 329 const char *name;
3fc6c082
FB		 330};
331
332/* Altivec registers (128 bits) */
c227f099 333union ppc_avr_t {
0f6fbcbc 334 float32 f[4];
a9d9eb8f
JM		 335 uint8_t u8[16];
336 uint16_t u16[8];
337 uint32_t u32[4];
ab5f265d
AJ		 338 int8_t s8[16];
339 int16_t s16[8];
340 int32_t s32[4];
a9d9eb8f 341 uint64_t u64[2];
3fc6c082 342};
9fddaa0c 343
3c7b48b7 344#if !defined(CONFIG_USER_ONLY)
3fc6c082 345/* Software TLB cache */
c227f099
AL		 346typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
347struct ppc6xx_tlb_t {
76a66253
JM		 348 target_ulong pte0;
349 target_ulong pte1;
350 target_ulong EPN;
1d0a48fb
JM		 351};
352
c227f099
AL		 353typedef struct ppcemb_tlb_t ppcemb_tlb_t;
354struct ppcemb_tlb_t {
355 target_phys_addr_t RPN;
1d0a48fb 356 target_ulong EPN;
76a66253 357 target_ulong PID;
c55e9aef
JM		 358 target_ulong size;
359 uint32_t prot;
360 uint32_t attr; /* Storage attributes */
1d0a48fb
JM		 361};
362
c227f099
AL		 363union ppc_tlb_t {
364 ppc6xx_tlb_t tlb6;
365 ppcemb_tlb_t tlbe;
3fc6c082 366};
3c7b48b7 367#endif
3fc6c082 368
bb593904
DG		 369#define SDR_32_HTABORG 0xFFFF0000UL
370#define SDR_32_HTABMASK 0x000001FFUL
371
372#if defined(TARGET_PPC64)
373#define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
374#define SDR_64_HTABSIZE 0x000000000000001FULL
375#endif /* defined(TARGET_PPC64 */
376
fda6a0ec
DG		 377#define HASH_PTE_SIZE_32 8
378#define HASH_PTE_SIZE_64 16
379
c227f099
AL		 380typedef struct ppc_slb_t ppc_slb_t;
381struct ppc_slb_t {
81762d6d
DG		 382 uint64_t esid;
383 uint64_t vsid;
8eee0af9
BS		 384};
385
81762d6d
DG		 386/* Bits in the SLB ESID word */
387#define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
388#define SLB_ESID_V 0x0000000008000000ULL /* valid */
389
390/* Bits in the SLB VSID word */
391#define SLB_VSID_SHIFT 12
cdaee006 392#define SLB_VSID_SHIFT_1T 24
81762d6d
DG		 393#define SLB_VSID_SSIZE_SHIFT 62
394#define SLB_VSID_B 0xc000000000000000ULL
395#define SLB_VSID_B_256M 0x0000000000000000ULL
cdaee006 396#define SLB_VSID_B_1T 0x4000000000000000ULL
81762d6d 397#define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
256cebe5 398#define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID)
81762d6d
DG		 399#define SLB_VSID_KS 0x0000000000000800ULL
400#define SLB_VSID_KP 0x0000000000000400ULL
401#define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
402#define SLB_VSID_L 0x0000000000000100ULL
403#define SLB_VSID_C 0x0000000000000080ULL /* class */
404#define SLB_VSID_LP 0x0000000000000030ULL
405#define SLB_VSID_ATTR 0x0000000000000FFFULL
406
407#define SEGMENT_SHIFT_256M 28
408#define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
409
cdaee006
DG		 410#define SEGMENT_SHIFT_1T 40
411#define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
412
413
3fc6c082
FB		 414/*****************************************************************************/
415/* Machine state register bits definition */
76a66253 416#define MSR_SF 63 /* Sixty-four-bit mode hflags */
bd928eba 417#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
3fc6c082 418#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
a4f30719 419#define MSR_SHV 60 /* hypervisor state hflags */
363be49c
JM		 420#define MSR_CM 31 /* Computation mode for BookE hflags */
421#define MSR_ICM 30 /* Interrupt computation mode for BookE */
a4f30719 422#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
71afeb61 423#define MSR_GS 28 /* guest state for BookE */
363be49c 424#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
d26bfc9a
JM		 425#define MSR_VR 25 /* altivec available x hflags */
426#define MSR_SPE 25 /* SPE enable for BookE x hflags */
76a66253
JM		 427#define MSR_AP 23 /* Access privilege state on 602 hflags */
428#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
3fc6c082 429#define MSR_KEY 19 /* key bit on 603e */
25ba3a68 430#define MSR_POW 18 /* Power management */
d26bfc9a
JM		 431#define MSR_TGPR 17 /* TGPR usage on 602/603 x */
432#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
3fc6c082
FB		 433#define MSR_ILE 16 /* Interrupt little-endian mode */
434#define MSR_EE 15 /* External interrupt enable */
76a66253
JM		 435#define MSR_PR 14 /* Problem state hflags */
436#define MSR_FP 13 /* Floating point available hflags */
3fc6c082 437#define MSR_ME 12 /* Machine check interrupt enable */
76a66253 438#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
d26bfc9a
JM		 439#define MSR_SE 10 /* Single-step trace enable x hflags */
440#define MSR_DWE 10 /* Debug wait enable on 405 x */
441#define MSR_UBLE 10 /* User BTB lock enable on e500 x */
442#define MSR_BE 9 /* Branch trace enable x hflags */
443#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
76a66253 444#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
3fc6c082 445#define MSR_AL 7 /* AL bit on POWER */
0411a972 446#define MSR_EP 6 /* Exception prefix on 601 */
3fc6c082 447#define MSR_IR 5 /* Instruction relocate */
3fc6c082 448#define MSR_DR 4 /* Data relocate */
25ba3a68 449#define MSR_PE 3 /* Protection enable on 403 */
d26bfc9a
JM		 450#define MSR_PX 2 /* Protection exclusive on 403 x */
451#define MSR_PMM 2 /* Performance monitor mark on POWER x */
452#define MSR_RI 1 /* Recoverable interrupt 1 */
453#define MSR_LE 0 /* Little-endian mode 1 hflags */
0411a972
JM		 454
455#define msr_sf ((env->msr >> MSR_SF) & 1)
456#define msr_isf ((env->msr >> MSR_ISF) & 1)
a4f30719 457#define msr_shv ((env->msr >> MSR_SHV) & 1)
0411a972
JM		 458#define msr_cm ((env->msr >> MSR_CM) & 1)
459#define msr_icm ((env->msr >> MSR_ICM) & 1)
a4f30719 460#define msr_thv ((env->msr >> MSR_THV) & 1)
71afeb61 461#define msr_gs ((env->msr >> MSR_GS) & 1)
0411a972
JM		 462#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
463#define msr_vr ((env->msr >> MSR_VR) & 1)
f9320410 464#define msr_spe ((env->msr >> MSR_SPE) & 1)
0411a972
JM		 465#define msr_ap ((env->msr >> MSR_AP) & 1)
466#define msr_sa ((env->msr >> MSR_SA) & 1)
467#define msr_key ((env->msr >> MSR_KEY) & 1)
468#define msr_pow ((env->msr >> MSR_POW) & 1)
469#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
470#define msr_ce ((env->msr >> MSR_CE) & 1)
471#define msr_ile ((env->msr >> MSR_ILE) & 1)
472#define msr_ee ((env->msr >> MSR_EE) & 1)
473#define msr_pr ((env->msr >> MSR_PR) & 1)
474#define msr_fp ((env->msr >> MSR_FP) & 1)
475#define msr_me ((env->msr >> MSR_ME) & 1)
476#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
477#define msr_se ((env->msr >> MSR_SE) & 1)
478#define msr_dwe ((env->msr >> MSR_DWE) & 1)
479#define msr_uble ((env->msr >> MSR_UBLE) & 1)
480#define msr_be ((env->msr >> MSR_BE) & 1)
481#define msr_de ((env->msr >> MSR_DE) & 1)
482#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
483#define msr_al ((env->msr >> MSR_AL) & 1)
484#define msr_ep ((env->msr >> MSR_EP) & 1)
485#define msr_ir ((env->msr >> MSR_IR) & 1)
486#define msr_dr ((env->msr >> MSR_DR) & 1)
487#define msr_pe ((env->msr >> MSR_PE) & 1)
488#define msr_px ((env->msr >> MSR_PX) & 1)
489#define msr_pmm ((env->msr >> MSR_PMM) & 1)
490#define msr_ri ((env->msr >> MSR_RI) & 1)
491#define msr_le ((env->msr >> MSR_LE) & 1)
a4f30719
JM		 492/* Hypervisor bit is more specific */
493#if defined(TARGET_PPC64)
494#define MSR_HVB (1ULL << MSR_SHV)
495#define msr_hv msr_shv
496#else
497#if defined(PPC_EMULATE_32BITS_HYPV)
498#define MSR_HVB (1ULL << MSR_THV)
499#define msr_hv msr_thv
a4f30719
JM		 500#else
501#define MSR_HVB (0ULL)
502#define msr_hv (0)
503#endif
504#endif
79aceca5 505
a586e548
EI		 506/* Exception state register bits definition */
507#define ESR_ST 23 /* Exception was caused by a store type access. */
508
d26bfc9a 509enum {
4018bae9 510 POWERPC_FLAG_NONE = 0x00000000,
d26bfc9a 511 /* Flag for MSR bit 25 signification (VRE/SPE) */
4018bae9
JM		 512 POWERPC_FLAG_SPE = 0x00000001,
513 POWERPC_FLAG_VRE = 0x00000002,
d26bfc9a 514 /* Flag for MSR bit 17 signification (TGPR/CE) */
4018bae9
JM		 515 POWERPC_FLAG_TGPR = 0x00000004,
516 POWERPC_FLAG_CE = 0x00000008,
d26bfc9a 517 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
4018bae9
JM		 518 POWERPC_FLAG_SE = 0x00000010,
519 POWERPC_FLAG_DWE = 0x00000020,
520 POWERPC_FLAG_UBLE = 0x00000040,
d26bfc9a 521 /* Flag for MSR bit 9 signification (BE/DE) */
4018bae9
JM		 522 POWERPC_FLAG_BE = 0x00000080,
523 POWERPC_FLAG_DE = 0x00000100,
a4f30719 524 /* Flag for MSR bit 2 signification (PX/PMM) */
4018bae9
JM		 525 POWERPC_FLAG_PX = 0x00000200,
526 POWERPC_FLAG_PMM = 0x00000400,
527 /* Flag for special features */
528 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
529 POWERPC_FLAG_RTC_CLK = 0x00010000,
530 POWERPC_FLAG_BUS_CLK = 0x00020000,
d26bfc9a
JM		 531};
532
7c58044c
JM		 533/*****************************************************************************/
534/* Floating point status and control register */
535#define FPSCR_FX 31 /* Floating-point exception summary */
536#define FPSCR_FEX 30 /* Floating-point enabled exception summary */
537#define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
538#define FPSCR_OX 28 /* Floating-point overflow exception */
539#define FPSCR_UX 27 /* Floating-point underflow exception */
540#define FPSCR_ZX 26 /* Floating-point zero divide exception */
541#define FPSCR_XX 25 /* Floating-point inexact exception */
542#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
543#define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
544#define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
545#define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
546#define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
547#define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
548#define FPSCR_FR 18 /* Floating-point fraction rounded */
549#define FPSCR_FI 17 /* Floating-point fraction inexact */
550#define FPSCR_C 16 /* Floating-point result class descriptor */
551#define FPSCR_FL 15 /* Floating-point less than or negative */
552#define FPSCR_FG 14 /* Floating-point greater than or negative */
553#define FPSCR_FE 13 /* Floating-point equal or zero */
554#define FPSCR_FU 12 /* Floating-point unordered or NaN */
555#define FPSCR_FPCC 12 /* Floating-point condition code */
556#define FPSCR_FPRF 12 /* Floating-point result flags */
557#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
558#define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
559#define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
560#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
561#define FPSCR_OE 6 /* Floating-point overflow exception enable */
562#define FPSCR_UE 5 /* Floating-point undeflow exception enable */
563#define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
564#define FPSCR_XE 3 /* Floating-point inexact exception enable */
565#define FPSCR_NI 2 /* Floating-point non-IEEE mode */
566#define FPSCR_RN1 1
567#define FPSCR_RN 0 /* Floating-point rounding control */
568#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
569#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
570#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
571#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
572#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
573#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
574#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
575#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
576#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
577#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
578#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
579#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
580#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
581#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
582#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
583#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
584#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
585#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
586#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
587#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
588#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
589#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
590#define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
591/* Invalid operation exception summary */
592#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
593 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
594 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
595 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
596 (1 << FPSCR_VXCVI)))
597/* exception summary */
598#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
599/* enabled exception summary */
600#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
601 0x1F)
602
603/*****************************************************************************/
6fa724a3
AJ		 604/* Vector status and control register */
605#define VSCR_NJ 16 /* Vector non-java */
606#define VSCR_SAT 0 /* Vector saturation */
607#define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
608#define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
609
01662f3e
AG		 610/*****************************************************************************/
611/* BookE e500 MMU registers */
612
613#define MAS0_NV_SHIFT 0
614#define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
615
616#define MAS0_WQ_SHIFT 12
617#define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
618/* Write TLB entry regardless of reservation */
619#define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
620/* Write TLB entry only already in use */
621#define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
622/* Clear TLB entry */
623#define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
624
625#define MAS0_HES_SHIFT 14
626#define MAS0_HES (1 << MAS0_HES_SHIFT)
627
628#define MAS0_ESEL_SHIFT 16
629#define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
630
631#define MAS0_TLBSEL_SHIFT 28
632#define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
633#define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
634#define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
635#define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
636#define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
637
638#define MAS0_ATSEL_SHIFT 31
639#define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
640#define MAS0_ATSEL_TLB 0
641#define MAS0_ATSEL_LRAT MAS0_ATSEL
642
643#define MAS1_TSIZE_SHIFT 8
644#define MAS1_TSIZE_MASK (0xf << MAS1_TSIZE_SHIFT)
645
646#define MAS1_TS_SHIFT 12
647#define MAS1_TS (1 << MAS1_TS_SHIFT)
648
649#define MAS1_IND_SHIFT 13
650#define MAS1_IND (1 << MAS1_IND_SHIFT)
651
652#define MAS1_TID_SHIFT 16
653#define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
654
655#define MAS1_IPROT_SHIFT 30
656#define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
657
658#define MAS1_VALID_SHIFT 31
659#define MAS1_VALID 0x80000000
660
661#define MAS2_EPN_SHIFT 12
662#define MAS2_EPN_MASK (0xfffff << MAS2_EPN_SHIFT)
663
664#define MAS2_ACM_SHIFT 6
665#define MAS2_ACM (1 << MAS2_ACM_SHIFT)
666
667#define MAS2_VLE_SHIFT 5
668#define MAS2_VLE (1 << MAS2_VLE_SHIFT)
669
670#define MAS2_W_SHIFT 4
671#define MAS2_W (1 << MAS2_W_SHIFT)
672
673#define MAS2_I_SHIFT 3
674#define MAS2_I (1 << MAS2_I_SHIFT)
675
676#define MAS2_M_SHIFT 2
677#define MAS2_M (1 << MAS2_M_SHIFT)
678
679#define MAS2_G_SHIFT 1
680#define MAS2_G (1 << MAS2_G_SHIFT)
681
682#define MAS2_E_SHIFT 0
683#define MAS2_E (1 << MAS2_E_SHIFT)
684
685#define MAS3_RPN_SHIFT 12
686#define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
687
688#define MAS3_U0 0x00000200
689#define MAS3_U1 0x00000100
690#define MAS3_U2 0x00000080
691#define MAS3_U3 0x00000040
692#define MAS3_UX 0x00000020
693#define MAS3_SX 0x00000010
694#define MAS3_UW 0x00000008
695#define MAS3_SW 0x00000004
696#define MAS3_UR 0x00000002
697#define MAS3_SR 0x00000001
698#define MAS3_SPSIZE_SHIFT 1
699#define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
700
701#define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
702#define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
703#define MAS4_TIDSELD_MASK 0x00030000
704#define MAS4_TIDSELD_PID0 0x00000000
705#define MAS4_TIDSELD_PID1 0x00010000
706#define MAS4_TIDSELD_PID2 0x00020000
707#define MAS4_TIDSELD_PIDZ 0x00030000
708#define MAS4_INDD 0x00008000 /* Default IND */
709#define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
710#define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
711#define MAS4_ACMD 0x00000040
712#define MAS4_VLED 0x00000020
713#define MAS4_WD 0x00000010
714#define MAS4_ID 0x00000008
715#define MAS4_MD 0x00000004
716#define MAS4_GD 0x00000002
717#define MAS4_ED 0x00000001
718#define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
719#define MAS4_WIMGED_SHIFT 0
720
721#define MAS5_SGS 0x80000000
722#define MAS5_SLPID_MASK 0x00000fff
723
724#define MAS6_SPID0 0x3fff0000
725#define MAS6_SPID1 0x00007ffe
726#define MAS6_ISIZE(x) MAS1_TSIZE(x)
727#define MAS6_SAS 0x00000001
728#define MAS6_SPID MAS6_SPID0
729#define MAS6_SIND 0x00000002 /* Indirect page */
730#define MAS6_SIND_SHIFT 1
731#define MAS6_SPID_MASK 0x3fff0000
732#define MAS6_SPID_SHIFT 16
733#define MAS6_ISIZE_MASK 0x00000f80
734#define MAS6_ISIZE_SHIFT 7
735
736#define MAS7_RPN 0xffffffff
737
738#define MAS8_TGS 0x80000000
739#define MAS8_VF 0x40000000
740#define MAS8_TLBPID 0x00000fff
741
742/* Bit definitions for MMUCFG */
743#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
744#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
745#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
746#define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
747#define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
748#define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
749#define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
750#define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
751#define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
752
753/* Bit definitions for MMUCSR0 */
754#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
755#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
756#define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
757#define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
758#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
759 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
760#define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
761#define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
762#define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
763#define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
764
765/* TLBnCFG encoding */
766#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
767#define TLBnCFG_HES 0x00002000 /* HW select supported */
768#define TLBnCFG_AVAIL 0x00004000 /* variable page size */
769#define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
770#define TLBnCFG_GTWE 0x00010000 /* Guest can write */
771#define TLBnCFG_IND 0x00020000 /* IND entries supported */
772#define TLBnCFG_PT 0x00040000 /* Can load from page table */
773#define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
774#define TLBnCFG_MINSIZE_SHIFT 20
775#define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
776#define TLBnCFG_MAXSIZE_SHIFT 16
777#define TLBnCFG_ASSOC 0xff000000 /* Associativity */
778#define TLBnCFG_ASSOC_SHIFT 24
779
780/* TLBnPS encoding */
781#define TLBnPS_4K 0x00000004
782#define TLBnPS_8K 0x00000008
783#define TLBnPS_16K 0x00000010
784#define TLBnPS_32K 0x00000020
785#define TLBnPS_64K 0x00000040
786#define TLBnPS_128K 0x00000080
787#define TLBnPS_256K 0x00000100
788#define TLBnPS_512K 0x00000200
789#define TLBnPS_1M 0x00000400
790#define TLBnPS_2M 0x00000800
791#define TLBnPS_4M 0x00001000
792#define TLBnPS_8M 0x00002000
793#define TLBnPS_16M 0x00004000
794#define TLBnPS_32M 0x00008000
795#define TLBnPS_64M 0x00010000
796#define TLBnPS_128M 0x00020000
797#define TLBnPS_256M 0x00040000
798#define TLBnPS_512M 0x00080000
799#define TLBnPS_1G 0x00100000
800#define TLBnPS_2G 0x00200000
801#define TLBnPS_4G 0x00400000
802#define TLBnPS_8G 0x00800000
803#define TLBnPS_16G 0x01000000
804#define TLBnPS_32G 0x02000000
805#define TLBnPS_64G 0x04000000
806#define TLBnPS_128G 0x08000000
807#define TLBnPS_256G 0x10000000
808
809/* tlbilx action encoding */
810#define TLBILX_T_ALL 0
811#define TLBILX_T_TID 1
812#define TLBILX_T_FULLMATCH 3
813#define TLBILX_T_CLASS0 4
814#define TLBILX_T_CLASS1 5
815#define TLBILX_T_CLASS2 6
816#define TLBILX_T_CLASS3 7
817
818/* BookE 2.06 helper defines */
819
820#define BOOKE206_FLUSH_TLB0 (1 << 0)
821#define BOOKE206_FLUSH_TLB1 (1 << 1)
822#define BOOKE206_FLUSH_TLB2 (1 << 2)
823#define BOOKE206_FLUSH_TLB3 (1 << 3)
824
825/* number of possible TLBs */
826#define BOOKE206_MAX_TLBN 4
827
6fa724a3 828/*****************************************************************************/
7c58044c 829/* The whole PowerPC CPU context */
6ebbf390 830#define NB_MMU_MODES 3
6ebbf390 831
3fc6c082
FB		 832struct CPUPPCState {
833 /* First are the most commonly used resources
834 * during translated code execution
835 */
79aceca5 836 /* general purpose registers */
bd7d9a6d 837 target_ulong gpr[32];
65d6c0f3 838#if !defined(TARGET_PPC64)
3cd7d1dd 839 /* Storage for GPR MSB, used by the SPE extension */
bd7d9a6d 840 target_ulong gprh[32];
3cd7d1dd 841#endif
3fc6c082
FB		 842 /* LR */
843 target_ulong lr;
844 /* CTR */
845 target_ulong ctr;
846 /* condition register */
47e4661c 847 uint32_t crf[8];
79aceca5 848 /* XER */
3d7b417e 849 target_ulong xer;
79aceca5 850 /* Reservation address */
18b21a2f
NF		 851 target_ulong reserve_addr;
852 /* Reservation value */
853 target_ulong reserve_val;
4425265b
NF		 854 /* Reservation store address */
855 target_ulong reserve_ea;
856 /* Reserved store source register and size */
857 target_ulong reserve_info;
3fc6c082
FB		 858
859 /* Those ones are used in supervisor mode only */
79aceca5 860 /* machine state register */
0411a972 861 target_ulong msr;
3fc6c082 862 /* temporary general purpose registers */
bd7d9a6d 863 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
3fc6c082
FB		 864
865 /* Floating point execution context */
4ecc3190 866 float_status fp_status;
3fc6c082
FB		 867 /* floating point registers */
868 float64 fpr[32];
869 /* floating point status and control register */
7c58044c 870 uint32_t fpscr;
4ecc3190 871
cb2dbfc3
AJ		 872 /* Next instruction pointer */
873 target_ulong nip;
a316d335 874
ac9eb073
FB		 875 int access_type; /* when a memory exception occurs, the access
876 type is stored here */
a541f297 877
cb2dbfc3
AJ		 878 CPU_COMMON
879
f2e63a42
JM		 880 /* MMU context - only relevant for full system emulation */
881#if !defined(CONFIG_USER_ONLY)
882#if defined(TARGET_PPC64)
3fc6c082
FB		 883 /* Address space register */
884 target_ulong asr;
f2e63a42 885 /* PowerPC 64 SLB area */
c227f099 886 ppc_slb_t slb[64];
f2e63a42
JM		 887 int slb_nr;
888#endif
3fc6c082 889 /* segment registers */
bb593904
DG		 890 target_phys_addr_t htab_base;
891 target_phys_addr_t htab_mask;
74d37793 892 target_ulong sr[32];
f43e3525
DG		 893 /* externally stored hash table */
894 uint8_t *external_htab;
3fc6c082
FB		 895 /* BATs */
896 int nb_BATs;
897 target_ulong DBAT[2][8];
898 target_ulong IBAT[2][8];
01662f3e 899 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
f2e63a42
JM		 900 int nb_tlb; /* Total number of TLB */
901 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
902 int nb_ways; /* Number of ways in the TLB set */
903 int last_way; /* Last used way used to allocate TLB in a LRU way */
904 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
905 int nb_pids; /* Number of available PID registers */
c227f099 906 ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
f2e63a42
JM		 907 /* 403 dedicated access protection registers */
908 target_ulong pb[4];
909#endif
9fddaa0c 910
3fc6c082
FB		 911 /* Other registers */
912 /* Special purpose registers */
913 target_ulong spr[1024];
c227f099 914 ppc_spr_t spr_cb[1024];
3fc6c082 915 /* Altivec registers */
c227f099 916 ppc_avr_t avr[32];
3fc6c082 917 uint32_t vscr;
d9bce9d9 918 /* SPE registers */
2231ef10 919 uint64_t spe_acc;
d9bce9d9 920 uint32_t spe_fscr;
fbd265b6
AJ		 921 /* SPE and Altivec can share a status since they will never be used
922 * simultaneously */
923 float_status vec_status;
3fc6c082
FB		 924
925 /* Internal devices resources */
9fddaa0c 926 /* Time base and decrementer */
c227f099 927 ppc_tb_t *tb_env;
3fc6c082 928 /* Device control registers */
c227f099 929 ppc_dcr_t *dcr_env;
3fc6c082 930
d63001d1
JM		 931 int dcache_line_size;
932 int icache_line_size;
933
3fc6c082
FB		 934 /* Those resources are used during exception processing */
935 /* CPU model definition */
a750fc0b 936 target_ulong msr_mask;
c227f099
AL		 937 powerpc_mmu_t mmu_model;
938 powerpc_excp_t excp_model;
939 powerpc_input_t bus_model;
237c0af0 940 int bfd_mach;
3fc6c082 941 uint32_t flags;
c29b735c 942 uint64_t insns_flags;
a5858d7a 943 uint64_t insns_flags2;
3fc6c082 944
ed120055
DG		 945#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
946 target_phys_addr_t vpa;
947 target_phys_addr_t slb_shadow;
948 target_phys_addr_t dispatch_trace_log;
949 uint32_t dtl_size;
950#endif /* TARGET_PPC64 */
951
3fc6c082 952 int error_code;
47103572 953 uint32_t pending_interrupts;
e9df014c
JM		 954#if !defined(CONFIG_USER_ONLY)
955 /* This is the IRQ controller, which is implementation dependant
956 * and only relevant when emulating a complete machine.
957 */
958 uint32_t irq_input_state;
959 void **irq_inputs;
e1833e1f
JM		 960 /* Exception vectors */
961 target_ulong excp_vectors[POWERPC_EXCP_NB];
962 target_ulong excp_prefix;
fc1c67bc 963 target_ulong hreset_excp_prefix;
e1833e1f
JM		 964 target_ulong ivor_mask;
965 target_ulong ivpr_mask;
d63001d1 966 target_ulong hreset_vector;
e9df014c 967#endif
3fc6c082
FB		 968
969 /* Those resources are used only during code translation */
3fc6c082 970 /* opcode handlers */
c227f099 971 opc_handler_t *opcodes[0x40];
3fc6c082
FB		 972
973 /* Those resources are used only in Qemu core */
056401ea
JM		 974 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
975 target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
6ebbf390 976 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
3fc6c082 977
9fddaa0c
FB		 978 /* Power management */
979 int power_mode;
cd346349 980 int (*check_pow)(CPUPPCState *env);
a541f297 981
2c50e26e
EI		 982#if !defined(CONFIG_USER_ONLY)
983 void *load_info; /* Holds boot loading state. */
984#endif
3fc6c082 985};
79aceca5 986
3c7b48b7 987#if !defined(CONFIG_USER_ONLY)
76a66253 988/* Context used internally during MMU translations */
c227f099
AL		 989typedef struct mmu_ctx_t mmu_ctx_t;
990struct mmu_ctx_t {
991 target_phys_addr_t raddr; /* Real address */
992 target_phys_addr_t eaddr; /* Effective address */
76a66253 993 int prot; /* Protection bits */
fda6a0ec 994 target_phys_addr_t hash[2]; /* Pagetable hash values */
76a66253
JM		 995 target_ulong ptem; /* Virtual segment ID | API */
996 int key; /* Access key */
b227a8e9 997 int nx; /* Non-execute area */
76a66253 998};
3c7b48b7 999#endif
76a66253 1000
3fc6c082 1001/*****************************************************************************/
aaed909a 1002CPUPPCState *cpu_ppc_init (const char *cpu_model);
2e70f6ef 1003void ppc_translate_init(void);
36081602
JM		 1004int cpu_ppc_exec (CPUPPCState *s);
1005void cpu_ppc_close (CPUPPCState *s);
79aceca5
FB		 1006/* you can call this signal handler from your SIGBUS and SIGSEGV
1007 signal handlers to inform the virtual CPU of exceptions. non zero
1008 is returned if the signal was handled by the virtual CPU. */
36081602
JM		 1009int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1010 void *puc);
93220573
AJ		 1011int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
1012 int mmu_idx, int is_softmmu);
0b5c1ce8 1013#define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
3c7b48b7 1014#if !defined(CONFIG_USER_ONLY)
c227f099 1015int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,
93220573 1016 int rw, int access_type);
3c7b48b7 1017#endif
a541f297 1018void do_interrupt (CPUPPCState *env);
e9df014c 1019void ppc_hw_interrupt (CPUPPCState *env);
a541f297 1020
93220573 1021void cpu_dump_rfi (target_ulong RA, target_ulong msr);
a541f297 1022
76a66253 1023#if !defined(CONFIG_USER_ONLY)
93220573
AJ		 1024void ppc6xx_tlb_store (CPUPPCState *env, target_ulong EPN, int way, int is_code,
1025 target_ulong pte0, target_ulong pte1);
45d827d2
AJ		 1026void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
1027void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
1028void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
1029void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
1030void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);
1031void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);
1032void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
d9bce9d9 1033#if defined(TARGET_PPC64)
d9bce9d9 1034void ppc_store_asr (CPUPPCState *env, target_ulong value);
12de9a39 1035target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
f6b868fc 1036target_ulong ppc_load_sr (CPUPPCState *env, int sr_nr);
81762d6d 1037int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
efdef95f
DG		 1038int ppc_load_slb_esid (CPUPPCState *env, target_ulong rb, target_ulong *rt);
1039int ppc_load_slb_vsid (CPUPPCState *env, target_ulong rb, target_ulong *rt);
12de9a39 1040#endif /* defined(TARGET_PPC64) */
45d827d2 1041void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value);
12de9a39 1042#endif /* !defined(CONFIG_USER_ONLY) */
0411a972 1043void ppc_store_msr (CPUPPCState *env, target_ulong value);
3fc6c082 1044
9a78eead 1045void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
aaed909a 1046
c227f099
AL		 1047const ppc_def_t *cpu_ppc_find_by_name (const char *name);
1048int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
85c4adf6 1049
9fddaa0c
FB		 1050/* Time-base and decrementer management */
1051#ifndef NO_CPU_IO_DEFS
e3ea6529 1052uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
9fddaa0c
FB		 1053uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1054void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1055void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
b711de95 1056uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
a062e36c
JM		 1057uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1058void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1059void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
9fddaa0c
FB		 1060uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1061void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
58a7d328
JM		 1062uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1063void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1064uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1065void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
d9bce9d9
JM		 1066uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1067uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1068#if !defined(CONFIG_USER_ONLY)
1069void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1070void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1071target_ulong load_40x_pit (CPUPPCState *env);
1072void store_40x_pit (CPUPPCState *env, target_ulong val);
8ecc7913 1073void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
c294fc58 1074void store_40x_sler (CPUPPCState *env, uint32_t val);
d9bce9d9
JM		 1075void store_booke_tcr (CPUPPCState *env, target_ulong val);
1076void store_booke_tsr (CPUPPCState *env, target_ulong val);
01662f3e
AG		 1077void booke206_flush_tlb(CPUState *env, int flags, const int check_iprot);
1078int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb,
1079 target_phys_addr_t *raddrp, target_ulong address,
1080 uint32_t pid, int ext, int i);
0a032cbe 1081void ppc_tlb_invalidate_all (CPUPPCState *env);
daf4f96e
JM		 1082void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1083#if defined(TARGET_PPC64)
1084void ppc_slb_invalidate_all (CPUPPCState *env);
1085void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
1086#endif
36081602 1087int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
d9bce9d9 1088#endif
9fddaa0c 1089#endif
79aceca5 1090
636aa200 1091static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
6b542af7
JM		 1092{
1093 uint64_t gprv;
1094
1095 gprv = env->gpr[gprn];
1096#if !defined(TARGET_PPC64)
1097 if (env->flags & POWERPC_FLAG_SPE) {
1098 /* If the CPU implements the SPE extension, we have to get the
1099 * high bits of the GPR from the gprh storage area
1100 */
1101 gprv &= 0xFFFFFFFFULL;
1102 gprv |= (uint64_t)env->gprh[gprn] << 32;
1103 }
1104#endif
1105
1106 return gprv;
1107}
1108
2e719ba3 1109/* Device control registers */
73b01960
AG		 1110int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1111int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
2e719ba3 1112
9467d44c
TS		 1113#define cpu_init cpu_ppc_init
1114#define cpu_exec cpu_ppc_exec
1115#define cpu_gen_code cpu_ppc_gen_code
1116#define cpu_signal_handler cpu_ppc_signal_handler
c732abe2 1117#define cpu_list ppc_cpu_list
9467d44c 1118
fc1c67bc 1119#define CPU_SAVE_VERSION 4
b3c7724c 1120
6ebbf390
JM		 1121/* MMU modes definitions */
1122#define MMU_MODE0_SUFFIX _user
1123#define MMU_MODE1_SUFFIX _kernel
6ebbf390 1124#define MMU_MODE2_SUFFIX _hypv
6ebbf390
JM		 1125#define MMU_USER_IDX 0
1126static inline int cpu_mmu_index (CPUState *env)
1127{
1128 return env->mmu_idx;
1129}
1130
6e68e076
PB		 1131#if defined(CONFIG_USER_ONLY)
1132static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
1133{
f8ed7070 1134 if (newsp)
6e68e076 1135 env->gpr[1] = newsp;
d11f69b2 1136 env->gpr[3] = 0;
6e68e076
PB		 1137}
1138#endif
1139
79aceca5
FB		 1140#include "cpu-all.h"
1141
3fc6c082 1142/*****************************************************************************/
e1571908 1143/* CRF definitions */
57951c27
AJ		 1144#define CRF_LT 3
1145#define CRF_GT 2
1146#define CRF_EQ 1
1147#define CRF_SO 0
e6bba2ef
NF		 1148#define CRF_CH (1 << CRF_LT)
1149#define CRF_CL (1 << CRF_GT)
1150#define CRF_CH_OR_CL (1 << CRF_EQ)
1151#define CRF_CH_AND_CL (1 << CRF_SO)
e1571908
AJ		 1152
1153/* XER definitions */
3d7b417e
AJ		 1154#define XER_SO 31
1155#define XER_OV 30
1156#define XER_CA 29
1157#define XER_CMP 8
1158#define XER_BC 0
1159#define xer_so ((env->xer >> XER_SO) & 1)
1160#define xer_ov ((env->xer >> XER_OV) & 1)
1161#define xer_ca ((env->xer >> XER_CA) & 1)
1162#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1163#define xer_bc ((env->xer >> XER_BC) & 0x7F)
79aceca5 1164
3fc6c082 1165/* SPR definitions */
80d11f44
JM		 1166#define SPR_MQ (0x000)
1167#define SPR_XER (0x001)
1168#define SPR_601_VRTCU (0x004)
1169#define SPR_601_VRTCL (0x005)
1170#define SPR_601_UDECR (0x006)
1171#define SPR_LR (0x008)
1172#define SPR_CTR (0x009)
1173#define SPR_DSISR (0x012)
1174#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1175#define SPR_601_RTCU (0x014)
1176#define SPR_601_RTCL (0x015)
1177#define SPR_DECR (0x016)
1178#define SPR_SDR1 (0x019)
1179#define SPR_SRR0 (0x01A)
1180#define SPR_SRR1 (0x01B)
1181#define SPR_AMR (0x01D)
1182#define SPR_BOOKE_PID (0x030)
1183#define SPR_BOOKE_DECAR (0x036)
1184#define SPR_BOOKE_CSRR0 (0x03A)
1185#define SPR_BOOKE_CSRR1 (0x03B)
1186#define SPR_BOOKE_DEAR (0x03D)
1187#define SPR_BOOKE_ESR (0x03E)
1188#define SPR_BOOKE_IVPR (0x03F)
1189#define SPR_MPC_EIE (0x050)
1190#define SPR_MPC_EID (0x051)
1191#define SPR_MPC_NRI (0x052)
1192#define SPR_CTRL (0x088)
1193#define SPR_MPC_CMPA (0x090)
1194#define SPR_MPC_CMPB (0x091)
1195#define SPR_MPC_CMPC (0x092)
1196#define SPR_MPC_CMPD (0x093)
1197#define SPR_MPC_ECR (0x094)
1198#define SPR_MPC_DER (0x095)
1199#define SPR_MPC_COUNTA (0x096)
1200#define SPR_MPC_COUNTB (0x097)
1201#define SPR_UCTRL (0x098)
1202#define SPR_MPC_CMPE (0x098)
1203#define SPR_MPC_CMPF (0x099)
1204#define SPR_MPC_CMPG (0x09A)
1205#define SPR_MPC_CMPH (0x09B)
1206#define SPR_MPC_LCTRL1 (0x09C)
1207#define SPR_MPC_LCTRL2 (0x09D)
1208#define SPR_MPC_ICTRL (0x09E)
1209#define SPR_MPC_BAR (0x09F)
1210#define SPR_VRSAVE (0x100)
1211#define SPR_USPRG0 (0x100)
1212#define SPR_USPRG1 (0x101)
1213#define SPR_USPRG2 (0x102)
1214#define SPR_USPRG3 (0x103)
1215#define SPR_USPRG4 (0x104)
1216#define SPR_USPRG5 (0x105)
1217#define SPR_USPRG6 (0x106)
1218#define SPR_USPRG7 (0x107)
1219#define SPR_VTBL (0x10C)
1220#define SPR_VTBU (0x10D)
1221#define SPR_SPRG0 (0x110)
1222#define SPR_SPRG1 (0x111)
1223#define SPR_SPRG2 (0x112)
1224#define SPR_SPRG3 (0x113)
1225#define SPR_SPRG4 (0x114)
1226#define SPR_SCOMC (0x114)
1227#define SPR_SPRG5 (0x115)
1228#define SPR_SCOMD (0x115)
1229#define SPR_SPRG6 (0x116)
1230#define SPR_SPRG7 (0x117)
1231#define SPR_ASR (0x118)
1232#define SPR_EAR (0x11A)
1233#define SPR_TBL (0x11C)
1234#define SPR_TBU (0x11D)
1235#define SPR_TBU40 (0x11E)
1236#define SPR_SVR (0x11E)
1237#define SPR_BOOKE_PIR (0x11E)
1238#define SPR_PVR (0x11F)
1239#define SPR_HSPRG0 (0x130)
1240#define SPR_BOOKE_DBSR (0x130)
1241#define SPR_HSPRG1 (0x131)
1242#define SPR_HDSISR (0x132)
1243#define SPR_HDAR (0x133)
90dc8812 1244#define SPR_BOOKE_EPCR (0x133)
9d52e907 1245#define SPR_SPURR (0x134)
80d11f44
JM		 1246#define SPR_BOOKE_DBCR0 (0x134)
1247#define SPR_IBCR (0x135)
1248#define SPR_PURR (0x135)
1249#define SPR_BOOKE_DBCR1 (0x135)
1250#define SPR_DBCR (0x136)
1251#define SPR_HDEC (0x136)
1252#define SPR_BOOKE_DBCR2 (0x136)
1253#define SPR_HIOR (0x137)
1254#define SPR_MBAR (0x137)
1255#define SPR_RMOR (0x138)
1256#define SPR_BOOKE_IAC1 (0x138)
1257#define SPR_HRMOR (0x139)
1258#define SPR_BOOKE_IAC2 (0x139)
1259#define SPR_HSRR0 (0x13A)
1260#define SPR_BOOKE_IAC3 (0x13A)
1261#define SPR_HSRR1 (0x13B)
1262#define SPR_BOOKE_IAC4 (0x13B)
1263#define SPR_LPCR (0x13C)
1264#define SPR_BOOKE_DAC1 (0x13C)
1265#define SPR_LPIDR (0x13D)
1266#define SPR_DABR2 (0x13D)
1267#define SPR_BOOKE_DAC2 (0x13D)
1268#define SPR_BOOKE_DVC1 (0x13E)
1269#define SPR_BOOKE_DVC2 (0x13F)
1270#define SPR_BOOKE_TSR (0x150)
1271#define SPR_BOOKE_TCR (0x154)
1272#define SPR_BOOKE_IVOR0 (0x190)
1273#define SPR_BOOKE_IVOR1 (0x191)
1274#define SPR_BOOKE_IVOR2 (0x192)
1275#define SPR_BOOKE_IVOR3 (0x193)
1276#define SPR_BOOKE_IVOR4 (0x194)
1277#define SPR_BOOKE_IVOR5 (0x195)
1278#define SPR_BOOKE_IVOR6 (0x196)
1279#define SPR_BOOKE_IVOR7 (0x197)
1280#define SPR_BOOKE_IVOR8 (0x198)
1281#define SPR_BOOKE_IVOR9 (0x199)
1282#define SPR_BOOKE_IVOR10 (0x19A)
1283#define SPR_BOOKE_IVOR11 (0x19B)
1284#define SPR_BOOKE_IVOR12 (0x19C)
1285#define SPR_BOOKE_IVOR13 (0x19D)
1286#define SPR_BOOKE_IVOR14 (0x19E)
1287#define SPR_BOOKE_IVOR15 (0x19F)
1288#define SPR_BOOKE_SPEFSCR (0x200)
1289#define SPR_Exxx_BBEAR (0x201)
1290#define SPR_Exxx_BBTAR (0x202)
1291#define SPR_Exxx_L1CFG0 (0x203)
1292#define SPR_Exxx_NPIDR (0x205)
1293#define SPR_ATBL (0x20E)
1294#define SPR_ATBU (0x20F)
1295#define SPR_IBAT0U (0x210)
1296#define SPR_BOOKE_IVOR32 (0x210)
1297#define SPR_RCPU_MI_GRA (0x210)
1298#define SPR_IBAT0L (0x211)
1299#define SPR_BOOKE_IVOR33 (0x211)
1300#define SPR_IBAT1U (0x212)
1301#define SPR_BOOKE_IVOR34 (0x212)
1302#define SPR_IBAT1L (0x213)
1303#define SPR_BOOKE_IVOR35 (0x213)
1304#define SPR_IBAT2U (0x214)
1305#define SPR_BOOKE_IVOR36 (0x214)
1306#define SPR_IBAT2L (0x215)
1307#define SPR_BOOKE_IVOR37 (0x215)
1308#define SPR_IBAT3U (0x216)
1309#define SPR_IBAT3L (0x217)
1310#define SPR_DBAT0U (0x218)
1311#define SPR_RCPU_L2U_GRA (0x218)
1312#define SPR_DBAT0L (0x219)
1313#define SPR_DBAT1U (0x21A)
1314#define SPR_DBAT1L (0x21B)
1315#define SPR_DBAT2U (0x21C)
1316#define SPR_DBAT2L (0x21D)
1317#define SPR_DBAT3U (0x21E)
1318#define SPR_DBAT3L (0x21F)
1319#define SPR_IBAT4U (0x230)
1320#define SPR_RPCU_BBCMCR (0x230)
1321#define SPR_MPC_IC_CST (0x230)
1322#define SPR_Exxx_CTXCR (0x230)
1323#define SPR_IBAT4L (0x231)
1324#define SPR_MPC_IC_ADR (0x231)
1325#define SPR_Exxx_DBCR3 (0x231)
1326#define SPR_IBAT5U (0x232)
1327#define SPR_MPC_IC_DAT (0x232)
1328#define SPR_Exxx_DBCNT (0x232)
1329#define SPR_IBAT5L (0x233)
1330#define SPR_IBAT6U (0x234)
1331#define SPR_IBAT6L (0x235)
1332#define SPR_IBAT7U (0x236)
1333#define SPR_IBAT7L (0x237)
1334#define SPR_DBAT4U (0x238)
1335#define SPR_RCPU_L2U_MCR (0x238)
1336#define SPR_MPC_DC_CST (0x238)
1337#define SPR_Exxx_ALTCTXCR (0x238)
1338#define SPR_DBAT4L (0x239)
1339#define SPR_MPC_DC_ADR (0x239)
1340#define SPR_DBAT5U (0x23A)
1341#define SPR_BOOKE_MCSRR0 (0x23A)
1342#define SPR_MPC_DC_DAT (0x23A)
1343#define SPR_DBAT5L (0x23B)
1344#define SPR_BOOKE_MCSRR1 (0x23B)
1345#define SPR_DBAT6U (0x23C)
1346#define SPR_BOOKE_MCSR (0x23C)
1347#define SPR_DBAT6L (0x23D)
1348#define SPR_Exxx_MCAR (0x23D)
1349#define SPR_DBAT7U (0x23E)
1350#define SPR_BOOKE_DSRR0 (0x23E)
1351#define SPR_DBAT7L (0x23F)
1352#define SPR_BOOKE_DSRR1 (0x23F)
1353#define SPR_BOOKE_SPRG8 (0x25C)
1354#define SPR_BOOKE_SPRG9 (0x25D)
1355#define SPR_BOOKE_MAS0 (0x270)
1356#define SPR_BOOKE_MAS1 (0x271)
1357#define SPR_BOOKE_MAS2 (0x272)
1358#define SPR_BOOKE_MAS3 (0x273)
1359#define SPR_BOOKE_MAS4 (0x274)
1360#define SPR_BOOKE_MAS5 (0x275)
1361#define SPR_BOOKE_MAS6 (0x276)
1362#define SPR_BOOKE_PID1 (0x279)
1363#define SPR_BOOKE_PID2 (0x27A)
1364#define SPR_MPC_DPDR (0x280)
1365#define SPR_MPC_IMMR (0x288)
1366#define SPR_BOOKE_TLB0CFG (0x2B0)
1367#define SPR_BOOKE_TLB1CFG (0x2B1)
1368#define SPR_BOOKE_TLB2CFG (0x2B2)
1369#define SPR_BOOKE_TLB3CFG (0x2B3)
1370#define SPR_BOOKE_EPR (0x2BE)
1371#define SPR_PERF0 (0x300)
1372#define SPR_RCPU_MI_RBA0 (0x300)
1373#define SPR_MPC_MI_CTR (0x300)
1374#define SPR_PERF1 (0x301)
1375#define SPR_RCPU_MI_RBA1 (0x301)
1376#define SPR_PERF2 (0x302)
1377#define SPR_RCPU_MI_RBA2 (0x302)
1378#define SPR_MPC_MI_AP (0x302)
1379#define SPR_PERF3 (0x303)
082c6681 1380#define SPR_620_PMC1R (0x303)
80d11f44
JM		 1381#define SPR_RCPU_MI_RBA3 (0x303)
1382#define SPR_MPC_MI_EPN (0x303)
1383#define SPR_PERF4 (0x304)
082c6681 1384#define SPR_620_PMC2R (0x304)
80d11f44
JM		 1385#define SPR_PERF5 (0x305)
1386#define SPR_MPC_MI_TWC (0x305)
1387#define SPR_PERF6 (0x306)
1388#define SPR_MPC_MI_RPN (0x306)
1389#define SPR_PERF7 (0x307)
1390#define SPR_PERF8 (0x308)
1391#define SPR_RCPU_L2U_RBA0 (0x308)
1392#define SPR_MPC_MD_CTR (0x308)
1393#define SPR_PERF9 (0x309)
1394#define SPR_RCPU_L2U_RBA1 (0x309)
1395#define SPR_MPC_MD_CASID (0x309)
1396#define SPR_PERFA (0x30A)
1397#define SPR_RCPU_L2U_RBA2 (0x30A)
1398#define SPR_MPC_MD_AP (0x30A)
1399#define SPR_PERFB (0x30B)
082c6681 1400#define SPR_620_MMCR0R (0x30B)
80d11f44
JM		 1401#define SPR_RCPU_L2U_RBA3 (0x30B)
1402#define SPR_MPC_MD_EPN (0x30B)
1403#define SPR_PERFC (0x30C)
1404#define SPR_MPC_MD_TWB (0x30C)
1405#define SPR_PERFD (0x30D)
1406#define SPR_MPC_MD_TWC (0x30D)
1407#define SPR_PERFE (0x30E)
1408#define SPR_MPC_MD_RPN (0x30E)
1409#define SPR_PERFF (0x30F)
1410#define SPR_MPC_MD_TW (0x30F)
1411#define SPR_UPERF0 (0x310)
1412#define SPR_UPERF1 (0x311)
1413#define SPR_UPERF2 (0x312)
1414#define SPR_UPERF3 (0x313)
082c6681 1415#define SPR_620_PMC1W (0x313)
80d11f44 1416#define SPR_UPERF4 (0x314)
082c6681 1417#define SPR_620_PMC2W (0x314)
80d11f44
JM		 1418#define SPR_UPERF5 (0x315)
1419#define SPR_UPERF6 (0x316)
1420#define SPR_UPERF7 (0x317)
1421#define SPR_UPERF8 (0x318)
1422#define SPR_UPERF9 (0x319)
1423#define SPR_UPERFA (0x31A)
1424#define SPR_UPERFB (0x31B)
082c6681 1425#define SPR_620_MMCR0W (0x31B)
80d11f44
JM		 1426#define SPR_UPERFC (0x31C)
1427#define SPR_UPERFD (0x31D)
1428#define SPR_UPERFE (0x31E)
1429#define SPR_UPERFF (0x31F)
1430#define SPR_RCPU_MI_RA0 (0x320)
1431#define SPR_MPC_MI_DBCAM (0x320)
1432#define SPR_RCPU_MI_RA1 (0x321)
1433#define SPR_MPC_MI_DBRAM0 (0x321)
1434#define SPR_RCPU_MI_RA2 (0x322)
1435#define SPR_MPC_MI_DBRAM1 (0x322)
1436#define SPR_RCPU_MI_RA3 (0x323)
1437#define SPR_RCPU_L2U_RA0 (0x328)
1438#define SPR_MPC_MD_DBCAM (0x328)
1439#define SPR_RCPU_L2U_RA1 (0x329)
1440#define SPR_MPC_MD_DBRAM0 (0x329)
1441#define SPR_RCPU_L2U_RA2 (0x32A)
1442#define SPR_MPC_MD_DBRAM1 (0x32A)
1443#define SPR_RCPU_L2U_RA3 (0x32B)
1444#define SPR_440_INV0 (0x370)
1445#define SPR_440_INV1 (0x371)
1446#define SPR_440_INV2 (0x372)
1447#define SPR_440_INV3 (0x373)
1448#define SPR_440_ITV0 (0x374)
1449#define SPR_440_ITV1 (0x375)
1450#define SPR_440_ITV2 (0x376)
1451#define SPR_440_ITV3 (0x377)
1452#define SPR_440_CCR1 (0x378)
1453#define SPR_DCRIPR (0x37B)
1454#define SPR_PPR (0x380)
bd928eba 1455#define SPR_750_GQR0 (0x390)
80d11f44 1456#define SPR_440_DNV0 (0x390)
bd928eba 1457#define SPR_750_GQR1 (0x391)
80d11f44 1458#define SPR_440_DNV1 (0x391)
bd928eba 1459#define SPR_750_GQR2 (0x392)
80d11f44 1460#define SPR_440_DNV2 (0x392)
bd928eba 1461#define SPR_750_GQR3 (0x393)
80d11f44 1462#define SPR_440_DNV3 (0x393)
bd928eba 1463#define SPR_750_GQR4 (0x394)
80d11f44 1464#define SPR_440_DTV0 (0x394)
bd928eba 1465#define SPR_750_GQR5 (0x395)
80d11f44 1466#define SPR_440_DTV1 (0x395)
bd928eba 1467#define SPR_750_GQR6 (0x396)
80d11f44 1468#define SPR_440_DTV2 (0x396)
bd928eba 1469#define SPR_750_GQR7 (0x397)
80d11f44 1470#define SPR_440_DTV3 (0x397)
bd928eba
JM		 1471#define SPR_750_THRM4 (0x398)
1472#define SPR_750CL_HID2 (0x398)
80d11f44 1473#define SPR_440_DVLIM (0x398)
bd928eba 1474#define SPR_750_WPAR (0x399)
80d11f44 1475#define SPR_440_IVLIM (0x399)
bd928eba
JM		 1476#define SPR_750_DMAU (0x39A)
1477#define SPR_750_DMAL (0x39B)
80d11f44
JM		 1478#define SPR_440_RSTCFG (0x39B)
1479#define SPR_BOOKE_DCDBTRL (0x39C)
1480#define SPR_BOOKE_DCDBTRH (0x39D)
1481#define SPR_BOOKE_ICDBTRL (0x39E)
1482#define SPR_BOOKE_ICDBTRH (0x39F)
1483#define SPR_UMMCR2 (0x3A0)
1484#define SPR_UPMC5 (0x3A1)
1485#define SPR_UPMC6 (0x3A2)
1486#define SPR_UBAMR (0x3A7)
1487#define SPR_UMMCR0 (0x3A8)
1488#define SPR_UPMC1 (0x3A9)
1489#define SPR_UPMC2 (0x3AA)
1490#define SPR_USIAR (0x3AB)
1491#define SPR_UMMCR1 (0x3AC)
1492#define SPR_UPMC3 (0x3AD)
1493#define SPR_UPMC4 (0x3AE)
1494#define SPR_USDA (0x3AF)
1495#define SPR_40x_ZPR (0x3B0)
1496#define SPR_BOOKE_MAS7 (0x3B0)
1497#define SPR_620_PMR0 (0x3B0)
1498#define SPR_MMCR2 (0x3B0)
1499#define SPR_PMC5 (0x3B1)
1500#define SPR_40x_PID (0x3B1)
1501#define SPR_620_PMR1 (0x3B1)
1502#define SPR_PMC6 (0x3B2)
1503#define SPR_440_MMUCR (0x3B2)
1504#define SPR_620_PMR2 (0x3B2)
1505#define SPR_4xx_CCR0 (0x3B3)
1506#define SPR_BOOKE_EPLC (0x3B3)
1507#define SPR_620_PMR3 (0x3B3)
1508#define SPR_405_IAC3 (0x3B4)
1509#define SPR_BOOKE_EPSC (0x3B4)
1510#define SPR_620_PMR4 (0x3B4)
1511#define SPR_405_IAC4 (0x3B5)
1512#define SPR_620_PMR5 (0x3B5)
1513#define SPR_405_DVC1 (0x3B6)
1514#define SPR_620_PMR6 (0x3B6)
1515#define SPR_405_DVC2 (0x3B7)
1516#define SPR_620_PMR7 (0x3B7)
1517#define SPR_BAMR (0x3B7)
1518#define SPR_MMCR0 (0x3B8)
1519#define SPR_620_PMR8 (0x3B8)
1520#define SPR_PMC1 (0x3B9)
1521#define SPR_40x_SGR (0x3B9)
1522#define SPR_620_PMR9 (0x3B9)
1523#define SPR_PMC2 (0x3BA)
1524#define SPR_40x_DCWR (0x3BA)
1525#define SPR_620_PMRA (0x3BA)
1526#define SPR_SIAR (0x3BB)
1527#define SPR_405_SLER (0x3BB)
1528#define SPR_620_PMRB (0x3BB)
1529#define SPR_MMCR1 (0x3BC)
1530#define SPR_405_SU0R (0x3BC)
1531#define SPR_620_PMRC (0x3BC)
1532#define SPR_401_SKR (0x3BC)
1533#define SPR_PMC3 (0x3BD)
1534#define SPR_405_DBCR1 (0x3BD)
1535#define SPR_620_PMRD (0x3BD)
1536#define SPR_PMC4 (0x3BE)
1537#define SPR_620_PMRE (0x3BE)
1538#define SPR_SDA (0x3BF)
1539#define SPR_620_PMRF (0x3BF)
1540#define SPR_403_VTBL (0x3CC)
1541#define SPR_403_VTBU (0x3CD)
1542#define SPR_DMISS (0x3D0)
1543#define SPR_DCMP (0x3D1)
1544#define SPR_HASH1 (0x3D2)
1545#define SPR_HASH2 (0x3D3)
1546#define SPR_BOOKE_ICDBDR (0x3D3)
1547#define SPR_TLBMISS (0x3D4)
1548#define SPR_IMISS (0x3D4)
1549#define SPR_40x_ESR (0x3D4)
1550#define SPR_PTEHI (0x3D5)
1551#define SPR_ICMP (0x3D5)
1552#define SPR_40x_DEAR (0x3D5)
1553#define SPR_PTELO (0x3D6)
1554#define SPR_RPA (0x3D6)
1555#define SPR_40x_EVPR (0x3D6)
1556#define SPR_L3PM (0x3D7)
1557#define SPR_403_CDBCR (0x3D7)
4e777442 1558#define SPR_L3ITCR0 (0x3D8)
80d11f44
JM		 1559#define SPR_TCR (0x3D8)
1560#define SPR_40x_TSR (0x3D8)
1561#define SPR_IBR (0x3DA)
1562#define SPR_40x_TCR (0x3DA)
1563#define SPR_ESASRR (0x3DB)
1564#define SPR_40x_PIT (0x3DB)
1565#define SPR_403_TBL (0x3DC)
1566#define SPR_403_TBU (0x3DD)
1567#define SPR_SEBR (0x3DE)
1568#define SPR_40x_SRR2 (0x3DE)
1569#define SPR_SER (0x3DF)
1570#define SPR_40x_SRR3 (0x3DF)
4e777442 1571#define SPR_L3OHCR (0x3E8)
80d11f44
JM		 1572#define SPR_L3ITCR1 (0x3E9)
1573#define SPR_L3ITCR2 (0x3EA)
1574#define SPR_L3ITCR3 (0x3EB)
1575#define SPR_HID0 (0x3F0)
1576#define SPR_40x_DBSR (0x3F0)
1577#define SPR_HID1 (0x3F1)
1578#define SPR_IABR (0x3F2)
1579#define SPR_40x_DBCR0 (0x3F2)
1580#define SPR_601_HID2 (0x3F2)
1581#define SPR_Exxx_L1CSR0 (0x3F2)
1582#define SPR_ICTRL (0x3F3)
1583#define SPR_HID2 (0x3F3)
bd928eba 1584#define SPR_750CL_HID4 (0x3F3)
80d11f44
JM		 1585#define SPR_Exxx_L1CSR1 (0x3F3)
1586#define SPR_440_DBDR (0x3F3)
1587#define SPR_LDSTDB (0x3F4)
bd928eba 1588#define SPR_750_TDCL (0x3F4)
80d11f44
JM		 1589#define SPR_40x_IAC1 (0x3F4)
1590#define SPR_MMUCSR0 (0x3F4)
1591#define SPR_DABR (0x3F5)
3fc6c082 1592#define DABR_MASK (~(target_ulong)0x7)
80d11f44
JM		 1593#define SPR_Exxx_BUCSR (0x3F5)
1594#define SPR_40x_IAC2 (0x3F5)
1595#define SPR_601_HID5 (0x3F5)
1596#define SPR_40x_DAC1 (0x3F6)
1597#define SPR_MSSCR0 (0x3F6)
1598#define SPR_970_HID5 (0x3F6)
1599#define SPR_MSSSR0 (0x3F7)
4e777442 1600#define SPR_MSSCR1 (0x3F7)
80d11f44
JM		 1601#define SPR_DABRX (0x3F7)
1602#define SPR_40x_DAC2 (0x3F7)
1603#define SPR_MMUCFG (0x3F7)
1604#define SPR_LDSTCR (0x3F8)
1605#define SPR_L2PMCR (0x3F8)
bd928eba 1606#define SPR_750FX_HID2 (0x3F8)
082c6681 1607#define SPR_620_BUSCSR (0x3F8)
80d11f44
JM		 1608#define SPR_Exxx_L1FINV0 (0x3F8)
1609#define SPR_L2CR (0x3F9)
082c6681 1610#define SPR_620_L2CR (0x3F9)
80d11f44 1611#define SPR_L3CR (0x3FA)
bd928eba 1612#define SPR_750_TDCH (0x3FA)
80d11f44
JM		 1613#define SPR_IABR2 (0x3FA)
1614#define SPR_40x_DCCR (0x3FA)
082c6681 1615#define SPR_620_L2SR (0x3FA)
80d11f44
JM		 1616#define SPR_ICTC (0x3FB)
1617#define SPR_40x_ICCR (0x3FB)
1618#define SPR_THRM1 (0x3FC)
1619#define SPR_403_PBL1 (0x3FC)
1620#define SPR_SP (0x3FD)
1621#define SPR_THRM2 (0x3FD)
1622#define SPR_403_PBU1 (0x3FD)
1623#define SPR_604_HID13 (0x3FD)
1624#define SPR_LT (0x3FE)
1625#define SPR_THRM3 (0x3FE)
1626#define SPR_RCPU_FPECR (0x3FE)
1627#define SPR_403_PBL2 (0x3FE)
1628#define SPR_PIR (0x3FF)
1629#define SPR_403_PBU2 (0x3FF)
1630#define SPR_601_HID15 (0x3FF)
1631#define SPR_604_HID15 (0x3FF)
1632#define SPR_E500_SVR (0x3FF)
79aceca5 1633
c29b735c
NF		 1634/*****************************************************************************/
1635/* PowerPC Instructions types definitions */
1636enum {
1637 PPC_NONE = 0x0000000000000000ULL,
1638 /* PowerPC base instructions set */
1639 PPC_INSNS_BASE = 0x0000000000000001ULL,
1640 /* integer operations instructions */
1641#define PPC_INTEGER PPC_INSNS_BASE
1642 /* flow control instructions */
1643#define PPC_FLOW PPC_INSNS_BASE
1644 /* virtual memory instructions */
1645#define PPC_MEM PPC_INSNS_BASE
1646 /* ld/st with reservation instructions */
1647#define PPC_RES PPC_INSNS_BASE
1648 /* spr/msr access instructions */
1649#define PPC_MISC PPC_INSNS_BASE
1650 /* Deprecated instruction sets */
1651 /* Original POWER instruction set */
1652 PPC_POWER = 0x0000000000000002ULL,
1653 /* POWER2 instruction set extension */
1654 PPC_POWER2 = 0x0000000000000004ULL,
1655 /* Power RTC support */
1656 PPC_POWER_RTC = 0x0000000000000008ULL,
1657 /* Power-to-PowerPC bridge (601) */
1658 PPC_POWER_BR = 0x0000000000000010ULL,
1659 /* 64 bits PowerPC instruction set */
1660 PPC_64B = 0x0000000000000020ULL,
1661 /* New 64 bits extensions (PowerPC 2.0x) */
1662 PPC_64BX = 0x0000000000000040ULL,
1663 /* 64 bits hypervisor extensions */
1664 PPC_64H = 0x0000000000000080ULL,
1665 /* New wait instruction (PowerPC 2.0x) */
1666 PPC_WAIT = 0x0000000000000100ULL,
1667 /* Time base mftb instruction */
1668 PPC_MFTB = 0x0000000000000200ULL,
1669
1670 /* Fixed-point unit extensions */
1671 /* PowerPC 602 specific */
1672 PPC_602_SPEC = 0x0000000000000400ULL,
1673 /* isel instruction */
1674 PPC_ISEL = 0x0000000000000800ULL,
1675 /* popcntb instruction */
1676 PPC_POPCNTB = 0x0000000000001000ULL,
1677 /* string load / store */
1678 PPC_STRING = 0x0000000000002000ULL,
1679
1680 /* Floating-point unit extensions */
1681 /* Optional floating point instructions */
1682 PPC_FLOAT = 0x0000000000010000ULL,
1683 /* New floating-point extensions (PowerPC 2.0x) */
1684 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1685 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1686 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1687 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1688 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1689 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1690 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1691
1692 /* Vector/SIMD extensions */
1693 /* Altivec support */
1694 PPC_ALTIVEC = 0x0000000001000000ULL,
1695 /* PowerPC 2.03 SPE extension */
1696 PPC_SPE = 0x0000000002000000ULL,
1697 /* PowerPC 2.03 SPE single-precision floating-point extension */
1698 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1699 /* PowerPC 2.03 SPE double-precision floating-point extension */
1700 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1701
1702 /* Optional memory control instructions */
1703 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1704 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1705 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1706 /* sync instruction */
1707 PPC_MEM_SYNC = 0x0000000080000000ULL,
1708 /* eieio instruction */
1709 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1710
1711 /* Cache control instructions */
1712 PPC_CACHE = 0x0000000200000000ULL,
1713 /* icbi instruction */
1714 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1715 /* dcbz instruction with fixed cache line size */
1716 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1717 /* dcbz instruction with tunable cache line size */
1718 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1719 /* dcba instruction */
1720 PPC_CACHE_DCBA = 0x0000002000000000ULL,
1721 /* Freescale cache locking instructions */
1722 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1723
1724 /* MMU related extensions */
1725 /* external control instructions */
1726 PPC_EXTERN = 0x0000010000000000ULL,
1727 /* segment register access instructions */
1728 PPC_SEGMENT = 0x0000020000000000ULL,
1729 /* PowerPC 6xx TLB management instructions */
1730 PPC_6xx_TLB = 0x0000040000000000ULL,
1731 /* PowerPC 74xx TLB management instructions */
1732 PPC_74xx_TLB = 0x0000080000000000ULL,
1733 /* PowerPC 40x TLB management instructions */
1734 PPC_40x_TLB = 0x0000100000000000ULL,
1735 /* segment register access instructions for PowerPC 64 "bridge" */
1736 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1737 /* SLB management */
1738 PPC_SLBI = 0x0000400000000000ULL,
1739
1740 /* Embedded PowerPC dedicated instructions */
1741 PPC_WRTEE = 0x0001000000000000ULL,
1742 /* PowerPC 40x exception model */
1743 PPC_40x_EXCP = 0x0002000000000000ULL,
1744 /* PowerPC 405 Mac instructions */
1745 PPC_405_MAC = 0x0004000000000000ULL,
1746 /* PowerPC 440 specific instructions */
1747 PPC_440_SPEC = 0x0008000000000000ULL,
1748 /* BookE (embedded) PowerPC specification */
1749 PPC_BOOKE = 0x0010000000000000ULL,
1750 /* mfapidi instruction */
1751 PPC_MFAPIDI = 0x0020000000000000ULL,
1752 /* tlbiva instruction */
1753 PPC_TLBIVA = 0x0040000000000000ULL,
1754 /* tlbivax instruction */
1755 PPC_TLBIVAX = 0x0080000000000000ULL,
1756 /* PowerPC 4xx dedicated instructions */
1757 PPC_4xx_COMMON = 0x0100000000000000ULL,
1758 /* PowerPC 40x ibct instructions */
1759 PPC_40x_ICBT = 0x0200000000000000ULL,
1760 /* rfmci is not implemented in all BookE PowerPC */
1761 PPC_RFMCI = 0x0400000000000000ULL,
1762 /* rfdi instruction */
1763 PPC_RFDI = 0x0800000000000000ULL,
1764 /* DCR accesses */
1765 PPC_DCR = 0x1000000000000000ULL,
1766 /* DCR extended accesse */
1767 PPC_DCRX = 0x2000000000000000ULL,
1768 /* user-mode DCR access, implemented in PowerPC 460 */
1769 PPC_DCRUX = 0x4000000000000000ULL,
eaabeef2
DG		 1770 /* popcntw and popcntd instructions */
1771 PPC_POPCNTWD = 0x8000000000000000ULL,
01662f3e
AG		 1772
1773 /* extended type values */
1774
1775 /* BookE 2.06 PowerPC specification */
1776 PPC2_BOOKE206 = 0x0000000000000001ULL,
c29b735c
NF		 1777};
1778
76a66253 1779/*****************************************************************************/
9a64fbe4
FB		 1780/* Memory access type :
1781 * may be needed for precise access rights control and precise exceptions.
1782 */
79aceca5 1783enum {
9a64fbe4
FB		 1784 /* 1 bit to define user level / supervisor access */
1785 ACCESS_USER = 0x00,
1786 ACCESS_SUPER = 0x01,
1787 /* Type of instruction that generated the access */
1788 ACCESS_CODE = 0x10, /* Code fetch access */
1789 ACCESS_INT = 0x20, /* Integer load/store access */
1790 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1791 ACCESS_RES = 0x40, /* load/store with reservation */
1792 ACCESS_EXT = 0x50, /* external access */
1793 ACCESS_CACHE = 0x60, /* Cache manipulation */
1794};
1795
47103572
JM		 1796/* Hardware interruption sources:
1797 * all those exception can be raised simulteaneously
1798 */
e9df014c
JM		 1799/* Input pins definitions */
1800enum {
1801 /* 6xx bus input pins */
24be5ae3
JM		 1802 PPC6xx_INPUT_HRESET = 0,
1803 PPC6xx_INPUT_SRESET = 1,
1804 PPC6xx_INPUT_CKSTP_IN = 2,
1805 PPC6xx_INPUT_MCP = 3,
1806 PPC6xx_INPUT_SMI = 4,
1807 PPC6xx_INPUT_INT = 5,
d68f1306
JM		 1808 PPC6xx_INPUT_TBEN = 6,
1809 PPC6xx_INPUT_WAKEUP = 7,
1810 PPC6xx_INPUT_NB,
24be5ae3
JM		 1811};
1812
1813enum {
e9df014c 1814 /* Embedded PowerPC input pins */
24be5ae3
JM		 1815 PPCBookE_INPUT_HRESET = 0,
1816 PPCBookE_INPUT_SRESET = 1,
1817 PPCBookE_INPUT_CKSTP_IN = 2,
1818 PPCBookE_INPUT_MCP = 3,
1819 PPCBookE_INPUT_SMI = 4,
1820 PPCBookE_INPUT_INT = 5,
1821 PPCBookE_INPUT_CINT = 6,
d68f1306 1822 PPCBookE_INPUT_NB,
24be5ae3
JM		 1823};
1824
9fdc60bf
AJ		 1825enum {
1826 /* PowerPC E500 input pins */
1827 PPCE500_INPUT_RESET_CORE = 0,
1828 PPCE500_INPUT_MCK = 1,
1829 PPCE500_INPUT_CINT = 3,
1830 PPCE500_INPUT_INT = 4,
1831 PPCE500_INPUT_DEBUG = 6,
1832 PPCE500_INPUT_NB,
1833};
1834
a750fc0b 1835enum {
4e290a0b
JM		 1836 /* PowerPC 40x input pins */
1837 PPC40x_INPUT_RESET_CORE = 0,
1838 PPC40x_INPUT_RESET_CHIP = 1,
1839 PPC40x_INPUT_RESET_SYS = 2,
1840 PPC40x_INPUT_CINT = 3,
1841 PPC40x_INPUT_INT = 4,
1842 PPC40x_INPUT_HALT = 5,
1843 PPC40x_INPUT_DEBUG = 6,
1844 PPC40x_INPUT_NB,
e9df014c
JM		 1845};
1846
b4095fed
JM		 1847enum {
1848 /* RCPU input pins */
1849 PPCRCPU_INPUT_PORESET = 0,
1850 PPCRCPU_INPUT_HRESET = 1,
1851 PPCRCPU_INPUT_SRESET = 2,
1852 PPCRCPU_INPUT_IRQ0 = 3,
1853 PPCRCPU_INPUT_IRQ1 = 4,
1854 PPCRCPU_INPUT_IRQ2 = 5,
1855 PPCRCPU_INPUT_IRQ3 = 6,
1856 PPCRCPU_INPUT_IRQ4 = 7,
1857 PPCRCPU_INPUT_IRQ5 = 8,
1858 PPCRCPU_INPUT_IRQ6 = 9,
1859 PPCRCPU_INPUT_IRQ7 = 10,
1860 PPCRCPU_INPUT_NB,
1861};
1862
00af685f 1863#if defined(TARGET_PPC64)
d0dfae6e
JM		 1864enum {
1865 /* PowerPC 970 input pins */
1866 PPC970_INPUT_HRESET = 0,
1867 PPC970_INPUT_SRESET = 1,
1868 PPC970_INPUT_CKSTP = 2,
1869 PPC970_INPUT_TBEN = 3,
1870 PPC970_INPUT_MCP = 4,
1871 PPC970_INPUT_INT = 5,
1872 PPC970_INPUT_THINT = 6,
7b62a955 1873 PPC970_INPUT_NB,
9d52e907
DG		 1874};
1875
1876enum {
1877 /* POWER7 input pins */
1878 POWER7_INPUT_INT = 0,
1879 /* POWER7 probably has other inputs, but we don't care about them
1880 * for any existing machine. We can wire these up when we need
1881 * them */
1882 POWER7_INPUT_NB,
d0dfae6e 1883};
00af685f 1884#endif
d0dfae6e 1885
e9df014c 1886/* Hardware exceptions definitions */
47103572 1887enum {
e9df014c 1888 /* External hardware exception sources */
e1833e1f 1889 PPC_INTERRUPT_RESET = 0, /* Reset exception */
d68f1306
JM		 1890 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
1891 PPC_INTERRUPT_MCK, /* Machine check exception */
1892 PPC_INTERRUPT_EXT, /* External interrupt */
1893 PPC_INTERRUPT_SMI, /* System management interrupt */
1894 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
1895 PPC_INTERRUPT_DEBUG, /* External debug exception */
1896 PPC_INTERRUPT_THERM, /* Thermal exception */
e9df014c 1897 /* Internal hardware exception sources */
d68f1306
JM		 1898 PPC_INTERRUPT_DECR, /* Decrementer exception */
1899 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
1900 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
1901 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
1902 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
1903 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
1904 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
1905 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
47103572
JM		 1906};
1907
9a64fbe4
FB		 1908/*****************************************************************************/
1909
6b917547
AL		 1910static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
1911 target_ulong *cs_base, int *flags)
1912{
1913 *pc = env->nip;
1914 *cs_base = 0;
1915 *flags = env->hflags;
1916}
1917
174c80d5
NF		 1918static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
1919{
1920#if defined(TARGET_PPC64)
1921 /* The kernel checks TIF_32BIT here; we don't support loading 32-bit
1922 binaries on PPC64 yet. */
1923 env->gpr[13] = newtls;
1924#else
1925 env->gpr[2] = newtls;
1926#endif
1927}
1928
01662f3e
AG		 1929#if !defined(CONFIG_USER_ONLY)
1930static inline int booke206_tlbe_id(CPUState *env, ppcemb_tlb_t *tlbe)
1931{
6d42fb31
SW		 1932 uintptr_t tlbel = (uintptr_t)tlbe;
1933 uintptr_t tlbl = (uintptr_t)env->tlb;
01662f3e
AG		 1934
1935 return (tlbel - tlbl) / sizeof(env->tlb[0]);
1936}
1937
1938static inline int booke206_tlb_size(CPUState *env, int tlbn)
1939{
1940 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
1941 int r = tlbncfg & TLBnCFG_N_ENTRY;
1942 return r;
1943}
1944
1945static inline int booke206_tlb_ways(CPUState *env, int tlbn)
1946{
1947 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
1948 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
1949 return r;
1950}
1951
1952static inline int booke206_tlbe_to_tlbn(CPUState *env, ppcemb_tlb_t *tlbe)
1953{
1954 int id = booke206_tlbe_id(env, tlbe);
1955 int end = 0;
1956 int i;
1957
1958 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
1959 end += booke206_tlb_size(env, i);
1960 if (id < end) {
1961 return i;
1962 }
1963 }
1964
1965 cpu_abort(env, "Unknown TLBe: %d\n", id);
1966 return 0;
1967}
1968
1969static inline int booke206_tlbe_to_way(CPUState *env, ppcemb_tlb_t *tlb)
1970{
1971 int tlbn = booke206_tlbe_to_tlbn(env, tlb);
1972 int tlbid = booke206_tlbe_id(env, tlb);
1973 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
1974}
1975
1976static inline ppcemb_tlb_t *booke206_get_tlbe(CPUState *env, const int tlbn,
1977 target_ulong ea, int way)
1978{
1979 int r;
1980 uint32_t ways = booke206_tlb_ways(env, tlbn);
1981 int ways_bits = ffs(ways) - 1;
1982 int tlb_bits = ffs(booke206_tlb_size(env, tlbn)) - 1;
1983 int i;
1984
1985 way &= ways - 1;
1986 ea >>= MAS2_EPN_SHIFT;
1987 ea &= (1 << (tlb_bits - ways_bits)) - 1;
1988 r = (ea << ways_bits) | way;
1989
1990 /* bump up to tlbn index */
1991 for (i = 0; i < tlbn; i++) {
1992 r += booke206_tlb_size(env, i);
1993 }
1994
1995 return &env->tlb[r].tlbe;
1996}
1997
1998#endif
1999
d569956e
DG		 2000extern void (*cpu_ppc_hypercall)(CPUState *);
2001
79aceca5 2002#endif /* !defined (__CPU_PPC_H__) */
Qemu copy for testing