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[qemu.git] / target-ppc / cpu.h
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation cpu definitions for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
79aceca5
FB		 18 */
19#if !defined (__CPU_PPC_H__)
20#define __CPU_PPC_H__
21
3fc6c082 22#include "config.h"
de270b3c 23#include <inttypes.h>
3fc6c082 24
a4f30719
JM		 25//#define PPC_EMULATE_32BITS_HYPV
26
76a66253 27#if defined (TARGET_PPC64)
3cd7d1dd 28/* PowerPC 64 definitions */
d9d7210c 29#define TARGET_LONG_BITS 64
35cdaad6 30#define TARGET_PAGE_BITS 12
3cd7d1dd 31
52705890
RH		 32/* Note that the official physical address space bits is 62-M where M
33 is implementation dependent. I've not looked up M for the set of
34 cpus we emulate at the system level. */
35#define TARGET_PHYS_ADDR_SPACE_BITS 62
36
37/* Note that the PPC environment architecture talks about 80 bit virtual
38 addresses, with segmentation. Obviously that's not all visible to a
39 single process, which is all we're concerned with here. */
40#ifdef TARGET_ABI32
41# define TARGET_VIRT_ADDR_SPACE_BITS 32
42#else
43# define TARGET_VIRT_ADDR_SPACE_BITS 64
44#endif
45
3cd7d1dd
JM		 46#else /* defined (TARGET_PPC64) */
47/* PowerPC 32 definitions */
d9d7210c 48#define TARGET_LONG_BITS 32
3cd7d1dd
JM		 49
50#if defined(TARGET_PPCEMB)
51/* Specific definitions for PowerPC embedded */
52/* BookE have 36 bits physical address space */
3cd7d1dd
JM		 53#if defined(CONFIG_USER_ONLY)
54/* It looks like a lot of Linux programs assume page size
55 * is 4kB long. This is evil, but we have to deal with it...
56 */
35cdaad6 57#define TARGET_PAGE_BITS 12
3cd7d1dd
JM		 58#else /* defined(CONFIG_USER_ONLY) */
59/* Pages can be 1 kB small */
60#define TARGET_PAGE_BITS 10
61#endif /* defined(CONFIG_USER_ONLY) */
62#else /* defined(TARGET_PPCEMB) */
63/* "standard" PowerPC 32 definitions */
64#define TARGET_PAGE_BITS 12
65#endif /* defined(TARGET_PPCEMB) */
66
52705890
RH		 67#define TARGET_PHYS_ADDR_SPACE_BITS 32
68#define TARGET_VIRT_ADDR_SPACE_BITS 32
69
3cd7d1dd 70#endif /* defined (TARGET_PPC64) */
3cf1e035 71
c2764719
PB		 72#define CPUState struct CPUPPCState
73
79aceca5
FB		 74#include "cpu-defs.h"
75
79aceca5
FB		 76#include <setjmp.h>
77
4ecc3190
FB		 78#include "softfloat.h"
79
1fddef4b
FB		 80#define TARGET_HAS_ICE 1
81
7f70c937 82#if defined (TARGET_PPC64)
76a66253
JM		 83#define ELF_MACHINE EM_PPC64
84#else
85#define ELF_MACHINE EM_PPC
86#endif
9042c0e2 87
3fc6c082 88/*****************************************************************************/
a750fc0b 89/* MMU model */
c227f099
AL		 90typedef enum powerpc_mmu_t powerpc_mmu_t;
91enum powerpc_mmu_t {
add78955 92 POWERPC_MMU_UNKNOWN = 0x00000000,
a750fc0b 93 /* Standard 32 bits PowerPC MMU */
add78955 94 POWERPC_MMU_32B = 0x00000001,
a750fc0b 95 /* PowerPC 6xx MMU with software TLB */
add78955 96 POWERPC_MMU_SOFT_6xx = 0x00000002,
a750fc0b 97 /* PowerPC 74xx MMU with software TLB */
add78955 98 POWERPC_MMU_SOFT_74xx = 0x00000003,
a750fc0b 99 /* PowerPC 4xx MMU with software TLB */
add78955 100 POWERPC_MMU_SOFT_4xx = 0x00000004,
a750fc0b 101 /* PowerPC 4xx MMU with software TLB and zones protections */
add78955 102 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
b4095fed 103 /* PowerPC MMU in real mode only */
add78955 104 POWERPC_MMU_REAL = 0x00000006,
b4095fed 105 /* Freescale MPC8xx MMU model */
add78955 106 POWERPC_MMU_MPC8xx = 0x00000007,
a750fc0b 107 /* BookE MMU model */
add78955 108 POWERPC_MMU_BOOKE = 0x00000008,
a750fc0b 109 /* BookE FSL MMU model */
add78955 110 POWERPC_MMU_BOOKE_FSL = 0x00000009,
faadf50e 111 /* PowerPC 601 MMU model (specific BATs format) */
add78955 112 POWERPC_MMU_601 = 0x0000000A,
00af685f 113#if defined(TARGET_PPC64)
add78955 114#define POWERPC_MMU_64 0x00010000
12de9a39 115 /* 64 bits PowerPC MMU */
add78955
JM		 116 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
117 /* 620 variant (no segment exceptions) */
118 POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002,
00af685f 119#endif /* defined(TARGET_PPC64) */
3fc6c082
FB		 120};
121
122/*****************************************************************************/
a750fc0b 123/* Exception model */
c227f099
AL		 124typedef enum powerpc_excp_t powerpc_excp_t;
125enum powerpc_excp_t {
a750fc0b 126 POWERPC_EXCP_UNKNOWN = 0,
3fc6c082 127 /* Standard PowerPC exception model */
a750fc0b 128 POWERPC_EXCP_STD,
2662a059 129 /* PowerPC 40x exception model */
a750fc0b 130 POWERPC_EXCP_40x,
2662a059 131 /* PowerPC 601 exception model */
a750fc0b 132 POWERPC_EXCP_601,
2662a059 133 /* PowerPC 602 exception model */
a750fc0b 134 POWERPC_EXCP_602,
2662a059 135 /* PowerPC 603 exception model */
a750fc0b
JM		 136 POWERPC_EXCP_603,
137 /* PowerPC 603e exception model */
138 POWERPC_EXCP_603E,
139 /* PowerPC G2 exception model */
140 POWERPC_EXCP_G2,
2662a059 141 /* PowerPC 604 exception model */
a750fc0b 142 POWERPC_EXCP_604,
2662a059 143 /* PowerPC 7x0 exception model */
a750fc0b 144 POWERPC_EXCP_7x0,
2662a059 145 /* PowerPC 7x5 exception model */
a750fc0b 146 POWERPC_EXCP_7x5,
2662a059 147 /* PowerPC 74xx exception model */
a750fc0b 148 POWERPC_EXCP_74xx,
2662a059 149 /* BookE exception model */
a750fc0b 150 POWERPC_EXCP_BOOKE,
00af685f
JM		 151#if defined(TARGET_PPC64)
152 /* PowerPC 970 exception model */
153 POWERPC_EXCP_970,
154#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 155};
156
e1833e1f
JM		 157/*****************************************************************************/
158/* Exception vectors definitions */
159enum {
160 POWERPC_EXCP_NONE = -1,
161 /* The 64 first entries are used by the PowerPC embedded specification */
162 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
163 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
164 POWERPC_EXCP_DSI = 2, /* Data storage exception */
165 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
166 POWERPC_EXCP_EXTERNAL = 4, /* External input */
167 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
168 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
169 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
170 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
171 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
172 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
173 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
174 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
b4095fed
JM		 175 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
176 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
e1833e1f
JM		 177 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
178 /* Vectors 16 to 31 are reserved */
e1833e1f
JM		 179 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
180 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
181 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
182 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
183 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
184 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
e1833e1f
JM		 185 /* Vectors 38 to 63 are reserved */
186 /* Exceptions defined in the PowerPC server specification */
187 POWERPC_EXCP_RESET = 64, /* System reset exception */
e1833e1f
JM		 188 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
189 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
e1833e1f 190 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
e1833e1f 191 POWERPC_EXCP_TRACE = 68, /* Trace exception */
e1833e1f
JM		 192 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
193 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
194 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
195 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
e1833e1f
JM		 196 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
197 /* 40x specific exceptions */
198 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
199 /* 601 specific exceptions */
200 POWERPC_EXCP_IO = 75, /* IO error exception */
201 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
202 /* 602 specific exceptions */
203 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
204 /* 602/603 specific exceptions */
b4095fed 205 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
e1833e1f
JM		 206 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
207 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
208 /* Exceptions available on most PowerPC */
209 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
b4095fed
JM		 210 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
211 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
212 POWERPC_EXCP_SMI = 84, /* System management interrupt */
213 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
e1833e1f 214 /* 7xx/74xx specific exceptions */
b4095fed 215 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
e1833e1f 216 /* 74xx specific exceptions */
b4095fed 217 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
e1833e1f 218 /* 970FX specific exceptions */
b4095fed
JM		 219 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
220 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
221 /* Freescale embeded cores specific exceptions */
222 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
223 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
224 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
225 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
e1833e1f
JM		 226 /* EOL */
227 POWERPC_EXCP_NB = 96,
228 /* Qemu exceptions: used internally during code translation */
229 POWERPC_EXCP_STOP = 0x200, /* stop translation */
230 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
231 /* Qemu exceptions: special cases we want to stop translation */
232 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
233 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
4425265b 234 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
e1833e1f
JM		 235};
236
e1833e1f
JM		 237/* Exceptions error codes */
238enum {
239 /* Exception subtypes for POWERPC_EXCP_ALIGN */
240 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
241 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
242 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
243 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
244 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
245 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
246 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
247 /* FP exceptions */
248 POWERPC_EXCP_FP = 0x10,
249 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
250 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
251 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
252 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
7c58044c 253 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
e1833e1f
JM		 254 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
255 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
256 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
257 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
258 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
259 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
260 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
261 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
262 /* Invalid instruction */
263 POWERPC_EXCP_INVAL = 0x20,
264 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
265 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
266 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
267 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
268 /* Privileged instruction */
269 POWERPC_EXCP_PRIV = 0x30,
270 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
271 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
272 /* Trap */
273 POWERPC_EXCP_TRAP = 0x40,
274};
275
a750fc0b
JM		 276/*****************************************************************************/
277/* Input pins model */
c227f099
AL		 278typedef enum powerpc_input_t powerpc_input_t;
279enum powerpc_input_t {
a750fc0b 280 PPC_FLAGS_INPUT_UNKNOWN = 0,
2662a059 281 /* PowerPC 6xx bus */
a750fc0b 282 PPC_FLAGS_INPUT_6xx,
2662a059 283 /* BookE bus */
a750fc0b
JM		 284 PPC_FLAGS_INPUT_BookE,
285 /* PowerPC 405 bus */
286 PPC_FLAGS_INPUT_405,
2662a059 287 /* PowerPC 970 bus */
a750fc0b
JM		 288 PPC_FLAGS_INPUT_970,
289 /* PowerPC 401 bus */
290 PPC_FLAGS_INPUT_401,
b4095fed
JM		 291 /* Freescale RCPU bus */
292 PPC_FLAGS_INPUT_RCPU,
3fc6c082
FB		 293};
294
a750fc0b 295#define PPC_INPUT(env) (env->bus_model)
3fc6c082 296
be147d08 297/*****************************************************************************/
c227f099
AL		 298typedef struct ppc_def_t ppc_def_t;
299typedef struct opc_handler_t opc_handler_t;
79aceca5 300
3fc6c082
FB		 301/*****************************************************************************/
302/* Types used to describe some PowerPC registers */
303typedef struct CPUPPCState CPUPPCState;
c227f099
AL		 304typedef struct ppc_tb_t ppc_tb_t;
305typedef struct ppc_spr_t ppc_spr_t;
306typedef struct ppc_dcr_t ppc_dcr_t;
307typedef union ppc_avr_t ppc_avr_t;
308typedef union ppc_tlb_t ppc_tlb_t;
76a66253 309
3fc6c082 310/* SPR access micro-ops generations callbacks */
c227f099 311struct ppc_spr_t {
45d827d2
AJ		 312 void (*uea_read)(void *opaque, int gpr_num, int spr_num);
313 void (*uea_write)(void *opaque, int spr_num, int gpr_num);
76a66253 314#if !defined(CONFIG_USER_ONLY)
45d827d2
AJ		 315 void (*oea_read)(void *opaque, int gpr_num, int spr_num);
316 void (*oea_write)(void *opaque, int spr_num, int gpr_num);
317 void (*hea_read)(void *opaque, int gpr_num, int spr_num);
318 void (*hea_write)(void *opaque, int spr_num, int gpr_num);
76a66253 319#endif
b55266b5 320 const char *name;
3fc6c082
FB		 321};
322
323/* Altivec registers (128 bits) */
c227f099 324union ppc_avr_t {
0f6fbcbc 325 float32 f[4];
a9d9eb8f
JM		 326 uint8_t u8[16];
327 uint16_t u16[8];
328 uint32_t u32[4];
ab5f265d
AJ		 329 int8_t s8[16];
330 int16_t s16[8];
331 int32_t s32[4];
a9d9eb8f 332 uint64_t u64[2];
3fc6c082 333};
9fddaa0c 334
3c7b48b7 335#if !defined(CONFIG_USER_ONLY)
3fc6c082 336/* Software TLB cache */
c227f099
AL		 337typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
338struct ppc6xx_tlb_t {
76a66253
JM		 339 target_ulong pte0;
340 target_ulong pte1;
341 target_ulong EPN;
1d0a48fb
JM		 342};
343
c227f099
AL		 344typedef struct ppcemb_tlb_t ppcemb_tlb_t;
345struct ppcemb_tlb_t {
346 target_phys_addr_t RPN;
1d0a48fb 347 target_ulong EPN;
76a66253 348 target_ulong PID;
c55e9aef
JM		 349 target_ulong size;
350 uint32_t prot;
351 uint32_t attr; /* Storage attributes */
1d0a48fb
JM		 352};
353
c227f099
AL		 354union ppc_tlb_t {
355 ppc6xx_tlb_t tlb6;
356 ppcemb_tlb_t tlbe;
3fc6c082 357};
3c7b48b7 358#endif
3fc6c082 359
c227f099
AL		 360typedef struct ppc_slb_t ppc_slb_t;
361struct ppc_slb_t {
8eee0af9
BS		 362 uint64_t tmp64;
363 uint32_t tmp;
364};
365
3fc6c082
FB		 366/*****************************************************************************/
367/* Machine state register bits definition */
76a66253 368#define MSR_SF 63 /* Sixty-four-bit mode hflags */
bd928eba 369#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
3fc6c082 370#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
a4f30719 371#define MSR_SHV 60 /* hypervisor state hflags */
363be49c
JM		 372#define MSR_CM 31 /* Computation mode for BookE hflags */
373#define MSR_ICM 30 /* Interrupt computation mode for BookE */
a4f30719 374#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
363be49c 375#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
d26bfc9a
JM		 376#define MSR_VR 25 /* altivec available x hflags */
377#define MSR_SPE 25 /* SPE enable for BookE x hflags */
76a66253
JM		 378#define MSR_AP 23 /* Access privilege state on 602 hflags */
379#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
3fc6c082 380#define MSR_KEY 19 /* key bit on 603e */
25ba3a68 381#define MSR_POW 18 /* Power management */
d26bfc9a
JM		 382#define MSR_TGPR 17 /* TGPR usage on 602/603 x */
383#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
3fc6c082
FB		 384#define MSR_ILE 16 /* Interrupt little-endian mode */
385#define MSR_EE 15 /* External interrupt enable */
76a66253
JM		 386#define MSR_PR 14 /* Problem state hflags */
387#define MSR_FP 13 /* Floating point available hflags */
3fc6c082 388#define MSR_ME 12 /* Machine check interrupt enable */
76a66253 389#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
d26bfc9a
JM		 390#define MSR_SE 10 /* Single-step trace enable x hflags */
391#define MSR_DWE 10 /* Debug wait enable on 405 x */
392#define MSR_UBLE 10 /* User BTB lock enable on e500 x */
393#define MSR_BE 9 /* Branch trace enable x hflags */
394#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
76a66253 395#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
3fc6c082 396#define MSR_AL 7 /* AL bit on POWER */
0411a972 397#define MSR_EP 6 /* Exception prefix on 601 */
3fc6c082 398#define MSR_IR 5 /* Instruction relocate */
3fc6c082 399#define MSR_DR 4 /* Data relocate */
25ba3a68 400#define MSR_PE 3 /* Protection enable on 403 */
d26bfc9a
JM		 401#define MSR_PX 2 /* Protection exclusive on 403 x */
402#define MSR_PMM 2 /* Performance monitor mark on POWER x */
403#define MSR_RI 1 /* Recoverable interrupt 1 */
404#define MSR_LE 0 /* Little-endian mode 1 hflags */
0411a972
JM		 405
406#define msr_sf ((env->msr >> MSR_SF) & 1)
407#define msr_isf ((env->msr >> MSR_ISF) & 1)
a4f30719 408#define msr_shv ((env->msr >> MSR_SHV) & 1)
0411a972
JM		 409#define msr_cm ((env->msr >> MSR_CM) & 1)
410#define msr_icm ((env->msr >> MSR_ICM) & 1)
a4f30719 411#define msr_thv ((env->msr >> MSR_THV) & 1)
0411a972
JM		 412#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
413#define msr_vr ((env->msr >> MSR_VR) & 1)
f9320410 414#define msr_spe ((env->msr >> MSR_SPE) & 1)
0411a972
JM		 415#define msr_ap ((env->msr >> MSR_AP) & 1)
416#define msr_sa ((env->msr >> MSR_SA) & 1)
417#define msr_key ((env->msr >> MSR_KEY) & 1)
418#define msr_pow ((env->msr >> MSR_POW) & 1)
419#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
420#define msr_ce ((env->msr >> MSR_CE) & 1)
421#define msr_ile ((env->msr >> MSR_ILE) & 1)
422#define msr_ee ((env->msr >> MSR_EE) & 1)
423#define msr_pr ((env->msr >> MSR_PR) & 1)
424#define msr_fp ((env->msr >> MSR_FP) & 1)
425#define msr_me ((env->msr >> MSR_ME) & 1)
426#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
427#define msr_se ((env->msr >> MSR_SE) & 1)
428#define msr_dwe ((env->msr >> MSR_DWE) & 1)
429#define msr_uble ((env->msr >> MSR_UBLE) & 1)
430#define msr_be ((env->msr >> MSR_BE) & 1)
431#define msr_de ((env->msr >> MSR_DE) & 1)
432#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
433#define msr_al ((env->msr >> MSR_AL) & 1)
434#define msr_ep ((env->msr >> MSR_EP) & 1)
435#define msr_ir ((env->msr >> MSR_IR) & 1)
436#define msr_dr ((env->msr >> MSR_DR) & 1)
437#define msr_pe ((env->msr >> MSR_PE) & 1)
438#define msr_px ((env->msr >> MSR_PX) & 1)
439#define msr_pmm ((env->msr >> MSR_PMM) & 1)
440#define msr_ri ((env->msr >> MSR_RI) & 1)
441#define msr_le ((env->msr >> MSR_LE) & 1)
a4f30719
JM		 442/* Hypervisor bit is more specific */
443#if defined(TARGET_PPC64)
444#define MSR_HVB (1ULL << MSR_SHV)
445#define msr_hv msr_shv
446#else
447#if defined(PPC_EMULATE_32BITS_HYPV)
448#define MSR_HVB (1ULL << MSR_THV)
449#define msr_hv msr_thv
a4f30719
JM		 450#else
451#define MSR_HVB (0ULL)
452#define msr_hv (0)
453#endif
454#endif
79aceca5 455
d26bfc9a 456enum {
4018bae9 457 POWERPC_FLAG_NONE = 0x00000000,
d26bfc9a 458 /* Flag for MSR bit 25 signification (VRE/SPE) */
4018bae9
JM		 459 POWERPC_FLAG_SPE = 0x00000001,
460 POWERPC_FLAG_VRE = 0x00000002,
d26bfc9a 461 /* Flag for MSR bit 17 signification (TGPR/CE) */
4018bae9
JM		 462 POWERPC_FLAG_TGPR = 0x00000004,
463 POWERPC_FLAG_CE = 0x00000008,
d26bfc9a 464 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
4018bae9
JM		 465 POWERPC_FLAG_SE = 0x00000010,
466 POWERPC_FLAG_DWE = 0x00000020,
467 POWERPC_FLAG_UBLE = 0x00000040,
d26bfc9a 468 /* Flag for MSR bit 9 signification (BE/DE) */
4018bae9
JM		 469 POWERPC_FLAG_BE = 0x00000080,
470 POWERPC_FLAG_DE = 0x00000100,
a4f30719 471 /* Flag for MSR bit 2 signification (PX/PMM) */
4018bae9
JM		 472 POWERPC_FLAG_PX = 0x00000200,
473 POWERPC_FLAG_PMM = 0x00000400,
474 /* Flag for special features */
475 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
476 POWERPC_FLAG_RTC_CLK = 0x00010000,
477 POWERPC_FLAG_BUS_CLK = 0x00020000,
d26bfc9a
JM		 478};
479
7c58044c
JM		 480/*****************************************************************************/
481/* Floating point status and control register */
482#define FPSCR_FX 31 /* Floating-point exception summary */
483#define FPSCR_FEX 30 /* Floating-point enabled exception summary */
484#define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
485#define FPSCR_OX 28 /* Floating-point overflow exception */
486#define FPSCR_UX 27 /* Floating-point underflow exception */
487#define FPSCR_ZX 26 /* Floating-point zero divide exception */
488#define FPSCR_XX 25 /* Floating-point inexact exception */
489#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
490#define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
491#define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
492#define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
493#define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
494#define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
495#define FPSCR_FR 18 /* Floating-point fraction rounded */
496#define FPSCR_FI 17 /* Floating-point fraction inexact */
497#define FPSCR_C 16 /* Floating-point result class descriptor */
498#define FPSCR_FL 15 /* Floating-point less than or negative */
499#define FPSCR_FG 14 /* Floating-point greater than or negative */
500#define FPSCR_FE 13 /* Floating-point equal or zero */
501#define FPSCR_FU 12 /* Floating-point unordered or NaN */
502#define FPSCR_FPCC 12 /* Floating-point condition code */
503#define FPSCR_FPRF 12 /* Floating-point result flags */
504#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
505#define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
506#define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
507#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
508#define FPSCR_OE 6 /* Floating-point overflow exception enable */
509#define FPSCR_UE 5 /* Floating-point undeflow exception enable */
510#define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
511#define FPSCR_XE 3 /* Floating-point inexact exception enable */
512#define FPSCR_NI 2 /* Floating-point non-IEEE mode */
513#define FPSCR_RN1 1
514#define FPSCR_RN 0 /* Floating-point rounding control */
515#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
516#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
517#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
518#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
519#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
520#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
521#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
522#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
523#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
524#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
525#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
526#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
527#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
528#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
529#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
530#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
531#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
532#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
533#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
534#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
535#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
536#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
537#define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
538/* Invalid operation exception summary */
539#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
540 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
541 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
542 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
543 (1 << FPSCR_VXCVI)))
544/* exception summary */
545#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
546/* enabled exception summary */
547#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
548 0x1F)
549
550/*****************************************************************************/
6fa724a3
AJ		 551/* Vector status and control register */
552#define VSCR_NJ 16 /* Vector non-java */
553#define VSCR_SAT 0 /* Vector saturation */
554#define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
555#define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
556
557/*****************************************************************************/
7c58044c 558/* The whole PowerPC CPU context */
6ebbf390 559#define NB_MMU_MODES 3
6ebbf390 560
3fc6c082
FB		 561struct CPUPPCState {
562 /* First are the most commonly used resources
563 * during translated code execution
564 */
79aceca5 565 /* general purpose registers */
bd7d9a6d 566 target_ulong gpr[32];
65d6c0f3 567#if !defined(TARGET_PPC64)
3cd7d1dd 568 /* Storage for GPR MSB, used by the SPE extension */
bd7d9a6d 569 target_ulong gprh[32];
3cd7d1dd 570#endif
3fc6c082
FB		 571 /* LR */
572 target_ulong lr;
573 /* CTR */
574 target_ulong ctr;
575 /* condition register */
47e4661c 576 uint32_t crf[8];
79aceca5 577 /* XER */
3d7b417e 578 target_ulong xer;
79aceca5 579 /* Reservation address */
18b21a2f
NF		 580 target_ulong reserve_addr;
581 /* Reservation value */
582 target_ulong reserve_val;
4425265b
NF		 583 /* Reservation store address */
584 target_ulong reserve_ea;
585 /* Reserved store source register and size */
586 target_ulong reserve_info;
3fc6c082
FB		 587
588 /* Those ones are used in supervisor mode only */
79aceca5 589 /* machine state register */
0411a972 590 target_ulong msr;
3fc6c082 591 /* temporary general purpose registers */
bd7d9a6d 592 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
3fc6c082
FB		 593
594 /* Floating point execution context */
4ecc3190 595 float_status fp_status;
3fc6c082
FB		 596 /* floating point registers */
597 float64 fpr[32];
598 /* floating point status and control register */
7c58044c 599 uint32_t fpscr;
4ecc3190 600
cb2dbfc3
AJ		 601 /* Next instruction pointer */
602 target_ulong nip;
a316d335 603
ac9eb073
FB		 604 int access_type; /* when a memory exception occurs, the access
605 type is stored here */
a541f297 606
cb2dbfc3
AJ		 607 CPU_COMMON
608
f2e63a42
JM		 609 /* MMU context - only relevant for full system emulation */
610#if !defined(CONFIG_USER_ONLY)
611#if defined(TARGET_PPC64)
3fc6c082
FB		 612 /* Address space register */
613 target_ulong asr;
f2e63a42 614 /* PowerPC 64 SLB area */
c227f099 615 ppc_slb_t slb[64];
f2e63a42
JM		 616 int slb_nr;
617#endif
3fc6c082
FB		 618 /* segment registers */
619 target_ulong sdr1;
74d37793 620 target_ulong sr[32];
3fc6c082
FB		 621 /* BATs */
622 int nb_BATs;
623 target_ulong DBAT[2][8];
624 target_ulong IBAT[2][8];
f2e63a42
JM		 625 /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
626 int nb_tlb; /* Total number of TLB */
627 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
628 int nb_ways; /* Number of ways in the TLB set */
629 int last_way; /* Last used way used to allocate TLB in a LRU way */
630 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
631 int nb_pids; /* Number of available PID registers */
c227f099 632 ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
f2e63a42
JM		 633 /* 403 dedicated access protection registers */
634 target_ulong pb[4];
635#endif
9fddaa0c 636
3fc6c082
FB		 637 /* Other registers */
638 /* Special purpose registers */
639 target_ulong spr[1024];
c227f099 640 ppc_spr_t spr_cb[1024];
3fc6c082 641 /* Altivec registers */
c227f099 642 ppc_avr_t avr[32];
3fc6c082 643 uint32_t vscr;
d9bce9d9 644 /* SPE registers */
2231ef10 645 uint64_t spe_acc;
d9bce9d9 646 uint32_t spe_fscr;
fbd265b6
AJ		 647 /* SPE and Altivec can share a status since they will never be used
648 * simultaneously */
649 float_status vec_status;
3fc6c082
FB		 650
651 /* Internal devices resources */
9fddaa0c 652 /* Time base and decrementer */
c227f099 653 ppc_tb_t *tb_env;
3fc6c082 654 /* Device control registers */
c227f099 655 ppc_dcr_t *dcr_env;
3fc6c082 656
d63001d1
JM		 657 int dcache_line_size;
658 int icache_line_size;
659
3fc6c082
FB		 660 /* Those resources are used during exception processing */
661 /* CPU model definition */
a750fc0b 662 target_ulong msr_mask;
c227f099
AL		 663 powerpc_mmu_t mmu_model;
664 powerpc_excp_t excp_model;
665 powerpc_input_t bus_model;
237c0af0 666 int bfd_mach;
3fc6c082 667 uint32_t flags;
c29b735c 668 uint64_t insns_flags;
3fc6c082 669
3fc6c082 670 int error_code;
47103572 671 uint32_t pending_interrupts;
e9df014c
JM		 672#if !defined(CONFIG_USER_ONLY)
673 /* This is the IRQ controller, which is implementation dependant
674 * and only relevant when emulating a complete machine.
675 */
676 uint32_t irq_input_state;
677 void **irq_inputs;
e1833e1f
JM		 678 /* Exception vectors */
679 target_ulong excp_vectors[POWERPC_EXCP_NB];
680 target_ulong excp_prefix;
fc1c67bc 681 target_ulong hreset_excp_prefix;
e1833e1f
JM		 682 target_ulong ivor_mask;
683 target_ulong ivpr_mask;
d63001d1 684 target_ulong hreset_vector;
e9df014c 685#endif
3fc6c082
FB		 686
687 /* Those resources are used only during code translation */
3fc6c082 688 /* opcode handlers */
c227f099 689 opc_handler_t *opcodes[0x40];
3fc6c082
FB		 690
691 /* Those resources are used only in Qemu core */
056401ea
JM		 692 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
693 target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
6ebbf390 694 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
3fc6c082 695
9fddaa0c
FB		 696 /* Power management */
697 int power_mode;
cd346349 698 int (*check_pow)(CPUPPCState *env);
a541f297 699
6d506e6d
FB		 700 /* temporary hack to handle OSI calls (only used if non NULL) */
701 int (*osi_call)(struct CPUPPCState *env);
3fc6c082 702};
79aceca5 703
3c7b48b7 704#if !defined(CONFIG_USER_ONLY)
76a66253 705/* Context used internally during MMU translations */
c227f099
AL		 706typedef struct mmu_ctx_t mmu_ctx_t;
707struct mmu_ctx_t {
708 target_phys_addr_t raddr; /* Real address */
709 target_phys_addr_t eaddr; /* Effective address */
76a66253 710 int prot; /* Protection bits */
c227f099 711 target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
76a66253
JM		 712 target_ulong ptem; /* Virtual segment ID | API */
713 int key; /* Access key */
b227a8e9 714 int nx; /* Non-execute area */
76a66253 715};
3c7b48b7 716#endif
76a66253 717
3fc6c082 718/*****************************************************************************/
aaed909a 719CPUPPCState *cpu_ppc_init (const char *cpu_model);
2e70f6ef 720void ppc_translate_init(void);
36081602
JM		 721int cpu_ppc_exec (CPUPPCState *s);
722void cpu_ppc_close (CPUPPCState *s);
79aceca5
FB		 723/* you can call this signal handler from your SIGBUS and SIGSEGV
724 signal handlers to inform the virtual CPU of exceptions. non zero
725 is returned if the signal was handled by the virtual CPU. */
36081602
JM		 726int cpu_ppc_signal_handler (int host_signum, void *pinfo,
727 void *puc);
93220573
AJ		 728int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
729 int mmu_idx, int is_softmmu);
0b5c1ce8 730#define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
3c7b48b7 731#if !defined(CONFIG_USER_ONLY)
c227f099 732int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,
93220573 733 int rw, int access_type);
3c7b48b7 734#endif
a541f297 735void do_interrupt (CPUPPCState *env);
e9df014c 736void ppc_hw_interrupt (CPUPPCState *env);
a541f297 737
93220573 738void cpu_dump_rfi (target_ulong RA, target_ulong msr);
a541f297 739
76a66253 740#if !defined(CONFIG_USER_ONLY)
93220573
AJ		 741void ppc6xx_tlb_store (CPUPPCState *env, target_ulong EPN, int way, int is_code,
742 target_ulong pte0, target_ulong pte1);
45d827d2
AJ		 743void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
744void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
745void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
746void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
747void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);
748void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);
749void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
d9bce9d9 750#if defined(TARGET_PPC64)
d9bce9d9 751void ppc_store_asr (CPUPPCState *env, target_ulong value);
12de9a39 752target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
f6b868fc
BS		 753target_ulong ppc_load_sr (CPUPPCState *env, int sr_nr);
754void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
12de9a39 755#endif /* defined(TARGET_PPC64) */
45d827d2 756void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value);
12de9a39 757#endif /* !defined(CONFIG_USER_ONLY) */
0411a972 758void ppc_store_msr (CPUPPCState *env, target_ulong value);
3fc6c082 759
3fc6c082 760void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
aaed909a 761
c227f099
AL		 762const ppc_def_t *cpu_ppc_find_by_name (const char *name);
763int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
85c4adf6 764
9fddaa0c
FB		 765/* Time-base and decrementer management */
766#ifndef NO_CPU_IO_DEFS
e3ea6529 767uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
9fddaa0c
FB		 768uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
769void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
770void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
b711de95 771uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
a062e36c
JM		 772uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
773void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
774void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
9fddaa0c
FB		 775uint32_t cpu_ppc_load_decr (CPUPPCState *env);
776void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
58a7d328
JM		 777uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
778void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
779uint64_t cpu_ppc_load_purr (CPUPPCState *env);
780void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
d9bce9d9
JM		 781uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
782uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
783#if !defined(CONFIG_USER_ONLY)
784void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
785void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
786target_ulong load_40x_pit (CPUPPCState *env);
787void store_40x_pit (CPUPPCState *env, target_ulong val);
8ecc7913 788void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
c294fc58 789void store_40x_sler (CPUPPCState *env, uint32_t val);
d9bce9d9
JM		 790void store_booke_tcr (CPUPPCState *env, target_ulong val);
791void store_booke_tsr (CPUPPCState *env, target_ulong val);
0a032cbe 792void ppc_tlb_invalidate_all (CPUPPCState *env);
daf4f96e
JM		 793void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
794#if defined(TARGET_PPC64)
795void ppc_slb_invalidate_all (CPUPPCState *env);
796void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
797#endif
36081602 798int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
d9bce9d9 799#endif
9fddaa0c 800#endif
79aceca5 801
636aa200 802static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
6b542af7
JM		 803{
804 uint64_t gprv;
805
806 gprv = env->gpr[gprn];
807#if !defined(TARGET_PPC64)
808 if (env->flags & POWERPC_FLAG_SPE) {
809 /* If the CPU implements the SPE extension, we have to get the
810 * high bits of the GPR from the gprh storage area
811 */
812 gprv &= 0xFFFFFFFFULL;
813 gprv |= (uint64_t)env->gprh[gprn] << 32;
814 }
815#endif
816
817 return gprv;
818}
819
2e719ba3 820/* Device control registers */
73b01960
AG		 821int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
822int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
2e719ba3 823
9467d44c
TS		 824#define cpu_init cpu_ppc_init
825#define cpu_exec cpu_ppc_exec
826#define cpu_gen_code cpu_ppc_gen_code
827#define cpu_signal_handler cpu_ppc_signal_handler
c732abe2 828#define cpu_list ppc_cpu_list
9467d44c 829
fc1c67bc 830#define CPU_SAVE_VERSION 4
b3c7724c 831
6ebbf390
JM		 832/* MMU modes definitions */
833#define MMU_MODE0_SUFFIX _user
834#define MMU_MODE1_SUFFIX _kernel
6ebbf390 835#define MMU_MODE2_SUFFIX _hypv
6ebbf390
JM		 836#define MMU_USER_IDX 0
837static inline int cpu_mmu_index (CPUState *env)
838{
839 return env->mmu_idx;
840}
841
6e68e076
PB		 842#if defined(CONFIG_USER_ONLY)
843static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
844{
f8ed7070 845 if (newsp)
6e68e076 846 env->gpr[1] = newsp;
d11f69b2 847 env->gpr[3] = 0;
6e68e076
PB		 848}
849#endif
850
79aceca5
FB		 851#include "cpu-all.h"
852
3fc6c082 853/*****************************************************************************/
e1571908 854/* CRF definitions */
57951c27
AJ		 855#define CRF_LT 3
856#define CRF_GT 2
857#define CRF_EQ 1
858#define CRF_SO 0
e6bba2ef
NF		 859#define CRF_CH (1 << CRF_LT)
860#define CRF_CL (1 << CRF_GT)
861#define CRF_CH_OR_CL (1 << CRF_EQ)
862#define CRF_CH_AND_CL (1 << CRF_SO)
e1571908
AJ		 863
864/* XER definitions */
3d7b417e
AJ		 865#define XER_SO 31
866#define XER_OV 30
867#define XER_CA 29
868#define XER_CMP 8
869#define XER_BC 0
870#define xer_so ((env->xer >> XER_SO) & 1)
871#define xer_ov ((env->xer >> XER_OV) & 1)
872#define xer_ca ((env->xer >> XER_CA) & 1)
873#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
874#define xer_bc ((env->xer >> XER_BC) & 0x7F)
79aceca5 875
3fc6c082 876/* SPR definitions */
80d11f44
JM		 877#define SPR_MQ (0x000)
878#define SPR_XER (0x001)
879#define SPR_601_VRTCU (0x004)
880#define SPR_601_VRTCL (0x005)
881#define SPR_601_UDECR (0x006)
882#define SPR_LR (0x008)
883#define SPR_CTR (0x009)
884#define SPR_DSISR (0x012)
885#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
886#define SPR_601_RTCU (0x014)
887#define SPR_601_RTCL (0x015)
888#define SPR_DECR (0x016)
889#define SPR_SDR1 (0x019)
890#define SPR_SRR0 (0x01A)
891#define SPR_SRR1 (0x01B)
892#define SPR_AMR (0x01D)
893#define SPR_BOOKE_PID (0x030)
894#define SPR_BOOKE_DECAR (0x036)
895#define SPR_BOOKE_CSRR0 (0x03A)
896#define SPR_BOOKE_CSRR1 (0x03B)
897#define SPR_BOOKE_DEAR (0x03D)
898#define SPR_BOOKE_ESR (0x03E)
899#define SPR_BOOKE_IVPR (0x03F)
900#define SPR_MPC_EIE (0x050)
901#define SPR_MPC_EID (0x051)
902#define SPR_MPC_NRI (0x052)
903#define SPR_CTRL (0x088)
904#define SPR_MPC_CMPA (0x090)
905#define SPR_MPC_CMPB (0x091)
906#define SPR_MPC_CMPC (0x092)
907#define SPR_MPC_CMPD (0x093)
908#define SPR_MPC_ECR (0x094)
909#define SPR_MPC_DER (0x095)
910#define SPR_MPC_COUNTA (0x096)
911#define SPR_MPC_COUNTB (0x097)
912#define SPR_UCTRL (0x098)
913#define SPR_MPC_CMPE (0x098)
914#define SPR_MPC_CMPF (0x099)
915#define SPR_MPC_CMPG (0x09A)
916#define SPR_MPC_CMPH (0x09B)
917#define SPR_MPC_LCTRL1 (0x09C)
918#define SPR_MPC_LCTRL2 (0x09D)
919#define SPR_MPC_ICTRL (0x09E)
920#define SPR_MPC_BAR (0x09F)
921#define SPR_VRSAVE (0x100)
922#define SPR_USPRG0 (0x100)
923#define SPR_USPRG1 (0x101)
924#define SPR_USPRG2 (0x102)
925#define SPR_USPRG3 (0x103)
926#define SPR_USPRG4 (0x104)
927#define SPR_USPRG5 (0x105)
928#define SPR_USPRG6 (0x106)
929#define SPR_USPRG7 (0x107)
930#define SPR_VTBL (0x10C)
931#define SPR_VTBU (0x10D)
932#define SPR_SPRG0 (0x110)
933#define SPR_SPRG1 (0x111)
934#define SPR_SPRG2 (0x112)
935#define SPR_SPRG3 (0x113)
936#define SPR_SPRG4 (0x114)
937#define SPR_SCOMC (0x114)
938#define SPR_SPRG5 (0x115)
939#define SPR_SCOMD (0x115)
940#define SPR_SPRG6 (0x116)
941#define SPR_SPRG7 (0x117)
942#define SPR_ASR (0x118)
943#define SPR_EAR (0x11A)
944#define SPR_TBL (0x11C)
945#define SPR_TBU (0x11D)
946#define SPR_TBU40 (0x11E)
947#define SPR_SVR (0x11E)
948#define SPR_BOOKE_PIR (0x11E)
949#define SPR_PVR (0x11F)
950#define SPR_HSPRG0 (0x130)
951#define SPR_BOOKE_DBSR (0x130)
952#define SPR_HSPRG1 (0x131)
953#define SPR_HDSISR (0x132)
954#define SPR_HDAR (0x133)
955#define SPR_BOOKE_DBCR0 (0x134)
956#define SPR_IBCR (0x135)
957#define SPR_PURR (0x135)
958#define SPR_BOOKE_DBCR1 (0x135)
959#define SPR_DBCR (0x136)
960#define SPR_HDEC (0x136)
961#define SPR_BOOKE_DBCR2 (0x136)
962#define SPR_HIOR (0x137)
963#define SPR_MBAR (0x137)
964#define SPR_RMOR (0x138)
965#define SPR_BOOKE_IAC1 (0x138)
966#define SPR_HRMOR (0x139)
967#define SPR_BOOKE_IAC2 (0x139)
968#define SPR_HSRR0 (0x13A)
969#define SPR_BOOKE_IAC3 (0x13A)
970#define SPR_HSRR1 (0x13B)
971#define SPR_BOOKE_IAC4 (0x13B)
972#define SPR_LPCR (0x13C)
973#define SPR_BOOKE_DAC1 (0x13C)
974#define SPR_LPIDR (0x13D)
975#define SPR_DABR2 (0x13D)
976#define SPR_BOOKE_DAC2 (0x13D)
977#define SPR_BOOKE_DVC1 (0x13E)
978#define SPR_BOOKE_DVC2 (0x13F)
979#define SPR_BOOKE_TSR (0x150)
980#define SPR_BOOKE_TCR (0x154)
981#define SPR_BOOKE_IVOR0 (0x190)
982#define SPR_BOOKE_IVOR1 (0x191)
983#define SPR_BOOKE_IVOR2 (0x192)
984#define SPR_BOOKE_IVOR3 (0x193)
985#define SPR_BOOKE_IVOR4 (0x194)
986#define SPR_BOOKE_IVOR5 (0x195)
987#define SPR_BOOKE_IVOR6 (0x196)
988#define SPR_BOOKE_IVOR7 (0x197)
989#define SPR_BOOKE_IVOR8 (0x198)
990#define SPR_BOOKE_IVOR9 (0x199)
991#define SPR_BOOKE_IVOR10 (0x19A)
992#define SPR_BOOKE_IVOR11 (0x19B)
993#define SPR_BOOKE_IVOR12 (0x19C)
994#define SPR_BOOKE_IVOR13 (0x19D)
995#define SPR_BOOKE_IVOR14 (0x19E)
996#define SPR_BOOKE_IVOR15 (0x19F)
997#define SPR_BOOKE_SPEFSCR (0x200)
998#define SPR_Exxx_BBEAR (0x201)
999#define SPR_Exxx_BBTAR (0x202)
1000#define SPR_Exxx_L1CFG0 (0x203)
1001#define SPR_Exxx_NPIDR (0x205)
1002#define SPR_ATBL (0x20E)
1003#define SPR_ATBU (0x20F)
1004#define SPR_IBAT0U (0x210)
1005#define SPR_BOOKE_IVOR32 (0x210)
1006#define SPR_RCPU_MI_GRA (0x210)
1007#define SPR_IBAT0L (0x211)
1008#define SPR_BOOKE_IVOR33 (0x211)
1009#define SPR_IBAT1U (0x212)
1010#define SPR_BOOKE_IVOR34 (0x212)
1011#define SPR_IBAT1L (0x213)
1012#define SPR_BOOKE_IVOR35 (0x213)
1013#define SPR_IBAT2U (0x214)
1014#define SPR_BOOKE_IVOR36 (0x214)
1015#define SPR_IBAT2L (0x215)
1016#define SPR_BOOKE_IVOR37 (0x215)
1017#define SPR_IBAT3U (0x216)
1018#define SPR_IBAT3L (0x217)
1019#define SPR_DBAT0U (0x218)
1020#define SPR_RCPU_L2U_GRA (0x218)
1021#define SPR_DBAT0L (0x219)
1022#define SPR_DBAT1U (0x21A)
1023#define SPR_DBAT1L (0x21B)
1024#define SPR_DBAT2U (0x21C)
1025#define SPR_DBAT2L (0x21D)
1026#define SPR_DBAT3U (0x21E)
1027#define SPR_DBAT3L (0x21F)
1028#define SPR_IBAT4U (0x230)
1029#define SPR_RPCU_BBCMCR (0x230)
1030#define SPR_MPC_IC_CST (0x230)
1031#define SPR_Exxx_CTXCR (0x230)
1032#define SPR_IBAT4L (0x231)
1033#define SPR_MPC_IC_ADR (0x231)
1034#define SPR_Exxx_DBCR3 (0x231)
1035#define SPR_IBAT5U (0x232)
1036#define SPR_MPC_IC_DAT (0x232)
1037#define SPR_Exxx_DBCNT (0x232)
1038#define SPR_IBAT5L (0x233)
1039#define SPR_IBAT6U (0x234)
1040#define SPR_IBAT6L (0x235)
1041#define SPR_IBAT7U (0x236)
1042#define SPR_IBAT7L (0x237)
1043#define SPR_DBAT4U (0x238)
1044#define SPR_RCPU_L2U_MCR (0x238)
1045#define SPR_MPC_DC_CST (0x238)
1046#define SPR_Exxx_ALTCTXCR (0x238)
1047#define SPR_DBAT4L (0x239)
1048#define SPR_MPC_DC_ADR (0x239)
1049#define SPR_DBAT5U (0x23A)
1050#define SPR_BOOKE_MCSRR0 (0x23A)
1051#define SPR_MPC_DC_DAT (0x23A)
1052#define SPR_DBAT5L (0x23B)
1053#define SPR_BOOKE_MCSRR1 (0x23B)
1054#define SPR_DBAT6U (0x23C)
1055#define SPR_BOOKE_MCSR (0x23C)
1056#define SPR_DBAT6L (0x23D)
1057#define SPR_Exxx_MCAR (0x23D)
1058#define SPR_DBAT7U (0x23E)
1059#define SPR_BOOKE_DSRR0 (0x23E)
1060#define SPR_DBAT7L (0x23F)
1061#define SPR_BOOKE_DSRR1 (0x23F)
1062#define SPR_BOOKE_SPRG8 (0x25C)
1063#define SPR_BOOKE_SPRG9 (0x25D)
1064#define SPR_BOOKE_MAS0 (0x270)
1065#define SPR_BOOKE_MAS1 (0x271)
1066#define SPR_BOOKE_MAS2 (0x272)
1067#define SPR_BOOKE_MAS3 (0x273)
1068#define SPR_BOOKE_MAS4 (0x274)
1069#define SPR_BOOKE_MAS5 (0x275)
1070#define SPR_BOOKE_MAS6 (0x276)
1071#define SPR_BOOKE_PID1 (0x279)
1072#define SPR_BOOKE_PID2 (0x27A)
1073#define SPR_MPC_DPDR (0x280)
1074#define SPR_MPC_IMMR (0x288)
1075#define SPR_BOOKE_TLB0CFG (0x2B0)
1076#define SPR_BOOKE_TLB1CFG (0x2B1)
1077#define SPR_BOOKE_TLB2CFG (0x2B2)
1078#define SPR_BOOKE_TLB3CFG (0x2B3)
1079#define SPR_BOOKE_EPR (0x2BE)
1080#define SPR_PERF0 (0x300)
1081#define SPR_RCPU_MI_RBA0 (0x300)
1082#define SPR_MPC_MI_CTR (0x300)
1083#define SPR_PERF1 (0x301)
1084#define SPR_RCPU_MI_RBA1 (0x301)
1085#define SPR_PERF2 (0x302)
1086#define SPR_RCPU_MI_RBA2 (0x302)
1087#define SPR_MPC_MI_AP (0x302)
1088#define SPR_PERF3 (0x303)
082c6681 1089#define SPR_620_PMC1R (0x303)
80d11f44
JM		 1090#define SPR_RCPU_MI_RBA3 (0x303)
1091#define SPR_MPC_MI_EPN (0x303)
1092#define SPR_PERF4 (0x304)
082c6681 1093#define SPR_620_PMC2R (0x304)
80d11f44
JM		 1094#define SPR_PERF5 (0x305)
1095#define SPR_MPC_MI_TWC (0x305)
1096#define SPR_PERF6 (0x306)
1097#define SPR_MPC_MI_RPN (0x306)
1098#define SPR_PERF7 (0x307)
1099#define SPR_PERF8 (0x308)
1100#define SPR_RCPU_L2U_RBA0 (0x308)
1101#define SPR_MPC_MD_CTR (0x308)
1102#define SPR_PERF9 (0x309)
1103#define SPR_RCPU_L2U_RBA1 (0x309)
1104#define SPR_MPC_MD_CASID (0x309)
1105#define SPR_PERFA (0x30A)
1106#define SPR_RCPU_L2U_RBA2 (0x30A)
1107#define SPR_MPC_MD_AP (0x30A)
1108#define SPR_PERFB (0x30B)
082c6681 1109#define SPR_620_MMCR0R (0x30B)
80d11f44
JM		 1110#define SPR_RCPU_L2U_RBA3 (0x30B)
1111#define SPR_MPC_MD_EPN (0x30B)
1112#define SPR_PERFC (0x30C)
1113#define SPR_MPC_MD_TWB (0x30C)
1114#define SPR_PERFD (0x30D)
1115#define SPR_MPC_MD_TWC (0x30D)
1116#define SPR_PERFE (0x30E)
1117#define SPR_MPC_MD_RPN (0x30E)
1118#define SPR_PERFF (0x30F)
1119#define SPR_MPC_MD_TW (0x30F)
1120#define SPR_UPERF0 (0x310)
1121#define SPR_UPERF1 (0x311)
1122#define SPR_UPERF2 (0x312)
1123#define SPR_UPERF3 (0x313)
082c6681 1124#define SPR_620_PMC1W (0x313)
80d11f44 1125#define SPR_UPERF4 (0x314)
082c6681 1126#define SPR_620_PMC2W (0x314)
80d11f44
JM		 1127#define SPR_UPERF5 (0x315)
1128#define SPR_UPERF6 (0x316)
1129#define SPR_UPERF7 (0x317)
1130#define SPR_UPERF8 (0x318)
1131#define SPR_UPERF9 (0x319)
1132#define SPR_UPERFA (0x31A)
1133#define SPR_UPERFB (0x31B)
082c6681 1134#define SPR_620_MMCR0W (0x31B)
80d11f44
JM		 1135#define SPR_UPERFC (0x31C)
1136#define SPR_UPERFD (0x31D)
1137#define SPR_UPERFE (0x31E)
1138#define SPR_UPERFF (0x31F)
1139#define SPR_RCPU_MI_RA0 (0x320)
1140#define SPR_MPC_MI_DBCAM (0x320)
1141#define SPR_RCPU_MI_RA1 (0x321)
1142#define SPR_MPC_MI_DBRAM0 (0x321)
1143#define SPR_RCPU_MI_RA2 (0x322)
1144#define SPR_MPC_MI_DBRAM1 (0x322)
1145#define SPR_RCPU_MI_RA3 (0x323)
1146#define SPR_RCPU_L2U_RA0 (0x328)
1147#define SPR_MPC_MD_DBCAM (0x328)
1148#define SPR_RCPU_L2U_RA1 (0x329)
1149#define SPR_MPC_MD_DBRAM0 (0x329)
1150#define SPR_RCPU_L2U_RA2 (0x32A)
1151#define SPR_MPC_MD_DBRAM1 (0x32A)
1152#define SPR_RCPU_L2U_RA3 (0x32B)
1153#define SPR_440_INV0 (0x370)
1154#define SPR_440_INV1 (0x371)
1155#define SPR_440_INV2 (0x372)
1156#define SPR_440_INV3 (0x373)
1157#define SPR_440_ITV0 (0x374)
1158#define SPR_440_ITV1 (0x375)
1159#define SPR_440_ITV2 (0x376)
1160#define SPR_440_ITV3 (0x377)
1161#define SPR_440_CCR1 (0x378)
1162#define SPR_DCRIPR (0x37B)
1163#define SPR_PPR (0x380)
bd928eba 1164#define SPR_750_GQR0 (0x390)
80d11f44 1165#define SPR_440_DNV0 (0x390)
bd928eba 1166#define SPR_750_GQR1 (0x391)
80d11f44 1167#define SPR_440_DNV1 (0x391)
bd928eba 1168#define SPR_750_GQR2 (0x392)
80d11f44 1169#define SPR_440_DNV2 (0x392)
bd928eba 1170#define SPR_750_GQR3 (0x393)
80d11f44 1171#define SPR_440_DNV3 (0x393)
bd928eba 1172#define SPR_750_GQR4 (0x394)
80d11f44 1173#define SPR_440_DTV0 (0x394)
bd928eba 1174#define SPR_750_GQR5 (0x395)
80d11f44 1175#define SPR_440_DTV1 (0x395)
bd928eba 1176#define SPR_750_GQR6 (0x396)
80d11f44 1177#define SPR_440_DTV2 (0x396)
bd928eba 1178#define SPR_750_GQR7 (0x397)
80d11f44 1179#define SPR_440_DTV3 (0x397)
bd928eba
JM		 1180#define SPR_750_THRM4 (0x398)
1181#define SPR_750CL_HID2 (0x398)
80d11f44 1182#define SPR_440_DVLIM (0x398)
bd928eba 1183#define SPR_750_WPAR (0x399)
80d11f44 1184#define SPR_440_IVLIM (0x399)
bd928eba
JM		 1185#define SPR_750_DMAU (0x39A)
1186#define SPR_750_DMAL (0x39B)
80d11f44
JM		 1187#define SPR_440_RSTCFG (0x39B)
1188#define SPR_BOOKE_DCDBTRL (0x39C)
1189#define SPR_BOOKE_DCDBTRH (0x39D)
1190#define SPR_BOOKE_ICDBTRL (0x39E)
1191#define SPR_BOOKE_ICDBTRH (0x39F)
1192#define SPR_UMMCR2 (0x3A0)
1193#define SPR_UPMC5 (0x3A1)
1194#define SPR_UPMC6 (0x3A2)
1195#define SPR_UBAMR (0x3A7)
1196#define SPR_UMMCR0 (0x3A8)
1197#define SPR_UPMC1 (0x3A9)
1198#define SPR_UPMC2 (0x3AA)
1199#define SPR_USIAR (0x3AB)
1200#define SPR_UMMCR1 (0x3AC)
1201#define SPR_UPMC3 (0x3AD)
1202#define SPR_UPMC4 (0x3AE)
1203#define SPR_USDA (0x3AF)
1204#define SPR_40x_ZPR (0x3B0)
1205#define SPR_BOOKE_MAS7 (0x3B0)
1206#define SPR_620_PMR0 (0x3B0)
1207#define SPR_MMCR2 (0x3B0)
1208#define SPR_PMC5 (0x3B1)
1209#define SPR_40x_PID (0x3B1)
1210#define SPR_620_PMR1 (0x3B1)
1211#define SPR_PMC6 (0x3B2)
1212#define SPR_440_MMUCR (0x3B2)
1213#define SPR_620_PMR2 (0x3B2)
1214#define SPR_4xx_CCR0 (0x3B3)
1215#define SPR_BOOKE_EPLC (0x3B3)
1216#define SPR_620_PMR3 (0x3B3)
1217#define SPR_405_IAC3 (0x3B4)
1218#define SPR_BOOKE_EPSC (0x3B4)
1219#define SPR_620_PMR4 (0x3B4)
1220#define SPR_405_IAC4 (0x3B5)
1221#define SPR_620_PMR5 (0x3B5)
1222#define SPR_405_DVC1 (0x3B6)
1223#define SPR_620_PMR6 (0x3B6)
1224#define SPR_405_DVC2 (0x3B7)
1225#define SPR_620_PMR7 (0x3B7)
1226#define SPR_BAMR (0x3B7)
1227#define SPR_MMCR0 (0x3B8)
1228#define SPR_620_PMR8 (0x3B8)
1229#define SPR_PMC1 (0x3B9)
1230#define SPR_40x_SGR (0x3B9)
1231#define SPR_620_PMR9 (0x3B9)
1232#define SPR_PMC2 (0x3BA)
1233#define SPR_40x_DCWR (0x3BA)
1234#define SPR_620_PMRA (0x3BA)
1235#define SPR_SIAR (0x3BB)
1236#define SPR_405_SLER (0x3BB)
1237#define SPR_620_PMRB (0x3BB)
1238#define SPR_MMCR1 (0x3BC)
1239#define SPR_405_SU0R (0x3BC)
1240#define SPR_620_PMRC (0x3BC)
1241#define SPR_401_SKR (0x3BC)
1242#define SPR_PMC3 (0x3BD)
1243#define SPR_405_DBCR1 (0x3BD)
1244#define SPR_620_PMRD (0x3BD)
1245#define SPR_PMC4 (0x3BE)
1246#define SPR_620_PMRE (0x3BE)
1247#define SPR_SDA (0x3BF)
1248#define SPR_620_PMRF (0x3BF)
1249#define SPR_403_VTBL (0x3CC)
1250#define SPR_403_VTBU (0x3CD)
1251#define SPR_DMISS (0x3D0)
1252#define SPR_DCMP (0x3D1)
1253#define SPR_HASH1 (0x3D2)
1254#define SPR_HASH2 (0x3D3)
1255#define SPR_BOOKE_ICDBDR (0x3D3)
1256#define SPR_TLBMISS (0x3D4)
1257#define SPR_IMISS (0x3D4)
1258#define SPR_40x_ESR (0x3D4)
1259#define SPR_PTEHI (0x3D5)
1260#define SPR_ICMP (0x3D5)
1261#define SPR_40x_DEAR (0x3D5)
1262#define SPR_PTELO (0x3D6)
1263#define SPR_RPA (0x3D6)
1264#define SPR_40x_EVPR (0x3D6)
1265#define SPR_L3PM (0x3D7)
1266#define SPR_403_CDBCR (0x3D7)
4e777442 1267#define SPR_L3ITCR0 (0x3D8)
80d11f44
JM		 1268#define SPR_TCR (0x3D8)
1269#define SPR_40x_TSR (0x3D8)
1270#define SPR_IBR (0x3DA)
1271#define SPR_40x_TCR (0x3DA)
1272#define SPR_ESASRR (0x3DB)
1273#define SPR_40x_PIT (0x3DB)
1274#define SPR_403_TBL (0x3DC)
1275#define SPR_403_TBU (0x3DD)
1276#define SPR_SEBR (0x3DE)
1277#define SPR_40x_SRR2 (0x3DE)
1278#define SPR_SER (0x3DF)
1279#define SPR_40x_SRR3 (0x3DF)
4e777442 1280#define SPR_L3OHCR (0x3E8)
80d11f44
JM		 1281#define SPR_L3ITCR1 (0x3E9)
1282#define SPR_L3ITCR2 (0x3EA)
1283#define SPR_L3ITCR3 (0x3EB)
1284#define SPR_HID0 (0x3F0)
1285#define SPR_40x_DBSR (0x3F0)
1286#define SPR_HID1 (0x3F1)
1287#define SPR_IABR (0x3F2)
1288#define SPR_40x_DBCR0 (0x3F2)
1289#define SPR_601_HID2 (0x3F2)
1290#define SPR_Exxx_L1CSR0 (0x3F2)
1291#define SPR_ICTRL (0x3F3)
1292#define SPR_HID2 (0x3F3)
bd928eba 1293#define SPR_750CL_HID4 (0x3F3)
80d11f44
JM		 1294#define SPR_Exxx_L1CSR1 (0x3F3)
1295#define SPR_440_DBDR (0x3F3)
1296#define SPR_LDSTDB (0x3F4)
bd928eba 1297#define SPR_750_TDCL (0x3F4)
80d11f44
JM		 1298#define SPR_40x_IAC1 (0x3F4)
1299#define SPR_MMUCSR0 (0x3F4)
1300#define SPR_DABR (0x3F5)
3fc6c082 1301#define DABR_MASK (~(target_ulong)0x7)
80d11f44
JM		 1302#define SPR_Exxx_BUCSR (0x3F5)
1303#define SPR_40x_IAC2 (0x3F5)
1304#define SPR_601_HID5 (0x3F5)
1305#define SPR_40x_DAC1 (0x3F6)
1306#define SPR_MSSCR0 (0x3F6)
1307#define SPR_970_HID5 (0x3F6)
1308#define SPR_MSSSR0 (0x3F7)
4e777442 1309#define SPR_MSSCR1 (0x3F7)
80d11f44
JM		 1310#define SPR_DABRX (0x3F7)
1311#define SPR_40x_DAC2 (0x3F7)
1312#define SPR_MMUCFG (0x3F7)
1313#define SPR_LDSTCR (0x3F8)
1314#define SPR_L2PMCR (0x3F8)
bd928eba 1315#define SPR_750FX_HID2 (0x3F8)
082c6681 1316#define SPR_620_BUSCSR (0x3F8)
80d11f44
JM		 1317#define SPR_Exxx_L1FINV0 (0x3F8)
1318#define SPR_L2CR (0x3F9)
082c6681 1319#define SPR_620_L2CR (0x3F9)
80d11f44 1320#define SPR_L3CR (0x3FA)
bd928eba 1321#define SPR_750_TDCH (0x3FA)
80d11f44
JM		 1322#define SPR_IABR2 (0x3FA)
1323#define SPR_40x_DCCR (0x3FA)
082c6681 1324#define SPR_620_L2SR (0x3FA)
80d11f44
JM		 1325#define SPR_ICTC (0x3FB)
1326#define SPR_40x_ICCR (0x3FB)
1327#define SPR_THRM1 (0x3FC)
1328#define SPR_403_PBL1 (0x3FC)
1329#define SPR_SP (0x3FD)
1330#define SPR_THRM2 (0x3FD)
1331#define SPR_403_PBU1 (0x3FD)
1332#define SPR_604_HID13 (0x3FD)
1333#define SPR_LT (0x3FE)
1334#define SPR_THRM3 (0x3FE)
1335#define SPR_RCPU_FPECR (0x3FE)
1336#define SPR_403_PBL2 (0x3FE)
1337#define SPR_PIR (0x3FF)
1338#define SPR_403_PBU2 (0x3FF)
1339#define SPR_601_HID15 (0x3FF)
1340#define SPR_604_HID15 (0x3FF)
1341#define SPR_E500_SVR (0x3FF)
79aceca5 1342
c29b735c
NF		 1343/*****************************************************************************/
1344/* PowerPC Instructions types definitions */
1345enum {
1346 PPC_NONE = 0x0000000000000000ULL,
1347 /* PowerPC base instructions set */
1348 PPC_INSNS_BASE = 0x0000000000000001ULL,
1349 /* integer operations instructions */
1350#define PPC_INTEGER PPC_INSNS_BASE
1351 /* flow control instructions */
1352#define PPC_FLOW PPC_INSNS_BASE
1353 /* virtual memory instructions */
1354#define PPC_MEM PPC_INSNS_BASE
1355 /* ld/st with reservation instructions */
1356#define PPC_RES PPC_INSNS_BASE
1357 /* spr/msr access instructions */
1358#define PPC_MISC PPC_INSNS_BASE
1359 /* Deprecated instruction sets */
1360 /* Original POWER instruction set */
1361 PPC_POWER = 0x0000000000000002ULL,
1362 /* POWER2 instruction set extension */
1363 PPC_POWER2 = 0x0000000000000004ULL,
1364 /* Power RTC support */
1365 PPC_POWER_RTC = 0x0000000000000008ULL,
1366 /* Power-to-PowerPC bridge (601) */
1367 PPC_POWER_BR = 0x0000000000000010ULL,
1368 /* 64 bits PowerPC instruction set */
1369 PPC_64B = 0x0000000000000020ULL,
1370 /* New 64 bits extensions (PowerPC 2.0x) */
1371 PPC_64BX = 0x0000000000000040ULL,
1372 /* 64 bits hypervisor extensions */
1373 PPC_64H = 0x0000000000000080ULL,
1374 /* New wait instruction (PowerPC 2.0x) */
1375 PPC_WAIT = 0x0000000000000100ULL,
1376 /* Time base mftb instruction */
1377 PPC_MFTB = 0x0000000000000200ULL,
1378
1379 /* Fixed-point unit extensions */
1380 /* PowerPC 602 specific */
1381 PPC_602_SPEC = 0x0000000000000400ULL,
1382 /* isel instruction */
1383 PPC_ISEL = 0x0000000000000800ULL,
1384 /* popcntb instruction */
1385 PPC_POPCNTB = 0x0000000000001000ULL,
1386 /* string load / store */
1387 PPC_STRING = 0x0000000000002000ULL,
1388
1389 /* Floating-point unit extensions */
1390 /* Optional floating point instructions */
1391 PPC_FLOAT = 0x0000000000010000ULL,
1392 /* New floating-point extensions (PowerPC 2.0x) */
1393 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1394 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1395 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1396 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1397 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1398 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1399 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1400
1401 /* Vector/SIMD extensions */
1402 /* Altivec support */
1403 PPC_ALTIVEC = 0x0000000001000000ULL,
1404 /* PowerPC 2.03 SPE extension */
1405 PPC_SPE = 0x0000000002000000ULL,
1406 /* PowerPC 2.03 SPE single-precision floating-point extension */
1407 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1408 /* PowerPC 2.03 SPE double-precision floating-point extension */
1409 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1410
1411 /* Optional memory control instructions */
1412 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1413 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1414 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1415 /* sync instruction */
1416 PPC_MEM_SYNC = 0x0000000080000000ULL,
1417 /* eieio instruction */
1418 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1419
1420 /* Cache control instructions */
1421 PPC_CACHE = 0x0000000200000000ULL,
1422 /* icbi instruction */
1423 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1424 /* dcbz instruction with fixed cache line size */
1425 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1426 /* dcbz instruction with tunable cache line size */
1427 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1428 /* dcba instruction */
1429 PPC_CACHE_DCBA = 0x0000002000000000ULL,
1430 /* Freescale cache locking instructions */
1431 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1432
1433 /* MMU related extensions */
1434 /* external control instructions */
1435 PPC_EXTERN = 0x0000010000000000ULL,
1436 /* segment register access instructions */
1437 PPC_SEGMENT = 0x0000020000000000ULL,
1438 /* PowerPC 6xx TLB management instructions */
1439 PPC_6xx_TLB = 0x0000040000000000ULL,
1440 /* PowerPC 74xx TLB management instructions */
1441 PPC_74xx_TLB = 0x0000080000000000ULL,
1442 /* PowerPC 40x TLB management instructions */
1443 PPC_40x_TLB = 0x0000100000000000ULL,
1444 /* segment register access instructions for PowerPC 64 "bridge" */
1445 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1446 /* SLB management */
1447 PPC_SLBI = 0x0000400000000000ULL,
1448
1449 /* Embedded PowerPC dedicated instructions */
1450 PPC_WRTEE = 0x0001000000000000ULL,
1451 /* PowerPC 40x exception model */
1452 PPC_40x_EXCP = 0x0002000000000000ULL,
1453 /* PowerPC 405 Mac instructions */
1454 PPC_405_MAC = 0x0004000000000000ULL,
1455 /* PowerPC 440 specific instructions */
1456 PPC_440_SPEC = 0x0008000000000000ULL,
1457 /* BookE (embedded) PowerPC specification */
1458 PPC_BOOKE = 0x0010000000000000ULL,
1459 /* mfapidi instruction */
1460 PPC_MFAPIDI = 0x0020000000000000ULL,
1461 /* tlbiva instruction */
1462 PPC_TLBIVA = 0x0040000000000000ULL,
1463 /* tlbivax instruction */
1464 PPC_TLBIVAX = 0x0080000000000000ULL,
1465 /* PowerPC 4xx dedicated instructions */
1466 PPC_4xx_COMMON = 0x0100000000000000ULL,
1467 /* PowerPC 40x ibct instructions */
1468 PPC_40x_ICBT = 0x0200000000000000ULL,
1469 /* rfmci is not implemented in all BookE PowerPC */
1470 PPC_RFMCI = 0x0400000000000000ULL,
1471 /* rfdi instruction */
1472 PPC_RFDI = 0x0800000000000000ULL,
1473 /* DCR accesses */
1474 PPC_DCR = 0x1000000000000000ULL,
1475 /* DCR extended accesse */
1476 PPC_DCRX = 0x2000000000000000ULL,
1477 /* user-mode DCR access, implemented in PowerPC 460 */
1478 PPC_DCRUX = 0x4000000000000000ULL,
1479};
1480
76a66253 1481/*****************************************************************************/
9a64fbe4
FB		 1482/* Memory access type :
1483 * may be needed for precise access rights control and precise exceptions.
1484 */
79aceca5 1485enum {
9a64fbe4
FB		 1486 /* 1 bit to define user level / supervisor access */
1487 ACCESS_USER = 0x00,
1488 ACCESS_SUPER = 0x01,
1489 /* Type of instruction that generated the access */
1490 ACCESS_CODE = 0x10, /* Code fetch access */
1491 ACCESS_INT = 0x20, /* Integer load/store access */
1492 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1493 ACCESS_RES = 0x40, /* load/store with reservation */
1494 ACCESS_EXT = 0x50, /* external access */
1495 ACCESS_CACHE = 0x60, /* Cache manipulation */
1496};
1497
47103572
JM		 1498/* Hardware interruption sources:
1499 * all those exception can be raised simulteaneously
1500 */
e9df014c
JM		 1501/* Input pins definitions */
1502enum {
1503 /* 6xx bus input pins */
24be5ae3
JM		 1504 PPC6xx_INPUT_HRESET = 0,
1505 PPC6xx_INPUT_SRESET = 1,
1506 PPC6xx_INPUT_CKSTP_IN = 2,
1507 PPC6xx_INPUT_MCP = 3,
1508 PPC6xx_INPUT_SMI = 4,
1509 PPC6xx_INPUT_INT = 5,
d68f1306
JM		 1510 PPC6xx_INPUT_TBEN = 6,
1511 PPC6xx_INPUT_WAKEUP = 7,
1512 PPC6xx_INPUT_NB,
24be5ae3
JM		 1513};
1514
1515enum {
e9df014c 1516 /* Embedded PowerPC input pins */
24be5ae3
JM		 1517 PPCBookE_INPUT_HRESET = 0,
1518 PPCBookE_INPUT_SRESET = 1,
1519 PPCBookE_INPUT_CKSTP_IN = 2,
1520 PPCBookE_INPUT_MCP = 3,
1521 PPCBookE_INPUT_SMI = 4,
1522 PPCBookE_INPUT_INT = 5,
1523 PPCBookE_INPUT_CINT = 6,
d68f1306 1524 PPCBookE_INPUT_NB,
24be5ae3
JM		 1525};
1526
9fdc60bf
AJ		 1527enum {
1528 /* PowerPC E500 input pins */
1529 PPCE500_INPUT_RESET_CORE = 0,
1530 PPCE500_INPUT_MCK = 1,
1531 PPCE500_INPUT_CINT = 3,
1532 PPCE500_INPUT_INT = 4,
1533 PPCE500_INPUT_DEBUG = 6,
1534 PPCE500_INPUT_NB,
1535};
1536
a750fc0b 1537enum {
4e290a0b
JM		 1538 /* PowerPC 40x input pins */
1539 PPC40x_INPUT_RESET_CORE = 0,
1540 PPC40x_INPUT_RESET_CHIP = 1,
1541 PPC40x_INPUT_RESET_SYS = 2,
1542 PPC40x_INPUT_CINT = 3,
1543 PPC40x_INPUT_INT = 4,
1544 PPC40x_INPUT_HALT = 5,
1545 PPC40x_INPUT_DEBUG = 6,
1546 PPC40x_INPUT_NB,
e9df014c
JM		 1547};
1548
b4095fed
JM		 1549enum {
1550 /* RCPU input pins */
1551 PPCRCPU_INPUT_PORESET = 0,
1552 PPCRCPU_INPUT_HRESET = 1,
1553 PPCRCPU_INPUT_SRESET = 2,
1554 PPCRCPU_INPUT_IRQ0 = 3,
1555 PPCRCPU_INPUT_IRQ1 = 4,
1556 PPCRCPU_INPUT_IRQ2 = 5,
1557 PPCRCPU_INPUT_IRQ3 = 6,
1558 PPCRCPU_INPUT_IRQ4 = 7,
1559 PPCRCPU_INPUT_IRQ5 = 8,
1560 PPCRCPU_INPUT_IRQ6 = 9,
1561 PPCRCPU_INPUT_IRQ7 = 10,
1562 PPCRCPU_INPUT_NB,
1563};
1564
00af685f 1565#if defined(TARGET_PPC64)
d0dfae6e
JM		 1566enum {
1567 /* PowerPC 970 input pins */
1568 PPC970_INPUT_HRESET = 0,
1569 PPC970_INPUT_SRESET = 1,
1570 PPC970_INPUT_CKSTP = 2,
1571 PPC970_INPUT_TBEN = 3,
1572 PPC970_INPUT_MCP = 4,
1573 PPC970_INPUT_INT = 5,
1574 PPC970_INPUT_THINT = 6,
7b62a955 1575 PPC970_INPUT_NB,
d0dfae6e 1576};
00af685f 1577#endif
d0dfae6e 1578
e9df014c 1579/* Hardware exceptions definitions */
47103572 1580enum {
e9df014c 1581 /* External hardware exception sources */
e1833e1f 1582 PPC_INTERRUPT_RESET = 0, /* Reset exception */
d68f1306
JM		 1583 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
1584 PPC_INTERRUPT_MCK, /* Machine check exception */
1585 PPC_INTERRUPT_EXT, /* External interrupt */
1586 PPC_INTERRUPT_SMI, /* System management interrupt */
1587 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
1588 PPC_INTERRUPT_DEBUG, /* External debug exception */
1589 PPC_INTERRUPT_THERM, /* Thermal exception */
e9df014c 1590 /* Internal hardware exception sources */
d68f1306
JM		 1591 PPC_INTERRUPT_DECR, /* Decrementer exception */
1592 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
1593 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
1594 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
1595 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
1596 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
1597 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
1598 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
47103572
JM		 1599};
1600
9a64fbe4
FB		 1601/*****************************************************************************/
1602
6b917547
AL		 1603static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
1604 target_ulong *cs_base, int *flags)
1605{
1606 *pc = env->nip;
1607 *cs_base = 0;
1608 *flags = env->hflags;
1609}
1610
174c80d5
NF		 1611static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
1612{
1613#if defined(TARGET_PPC64)
1614 /* The kernel checks TIF_32BIT here; we don't support loading 32-bit
1615 binaries on PPC64 yet. */
1616 env->gpr[13] = newtls;
1617#else
1618 env->gpr[2] = newtls;
1619#endif
1620}
1621
79aceca5 1622#endif /* !defined (__CPU_PPC_H__) */
Qemu copy for testing