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79aceca5 1/*
3fc6c082 2 * PowerPC emulation cpu definitions for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
79aceca5
FB
18 */
19#if !defined (__CPU_PPC_H__)
20#define __CPU_PPC_H__
21
3fc6c082 22#include "config.h"
9a78eead 23#include "qemu-common.h"
3fc6c082 24
a4f30719
JM
25//#define PPC_EMULATE_32BITS_HYPV
26
76a66253 27#if defined (TARGET_PPC64)
3cd7d1dd 28/* PowerPC 64 definitions */
d9d7210c 29#define TARGET_LONG_BITS 64
35cdaad6 30#define TARGET_PAGE_BITS 12
3cd7d1dd 31
52705890
RH
32/* Note that the official physical address space bits is 62-M where M
33 is implementation dependent. I've not looked up M for the set of
34 cpus we emulate at the system level. */
35#define TARGET_PHYS_ADDR_SPACE_BITS 62
36
37/* Note that the PPC environment architecture talks about 80 bit virtual
38 addresses, with segmentation. Obviously that's not all visible to a
39 single process, which is all we're concerned with here. */
40#ifdef TARGET_ABI32
41# define TARGET_VIRT_ADDR_SPACE_BITS 32
42#else
43# define TARGET_VIRT_ADDR_SPACE_BITS 64
44#endif
45
81762d6d
DG
46#define TARGET_PAGE_BITS_16M 24
47
3cd7d1dd
JM
48#else /* defined (TARGET_PPC64) */
49/* PowerPC 32 definitions */
d9d7210c 50#define TARGET_LONG_BITS 32
3cd7d1dd
JM
51
52#if defined(TARGET_PPCEMB)
53/* Specific definitions for PowerPC embedded */
54/* BookE have 36 bits physical address space */
3cd7d1dd
JM
55#if defined(CONFIG_USER_ONLY)
56/* It looks like a lot of Linux programs assume page size
57 * is 4kB long. This is evil, but we have to deal with it...
58 */
35cdaad6 59#define TARGET_PAGE_BITS 12
3cd7d1dd
JM
60#else /* defined(CONFIG_USER_ONLY) */
61/* Pages can be 1 kB small */
62#define TARGET_PAGE_BITS 10
63#endif /* defined(CONFIG_USER_ONLY) */
64#else /* defined(TARGET_PPCEMB) */
65/* "standard" PowerPC 32 definitions */
66#define TARGET_PAGE_BITS 12
67#endif /* defined(TARGET_PPCEMB) */
68
52705890
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69#define TARGET_PHYS_ADDR_SPACE_BITS 32
70#define TARGET_VIRT_ADDR_SPACE_BITS 32
71
3cd7d1dd 72#endif /* defined (TARGET_PPC64) */
3cf1e035 73
c2764719
PB
74#define CPUState struct CPUPPCState
75
79aceca5
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76#include "cpu-defs.h"
77
4ecc3190
FB
78#include "softfloat.h"
79
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80#define TARGET_HAS_ICE 1
81
7f70c937 82#if defined (TARGET_PPC64)
76a66253
JM
83#define ELF_MACHINE EM_PPC64
84#else
85#define ELF_MACHINE EM_PPC
86#endif
9042c0e2 87
3fc6c082 88/*****************************************************************************/
a750fc0b 89/* MMU model */
c227f099
AL
90typedef enum powerpc_mmu_t powerpc_mmu_t;
91enum powerpc_mmu_t {
add78955 92 POWERPC_MMU_UNKNOWN = 0x00000000,
a750fc0b 93 /* Standard 32 bits PowerPC MMU */
add78955 94 POWERPC_MMU_32B = 0x00000001,
a750fc0b 95 /* PowerPC 6xx MMU with software TLB */
add78955 96 POWERPC_MMU_SOFT_6xx = 0x00000002,
a750fc0b 97 /* PowerPC 74xx MMU with software TLB */
add78955 98 POWERPC_MMU_SOFT_74xx = 0x00000003,
a750fc0b 99 /* PowerPC 4xx MMU with software TLB */
add78955 100 POWERPC_MMU_SOFT_4xx = 0x00000004,
a750fc0b 101 /* PowerPC 4xx MMU with software TLB and zones protections */
add78955 102 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
b4095fed 103 /* PowerPC MMU in real mode only */
add78955 104 POWERPC_MMU_REAL = 0x00000006,
b4095fed 105 /* Freescale MPC8xx MMU model */
add78955 106 POWERPC_MMU_MPC8xx = 0x00000007,
a750fc0b 107 /* BookE MMU model */
add78955 108 POWERPC_MMU_BOOKE = 0x00000008,
01662f3e
AG
109 /* BookE 2.06 MMU model */
110 POWERPC_MMU_BOOKE206 = 0x00000009,
faadf50e 111 /* PowerPC 601 MMU model (specific BATs format) */
add78955 112 POWERPC_MMU_601 = 0x0000000A,
00af685f 113#if defined(TARGET_PPC64)
add78955 114#define POWERPC_MMU_64 0x00010000
cdaee006 115#define POWERPC_MMU_1TSEG 0x00020000
12de9a39 116 /* 64 bits PowerPC MMU */
add78955
JM
117 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
118 /* 620 variant (no segment exceptions) */
119 POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002,
9d52e907
DG
120 /* Architecture 2.06 variant */
121 POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | 0x00000003,
00af685f 122#endif /* defined(TARGET_PPC64) */
3fc6c082
FB
123};
124
125/*****************************************************************************/
a750fc0b 126/* Exception model */
c227f099
AL
127typedef enum powerpc_excp_t powerpc_excp_t;
128enum powerpc_excp_t {
a750fc0b 129 POWERPC_EXCP_UNKNOWN = 0,
3fc6c082 130 /* Standard PowerPC exception model */
a750fc0b 131 POWERPC_EXCP_STD,
2662a059 132 /* PowerPC 40x exception model */
a750fc0b 133 POWERPC_EXCP_40x,
2662a059 134 /* PowerPC 601 exception model */
a750fc0b 135 POWERPC_EXCP_601,
2662a059 136 /* PowerPC 602 exception model */
a750fc0b 137 POWERPC_EXCP_602,
2662a059 138 /* PowerPC 603 exception model */
a750fc0b
JM
139 POWERPC_EXCP_603,
140 /* PowerPC 603e exception model */
141 POWERPC_EXCP_603E,
142 /* PowerPC G2 exception model */
143 POWERPC_EXCP_G2,
2662a059 144 /* PowerPC 604 exception model */
a750fc0b 145 POWERPC_EXCP_604,
2662a059 146 /* PowerPC 7x0 exception model */
a750fc0b 147 POWERPC_EXCP_7x0,
2662a059 148 /* PowerPC 7x5 exception model */
a750fc0b 149 POWERPC_EXCP_7x5,
2662a059 150 /* PowerPC 74xx exception model */
a750fc0b 151 POWERPC_EXCP_74xx,
2662a059 152 /* BookE exception model */
a750fc0b 153 POWERPC_EXCP_BOOKE,
00af685f
JM
154#if defined(TARGET_PPC64)
155 /* PowerPC 970 exception model */
156 POWERPC_EXCP_970,
9d52e907
DG
157 /* POWER7 exception model */
158 POWERPC_EXCP_POWER7,
00af685f 159#endif /* defined(TARGET_PPC64) */
a750fc0b
JM
160};
161
e1833e1f
JM
162/*****************************************************************************/
163/* Exception vectors definitions */
164enum {
165 POWERPC_EXCP_NONE = -1,
166 /* The 64 first entries are used by the PowerPC embedded specification */
167 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
168 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
169 POWERPC_EXCP_DSI = 2, /* Data storage exception */
170 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
171 POWERPC_EXCP_EXTERNAL = 4, /* External input */
172 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
173 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
174 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
175 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
176 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
177 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
178 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
179 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
b4095fed
JM
180 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
181 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
e1833e1f
JM
182 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
183 /* Vectors 16 to 31 are reserved */
e1833e1f
JM
184 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
185 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
186 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
187 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
188 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
189 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
e1833e1f
JM
190 /* Vectors 38 to 63 are reserved */
191 /* Exceptions defined in the PowerPC server specification */
192 POWERPC_EXCP_RESET = 64, /* System reset exception */
e1833e1f
JM
193 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
194 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
e1833e1f 195 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
e1833e1f 196 POWERPC_EXCP_TRACE = 68, /* Trace exception */
e1833e1f
JM
197 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
198 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
199 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
200 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
e1833e1f
JM
201 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
202 /* 40x specific exceptions */
203 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
204 /* 601 specific exceptions */
205 POWERPC_EXCP_IO = 75, /* IO error exception */
206 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
207 /* 602 specific exceptions */
208 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
209 /* 602/603 specific exceptions */
b4095fed 210 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
e1833e1f
JM
211 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
212 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
213 /* Exceptions available on most PowerPC */
214 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
b4095fed
JM
215 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
216 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
217 POWERPC_EXCP_SMI = 84, /* System management interrupt */
218 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
e1833e1f 219 /* 7xx/74xx specific exceptions */
b4095fed 220 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
e1833e1f 221 /* 74xx specific exceptions */
b4095fed 222 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
e1833e1f 223 /* 970FX specific exceptions */
b4095fed
JM
224 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
225 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
5b46d07d 226 /* Freescale embedded cores specific exceptions */
b4095fed
JM
227 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
228 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
229 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
230 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
e1833e1f
JM
231 /* EOL */
232 POWERPC_EXCP_NB = 96,
233 /* Qemu exceptions: used internally during code translation */
234 POWERPC_EXCP_STOP = 0x200, /* stop translation */
235 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
236 /* Qemu exceptions: special cases we want to stop translation */
237 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
238 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
4425265b 239 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
e1833e1f
JM
240};
241
e1833e1f
JM
242/* Exceptions error codes */
243enum {
244 /* Exception subtypes for POWERPC_EXCP_ALIGN */
245 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
246 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
247 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
248 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
249 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
250 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
251 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
252 /* FP exceptions */
253 POWERPC_EXCP_FP = 0x10,
254 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
255 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
256 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
257 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
7c58044c 258 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
e1833e1f
JM
259 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
260 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
261 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
262 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
263 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
264 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
265 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
266 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
267 /* Invalid instruction */
268 POWERPC_EXCP_INVAL = 0x20,
269 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
270 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
271 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
272 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
273 /* Privileged instruction */
274 POWERPC_EXCP_PRIV = 0x30,
275 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
276 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
277 /* Trap */
278 POWERPC_EXCP_TRAP = 0x40,
279};
280
a750fc0b
JM
281/*****************************************************************************/
282/* Input pins model */
c227f099
AL
283typedef enum powerpc_input_t powerpc_input_t;
284enum powerpc_input_t {
a750fc0b 285 PPC_FLAGS_INPUT_UNKNOWN = 0,
2662a059 286 /* PowerPC 6xx bus */
a750fc0b 287 PPC_FLAGS_INPUT_6xx,
2662a059 288 /* BookE bus */
a750fc0b
JM
289 PPC_FLAGS_INPUT_BookE,
290 /* PowerPC 405 bus */
291 PPC_FLAGS_INPUT_405,
2662a059 292 /* PowerPC 970 bus */
a750fc0b 293 PPC_FLAGS_INPUT_970,
9d52e907
DG
294 /* PowerPC POWER7 bus */
295 PPC_FLAGS_INPUT_POWER7,
a750fc0b
JM
296 /* PowerPC 401 bus */
297 PPC_FLAGS_INPUT_401,
b4095fed
JM
298 /* Freescale RCPU bus */
299 PPC_FLAGS_INPUT_RCPU,
3fc6c082
FB
300};
301
a750fc0b 302#define PPC_INPUT(env) (env->bus_model)
3fc6c082 303
be147d08 304/*****************************************************************************/
c227f099
AL
305typedef struct ppc_def_t ppc_def_t;
306typedef struct opc_handler_t opc_handler_t;
79aceca5 307
3fc6c082
FB
308/*****************************************************************************/
309/* Types used to describe some PowerPC registers */
310typedef struct CPUPPCState CPUPPCState;
c227f099
AL
311typedef struct ppc_tb_t ppc_tb_t;
312typedef struct ppc_spr_t ppc_spr_t;
313typedef struct ppc_dcr_t ppc_dcr_t;
314typedef union ppc_avr_t ppc_avr_t;
315typedef union ppc_tlb_t ppc_tlb_t;
76a66253 316
3fc6c082 317/* SPR access micro-ops generations callbacks */
c227f099 318struct ppc_spr_t {
45d827d2
AJ
319 void (*uea_read)(void *opaque, int gpr_num, int spr_num);
320 void (*uea_write)(void *opaque, int spr_num, int gpr_num);
76a66253 321#if !defined(CONFIG_USER_ONLY)
45d827d2
AJ
322 void (*oea_read)(void *opaque, int gpr_num, int spr_num);
323 void (*oea_write)(void *opaque, int spr_num, int gpr_num);
324 void (*hea_read)(void *opaque, int gpr_num, int spr_num);
325 void (*hea_write)(void *opaque, int spr_num, int gpr_num);
76a66253 326#endif
b55266b5 327 const char *name;
3fc6c082
FB
328};
329
330/* Altivec registers (128 bits) */
c227f099 331union ppc_avr_t {
0f6fbcbc 332 float32 f[4];
a9d9eb8f
JM
333 uint8_t u8[16];
334 uint16_t u16[8];
335 uint32_t u32[4];
ab5f265d
AJ
336 int8_t s8[16];
337 int16_t s16[8];
338 int32_t s32[4];
a9d9eb8f 339 uint64_t u64[2];
3fc6c082 340};
9fddaa0c 341
3c7b48b7 342#if !defined(CONFIG_USER_ONLY)
3fc6c082 343/* Software TLB cache */
c227f099
AL
344typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
345struct ppc6xx_tlb_t {
76a66253
JM
346 target_ulong pte0;
347 target_ulong pte1;
348 target_ulong EPN;
1d0a48fb
JM
349};
350
c227f099
AL
351typedef struct ppcemb_tlb_t ppcemb_tlb_t;
352struct ppcemb_tlb_t {
353 target_phys_addr_t RPN;
1d0a48fb 354 target_ulong EPN;
76a66253 355 target_ulong PID;
c55e9aef
JM
356 target_ulong size;
357 uint32_t prot;
358 uint32_t attr; /* Storage attributes */
1d0a48fb
JM
359};
360
d1e256fe
AG
361typedef struct ppcmas_tlb_t {
362 uint32_t mas8;
363 uint32_t mas1;
364 uint64_t mas2;
365 uint64_t mas7_3;
366} ppcmas_tlb_t;
367
c227f099 368union ppc_tlb_t {
1c53accc
AG
369 ppc6xx_tlb_t *tlb6;
370 ppcemb_tlb_t *tlbe;
371 ppcmas_tlb_t *tlbm;
3fc6c082 372};
1c53accc
AG
373
374/* possible TLB variants */
375#define TLB_NONE 0
376#define TLB_6XX 1
377#define TLB_EMB 2
378#define TLB_MAS 3
3c7b48b7 379#endif
3fc6c082 380
bb593904
DG
381#define SDR_32_HTABORG 0xFFFF0000UL
382#define SDR_32_HTABMASK 0x000001FFUL
383
384#if defined(TARGET_PPC64)
385#define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
386#define SDR_64_HTABSIZE 0x000000000000001FULL
387#endif /* defined(TARGET_PPC64 */
388
fda6a0ec
DG
389#define HASH_PTE_SIZE_32 8
390#define HASH_PTE_SIZE_64 16
391
c227f099
AL
392typedef struct ppc_slb_t ppc_slb_t;
393struct ppc_slb_t {
81762d6d
DG
394 uint64_t esid;
395 uint64_t vsid;
8eee0af9
BS
396};
397
81762d6d
DG
398/* Bits in the SLB ESID word */
399#define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
400#define SLB_ESID_V 0x0000000008000000ULL /* valid */
401
402/* Bits in the SLB VSID word */
403#define SLB_VSID_SHIFT 12
cdaee006 404#define SLB_VSID_SHIFT_1T 24
81762d6d
DG
405#define SLB_VSID_SSIZE_SHIFT 62
406#define SLB_VSID_B 0xc000000000000000ULL
407#define SLB_VSID_B_256M 0x0000000000000000ULL
cdaee006 408#define SLB_VSID_B_1T 0x4000000000000000ULL
81762d6d 409#define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
256cebe5 410#define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID)
81762d6d
DG
411#define SLB_VSID_KS 0x0000000000000800ULL
412#define SLB_VSID_KP 0x0000000000000400ULL
413#define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
414#define SLB_VSID_L 0x0000000000000100ULL
415#define SLB_VSID_C 0x0000000000000080ULL /* class */
416#define SLB_VSID_LP 0x0000000000000030ULL
417#define SLB_VSID_ATTR 0x0000000000000FFFULL
418
419#define SEGMENT_SHIFT_256M 28
420#define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
421
cdaee006
DG
422#define SEGMENT_SHIFT_1T 40
423#define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
424
425
3fc6c082
FB
426/*****************************************************************************/
427/* Machine state register bits definition */
76a66253 428#define MSR_SF 63 /* Sixty-four-bit mode hflags */
bd928eba 429#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
3fc6c082 430#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
a4f30719 431#define MSR_SHV 60 /* hypervisor state hflags */
363be49c
JM
432#define MSR_CM 31 /* Computation mode for BookE hflags */
433#define MSR_ICM 30 /* Interrupt computation mode for BookE */
a4f30719 434#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
71afeb61 435#define MSR_GS 28 /* guest state for BookE */
363be49c 436#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
d26bfc9a
JM
437#define MSR_VR 25 /* altivec available x hflags */
438#define MSR_SPE 25 /* SPE enable for BookE x hflags */
76a66253
JM
439#define MSR_AP 23 /* Access privilege state on 602 hflags */
440#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
3fc6c082 441#define MSR_KEY 19 /* key bit on 603e */
25ba3a68 442#define MSR_POW 18 /* Power management */
d26bfc9a
JM
443#define MSR_TGPR 17 /* TGPR usage on 602/603 x */
444#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
3fc6c082
FB
445#define MSR_ILE 16 /* Interrupt little-endian mode */
446#define MSR_EE 15 /* External interrupt enable */
76a66253
JM
447#define MSR_PR 14 /* Problem state hflags */
448#define MSR_FP 13 /* Floating point available hflags */
3fc6c082 449#define MSR_ME 12 /* Machine check interrupt enable */
76a66253 450#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
d26bfc9a
JM
451#define MSR_SE 10 /* Single-step trace enable x hflags */
452#define MSR_DWE 10 /* Debug wait enable on 405 x */
453#define MSR_UBLE 10 /* User BTB lock enable on e500 x */
454#define MSR_BE 9 /* Branch trace enable x hflags */
455#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
76a66253 456#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
3fc6c082 457#define MSR_AL 7 /* AL bit on POWER */
0411a972 458#define MSR_EP 6 /* Exception prefix on 601 */
3fc6c082 459#define MSR_IR 5 /* Instruction relocate */
3fc6c082 460#define MSR_DR 4 /* Data relocate */
25ba3a68 461#define MSR_PE 3 /* Protection enable on 403 */
d26bfc9a
JM
462#define MSR_PX 2 /* Protection exclusive on 403 x */
463#define MSR_PMM 2 /* Performance monitor mark on POWER x */
464#define MSR_RI 1 /* Recoverable interrupt 1 */
465#define MSR_LE 0 /* Little-endian mode 1 hflags */
0411a972
JM
466
467#define msr_sf ((env->msr >> MSR_SF) & 1)
468#define msr_isf ((env->msr >> MSR_ISF) & 1)
a4f30719 469#define msr_shv ((env->msr >> MSR_SHV) & 1)
0411a972
JM
470#define msr_cm ((env->msr >> MSR_CM) & 1)
471#define msr_icm ((env->msr >> MSR_ICM) & 1)
a4f30719 472#define msr_thv ((env->msr >> MSR_THV) & 1)
71afeb61 473#define msr_gs ((env->msr >> MSR_GS) & 1)
0411a972
JM
474#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
475#define msr_vr ((env->msr >> MSR_VR) & 1)
f9320410 476#define msr_spe ((env->msr >> MSR_SPE) & 1)
0411a972
JM
477#define msr_ap ((env->msr >> MSR_AP) & 1)
478#define msr_sa ((env->msr >> MSR_SA) & 1)
479#define msr_key ((env->msr >> MSR_KEY) & 1)
480#define msr_pow ((env->msr >> MSR_POW) & 1)
481#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
482#define msr_ce ((env->msr >> MSR_CE) & 1)
483#define msr_ile ((env->msr >> MSR_ILE) & 1)
484#define msr_ee ((env->msr >> MSR_EE) & 1)
485#define msr_pr ((env->msr >> MSR_PR) & 1)
486#define msr_fp ((env->msr >> MSR_FP) & 1)
487#define msr_me ((env->msr >> MSR_ME) & 1)
488#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
489#define msr_se ((env->msr >> MSR_SE) & 1)
490#define msr_dwe ((env->msr >> MSR_DWE) & 1)
491#define msr_uble ((env->msr >> MSR_UBLE) & 1)
492#define msr_be ((env->msr >> MSR_BE) & 1)
493#define msr_de ((env->msr >> MSR_DE) & 1)
494#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
495#define msr_al ((env->msr >> MSR_AL) & 1)
496#define msr_ep ((env->msr >> MSR_EP) & 1)
497#define msr_ir ((env->msr >> MSR_IR) & 1)
498#define msr_dr ((env->msr >> MSR_DR) & 1)
499#define msr_pe ((env->msr >> MSR_PE) & 1)
500#define msr_px ((env->msr >> MSR_PX) & 1)
501#define msr_pmm ((env->msr >> MSR_PMM) & 1)
502#define msr_ri ((env->msr >> MSR_RI) & 1)
503#define msr_le ((env->msr >> MSR_LE) & 1)
a4f30719
JM
504/* Hypervisor bit is more specific */
505#if defined(TARGET_PPC64)
506#define MSR_HVB (1ULL << MSR_SHV)
507#define msr_hv msr_shv
508#else
509#if defined(PPC_EMULATE_32BITS_HYPV)
510#define MSR_HVB (1ULL << MSR_THV)
511#define msr_hv msr_thv
a4f30719
JM
512#else
513#define MSR_HVB (0ULL)
514#define msr_hv (0)
515#endif
516#endif
79aceca5 517
a586e548 518/* Exception state register bits definition */
542df9bf
AG
519#define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
520#define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
521#define ESR_PTR (1 << (63 - 38)) /* Trap */
522#define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
523#define ESR_ST (1 << (63 - 40)) /* Store Operation */
524#define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
525#define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
526#define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
527#define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
528#define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
529#define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
530#define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
531#define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
532#define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
533#define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
534#define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
a586e548 535
d26bfc9a 536enum {
4018bae9 537 POWERPC_FLAG_NONE = 0x00000000,
d26bfc9a 538 /* Flag for MSR bit 25 signification (VRE/SPE) */
4018bae9
JM
539 POWERPC_FLAG_SPE = 0x00000001,
540 POWERPC_FLAG_VRE = 0x00000002,
d26bfc9a 541 /* Flag for MSR bit 17 signification (TGPR/CE) */
4018bae9
JM
542 POWERPC_FLAG_TGPR = 0x00000004,
543 POWERPC_FLAG_CE = 0x00000008,
d26bfc9a 544 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
4018bae9
JM
545 POWERPC_FLAG_SE = 0x00000010,
546 POWERPC_FLAG_DWE = 0x00000020,
547 POWERPC_FLAG_UBLE = 0x00000040,
d26bfc9a 548 /* Flag for MSR bit 9 signification (BE/DE) */
4018bae9
JM
549 POWERPC_FLAG_BE = 0x00000080,
550 POWERPC_FLAG_DE = 0x00000100,
a4f30719 551 /* Flag for MSR bit 2 signification (PX/PMM) */
4018bae9
JM
552 POWERPC_FLAG_PX = 0x00000200,
553 POWERPC_FLAG_PMM = 0x00000400,
554 /* Flag for special features */
555 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
556 POWERPC_FLAG_RTC_CLK = 0x00010000,
557 POWERPC_FLAG_BUS_CLK = 0x00020000,
d26bfc9a
JM
558};
559
7c58044c
JM
560/*****************************************************************************/
561/* Floating point status and control register */
562#define FPSCR_FX 31 /* Floating-point exception summary */
563#define FPSCR_FEX 30 /* Floating-point enabled exception summary */
564#define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
565#define FPSCR_OX 28 /* Floating-point overflow exception */
566#define FPSCR_UX 27 /* Floating-point underflow exception */
567#define FPSCR_ZX 26 /* Floating-point zero divide exception */
568#define FPSCR_XX 25 /* Floating-point inexact exception */
569#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
570#define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
571#define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
572#define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
573#define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
574#define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
575#define FPSCR_FR 18 /* Floating-point fraction rounded */
576#define FPSCR_FI 17 /* Floating-point fraction inexact */
577#define FPSCR_C 16 /* Floating-point result class descriptor */
578#define FPSCR_FL 15 /* Floating-point less than or negative */
579#define FPSCR_FG 14 /* Floating-point greater than or negative */
580#define FPSCR_FE 13 /* Floating-point equal or zero */
581#define FPSCR_FU 12 /* Floating-point unordered or NaN */
582#define FPSCR_FPCC 12 /* Floating-point condition code */
583#define FPSCR_FPRF 12 /* Floating-point result flags */
584#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
585#define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
586#define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
587#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
588#define FPSCR_OE 6 /* Floating-point overflow exception enable */
589#define FPSCR_UE 5 /* Floating-point undeflow exception enable */
590#define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
591#define FPSCR_XE 3 /* Floating-point inexact exception enable */
592#define FPSCR_NI 2 /* Floating-point non-IEEE mode */
593#define FPSCR_RN1 1
594#define FPSCR_RN 0 /* Floating-point rounding control */
595#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
596#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
597#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
598#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
599#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
600#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
601#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
602#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
603#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
604#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
605#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
606#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
607#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
608#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
609#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
610#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
611#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
612#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
613#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
614#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
615#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
616#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
617#define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
618/* Invalid operation exception summary */
619#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
620 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
621 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
622 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
623 (1 << FPSCR_VXCVI)))
624/* exception summary */
625#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
626/* enabled exception summary */
627#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
628 0x1F)
629
630/*****************************************************************************/
6fa724a3
AJ
631/* Vector status and control register */
632#define VSCR_NJ 16 /* Vector non-java */
633#define VSCR_SAT 0 /* Vector saturation */
634#define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
635#define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
636
01662f3e
AG
637/*****************************************************************************/
638/* BookE e500 MMU registers */
639
640#define MAS0_NV_SHIFT 0
641#define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
642
643#define MAS0_WQ_SHIFT 12
644#define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
645/* Write TLB entry regardless of reservation */
646#define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
647/* Write TLB entry only already in use */
648#define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
649/* Clear TLB entry */
650#define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
651
652#define MAS0_HES_SHIFT 14
653#define MAS0_HES (1 << MAS0_HES_SHIFT)
654
655#define MAS0_ESEL_SHIFT 16
656#define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
657
658#define MAS0_TLBSEL_SHIFT 28
659#define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
660#define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
661#define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
662#define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
663#define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
664
665#define MAS0_ATSEL_SHIFT 31
666#define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
667#define MAS0_ATSEL_TLB 0
668#define MAS0_ATSEL_LRAT MAS0_ATSEL
669
670#define MAS1_TSIZE_SHIFT 8
671#define MAS1_TSIZE_MASK (0xf << MAS1_TSIZE_SHIFT)
672
673#define MAS1_TS_SHIFT 12
674#define MAS1_TS (1 << MAS1_TS_SHIFT)
675
676#define MAS1_IND_SHIFT 13
677#define MAS1_IND (1 << MAS1_IND_SHIFT)
678
679#define MAS1_TID_SHIFT 16
680#define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
681
682#define MAS1_IPROT_SHIFT 30
683#define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
684
685#define MAS1_VALID_SHIFT 31
686#define MAS1_VALID 0x80000000
687
688#define MAS2_EPN_SHIFT 12
689#define MAS2_EPN_MASK (0xfffff << MAS2_EPN_SHIFT)
690
691#define MAS2_ACM_SHIFT 6
692#define MAS2_ACM (1 << MAS2_ACM_SHIFT)
693
694#define MAS2_VLE_SHIFT 5
695#define MAS2_VLE (1 << MAS2_VLE_SHIFT)
696
697#define MAS2_W_SHIFT 4
698#define MAS2_W (1 << MAS2_W_SHIFT)
699
700#define MAS2_I_SHIFT 3
701#define MAS2_I (1 << MAS2_I_SHIFT)
702
703#define MAS2_M_SHIFT 2
704#define MAS2_M (1 << MAS2_M_SHIFT)
705
706#define MAS2_G_SHIFT 1
707#define MAS2_G (1 << MAS2_G_SHIFT)
708
709#define MAS2_E_SHIFT 0
710#define MAS2_E (1 << MAS2_E_SHIFT)
711
712#define MAS3_RPN_SHIFT 12
713#define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
714
715#define MAS3_U0 0x00000200
716#define MAS3_U1 0x00000100
717#define MAS3_U2 0x00000080
718#define MAS3_U3 0x00000040
719#define MAS3_UX 0x00000020
720#define MAS3_SX 0x00000010
721#define MAS3_UW 0x00000008
722#define MAS3_SW 0x00000004
723#define MAS3_UR 0x00000002
724#define MAS3_SR 0x00000001
725#define MAS3_SPSIZE_SHIFT 1
726#define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
727
728#define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
729#define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
730#define MAS4_TIDSELD_MASK 0x00030000
731#define MAS4_TIDSELD_PID0 0x00000000
732#define MAS4_TIDSELD_PID1 0x00010000
733#define MAS4_TIDSELD_PID2 0x00020000
734#define MAS4_TIDSELD_PIDZ 0x00030000
735#define MAS4_INDD 0x00008000 /* Default IND */
736#define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
737#define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
738#define MAS4_ACMD 0x00000040
739#define MAS4_VLED 0x00000020
740#define MAS4_WD 0x00000010
741#define MAS4_ID 0x00000008
742#define MAS4_MD 0x00000004
743#define MAS4_GD 0x00000002
744#define MAS4_ED 0x00000001
745#define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
746#define MAS4_WIMGED_SHIFT 0
747
748#define MAS5_SGS 0x80000000
749#define MAS5_SLPID_MASK 0x00000fff
750
751#define MAS6_SPID0 0x3fff0000
752#define MAS6_SPID1 0x00007ffe
753#define MAS6_ISIZE(x) MAS1_TSIZE(x)
754#define MAS6_SAS 0x00000001
755#define MAS6_SPID MAS6_SPID0
756#define MAS6_SIND 0x00000002 /* Indirect page */
757#define MAS6_SIND_SHIFT 1
758#define MAS6_SPID_MASK 0x3fff0000
759#define MAS6_SPID_SHIFT 16
760#define MAS6_ISIZE_MASK 0x00000f80
761#define MAS6_ISIZE_SHIFT 7
762
763#define MAS7_RPN 0xffffffff
764
765#define MAS8_TGS 0x80000000
766#define MAS8_VF 0x40000000
767#define MAS8_TLBPID 0x00000fff
768
769/* Bit definitions for MMUCFG */
770#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
771#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
772#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
773#define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
774#define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
775#define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
776#define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
777#define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
778#define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
779
780/* Bit definitions for MMUCSR0 */
781#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
782#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
783#define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
784#define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
785#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
786 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
787#define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
788#define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
789#define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
790#define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
791
792/* TLBnCFG encoding */
793#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
794#define TLBnCFG_HES 0x00002000 /* HW select supported */
795#define TLBnCFG_AVAIL 0x00004000 /* variable page size */
796#define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
797#define TLBnCFG_GTWE 0x00010000 /* Guest can write */
798#define TLBnCFG_IND 0x00020000 /* IND entries supported */
799#define TLBnCFG_PT 0x00040000 /* Can load from page table */
800#define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
801#define TLBnCFG_MINSIZE_SHIFT 20
802#define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
803#define TLBnCFG_MAXSIZE_SHIFT 16
804#define TLBnCFG_ASSOC 0xff000000 /* Associativity */
805#define TLBnCFG_ASSOC_SHIFT 24
806
807/* TLBnPS encoding */
808#define TLBnPS_4K 0x00000004
809#define TLBnPS_8K 0x00000008
810#define TLBnPS_16K 0x00000010
811#define TLBnPS_32K 0x00000020
812#define TLBnPS_64K 0x00000040
813#define TLBnPS_128K 0x00000080
814#define TLBnPS_256K 0x00000100
815#define TLBnPS_512K 0x00000200
816#define TLBnPS_1M 0x00000400
817#define TLBnPS_2M 0x00000800
818#define TLBnPS_4M 0x00001000
819#define TLBnPS_8M 0x00002000
820#define TLBnPS_16M 0x00004000
821#define TLBnPS_32M 0x00008000
822#define TLBnPS_64M 0x00010000
823#define TLBnPS_128M 0x00020000
824#define TLBnPS_256M 0x00040000
825#define TLBnPS_512M 0x00080000
826#define TLBnPS_1G 0x00100000
827#define TLBnPS_2G 0x00200000
828#define TLBnPS_4G 0x00400000
829#define TLBnPS_8G 0x00800000
830#define TLBnPS_16G 0x01000000
831#define TLBnPS_32G 0x02000000
832#define TLBnPS_64G 0x04000000
833#define TLBnPS_128G 0x08000000
834#define TLBnPS_256G 0x10000000
835
836/* tlbilx action encoding */
837#define TLBILX_T_ALL 0
838#define TLBILX_T_TID 1
839#define TLBILX_T_FULLMATCH 3
840#define TLBILX_T_CLASS0 4
841#define TLBILX_T_CLASS1 5
842#define TLBILX_T_CLASS2 6
843#define TLBILX_T_CLASS3 7
844
845/* BookE 2.06 helper defines */
846
847#define BOOKE206_FLUSH_TLB0 (1 << 0)
848#define BOOKE206_FLUSH_TLB1 (1 << 1)
849#define BOOKE206_FLUSH_TLB2 (1 << 2)
850#define BOOKE206_FLUSH_TLB3 (1 << 3)
851
852/* number of possible TLBs */
853#define BOOKE206_MAX_TLBN 4
854
6fa724a3 855/*****************************************************************************/
7c58044c 856/* The whole PowerPC CPU context */
6ebbf390 857#define NB_MMU_MODES 3
6ebbf390 858
3fc6c082
FB
859struct CPUPPCState {
860 /* First are the most commonly used resources
861 * during translated code execution
862 */
79aceca5 863 /* general purpose registers */
bd7d9a6d 864 target_ulong gpr[32];
65d6c0f3 865#if !defined(TARGET_PPC64)
3cd7d1dd 866 /* Storage for GPR MSB, used by the SPE extension */
bd7d9a6d 867 target_ulong gprh[32];
3cd7d1dd 868#endif
3fc6c082
FB
869 /* LR */
870 target_ulong lr;
871 /* CTR */
872 target_ulong ctr;
873 /* condition register */
47e4661c 874 uint32_t crf[8];
79aceca5 875 /* XER */
3d7b417e 876 target_ulong xer;
79aceca5 877 /* Reservation address */
18b21a2f
NF
878 target_ulong reserve_addr;
879 /* Reservation value */
880 target_ulong reserve_val;
4425265b
NF
881 /* Reservation store address */
882 target_ulong reserve_ea;
883 /* Reserved store source register and size */
884 target_ulong reserve_info;
3fc6c082
FB
885
886 /* Those ones are used in supervisor mode only */
79aceca5 887 /* machine state register */
0411a972 888 target_ulong msr;
3fc6c082 889 /* temporary general purpose registers */
bd7d9a6d 890 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
3fc6c082
FB
891
892 /* Floating point execution context */
4ecc3190 893 float_status fp_status;
3fc6c082
FB
894 /* floating point registers */
895 float64 fpr[32];
896 /* floating point status and control register */
7c58044c 897 uint32_t fpscr;
4ecc3190 898
cb2dbfc3
AJ
899 /* Next instruction pointer */
900 target_ulong nip;
a316d335 901
ac9eb073
FB
902 int access_type; /* when a memory exception occurs, the access
903 type is stored here */
a541f297 904
cb2dbfc3
AJ
905 CPU_COMMON
906
f2e63a42
JM
907 /* MMU context - only relevant for full system emulation */
908#if !defined(CONFIG_USER_ONLY)
909#if defined(TARGET_PPC64)
3fc6c082
FB
910 /* Address space register */
911 target_ulong asr;
f2e63a42 912 /* PowerPC 64 SLB area */
c227f099 913 ppc_slb_t slb[64];
f2e63a42
JM
914 int slb_nr;
915#endif
3fc6c082 916 /* segment registers */
bb593904
DG
917 target_phys_addr_t htab_base;
918 target_phys_addr_t htab_mask;
74d37793 919 target_ulong sr[32];
f43e3525
DG
920 /* externally stored hash table */
921 uint8_t *external_htab;
3fc6c082
FB
922 /* BATs */
923 int nb_BATs;
924 target_ulong DBAT[2][8];
925 target_ulong IBAT[2][8];
01662f3e 926 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
f2e63a42
JM
927 int nb_tlb; /* Total number of TLB */
928 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
929 int nb_ways; /* Number of ways in the TLB set */
930 int last_way; /* Last used way used to allocate TLB in a LRU way */
931 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
932 int nb_pids; /* Number of available PID registers */
1c53accc
AG
933 int tlb_type; /* Type of TLB we're dealing with */
934 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
f2e63a42
JM
935 /* 403 dedicated access protection registers */
936 target_ulong pb[4];
937#endif
9fddaa0c 938
3fc6c082
FB
939 /* Other registers */
940 /* Special purpose registers */
941 target_ulong spr[1024];
c227f099 942 ppc_spr_t spr_cb[1024];
3fc6c082 943 /* Altivec registers */
c227f099 944 ppc_avr_t avr[32];
3fc6c082 945 uint32_t vscr;
d9bce9d9 946 /* SPE registers */
2231ef10 947 uint64_t spe_acc;
d9bce9d9 948 uint32_t spe_fscr;
fbd265b6
AJ
949 /* SPE and Altivec can share a status since they will never be used
950 * simultaneously */
951 float_status vec_status;
3fc6c082
FB
952
953 /* Internal devices resources */
9fddaa0c 954 /* Time base and decrementer */
c227f099 955 ppc_tb_t *tb_env;
3fc6c082 956 /* Device control registers */
c227f099 957 ppc_dcr_t *dcr_env;
3fc6c082 958
d63001d1
JM
959 int dcache_line_size;
960 int icache_line_size;
961
3fc6c082
FB
962 /* Those resources are used during exception processing */
963 /* CPU model definition */
a750fc0b 964 target_ulong msr_mask;
c227f099
AL
965 powerpc_mmu_t mmu_model;
966 powerpc_excp_t excp_model;
967 powerpc_input_t bus_model;
237c0af0 968 int bfd_mach;
3fc6c082 969 uint32_t flags;
c29b735c 970 uint64_t insns_flags;
a5858d7a 971 uint64_t insns_flags2;
3fc6c082 972
ed120055
DG
973#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
974 target_phys_addr_t vpa;
975 target_phys_addr_t slb_shadow;
976 target_phys_addr_t dispatch_trace_log;
977 uint32_t dtl_size;
978#endif /* TARGET_PPC64 */
979
3fc6c082 980 int error_code;
47103572 981 uint32_t pending_interrupts;
e9df014c
JM
982#if !defined(CONFIG_USER_ONLY)
983 /* This is the IRQ controller, which is implementation dependant
984 * and only relevant when emulating a complete machine.
985 */
986 uint32_t irq_input_state;
987 void **irq_inputs;
e1833e1f
JM
988 /* Exception vectors */
989 target_ulong excp_vectors[POWERPC_EXCP_NB];
990 target_ulong excp_prefix;
fc1c67bc 991 target_ulong hreset_excp_prefix;
e1833e1f
JM
992 target_ulong ivor_mask;
993 target_ulong ivpr_mask;
d63001d1 994 target_ulong hreset_vector;
e9df014c 995#endif
3fc6c082
FB
996
997 /* Those resources are used only during code translation */
3fc6c082 998 /* opcode handlers */
c227f099 999 opc_handler_t *opcodes[0x40];
3fc6c082
FB
1000
1001 /* Those resources are used only in Qemu core */
056401ea
JM
1002 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
1003 target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
6ebbf390 1004 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
3fc6c082 1005
9fddaa0c
FB
1006 /* Power management */
1007 int power_mode;
cd346349 1008 int (*check_pow)(CPUPPCState *env);
a541f297 1009
2c50e26e
EI
1010#if !defined(CONFIG_USER_ONLY)
1011 void *load_info; /* Holds boot loading state. */
1012#endif
3fc6c082 1013};
79aceca5 1014
3c7b48b7 1015#if !defined(CONFIG_USER_ONLY)
76a66253 1016/* Context used internally during MMU translations */
c227f099
AL
1017typedef struct mmu_ctx_t mmu_ctx_t;
1018struct mmu_ctx_t {
1019 target_phys_addr_t raddr; /* Real address */
1020 target_phys_addr_t eaddr; /* Effective address */
76a66253 1021 int prot; /* Protection bits */
fda6a0ec 1022 target_phys_addr_t hash[2]; /* Pagetable hash values */
76a66253
JM
1023 target_ulong ptem; /* Virtual segment ID | API */
1024 int key; /* Access key */
b227a8e9 1025 int nx; /* Non-execute area */
76a66253 1026};
3c7b48b7 1027#endif
76a66253 1028
3fc6c082 1029/*****************************************************************************/
aaed909a 1030CPUPPCState *cpu_ppc_init (const char *cpu_model);
2e70f6ef 1031void ppc_translate_init(void);
36081602
JM
1032int cpu_ppc_exec (CPUPPCState *s);
1033void cpu_ppc_close (CPUPPCState *s);
79aceca5
FB
1034/* you can call this signal handler from your SIGBUS and SIGSEGV
1035 signal handlers to inform the virtual CPU of exceptions. non zero
1036 is returned if the signal was handled by the virtual CPU. */
36081602
JM
1037int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1038 void *puc);
93220573 1039int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
97b348e7 1040 int mmu_idx);
0b5c1ce8 1041#define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
3c7b48b7 1042#if !defined(CONFIG_USER_ONLY)
c227f099 1043int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,
93220573 1044 int rw, int access_type);
3c7b48b7 1045#endif
a541f297 1046void do_interrupt (CPUPPCState *env);
e9df014c 1047void ppc_hw_interrupt (CPUPPCState *env);
a541f297 1048
93220573 1049void cpu_dump_rfi (target_ulong RA, target_ulong msr);
a541f297 1050
76a66253 1051#if !defined(CONFIG_USER_ONLY)
93220573
AJ
1052void ppc6xx_tlb_store (CPUPPCState *env, target_ulong EPN, int way, int is_code,
1053 target_ulong pte0, target_ulong pte1);
45d827d2
AJ
1054void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
1055void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
1056void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
1057void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
1058void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);
1059void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);
1060void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
d9bce9d9 1061#if defined(TARGET_PPC64)
d9bce9d9 1062void ppc_store_asr (CPUPPCState *env, target_ulong value);
12de9a39 1063target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
f6b868fc 1064target_ulong ppc_load_sr (CPUPPCState *env, int sr_nr);
81762d6d 1065int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
efdef95f
DG
1066int ppc_load_slb_esid (CPUPPCState *env, target_ulong rb, target_ulong *rt);
1067int ppc_load_slb_vsid (CPUPPCState *env, target_ulong rb, target_ulong *rt);
12de9a39 1068#endif /* defined(TARGET_PPC64) */
45d827d2 1069void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value);
12de9a39 1070#endif /* !defined(CONFIG_USER_ONLY) */
0411a972 1071void ppc_store_msr (CPUPPCState *env, target_ulong value);
3fc6c082 1072
9a78eead 1073void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
aaed909a 1074
c227f099
AL
1075const ppc_def_t *cpu_ppc_find_by_name (const char *name);
1076int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
85c4adf6 1077
9fddaa0c
FB
1078/* Time-base and decrementer management */
1079#ifndef NO_CPU_IO_DEFS
e3ea6529 1080uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
9fddaa0c
FB
1081uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1082void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1083void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
b711de95 1084uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
a062e36c
JM
1085uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1086void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1087void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
9fddaa0c
FB
1088uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1089void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
58a7d328
JM
1090uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1091void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1092uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1093void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
d9bce9d9
JM
1094uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1095uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1096#if !defined(CONFIG_USER_ONLY)
1097void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1098void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1099target_ulong load_40x_pit (CPUPPCState *env);
1100void store_40x_pit (CPUPPCState *env, target_ulong val);
8ecc7913 1101void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
c294fc58 1102void store_40x_sler (CPUPPCState *env, uint32_t val);
d9bce9d9
JM
1103void store_booke_tcr (CPUPPCState *env, target_ulong val);
1104void store_booke_tsr (CPUPPCState *env, target_ulong val);
01662f3e 1105void booke206_flush_tlb(CPUState *env, int flags, const int check_iprot);
d1e256fe 1106target_phys_addr_t booke206_tlb_to_page_size(CPUState *env, ppcmas_tlb_t *tlb);
01662f3e
AG
1107int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb,
1108 target_phys_addr_t *raddrp, target_ulong address,
1109 uint32_t pid, int ext, int i);
d1e256fe
AG
1110int ppcmas_tlb_check(CPUState *env, ppcmas_tlb_t *tlb,
1111 target_phys_addr_t *raddrp, target_ulong address,
1112 uint32_t pid);
0a032cbe 1113void ppc_tlb_invalidate_all (CPUPPCState *env);
daf4f96e
JM
1114void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1115#if defined(TARGET_PPC64)
1116void ppc_slb_invalidate_all (CPUPPCState *env);
1117void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
1118#endif
36081602 1119int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
d9bce9d9 1120#endif
9fddaa0c 1121#endif
79aceca5 1122
636aa200 1123static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
6b542af7
JM
1124{
1125 uint64_t gprv;
1126
1127 gprv = env->gpr[gprn];
1128#if !defined(TARGET_PPC64)
1129 if (env->flags & POWERPC_FLAG_SPE) {
1130 /* If the CPU implements the SPE extension, we have to get the
1131 * high bits of the GPR from the gprh storage area
1132 */
1133 gprv &= 0xFFFFFFFFULL;
1134 gprv |= (uint64_t)env->gprh[gprn] << 32;
1135 }
1136#endif
1137
1138 return gprv;
1139}
1140
2e719ba3 1141/* Device control registers */
73b01960
AG
1142int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1143int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
2e719ba3 1144
9467d44c
TS
1145#define cpu_init cpu_ppc_init
1146#define cpu_exec cpu_ppc_exec
1147#define cpu_gen_code cpu_ppc_gen_code
1148#define cpu_signal_handler cpu_ppc_signal_handler
c732abe2 1149#define cpu_list ppc_cpu_list
9467d44c 1150
fc1c67bc 1151#define CPU_SAVE_VERSION 4
b3c7724c 1152
6ebbf390
JM
1153/* MMU modes definitions */
1154#define MMU_MODE0_SUFFIX _user
1155#define MMU_MODE1_SUFFIX _kernel
6ebbf390 1156#define MMU_MODE2_SUFFIX _hypv
6ebbf390
JM
1157#define MMU_USER_IDX 0
1158static inline int cpu_mmu_index (CPUState *env)
1159{
1160 return env->mmu_idx;
1161}
1162
6e68e076
PB
1163#if defined(CONFIG_USER_ONLY)
1164static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
1165{
f8ed7070 1166 if (newsp)
6e68e076 1167 env->gpr[1] = newsp;
d11f69b2 1168 env->gpr[3] = 0;
6e68e076
PB
1169}
1170#endif
1171
79aceca5
FB
1172#include "cpu-all.h"
1173
3fc6c082 1174/*****************************************************************************/
e1571908 1175/* CRF definitions */
57951c27
AJ
1176#define CRF_LT 3
1177#define CRF_GT 2
1178#define CRF_EQ 1
1179#define CRF_SO 0
e6bba2ef
NF
1180#define CRF_CH (1 << CRF_LT)
1181#define CRF_CL (1 << CRF_GT)
1182#define CRF_CH_OR_CL (1 << CRF_EQ)
1183#define CRF_CH_AND_CL (1 << CRF_SO)
e1571908
AJ
1184
1185/* XER definitions */
3d7b417e
AJ
1186#define XER_SO 31
1187#define XER_OV 30
1188#define XER_CA 29
1189#define XER_CMP 8
1190#define XER_BC 0
1191#define xer_so ((env->xer >> XER_SO) & 1)
1192#define xer_ov ((env->xer >> XER_OV) & 1)
1193#define xer_ca ((env->xer >> XER_CA) & 1)
1194#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1195#define xer_bc ((env->xer >> XER_BC) & 0x7F)
79aceca5 1196
3fc6c082 1197/* SPR definitions */
80d11f44
JM
1198#define SPR_MQ (0x000)
1199#define SPR_XER (0x001)
1200#define SPR_601_VRTCU (0x004)
1201#define SPR_601_VRTCL (0x005)
1202#define SPR_601_UDECR (0x006)
1203#define SPR_LR (0x008)
1204#define SPR_CTR (0x009)
1205#define SPR_DSISR (0x012)
1206#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1207#define SPR_601_RTCU (0x014)
1208#define SPR_601_RTCL (0x015)
1209#define SPR_DECR (0x016)
1210#define SPR_SDR1 (0x019)
1211#define SPR_SRR0 (0x01A)
1212#define SPR_SRR1 (0x01B)
1213#define SPR_AMR (0x01D)
1214#define SPR_BOOKE_PID (0x030)
1215#define SPR_BOOKE_DECAR (0x036)
1216#define SPR_BOOKE_CSRR0 (0x03A)
1217#define SPR_BOOKE_CSRR1 (0x03B)
1218#define SPR_BOOKE_DEAR (0x03D)
1219#define SPR_BOOKE_ESR (0x03E)
1220#define SPR_BOOKE_IVPR (0x03F)
1221#define SPR_MPC_EIE (0x050)
1222#define SPR_MPC_EID (0x051)
1223#define SPR_MPC_NRI (0x052)
1224#define SPR_CTRL (0x088)
1225#define SPR_MPC_CMPA (0x090)
1226#define SPR_MPC_CMPB (0x091)
1227#define SPR_MPC_CMPC (0x092)
1228#define SPR_MPC_CMPD (0x093)
1229#define SPR_MPC_ECR (0x094)
1230#define SPR_MPC_DER (0x095)
1231#define SPR_MPC_COUNTA (0x096)
1232#define SPR_MPC_COUNTB (0x097)
1233#define SPR_UCTRL (0x098)
1234#define SPR_MPC_CMPE (0x098)
1235#define SPR_MPC_CMPF (0x099)
1236#define SPR_MPC_CMPG (0x09A)
1237#define SPR_MPC_CMPH (0x09B)
1238#define SPR_MPC_LCTRL1 (0x09C)
1239#define SPR_MPC_LCTRL2 (0x09D)
1240#define SPR_MPC_ICTRL (0x09E)
1241#define SPR_MPC_BAR (0x09F)
1242#define SPR_VRSAVE (0x100)
1243#define SPR_USPRG0 (0x100)
1244#define SPR_USPRG1 (0x101)
1245#define SPR_USPRG2 (0x102)
1246#define SPR_USPRG3 (0x103)
1247#define SPR_USPRG4 (0x104)
1248#define SPR_USPRG5 (0x105)
1249#define SPR_USPRG6 (0x106)
1250#define SPR_USPRG7 (0x107)
1251#define SPR_VTBL (0x10C)
1252#define SPR_VTBU (0x10D)
1253#define SPR_SPRG0 (0x110)
1254#define SPR_SPRG1 (0x111)
1255#define SPR_SPRG2 (0x112)
1256#define SPR_SPRG3 (0x113)
1257#define SPR_SPRG4 (0x114)
1258#define SPR_SCOMC (0x114)
1259#define SPR_SPRG5 (0x115)
1260#define SPR_SCOMD (0x115)
1261#define SPR_SPRG6 (0x116)
1262#define SPR_SPRG7 (0x117)
1263#define SPR_ASR (0x118)
1264#define SPR_EAR (0x11A)
1265#define SPR_TBL (0x11C)
1266#define SPR_TBU (0x11D)
1267#define SPR_TBU40 (0x11E)
1268#define SPR_SVR (0x11E)
1269#define SPR_BOOKE_PIR (0x11E)
1270#define SPR_PVR (0x11F)
1271#define SPR_HSPRG0 (0x130)
1272#define SPR_BOOKE_DBSR (0x130)
1273#define SPR_HSPRG1 (0x131)
1274#define SPR_HDSISR (0x132)
1275#define SPR_HDAR (0x133)
90dc8812 1276#define SPR_BOOKE_EPCR (0x133)
9d52e907 1277#define SPR_SPURR (0x134)
80d11f44
JM
1278#define SPR_BOOKE_DBCR0 (0x134)
1279#define SPR_IBCR (0x135)
1280#define SPR_PURR (0x135)
1281#define SPR_BOOKE_DBCR1 (0x135)
1282#define SPR_DBCR (0x136)
1283#define SPR_HDEC (0x136)
1284#define SPR_BOOKE_DBCR2 (0x136)
1285#define SPR_HIOR (0x137)
1286#define SPR_MBAR (0x137)
1287#define SPR_RMOR (0x138)
1288#define SPR_BOOKE_IAC1 (0x138)
1289#define SPR_HRMOR (0x139)
1290#define SPR_BOOKE_IAC2 (0x139)
1291#define SPR_HSRR0 (0x13A)
1292#define SPR_BOOKE_IAC3 (0x13A)
1293#define SPR_HSRR1 (0x13B)
1294#define SPR_BOOKE_IAC4 (0x13B)
1295#define SPR_LPCR (0x13C)
1296#define SPR_BOOKE_DAC1 (0x13C)
1297#define SPR_LPIDR (0x13D)
1298#define SPR_DABR2 (0x13D)
1299#define SPR_BOOKE_DAC2 (0x13D)
1300#define SPR_BOOKE_DVC1 (0x13E)
1301#define SPR_BOOKE_DVC2 (0x13F)
1302#define SPR_BOOKE_TSR (0x150)
1303#define SPR_BOOKE_TCR (0x154)
1304#define SPR_BOOKE_IVOR0 (0x190)
1305#define SPR_BOOKE_IVOR1 (0x191)
1306#define SPR_BOOKE_IVOR2 (0x192)
1307#define SPR_BOOKE_IVOR3 (0x193)
1308#define SPR_BOOKE_IVOR4 (0x194)
1309#define SPR_BOOKE_IVOR5 (0x195)
1310#define SPR_BOOKE_IVOR6 (0x196)
1311#define SPR_BOOKE_IVOR7 (0x197)
1312#define SPR_BOOKE_IVOR8 (0x198)
1313#define SPR_BOOKE_IVOR9 (0x199)
1314#define SPR_BOOKE_IVOR10 (0x19A)
1315#define SPR_BOOKE_IVOR11 (0x19B)
1316#define SPR_BOOKE_IVOR12 (0x19C)
1317#define SPR_BOOKE_IVOR13 (0x19D)
1318#define SPR_BOOKE_IVOR14 (0x19E)
1319#define SPR_BOOKE_IVOR15 (0x19F)
1320#define SPR_BOOKE_SPEFSCR (0x200)
1321#define SPR_Exxx_BBEAR (0x201)
1322#define SPR_Exxx_BBTAR (0x202)
1323#define SPR_Exxx_L1CFG0 (0x203)
1324#define SPR_Exxx_NPIDR (0x205)
1325#define SPR_ATBL (0x20E)
1326#define SPR_ATBU (0x20F)
1327#define SPR_IBAT0U (0x210)
1328#define SPR_BOOKE_IVOR32 (0x210)
1329#define SPR_RCPU_MI_GRA (0x210)
1330#define SPR_IBAT0L (0x211)
1331#define SPR_BOOKE_IVOR33 (0x211)
1332#define SPR_IBAT1U (0x212)
1333#define SPR_BOOKE_IVOR34 (0x212)
1334#define SPR_IBAT1L (0x213)
1335#define SPR_BOOKE_IVOR35 (0x213)
1336#define SPR_IBAT2U (0x214)
1337#define SPR_BOOKE_IVOR36 (0x214)
1338#define SPR_IBAT2L (0x215)
1339#define SPR_BOOKE_IVOR37 (0x215)
1340#define SPR_IBAT3U (0x216)
1341#define SPR_IBAT3L (0x217)
1342#define SPR_DBAT0U (0x218)
1343#define SPR_RCPU_L2U_GRA (0x218)
1344#define SPR_DBAT0L (0x219)
1345#define SPR_DBAT1U (0x21A)
1346#define SPR_DBAT1L (0x21B)
1347#define SPR_DBAT2U (0x21C)
1348#define SPR_DBAT2L (0x21D)
1349#define SPR_DBAT3U (0x21E)
1350#define SPR_DBAT3L (0x21F)
1351#define SPR_IBAT4U (0x230)
1352#define SPR_RPCU_BBCMCR (0x230)
1353#define SPR_MPC_IC_CST (0x230)
1354#define SPR_Exxx_CTXCR (0x230)
1355#define SPR_IBAT4L (0x231)
1356#define SPR_MPC_IC_ADR (0x231)
1357#define SPR_Exxx_DBCR3 (0x231)
1358#define SPR_IBAT5U (0x232)
1359#define SPR_MPC_IC_DAT (0x232)
1360#define SPR_Exxx_DBCNT (0x232)
1361#define SPR_IBAT5L (0x233)
1362#define SPR_IBAT6U (0x234)
1363#define SPR_IBAT6L (0x235)
1364#define SPR_IBAT7U (0x236)
1365#define SPR_IBAT7L (0x237)
1366#define SPR_DBAT4U (0x238)
1367#define SPR_RCPU_L2U_MCR (0x238)
1368#define SPR_MPC_DC_CST (0x238)
1369#define SPR_Exxx_ALTCTXCR (0x238)
1370#define SPR_DBAT4L (0x239)
1371#define SPR_MPC_DC_ADR (0x239)
1372#define SPR_DBAT5U (0x23A)
1373#define SPR_BOOKE_MCSRR0 (0x23A)
1374#define SPR_MPC_DC_DAT (0x23A)
1375#define SPR_DBAT5L (0x23B)
1376#define SPR_BOOKE_MCSRR1 (0x23B)
1377#define SPR_DBAT6U (0x23C)
1378#define SPR_BOOKE_MCSR (0x23C)
1379#define SPR_DBAT6L (0x23D)
1380#define SPR_Exxx_MCAR (0x23D)
1381#define SPR_DBAT7U (0x23E)
1382#define SPR_BOOKE_DSRR0 (0x23E)
1383#define SPR_DBAT7L (0x23F)
1384#define SPR_BOOKE_DSRR1 (0x23F)
1385#define SPR_BOOKE_SPRG8 (0x25C)
1386#define SPR_BOOKE_SPRG9 (0x25D)
1387#define SPR_BOOKE_MAS0 (0x270)
1388#define SPR_BOOKE_MAS1 (0x271)
1389#define SPR_BOOKE_MAS2 (0x272)
1390#define SPR_BOOKE_MAS3 (0x273)
1391#define SPR_BOOKE_MAS4 (0x274)
1392#define SPR_BOOKE_MAS5 (0x275)
1393#define SPR_BOOKE_MAS6 (0x276)
1394#define SPR_BOOKE_PID1 (0x279)
1395#define SPR_BOOKE_PID2 (0x27A)
1396#define SPR_MPC_DPDR (0x280)
1397#define SPR_MPC_IMMR (0x288)
1398#define SPR_BOOKE_TLB0CFG (0x2B0)
1399#define SPR_BOOKE_TLB1CFG (0x2B1)
1400#define SPR_BOOKE_TLB2CFG (0x2B2)
1401#define SPR_BOOKE_TLB3CFG (0x2B3)
1402#define SPR_BOOKE_EPR (0x2BE)
1403#define SPR_PERF0 (0x300)
1404#define SPR_RCPU_MI_RBA0 (0x300)
1405#define SPR_MPC_MI_CTR (0x300)
1406#define SPR_PERF1 (0x301)
1407#define SPR_RCPU_MI_RBA1 (0x301)
1408#define SPR_PERF2 (0x302)
1409#define SPR_RCPU_MI_RBA2 (0x302)
1410#define SPR_MPC_MI_AP (0x302)
1411#define SPR_PERF3 (0x303)
082c6681 1412#define SPR_620_PMC1R (0x303)
80d11f44
JM
1413#define SPR_RCPU_MI_RBA3 (0x303)
1414#define SPR_MPC_MI_EPN (0x303)
1415#define SPR_PERF4 (0x304)
082c6681 1416#define SPR_620_PMC2R (0x304)
80d11f44
JM
1417#define SPR_PERF5 (0x305)
1418#define SPR_MPC_MI_TWC (0x305)
1419#define SPR_PERF6 (0x306)
1420#define SPR_MPC_MI_RPN (0x306)
1421#define SPR_PERF7 (0x307)
1422#define SPR_PERF8 (0x308)
1423#define SPR_RCPU_L2U_RBA0 (0x308)
1424#define SPR_MPC_MD_CTR (0x308)
1425#define SPR_PERF9 (0x309)
1426#define SPR_RCPU_L2U_RBA1 (0x309)
1427#define SPR_MPC_MD_CASID (0x309)
1428#define SPR_PERFA (0x30A)
1429#define SPR_RCPU_L2U_RBA2 (0x30A)
1430#define SPR_MPC_MD_AP (0x30A)
1431#define SPR_PERFB (0x30B)
082c6681 1432#define SPR_620_MMCR0R (0x30B)
80d11f44
JM
1433#define SPR_RCPU_L2U_RBA3 (0x30B)
1434#define SPR_MPC_MD_EPN (0x30B)
1435#define SPR_PERFC (0x30C)
1436#define SPR_MPC_MD_TWB (0x30C)
1437#define SPR_PERFD (0x30D)
1438#define SPR_MPC_MD_TWC (0x30D)
1439#define SPR_PERFE (0x30E)
1440#define SPR_MPC_MD_RPN (0x30E)
1441#define SPR_PERFF (0x30F)
1442#define SPR_MPC_MD_TW (0x30F)
1443#define SPR_UPERF0 (0x310)
1444#define SPR_UPERF1 (0x311)
1445#define SPR_UPERF2 (0x312)
1446#define SPR_UPERF3 (0x313)
082c6681 1447#define SPR_620_PMC1W (0x313)
80d11f44 1448#define SPR_UPERF4 (0x314)
082c6681 1449#define SPR_620_PMC2W (0x314)
80d11f44
JM
1450#define SPR_UPERF5 (0x315)
1451#define SPR_UPERF6 (0x316)
1452#define SPR_UPERF7 (0x317)
1453#define SPR_UPERF8 (0x318)
1454#define SPR_UPERF9 (0x319)
1455#define SPR_UPERFA (0x31A)
1456#define SPR_UPERFB (0x31B)
082c6681 1457#define SPR_620_MMCR0W (0x31B)
80d11f44
JM
1458#define SPR_UPERFC (0x31C)
1459#define SPR_UPERFD (0x31D)
1460#define SPR_UPERFE (0x31E)
1461#define SPR_UPERFF (0x31F)
1462#define SPR_RCPU_MI_RA0 (0x320)
1463#define SPR_MPC_MI_DBCAM (0x320)
1464#define SPR_RCPU_MI_RA1 (0x321)
1465#define SPR_MPC_MI_DBRAM0 (0x321)
1466#define SPR_RCPU_MI_RA2 (0x322)
1467#define SPR_MPC_MI_DBRAM1 (0x322)
1468#define SPR_RCPU_MI_RA3 (0x323)
1469#define SPR_RCPU_L2U_RA0 (0x328)
1470#define SPR_MPC_MD_DBCAM (0x328)
1471#define SPR_RCPU_L2U_RA1 (0x329)
1472#define SPR_MPC_MD_DBRAM0 (0x329)
1473#define SPR_RCPU_L2U_RA2 (0x32A)
1474#define SPR_MPC_MD_DBRAM1 (0x32A)
1475#define SPR_RCPU_L2U_RA3 (0x32B)
1476#define SPR_440_INV0 (0x370)
1477#define SPR_440_INV1 (0x371)
1478#define SPR_440_INV2 (0x372)
1479#define SPR_440_INV3 (0x373)
1480#define SPR_440_ITV0 (0x374)
1481#define SPR_440_ITV1 (0x375)
1482#define SPR_440_ITV2 (0x376)
1483#define SPR_440_ITV3 (0x377)
1484#define SPR_440_CCR1 (0x378)
1485#define SPR_DCRIPR (0x37B)
1486#define SPR_PPR (0x380)
bd928eba 1487#define SPR_750_GQR0 (0x390)
80d11f44 1488#define SPR_440_DNV0 (0x390)
bd928eba 1489#define SPR_750_GQR1 (0x391)
80d11f44 1490#define SPR_440_DNV1 (0x391)
bd928eba 1491#define SPR_750_GQR2 (0x392)
80d11f44 1492#define SPR_440_DNV2 (0x392)
bd928eba 1493#define SPR_750_GQR3 (0x393)
80d11f44 1494#define SPR_440_DNV3 (0x393)
bd928eba 1495#define SPR_750_GQR4 (0x394)
80d11f44 1496#define SPR_440_DTV0 (0x394)
bd928eba 1497#define SPR_750_GQR5 (0x395)
80d11f44 1498#define SPR_440_DTV1 (0x395)
bd928eba 1499#define SPR_750_GQR6 (0x396)
80d11f44 1500#define SPR_440_DTV2 (0x396)
bd928eba 1501#define SPR_750_GQR7 (0x397)
80d11f44 1502#define SPR_440_DTV3 (0x397)
bd928eba
JM
1503#define SPR_750_THRM4 (0x398)
1504#define SPR_750CL_HID2 (0x398)
80d11f44 1505#define SPR_440_DVLIM (0x398)
bd928eba 1506#define SPR_750_WPAR (0x399)
80d11f44 1507#define SPR_440_IVLIM (0x399)
bd928eba
JM
1508#define SPR_750_DMAU (0x39A)
1509#define SPR_750_DMAL (0x39B)
80d11f44
JM
1510#define SPR_440_RSTCFG (0x39B)
1511#define SPR_BOOKE_DCDBTRL (0x39C)
1512#define SPR_BOOKE_DCDBTRH (0x39D)
1513#define SPR_BOOKE_ICDBTRL (0x39E)
1514#define SPR_BOOKE_ICDBTRH (0x39F)
1515#define SPR_UMMCR2 (0x3A0)
1516#define SPR_UPMC5 (0x3A1)
1517#define SPR_UPMC6 (0x3A2)
1518#define SPR_UBAMR (0x3A7)
1519#define SPR_UMMCR0 (0x3A8)
1520#define SPR_UPMC1 (0x3A9)
1521#define SPR_UPMC2 (0x3AA)
1522#define SPR_USIAR (0x3AB)
1523#define SPR_UMMCR1 (0x3AC)
1524#define SPR_UPMC3 (0x3AD)
1525#define SPR_UPMC4 (0x3AE)
1526#define SPR_USDA (0x3AF)
1527#define SPR_40x_ZPR (0x3B0)
1528#define SPR_BOOKE_MAS7 (0x3B0)
1529#define SPR_620_PMR0 (0x3B0)
1530#define SPR_MMCR2 (0x3B0)
1531#define SPR_PMC5 (0x3B1)
1532#define SPR_40x_PID (0x3B1)
1533#define SPR_620_PMR1 (0x3B1)
1534#define SPR_PMC6 (0x3B2)
1535#define SPR_440_MMUCR (0x3B2)
1536#define SPR_620_PMR2 (0x3B2)
1537#define SPR_4xx_CCR0 (0x3B3)
1538#define SPR_BOOKE_EPLC (0x3B3)
1539#define SPR_620_PMR3 (0x3B3)
1540#define SPR_405_IAC3 (0x3B4)
1541#define SPR_BOOKE_EPSC (0x3B4)
1542#define SPR_620_PMR4 (0x3B4)
1543#define SPR_405_IAC4 (0x3B5)
1544#define SPR_620_PMR5 (0x3B5)
1545#define SPR_405_DVC1 (0x3B6)
1546#define SPR_620_PMR6 (0x3B6)
1547#define SPR_405_DVC2 (0x3B7)
1548#define SPR_620_PMR7 (0x3B7)
1549#define SPR_BAMR (0x3B7)
1550#define SPR_MMCR0 (0x3B8)
1551#define SPR_620_PMR8 (0x3B8)
1552#define SPR_PMC1 (0x3B9)
1553#define SPR_40x_SGR (0x3B9)
1554#define SPR_620_PMR9 (0x3B9)
1555#define SPR_PMC2 (0x3BA)
1556#define SPR_40x_DCWR (0x3BA)
1557#define SPR_620_PMRA (0x3BA)
1558#define SPR_SIAR (0x3BB)
1559#define SPR_405_SLER (0x3BB)
1560#define SPR_620_PMRB (0x3BB)
1561#define SPR_MMCR1 (0x3BC)
1562#define SPR_405_SU0R (0x3BC)
1563#define SPR_620_PMRC (0x3BC)
1564#define SPR_401_SKR (0x3BC)
1565#define SPR_PMC3 (0x3BD)
1566#define SPR_405_DBCR1 (0x3BD)
1567#define SPR_620_PMRD (0x3BD)
1568#define SPR_PMC4 (0x3BE)
1569#define SPR_620_PMRE (0x3BE)
1570#define SPR_SDA (0x3BF)
1571#define SPR_620_PMRF (0x3BF)
1572#define SPR_403_VTBL (0x3CC)
1573#define SPR_403_VTBU (0x3CD)
1574#define SPR_DMISS (0x3D0)
1575#define SPR_DCMP (0x3D1)
1576#define SPR_HASH1 (0x3D2)
1577#define SPR_HASH2 (0x3D3)
1578#define SPR_BOOKE_ICDBDR (0x3D3)
1579#define SPR_TLBMISS (0x3D4)
1580#define SPR_IMISS (0x3D4)
1581#define SPR_40x_ESR (0x3D4)
1582#define SPR_PTEHI (0x3D5)
1583#define SPR_ICMP (0x3D5)
1584#define SPR_40x_DEAR (0x3D5)
1585#define SPR_PTELO (0x3D6)
1586#define SPR_RPA (0x3D6)
1587#define SPR_40x_EVPR (0x3D6)
1588#define SPR_L3PM (0x3D7)
1589#define SPR_403_CDBCR (0x3D7)
4e777442 1590#define SPR_L3ITCR0 (0x3D8)
80d11f44
JM
1591#define SPR_TCR (0x3D8)
1592#define SPR_40x_TSR (0x3D8)
1593#define SPR_IBR (0x3DA)
1594#define SPR_40x_TCR (0x3DA)
1595#define SPR_ESASRR (0x3DB)
1596#define SPR_40x_PIT (0x3DB)
1597#define SPR_403_TBL (0x3DC)
1598#define SPR_403_TBU (0x3DD)
1599#define SPR_SEBR (0x3DE)
1600#define SPR_40x_SRR2 (0x3DE)
1601#define SPR_SER (0x3DF)
1602#define SPR_40x_SRR3 (0x3DF)
4e777442 1603#define SPR_L3OHCR (0x3E8)
80d11f44
JM
1604#define SPR_L3ITCR1 (0x3E9)
1605#define SPR_L3ITCR2 (0x3EA)
1606#define SPR_L3ITCR3 (0x3EB)
1607#define SPR_HID0 (0x3F0)
1608#define SPR_40x_DBSR (0x3F0)
1609#define SPR_HID1 (0x3F1)
1610#define SPR_IABR (0x3F2)
1611#define SPR_40x_DBCR0 (0x3F2)
1612#define SPR_601_HID2 (0x3F2)
1613#define SPR_Exxx_L1CSR0 (0x3F2)
1614#define SPR_ICTRL (0x3F3)
1615#define SPR_HID2 (0x3F3)
bd928eba 1616#define SPR_750CL_HID4 (0x3F3)
80d11f44
JM
1617#define SPR_Exxx_L1CSR1 (0x3F3)
1618#define SPR_440_DBDR (0x3F3)
1619#define SPR_LDSTDB (0x3F4)
bd928eba 1620#define SPR_750_TDCL (0x3F4)
80d11f44
JM
1621#define SPR_40x_IAC1 (0x3F4)
1622#define SPR_MMUCSR0 (0x3F4)
1623#define SPR_DABR (0x3F5)
3fc6c082 1624#define DABR_MASK (~(target_ulong)0x7)
80d11f44
JM
1625#define SPR_Exxx_BUCSR (0x3F5)
1626#define SPR_40x_IAC2 (0x3F5)
1627#define SPR_601_HID5 (0x3F5)
1628#define SPR_40x_DAC1 (0x3F6)
1629#define SPR_MSSCR0 (0x3F6)
1630#define SPR_970_HID5 (0x3F6)
1631#define SPR_MSSSR0 (0x3F7)
4e777442 1632#define SPR_MSSCR1 (0x3F7)
80d11f44
JM
1633#define SPR_DABRX (0x3F7)
1634#define SPR_40x_DAC2 (0x3F7)
1635#define SPR_MMUCFG (0x3F7)
1636#define SPR_LDSTCR (0x3F8)
1637#define SPR_L2PMCR (0x3F8)
bd928eba 1638#define SPR_750FX_HID2 (0x3F8)
082c6681 1639#define SPR_620_BUSCSR (0x3F8)
80d11f44
JM
1640#define SPR_Exxx_L1FINV0 (0x3F8)
1641#define SPR_L2CR (0x3F9)
082c6681 1642#define SPR_620_L2CR (0x3F9)
80d11f44 1643#define SPR_L3CR (0x3FA)
bd928eba 1644#define SPR_750_TDCH (0x3FA)
80d11f44
JM
1645#define SPR_IABR2 (0x3FA)
1646#define SPR_40x_DCCR (0x3FA)
082c6681 1647#define SPR_620_L2SR (0x3FA)
80d11f44
JM
1648#define SPR_ICTC (0x3FB)
1649#define SPR_40x_ICCR (0x3FB)
1650#define SPR_THRM1 (0x3FC)
1651#define SPR_403_PBL1 (0x3FC)
1652#define SPR_SP (0x3FD)
1653#define SPR_THRM2 (0x3FD)
1654#define SPR_403_PBU1 (0x3FD)
1655#define SPR_604_HID13 (0x3FD)
1656#define SPR_LT (0x3FE)
1657#define SPR_THRM3 (0x3FE)
1658#define SPR_RCPU_FPECR (0x3FE)
1659#define SPR_403_PBL2 (0x3FE)
1660#define SPR_PIR (0x3FF)
1661#define SPR_403_PBU2 (0x3FF)
1662#define SPR_601_HID15 (0x3FF)
1663#define SPR_604_HID15 (0x3FF)
1664#define SPR_E500_SVR (0x3FF)
79aceca5 1665
c29b735c
NF
1666/*****************************************************************************/
1667/* PowerPC Instructions types definitions */
1668enum {
1669 PPC_NONE = 0x0000000000000000ULL,
1670 /* PowerPC base instructions set */
1671 PPC_INSNS_BASE = 0x0000000000000001ULL,
1672 /* integer operations instructions */
1673#define PPC_INTEGER PPC_INSNS_BASE
1674 /* flow control instructions */
1675#define PPC_FLOW PPC_INSNS_BASE
1676 /* virtual memory instructions */
1677#define PPC_MEM PPC_INSNS_BASE
1678 /* ld/st with reservation instructions */
1679#define PPC_RES PPC_INSNS_BASE
1680 /* spr/msr access instructions */
1681#define PPC_MISC PPC_INSNS_BASE
1682 /* Deprecated instruction sets */
1683 /* Original POWER instruction set */
1684 PPC_POWER = 0x0000000000000002ULL,
1685 /* POWER2 instruction set extension */
1686 PPC_POWER2 = 0x0000000000000004ULL,
1687 /* Power RTC support */
1688 PPC_POWER_RTC = 0x0000000000000008ULL,
1689 /* Power-to-PowerPC bridge (601) */
1690 PPC_POWER_BR = 0x0000000000000010ULL,
1691 /* 64 bits PowerPC instruction set */
1692 PPC_64B = 0x0000000000000020ULL,
1693 /* New 64 bits extensions (PowerPC 2.0x) */
1694 PPC_64BX = 0x0000000000000040ULL,
1695 /* 64 bits hypervisor extensions */
1696 PPC_64H = 0x0000000000000080ULL,
1697 /* New wait instruction (PowerPC 2.0x) */
1698 PPC_WAIT = 0x0000000000000100ULL,
1699 /* Time base mftb instruction */
1700 PPC_MFTB = 0x0000000000000200ULL,
1701
1702 /* Fixed-point unit extensions */
1703 /* PowerPC 602 specific */
1704 PPC_602_SPEC = 0x0000000000000400ULL,
1705 /* isel instruction */
1706 PPC_ISEL = 0x0000000000000800ULL,
1707 /* popcntb instruction */
1708 PPC_POPCNTB = 0x0000000000001000ULL,
1709 /* string load / store */
1710 PPC_STRING = 0x0000000000002000ULL,
1711
1712 /* Floating-point unit extensions */
1713 /* Optional floating point instructions */
1714 PPC_FLOAT = 0x0000000000010000ULL,
1715 /* New floating-point extensions (PowerPC 2.0x) */
1716 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1717 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1718 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1719 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1720 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1721 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1722 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1723
1724 /* Vector/SIMD extensions */
1725 /* Altivec support */
1726 PPC_ALTIVEC = 0x0000000001000000ULL,
1727 /* PowerPC 2.03 SPE extension */
1728 PPC_SPE = 0x0000000002000000ULL,
1729 /* PowerPC 2.03 SPE single-precision floating-point extension */
1730 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1731 /* PowerPC 2.03 SPE double-precision floating-point extension */
1732 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1733
1734 /* Optional memory control instructions */
1735 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1736 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1737 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1738 /* sync instruction */
1739 PPC_MEM_SYNC = 0x0000000080000000ULL,
1740 /* eieio instruction */
1741 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1742
1743 /* Cache control instructions */
1744 PPC_CACHE = 0x0000000200000000ULL,
1745 /* icbi instruction */
1746 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1747 /* dcbz instruction with fixed cache line size */
1748 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1749 /* dcbz instruction with tunable cache line size */
1750 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1751 /* dcba instruction */
1752 PPC_CACHE_DCBA = 0x0000002000000000ULL,
1753 /* Freescale cache locking instructions */
1754 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1755
1756 /* MMU related extensions */
1757 /* external control instructions */
1758 PPC_EXTERN = 0x0000010000000000ULL,
1759 /* segment register access instructions */
1760 PPC_SEGMENT = 0x0000020000000000ULL,
1761 /* PowerPC 6xx TLB management instructions */
1762 PPC_6xx_TLB = 0x0000040000000000ULL,
1763 /* PowerPC 74xx TLB management instructions */
1764 PPC_74xx_TLB = 0x0000080000000000ULL,
1765 /* PowerPC 40x TLB management instructions */
1766 PPC_40x_TLB = 0x0000100000000000ULL,
1767 /* segment register access instructions for PowerPC 64 "bridge" */
1768 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1769 /* SLB management */
1770 PPC_SLBI = 0x0000400000000000ULL,
1771
1772 /* Embedded PowerPC dedicated instructions */
1773 PPC_WRTEE = 0x0001000000000000ULL,
1774 /* PowerPC 40x exception model */
1775 PPC_40x_EXCP = 0x0002000000000000ULL,
1776 /* PowerPC 405 Mac instructions */
1777 PPC_405_MAC = 0x0004000000000000ULL,
1778 /* PowerPC 440 specific instructions */
1779 PPC_440_SPEC = 0x0008000000000000ULL,
1780 /* BookE (embedded) PowerPC specification */
1781 PPC_BOOKE = 0x0010000000000000ULL,
1782 /* mfapidi instruction */
1783 PPC_MFAPIDI = 0x0020000000000000ULL,
1784 /* tlbiva instruction */
1785 PPC_TLBIVA = 0x0040000000000000ULL,
1786 /* tlbivax instruction */
1787 PPC_TLBIVAX = 0x0080000000000000ULL,
1788 /* PowerPC 4xx dedicated instructions */
1789 PPC_4xx_COMMON = 0x0100000000000000ULL,
1790 /* PowerPC 40x ibct instructions */
1791 PPC_40x_ICBT = 0x0200000000000000ULL,
1792 /* rfmci is not implemented in all BookE PowerPC */
1793 PPC_RFMCI = 0x0400000000000000ULL,
1794 /* rfdi instruction */
1795 PPC_RFDI = 0x0800000000000000ULL,
1796 /* DCR accesses */
1797 PPC_DCR = 0x1000000000000000ULL,
1798 /* DCR extended accesse */
1799 PPC_DCRX = 0x2000000000000000ULL,
1800 /* user-mode DCR access, implemented in PowerPC 460 */
1801 PPC_DCRUX = 0x4000000000000000ULL,
eaabeef2
DG
1802 /* popcntw and popcntd instructions */
1803 PPC_POPCNTWD = 0x8000000000000000ULL,
01662f3e
AG
1804
1805 /* extended type values */
1806
1807 /* BookE 2.06 PowerPC specification */
1808 PPC2_BOOKE206 = 0x0000000000000001ULL,
c29b735c
NF
1809};
1810
76a66253 1811/*****************************************************************************/
9a64fbe4
FB
1812/* Memory access type :
1813 * may be needed for precise access rights control and precise exceptions.
1814 */
79aceca5 1815enum {
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FB
1816 /* 1 bit to define user level / supervisor access */
1817 ACCESS_USER = 0x00,
1818 ACCESS_SUPER = 0x01,
1819 /* Type of instruction that generated the access */
1820 ACCESS_CODE = 0x10, /* Code fetch access */
1821 ACCESS_INT = 0x20, /* Integer load/store access */
1822 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1823 ACCESS_RES = 0x40, /* load/store with reservation */
1824 ACCESS_EXT = 0x50, /* external access */
1825 ACCESS_CACHE = 0x60, /* Cache manipulation */
1826};
1827
47103572
JM
1828/* Hardware interruption sources:
1829 * all those exception can be raised simulteaneously
1830 */
e9df014c
JM
1831/* Input pins definitions */
1832enum {
1833 /* 6xx bus input pins */
24be5ae3
JM
1834 PPC6xx_INPUT_HRESET = 0,
1835 PPC6xx_INPUT_SRESET = 1,
1836 PPC6xx_INPUT_CKSTP_IN = 2,
1837 PPC6xx_INPUT_MCP = 3,
1838 PPC6xx_INPUT_SMI = 4,
1839 PPC6xx_INPUT_INT = 5,
d68f1306
JM
1840 PPC6xx_INPUT_TBEN = 6,
1841 PPC6xx_INPUT_WAKEUP = 7,
1842 PPC6xx_INPUT_NB,
24be5ae3
JM
1843};
1844
1845enum {
e9df014c 1846 /* Embedded PowerPC input pins */
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JM
1847 PPCBookE_INPUT_HRESET = 0,
1848 PPCBookE_INPUT_SRESET = 1,
1849 PPCBookE_INPUT_CKSTP_IN = 2,
1850 PPCBookE_INPUT_MCP = 3,
1851 PPCBookE_INPUT_SMI = 4,
1852 PPCBookE_INPUT_INT = 5,
1853 PPCBookE_INPUT_CINT = 6,
d68f1306 1854 PPCBookE_INPUT_NB,
24be5ae3
JM
1855};
1856
9fdc60bf
AJ
1857enum {
1858 /* PowerPC E500 input pins */
1859 PPCE500_INPUT_RESET_CORE = 0,
1860 PPCE500_INPUT_MCK = 1,
1861 PPCE500_INPUT_CINT = 3,
1862 PPCE500_INPUT_INT = 4,
1863 PPCE500_INPUT_DEBUG = 6,
1864 PPCE500_INPUT_NB,
1865};
1866
a750fc0b 1867enum {
4e290a0b
JM
1868 /* PowerPC 40x input pins */
1869 PPC40x_INPUT_RESET_CORE = 0,
1870 PPC40x_INPUT_RESET_CHIP = 1,
1871 PPC40x_INPUT_RESET_SYS = 2,
1872 PPC40x_INPUT_CINT = 3,
1873 PPC40x_INPUT_INT = 4,
1874 PPC40x_INPUT_HALT = 5,
1875 PPC40x_INPUT_DEBUG = 6,
1876 PPC40x_INPUT_NB,
e9df014c
JM
1877};
1878
b4095fed
JM
1879enum {
1880 /* RCPU input pins */
1881 PPCRCPU_INPUT_PORESET = 0,
1882 PPCRCPU_INPUT_HRESET = 1,
1883 PPCRCPU_INPUT_SRESET = 2,
1884 PPCRCPU_INPUT_IRQ0 = 3,
1885 PPCRCPU_INPUT_IRQ1 = 4,
1886 PPCRCPU_INPUT_IRQ2 = 5,
1887 PPCRCPU_INPUT_IRQ3 = 6,
1888 PPCRCPU_INPUT_IRQ4 = 7,
1889 PPCRCPU_INPUT_IRQ5 = 8,
1890 PPCRCPU_INPUT_IRQ6 = 9,
1891 PPCRCPU_INPUT_IRQ7 = 10,
1892 PPCRCPU_INPUT_NB,
1893};
1894
00af685f 1895#if defined(TARGET_PPC64)
d0dfae6e
JM
1896enum {
1897 /* PowerPC 970 input pins */
1898 PPC970_INPUT_HRESET = 0,
1899 PPC970_INPUT_SRESET = 1,
1900 PPC970_INPUT_CKSTP = 2,
1901 PPC970_INPUT_TBEN = 3,
1902 PPC970_INPUT_MCP = 4,
1903 PPC970_INPUT_INT = 5,
1904 PPC970_INPUT_THINT = 6,
7b62a955 1905 PPC970_INPUT_NB,
9d52e907
DG
1906};
1907
1908enum {
1909 /* POWER7 input pins */
1910 POWER7_INPUT_INT = 0,
1911 /* POWER7 probably has other inputs, but we don't care about them
1912 * for any existing machine. We can wire these up when we need
1913 * them */
1914 POWER7_INPUT_NB,
d0dfae6e 1915};
00af685f 1916#endif
d0dfae6e 1917
e9df014c 1918/* Hardware exceptions definitions */
47103572 1919enum {
e9df014c 1920 /* External hardware exception sources */
e1833e1f 1921 PPC_INTERRUPT_RESET = 0, /* Reset exception */
d68f1306
JM
1922 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
1923 PPC_INTERRUPT_MCK, /* Machine check exception */
1924 PPC_INTERRUPT_EXT, /* External interrupt */
1925 PPC_INTERRUPT_SMI, /* System management interrupt */
1926 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
1927 PPC_INTERRUPT_DEBUG, /* External debug exception */
1928 PPC_INTERRUPT_THERM, /* Thermal exception */
e9df014c 1929 /* Internal hardware exception sources */
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JM
1930 PPC_INTERRUPT_DECR, /* Decrementer exception */
1931 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
1932 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
1933 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
1934 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
1935 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
1936 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
1937 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
47103572
JM
1938};
1939
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FB
1940/*****************************************************************************/
1941
6b917547
AL
1942static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
1943 target_ulong *cs_base, int *flags)
1944{
1945 *pc = env->nip;
1946 *cs_base = 0;
1947 *flags = env->hflags;
1948}
1949
174c80d5
NF
1950static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
1951{
1952#if defined(TARGET_PPC64)
1953 /* The kernel checks TIF_32BIT here; we don't support loading 32-bit
1954 binaries on PPC64 yet. */
1955 env->gpr[13] = newtls;
1956#else
1957 env->gpr[2] = newtls;
1958#endif
1959}
1960
01662f3e 1961#if !defined(CONFIG_USER_ONLY)
d1e256fe 1962static inline int booke206_tlbm_id(CPUState *env, ppcmas_tlb_t *tlbm)
01662f3e 1963{
d1e256fe 1964 uintptr_t tlbml = (uintptr_t)tlbm;
1c53accc 1965 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
01662f3e 1966
1c53accc 1967 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
01662f3e
AG
1968}
1969
1970static inline int booke206_tlb_size(CPUState *env, int tlbn)
1971{
1972 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
1973 int r = tlbncfg & TLBnCFG_N_ENTRY;
1974 return r;
1975}
1976
1977static inline int booke206_tlb_ways(CPUState *env, int tlbn)
1978{
1979 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
1980 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
1981 return r;
1982}
1983
d1e256fe 1984static inline int booke206_tlbm_to_tlbn(CPUState *env, ppcmas_tlb_t *tlbm)
01662f3e 1985{
d1e256fe 1986 int id = booke206_tlbm_id(env, tlbm);
01662f3e
AG
1987 int end = 0;
1988 int i;
1989
1990 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
1991 end += booke206_tlb_size(env, i);
1992 if (id < end) {
1993 return i;
1994 }
1995 }
1996
1997 cpu_abort(env, "Unknown TLBe: %d\n", id);
1998 return 0;
1999}
2000
d1e256fe 2001static inline int booke206_tlbm_to_way(CPUState *env, ppcmas_tlb_t *tlb)
01662f3e 2002{
d1e256fe
AG
2003 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2004 int tlbid = booke206_tlbm_id(env, tlb);
01662f3e
AG
2005 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2006}
2007
d1e256fe 2008static inline ppcmas_tlb_t *booke206_get_tlbm(CPUState *env, const int tlbn,
01662f3e
AG
2009 target_ulong ea, int way)
2010{
2011 int r;
2012 uint32_t ways = booke206_tlb_ways(env, tlbn);
2013 int ways_bits = ffs(ways) - 1;
2014 int tlb_bits = ffs(booke206_tlb_size(env, tlbn)) - 1;
2015 int i;
2016
2017 way &= ways - 1;
2018 ea >>= MAS2_EPN_SHIFT;
2019 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2020 r = (ea << ways_bits) | way;
2021
2022 /* bump up to tlbn index */
2023 for (i = 0; i < tlbn; i++) {
2024 r += booke206_tlb_size(env, i);
2025 }
2026
1c53accc 2027 return &env->tlb.tlbm[r];
01662f3e
AG
2028}
2029
2030#endif
2031
d569956e
DG
2032extern void (*cpu_ppc_hypercall)(CPUState *);
2033
f081c76c
BS
2034static inline bool cpu_has_work(CPUState *env)
2035{
2036 return msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD);
2037}
2038
2039#include "exec-all.h"
2040
2041static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
2042{
2043 env->nip = tb->pc;
2044}
2045
79aceca5 2046#endif /* !defined (__CPU_PPC_H__) */