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hflags computation cleanup, by Aurelien Jarno.
[qemu.git] / target-ppc / cpu.h
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation cpu definitions for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#if !defined (__CPU_PPC_H__)
21#define __CPU_PPC_H__
22
3fc6c082 23#include "config.h"
de270b3c 24#include <inttypes.h>
3fc6c082 25
76a66253
JM		 26#if defined (TARGET_PPC64)
27typedef uint64_t ppc_gpr_t;
0487d6a8 28#define TARGET_GPR_BITS 64
d9d7210c 29#define TARGET_LONG_BITS 64
76a66253 30#define REGX "%016" PRIx64
35cdaad6
JM		 31#define TARGET_PAGE_BITS 12
32#elif defined(TARGET_PPCEMB)
8b67546f 33/* BookE have 36 bits physical address space */
e96efcfc 34#define TARGET_PHYS_ADDR_BITS 64
76a66253
JM		 35/* GPR are 64 bits: used by vector extension */
36typedef uint64_t ppc_gpr_t;
0487d6a8 37#define TARGET_GPR_BITS 64
d9d7210c 38#define TARGET_LONG_BITS 32
1b9eb036 39#define REGX "%016" PRIx64
d9d7210c
JM		 40#if defined(CONFIG_USER_ONLY)
41/* It looks like a lot of Linux programs assume page size
42 * is 4kB long. This is evil, but we have to deal with it...
43 */
44#define TARGET_PAGE_BITS 12
45#else
35cdaad6
JM		 46/* Pages can be 1 kB small */
47#define TARGET_PAGE_BITS 10
d9d7210c
JM		 48#endif
49#else
50#if (HOST_LONG_BITS >= 64)
51/* When using 64 bits temporary registers,
52 * we can use 64 bits GPR with no extra cost
53 * It's even an optimization as it will prevent
54 * the compiler to do unuseful masking in the micro-ops.
55 */
56typedef uint64_t ppc_gpr_t;
57#define TARGET_GPR_BITS 64
71c8b8fd 58#define REGX "%08" PRIx64
76a66253
JM		 59#else
60typedef uint32_t ppc_gpr_t;
0487d6a8 61#define TARGET_GPR_BITS 32
71c8b8fd 62#define REGX "%08" PRIx32
d9d7210c
JM		 63#endif
64#define TARGET_LONG_BITS 32
35cdaad6 65#define TARGET_PAGE_BITS 12
76a66253 66#endif
3cf1e035 67
79aceca5
FB		 68#include "cpu-defs.h"
69
e96efcfc
JM		 70#define ADDRX TARGET_FMT_lx
71#define PADDRX TARGET_FMT_plx
72
79aceca5
FB		 73#include <setjmp.h>
74
4ecc3190
FB		 75#include "softfloat.h"
76
1fddef4b
FB		 77#define TARGET_HAS_ICE 1
78
76a66253
JM		 79#if defined (TARGET_PPC64)
80#define ELF_MACHINE EM_PPC64
81#else
82#define ELF_MACHINE EM_PPC
83#endif
9042c0e2 84
fdabc366
FB		 85/* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC
86 * have different cache line sizes
87 */
88#define ICACHE_LINE_SIZE 32
89#define DCACHE_LINE_SIZE 32
90
3fc6c082
FB		 91/*****************************************************************************/
92/* PVR definitions for most known PowerPC */
93enum {
94 /* PowerPC 401 cores */
95 CPU_PPC_401A1 = 0x00210000,
96 CPU_PPC_401B2 = 0x00220000,
2662a059
JM		 97#if 0
98 CPU_PPC_401B3 = xxx,
99#endif
3fc6c082
FB		 100 CPU_PPC_401C2 = 0x00230000,
101 CPU_PPC_401D2 = 0x00240000,
102 CPU_PPC_401E2 = 0x00250000,
103 CPU_PPC_401F2 = 0x00260000,
104 CPU_PPC_401G2 = 0x00270000,
2662a059
JM		 105#if 0
106 CPU_PPC_401GF = xxx,
107#endif
76a66253
JM		 108#define CPU_PPC_401 CPU_PPC_401G2
109 CPU_PPC_IOP480 = 0x40100000, /* 401B2 ? */
110 CPU_PPC_COBRA = 0x10100000, /* IBM Processor for Network Resources */
3fc6c082 111 /* PowerPC 403 cores */
76a66253 112 CPU_PPC_403GA = 0x00200011,
3fc6c082
FB		 113 CPU_PPC_403GB = 0x00200100,
114 CPU_PPC_403GC = 0x00200200,
115 CPU_PPC_403GCX = 0x00201400,
2662a059
JM		 116#if 0
117 CPU_PPC_403GP = xxx,
118#endif
76a66253 119#define CPU_PPC_403 CPU_PPC_403GCX
3fc6c082 120 /* PowerPC 405 cores */
2662a059
JM		 121#if 0
122 CPU_PPC_405A3 = xxx,
123#endif
124#if 0
125 CPU_PPC_405A4 = xxx,
126#endif
127#if 0
128 CPU_PPC_405B3 = xxx,
129#endif
130 CPU_PPC_405D2 = 0x20010000,
131 CPU_PPC_405D4 = 0x41810000,
76a66253
JM		 132 CPU_PPC_405CR = 0x40110145,
133#define CPU_PPC_405GP CPU_PPC_405CR
134 CPU_PPC_405EP = 0x51210950,
2662a059
JM		 135#if 0
136 CPU_PPC_405EZ = xxx,
137#endif
76a66253 138 CPU_PPC_405GPR = 0x50910951,
2662a059
JM		 139#if 0
140 CPU_PPC_405LP = xxx,
141#endif
76a66253
JM		 142#define CPU_PPC_405 CPU_PPC_405D4
143 CPU_PPC_NPE405H = 0x414100C0,
144 CPU_PPC_NPE405H2 = 0x41410140,
145 CPU_PPC_NPE405L = 0x416100C0,
2662a059
JM		 146#if 0
147 CPU_PPC_LC77700 = xxx,
148#endif
76a66253
JM		 149 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
150#if 0
151 CPU_PPC_STB01000 = xxx,
152#endif
3fc6c082 153#if 0
76a66253
JM		 154 CPU_PPC_STB01010 = xxx,
155#endif
156#if 0
157 CPU_PPC_STB0210 = xxx,
3fc6c082
FB		 158#endif
159 CPU_PPC_STB03 = 0x40310000,
160#if 0
76a66253 161 CPU_PPC_STB043 = xxx,
3fc6c082 162#endif
76a66253
JM		 163#if 0
164 CPU_PPC_STB045 = xxx,
165#endif
166 CPU_PPC_STB25 = 0x51510950,
3fc6c082
FB		 167#if 0
168 CPU_PPC_STB130 = xxx,
169#endif
76a66253
JM		 170 /* Xilinx cores */
171 CPU_PPC_X2VP4 = 0x20010820,
172#define CPU_PPC_X2VP7 CPU_PPC_X2VP4
173 CPU_PPC_X2VP20 = 0x20010860,
174#define CPU_PPC_X2VP50 CPU_PPC_X2VP20
3fc6c082 175 /* PowerPC 440 cores */
76a66253
JM		 176 CPU_PPC_440EP = 0x422218D3,
177#define CPU_PPC_440GR CPU_PPC_440EP
178 CPU_PPC_440GP = 0x40120481,
2662a059
JM		 179#if 0
180 CPU_PPC_440GRX = xxx,
181#endif
76a66253
JM		 182 CPU_PPC_440GX = 0x51B21850,
183 CPU_PPC_440GXc = 0x51B21892,
184 CPU_PPC_440GXf = 0x51B21894,
185 CPU_PPC_440SP = 0x53221850,
186 CPU_PPC_440SP2 = 0x53221891,
187 CPU_PPC_440SPE = 0x53421890,
2662a059
JM		 188 /* PowerPC 460 cores */
189#if 0
190 CPU_PPC_464H90 = xxx,
191#endif
192#if 0
193 CPU_PPC_464H90FP = xxx,
194#endif
76a66253
JM		 195 /* PowerPC MPC 5xx cores */
196 CPU_PPC_5xx = 0x00020020,
197 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
3fc6c082 198 CPU_PPC_8xx = 0x00500000,
76a66253
JM		 199 /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
200 CPU_PPC_82xx_HIP3 = 0x00810101,
201 CPU_PPC_82xx_HIP4 = 0x80811014,
202 CPU_PPC_827x = 0x80822013,
203 /* eCores */
204 CPU_PPC_e200 = 0x81120000,
205 CPU_PPC_e500v110 = 0x80200010,
206 CPU_PPC_e500v120 = 0x80200020,
207 CPU_PPC_e500v210 = 0x80210010,
208 CPU_PPC_e500v220 = 0x80210020,
209#define CPU_PPC_e500 CPU_PPC_e500v220
210 CPU_PPC_e600 = 0x80040010,
3fc6c082 211 /* PowerPC 6xx cores */
76a66253
JM		 212 CPU_PPC_601 = 0x00010001,
213 CPU_PPC_602 = 0x00050100,
214 CPU_PPC_603 = 0x00030100,
215 CPU_PPC_603E = 0x00060101,
216 CPU_PPC_603P = 0x00070000,
217 CPU_PPC_603E7v = 0x00070100,
218 CPU_PPC_603E7v2 = 0x00070201,
219 CPU_PPC_603E7 = 0x00070200,
220 CPU_PPC_603R = 0x00071201,
221 CPU_PPC_G2 = 0x00810011,
222 CPU_PPC_G2H4 = 0x80811010,
223 CPU_PPC_G2gp = 0x80821010,
224 CPU_PPC_G2ls = 0x90810010,
225 CPU_PPC_G2LE = 0x80820010,
226 CPU_PPC_G2LEgp = 0x80822010,
227 CPU_PPC_G2LEls = 0xA0822010,
3fc6c082 228 CPU_PPC_604 = 0x00040000,
76a66253
JM		 229 CPU_PPC_604E = 0x00090100, /* Also 2110 & 2120 */
230 CPU_PPC_604R = 0x000a0101,
3fc6c082
FB		 231 /* PowerPC 74x/75x cores (aka G3) */
232 CPU_PPC_74x = 0x00080000,
76a66253 233 CPU_PPC_740E = 0x00080100,
3fc6c082 234 CPU_PPC_74xP = 0x10080000,
2662a059 235 CPU_PPC_750E = 0x00080200,
76a66253
JM		 236 CPU_PPC_750CXE21 = 0x00082201,
237 CPU_PPC_750CXE22 = 0x00082212,
238 CPU_PPC_750CXE23 = 0x00082203,
3fc6c082
FB		 239 CPU_PPC_750CXE24 = 0x00082214,
240 CPU_PPC_750CXE24b = 0x00083214,
241 CPU_PPC_750CXE31 = 0x00083211,
242 CPU_PPC_750CXE31b = 0x00083311,
243#define CPU_PPC_750CXE CPU_PPC_750CXE31b
76a66253
JM		 244 CPU_PPC_750CXR = 0x00083410,
245 CPU_PPC_750FX10 = 0x70000100,
246 CPU_PPC_750FX20 = 0x70000200,
247 CPU_PPC_750FX21 = 0x70000201,
248 CPU_PPC_750FX22 = 0x70000202,
249 CPU_PPC_750FX23 = 0x70000203,
250#define CPU_PPC_750FX CPU_PPC_750FX23
251 CPU_PPC_750FL = 0x700A0203,
252 CPU_PPC_750GX10 = 0x70020100,
253 CPU_PPC_750GX11 = 0x70020101,
254 CPU_PPC_750GX12 = 0x70020102,
255#define CPU_PPC_750GX CPU_PPC_750GX12
256 CPU_PPC_750GL = 0x70020102,
257 CPU_PPC_750L30 = 0x00088300,
258 CPU_PPC_750L32 = 0x00088302,
2662a059 259#define CPU_PPC_750L CPU_PPC_750L32
76a66253 260 CPU_PPC_750CL = 0x00087200,
2662a059
JM		 261 CPU_PPC_755_10 = 0x00083100,
262 CPU_PPC_755_11 = 0x00083101,
263 CPU_PPC_755_20 = 0x00083200,
264 CPU_PPC_755D = 0x00083202,
265 CPU_PPC_755E = 0x00083203,
266#define CPU_PPC_755 CPU_PPC_755E
3fc6c082 267 /* PowerPC 74xx cores (aka G4) */
76a66253
JM		 268 CPU_PPC_7400 = 0x000C0100,
269 CPU_PPC_7410C = 0x800C1102,
270 CPU_PPC_7410D = 0x800C1103,
271 CPU_PPC_7410E = 0x800C1104,
2662a059 272#define CPU_PPC_7410 CPU_PPC_7410E
76a66253
JM		 273 CPU_PPC_7441 = 0x80000210,
274 CPU_PPC_7445 = 0x80010100,
275 CPU_PPC_7447 = 0x80020100,
276 CPU_PPC_7447A = 0x80030101,
277 CPU_PPC_7448 = 0x80040100,
278 CPU_PPC_7450 = 0x80000200,
279 CPU_PPC_7450b = 0x80000201,
3fc6c082 280 CPU_PPC_7451 = 0x80000203,
76a66253
JM		 281 CPU_PPC_7451G = 0x80000210,
282 CPU_PPC_7455 = 0x80010201,
283 CPU_PPC_7455F = 0x80010303,
284 CPU_PPC_7455G = 0x80010304,
285 CPU_PPC_7457 = 0x80020101,
286 CPU_PPC_7457C = 0x80020102,
3fc6c082
FB		 287 CPU_PPC_7457A = 0x80030000,
288 /* 64 bits PowerPC */
289 CPU_PPC_620 = 0x00140000,
290 CPU_PPC_630 = 0x00400000,
291 CPU_PPC_631 = 0x00410000,
292 CPU_PPC_POWER4 = 0x00350000,
293 CPU_PPC_POWER4P = 0x00380000,
294 CPU_PPC_POWER5 = 0x003A0000,
295 CPU_PPC_POWER5P = 0x003B0000,
2662a059
JM		 296#if 0
297 CPU_PPC_POWER6 = xxx,
298#endif
3fc6c082 299 CPU_PPC_970 = 0x00390000,
76a66253
JM		 300 CPU_PPC_970FX10 = 0x00391100,
301 CPU_PPC_970FX20 = 0x003C0200,
302 CPU_PPC_970FX21 = 0x003C0201,
303 CPU_PPC_970FX30 = 0x003C0300,
304 CPU_PPC_970FX31 = 0x003C0301,
305#define CPU_PPC_970FX CPU_PPC_970FX31
306 CPU_PPC_970MP10 = 0x00440100,
307 CPU_PPC_970MP11 = 0x00440101,
308#define CPU_PPC_970MP CPU_PPC_970MP11
309 CPU_PPC_CELL10 = 0x00700100,
310 CPU_PPC_CELL20 = 0x00700400,
311 CPU_PPC_CELL30 = 0x00700500,
312 CPU_PPC_CELL31 = 0x00700501,
313#define CPU_PPC_CELL32 CPU_PPC_CELL31
314#define CPU_PPC_CELL CPU_PPC_CELL32
3fc6c082
FB		 315 CPU_PPC_RS64 = 0x00330000,
316 CPU_PPC_RS64II = 0x00340000,
317 CPU_PPC_RS64III = 0x00360000,
318 CPU_PPC_RS64IV = 0x00370000,
319 /* Original POWER */
320 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
321 * POWER2 (RIOS2) & RSC2 (P2SC) here
322 */
323#if 0
324 CPU_POWER = xxx,
325#endif
326#if 0
327 CPU_POWER2 = xxx,
328#endif
329};
330
76a66253 331/* System version register (used on MPC 8xxx) */
3fc6c082
FB		 332enum {
333 PPC_SVR_8540 = 0x80300000,
76a66253
JM		 334 PPC_SVR_8541E = 0x807A0010,
335 PPC_SVR_8543v10 = 0x80320010,
336 PPC_SVR_8543v11 = 0x80320011,
337 PPC_SVR_8543v20 = 0x80320020,
338 PPC_SVR_8543Ev10 = 0x803A0010,
339 PPC_SVR_8543Ev11 = 0x803A0011,
340 PPC_SVR_8543Ev20 = 0x803A0020,
341 PPC_SVR_8545 = 0x80310220,
342 PPC_SVR_8545E = 0x80390220,
343 PPC_SVR_8547E = 0x80390120,
344 PPC_SCR_8548v10 = 0x80310010,
345 PPC_SCR_8548v11 = 0x80310011,
346 PPC_SCR_8548v20 = 0x80310020,
347 PPC_SVR_8548Ev10 = 0x80390010,
348 PPC_SVR_8548Ev11 = 0x80390011,
349 PPC_SVR_8548Ev20 = 0x80390020,
350 PPC_SVR_8555E = 0x80790010,
351 PPC_SVR_8560v10 = 0x80700010,
352 PPC_SVR_8560v20 = 0x80700020,
3fc6c082
FB		 353};
354
355/*****************************************************************************/
9a64fbe4
FB		 356/* Instruction types */
357enum {
3fc6c082
FB		 358 PPC_NONE = 0x00000000,
359 /* integer operations instructions */
360 /* flow control instructions */
361 /* virtual memory instructions */
362 /* ld/st with reservation instructions */
363 /* cache control instructions */
364 /* spr/msr access instructions */
0487d6a8 365 PPC_INSNS_BASE = 0x0000000000000001ULL,
3fc6c082
FB		 366#define PPC_INTEGER PPC_INSNS_BASE
367#define PPC_FLOW PPC_INSNS_BASE
368#define PPC_MEM PPC_INSNS_BASE
369#define PPC_RES PPC_INSNS_BASE
370#define PPC_CACHE PPC_INSNS_BASE
371#define PPC_MISC PPC_INSNS_BASE
372 /* floating point operations instructions */
0487d6a8 373 PPC_FLOAT = 0x0000000000000002ULL,
3fc6c082 374 /* more floating point operations instructions */
0487d6a8 375 PPC_FLOAT_EXT = 0x0000000000000004ULL,
3fc6c082 376 /* external control instructions */
0487d6a8 377 PPC_EXTERN = 0x0000000000000008ULL,
3fc6c082 378 /* segment register access instructions */
0487d6a8 379 PPC_SEGMENT = 0x0000000000000010ULL,
3fc6c082 380 /* Optional cache control instructions */
0487d6a8 381 PPC_CACHE_OPT = 0x0000000000000020ULL,
3fc6c082 382 /* Optional floating point op instructions */
0487d6a8 383 PPC_FLOAT_OPT = 0x0000000000000040ULL,
3fc6c082 384 /* Optional memory control instructions */
0487d6a8
JM		 385 PPC_MEM_TLBIA = 0x0000000000000080ULL,
386 PPC_MEM_TLBIE = 0x0000000000000100ULL,
387 PPC_MEM_TLBSYNC = 0x0000000000000200ULL,
3fc6c082 388 /* eieio & sync */
0487d6a8 389 PPC_MEM_SYNC = 0x0000000000000400ULL,
3fc6c082 390 /* PowerPC 6xx TLB management instructions */
0487d6a8 391 PPC_6xx_TLB = 0x0000000000000800ULL,
3fc6c082 392 /* Altivec support */
0487d6a8 393 PPC_ALTIVEC = 0x0000000000001000ULL,
3fc6c082 394 /* Time base support */
0487d6a8 395 PPC_TB = 0x0000000000002000ULL,
3fc6c082 396 /* Embedded PowerPC dedicated instructions */
0487d6a8 397 PPC_EMB_COMMON = 0x0000000000004000ULL,
3fc6c082 398 /* PowerPC 40x exception model */
0487d6a8 399 PPC_40x_EXCP = 0x0000000000008000ULL,
3fc6c082 400 /* PowerPC 40x specific instructions */
0487d6a8 401 PPC_40x_SPEC = 0x0000000000010000ULL,
3fc6c082 402 /* PowerPC 405 Mac instructions */
0487d6a8 403 PPC_405_MAC = 0x0000000000020000ULL,
3fc6c082 404 /* PowerPC 440 specific instructions */
0487d6a8 405 PPC_440_SPEC = 0x0000000000040000ULL,
3fc6c082
FB		 406 /* Specific extensions */
407 /* Power-to-PowerPC bridge (601) */
0487d6a8 408 PPC_POWER_BR = 0x0000000000080000ULL,
3fc6c082 409 /* PowerPC 602 specific */
0487d6a8 410 PPC_602_SPEC = 0x0000000000100000ULL,
3fc6c082
FB		 411 /* Deprecated instructions */
412 /* Original POWER instruction set */
0487d6a8 413 PPC_POWER = 0x0000000000200000ULL,
3fc6c082 414 /* POWER2 instruction set extension */
0487d6a8 415 PPC_POWER2 = 0x0000000000400000ULL,
3fc6c082 416 /* Power RTC support */
0487d6a8 417 PPC_POWER_RTC = 0x0000000000800000ULL,
3fc6c082
FB		 418 /* 64 bits PowerPC instructions */
419 /* 64 bits PowerPC instruction set */
0487d6a8 420 PPC_64B = 0x0000000001000000ULL,
3fc6c082 421 /* 64 bits hypervisor extensions */
0487d6a8 422 PPC_64H = 0x0000000002000000ULL,
3fc6c082 423 /* 64 bits PowerPC "bridge" features */
0487d6a8 424 PPC_64_BRIDGE = 0x0000000004000000ULL,
76a66253 425 /* BookE (embedded) PowerPC specification */
0487d6a8 426 PPC_BOOKE = 0x0000000008000000ULL,
8b67546f 427 /* eieio */
0487d6a8 428 PPC_MEM_EIEIO = 0x0000000010000000ULL,
8b67546f 429 /* e500 vector instructions */
0487d6a8 430 PPC_E500_VECTOR = 0x0000000020000000ULL,
8b67546f 431 /* PowerPC 4xx dedicated instructions */
0487d6a8 432 PPC_4xx_COMMON = 0x0000000040000000ULL,
8b67546f 433 /* PowerPC 2.03 specification extensions */
0487d6a8 434 PPC_203 = 0x0000000080000000ULL,
8b67546f 435 /* PowerPC 2.03 SPE extension */
0487d6a8 436 PPC_SPE = 0x0000000100000000ULL,
8b67546f 437 /* PowerPC 2.03 SPE floating-point extension */
0487d6a8 438 PPC_SPEFPU = 0x0000000200000000ULL,
8b67546f 439 /* SLB management */
426613db 440 PPC_SLBI = 0x0000000400000000ULL,
2662a059
JM		 441 /* PowerPC 40x ibct instructions */
442 PPC_40x_ICBT = 0x0000000800000000ULL,
9a64fbe4 443};
79aceca5 444
3fc6c082
FB		 445/* CPU run-time flags (MMU and exception model) */
446enum {
2662a059 447 /* MMU model */
d0dfae6e 448 PPC_FLAGS_MMU_MASK = 0x000000FF,
2662a059 449 /* Standard 32 bits PowerPC MMU */
d0dfae6e 450 PPC_FLAGS_MMU_32B = 0x00000000,
2662a059 451 /* Standard 64 bits PowerPC MMU */
d0dfae6e 452 PPC_FLAGS_MMU_64B = 0x00000001,
2662a059 453 /* PowerPC 601 MMU */
d0dfae6e 454 PPC_FLAGS_MMU_601 = 0x00000002,
3fc6c082 455 /* PowerPC 6xx MMU with software TLB */
d0dfae6e 456 PPC_FLAGS_MMU_SOFT_6xx = 0x00000003,
3fc6c082 457 /* PowerPC 4xx MMU with software TLB */
d0dfae6e 458 PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,
2662a059 459 /* PowerPC 403 MMU */
d0dfae6e 460 PPC_FLAGS_MMU_403 = 0x00000005,
2662a059 461 /* BookE FSL MMU model */
d0dfae6e 462 PPC_FLAGS_MMU_BOOKE_FSL = 0x00000006,
2662a059 463 /* BookE MMU model */
d0dfae6e 464 PPC_FLAGS_MMU_BOOKE = 0x00000007,
2662a059 465 /* 64 bits "bridge" PowerPC MMU */
d0dfae6e 466 PPC_FLAGS_MMU_64BRIDGE = 0x00000008,
2662a059
JM		 467 /* PowerPC 401 MMU (real mode only) */
468 PPC_FLAGS_MMU_401 = 0x00000009,
469 /* Exception model */
d0dfae6e 470 PPC_FLAGS_EXCP_MASK = 0x0000FF00,
3fc6c082 471 /* Standard PowerPC exception model */
d0dfae6e 472 PPC_FLAGS_EXCP_STD = 0x00000000,
2662a059 473 /* PowerPC 40x exception model */
d0dfae6e 474 PPC_FLAGS_EXCP_40x = 0x00000100,
2662a059 475 /* PowerPC 601 exception model */
d0dfae6e 476 PPC_FLAGS_EXCP_601 = 0x00000200,
2662a059 477 /* PowerPC 602 exception model */
d0dfae6e 478 PPC_FLAGS_EXCP_602 = 0x00000300,
2662a059 479 /* PowerPC 603 exception model */
d0dfae6e 480 PPC_FLAGS_EXCP_603 = 0x00000400,
2662a059 481 /* PowerPC 604 exception model */
d0dfae6e 482 PPC_FLAGS_EXCP_604 = 0x00000500,
2662a059 483 /* PowerPC 7x0 exception model */
d0dfae6e 484 PPC_FLAGS_EXCP_7x0 = 0x00000600,
2662a059 485 /* PowerPC 7x5 exception model */
d0dfae6e 486 PPC_FLAGS_EXCP_7x5 = 0x00000700,
2662a059 487 /* PowerPC 74xx exception model */
d0dfae6e 488 PPC_FLAGS_EXCP_74xx = 0x00000800,
2662a059 489 /* PowerPC 970 exception model */
d0dfae6e 490 PPC_FLAGS_EXCP_970 = 0x00000900,
2662a059 491 /* BookE exception model */
d0dfae6e 492 PPC_FLAGS_EXCP_BOOKE = 0x00000A00,
2662a059 493 /* Input pins model */
d0dfae6e 494 PPC_FLAGS_INPUT_MASK = 0x000F0000,
2662a059 495 /* PowerPC 6xx bus */
d0dfae6e 496 PPC_FLAGS_INPUT_6xx = 0x00000000,
2662a059 497 /* BookE bus */
d0dfae6e 498 PPC_FLAGS_INPUT_BookE = 0x00010000,
2662a059 499 /* PowerPC 4xx bus */
d0dfae6e 500 PPC_FLAGS_INPUT_40x = 0x00020000,
2662a059 501 /* PowerPC 970 bus */
d0dfae6e 502 PPC_FLAGS_INPUT_970 = 0x00030000,
3fc6c082
FB		 503};
504
505#define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK)
506#define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK)
d0dfae6e 507#define PPC_INPUT(env) (env->flags & PPC_FLAGS_INPUT_MASK)
3fc6c082
FB		 508
509/*****************************************************************************/
510/* Supported instruction set definitions */
511/* This generates an empty opcode table... */
512#define PPC_INSNS_TODO (PPC_NONE)
513#define PPC_FLAGS_TODO (0x00000000)
514
515/* PowerPC 40x instruction set */
2662a059 516#define PPC_INSNS_EMB (PPC_INSNS_BASE | PPC_EMB_COMMON)
3fc6c082 517/* PowerPC 401 */
2662a059
JM		 518#define PPC_INSNS_401 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
519 PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
520#define PPC_FLAGS_401 (PPC_FLAGS_MMU_401 | PPC_FLAGS_EXCP_40x | \
521 PPC_FLAGS_INPUT_40x)
3fc6c082 522/* PowerPC 403 */
76a66253 523#define PPC_INSNS_403 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2662a059
JM		 524 PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | PPC_4xx_COMMON | \
525 PPC_40x_EXCP | PPC_40x_SPEC | PPC_40x_ICBT)
d0dfae6e
JM		 526#define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x | \
527 PPC_FLAGS_INPUT_40x)
3fc6c082 528/* PowerPC 405 */
76a66253 529#define PPC_INSNS_405 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
2662a059
JM		 530 PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
531 PPC_TB | PPC_4xx_COMMON | PPC_40x_SPEC | \
532 PPC_40x_ICBT | PPC_40x_EXCP | PPC_405_MAC)
d0dfae6e
JM		 533#define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \
534 PPC_FLAGS_INPUT_40x)
3fc6c082 535/* PowerPC 440 */
76a66253 536#define PPC_INSNS_440 (PPC_INSNS_EMB | PPC_CACHE_OPT | PPC_BOOKE | \
2662a059
JM		 537 PPC_MEM_TLBSYNC | PPC_4xx_COMMON | PPC_405_MAC | \
538 PPC_440_SPEC)
d0dfae6e
JM		 539#define PPC_FLAGS_440 (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \
540 PPC_FLAGS_INPUT_BookE)
76a66253 541/* Generic BookE PowerPC */
2662a059
JM		 542#define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_MEM_TLBSYNC | PPC_BOOKE | \
543 PPC_MEM_EIEIO | PPC_FLOAT | PPC_FLOAT_OPT | \
544 PPC_CACHE_OPT)
d0dfae6e
JM		 545#define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \
546 PPC_FLAGS_INPUT_BookE)
76a66253 547/* e500 core */
2662a059
JM		 548#define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_MEM_TLBSYNC | PPC_BOOKE | \
549 PPC_MEM_EIEIO | PPC_CACHE_OPT | PPC_E500_VECTOR)
d0dfae6e
JM		 550#define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \
551 PPC_FLAGS_INPUT_BookE)
3fc6c082
FB		 552/* Non-embedded PowerPC */
553#define PPC_INSNS_COMMON (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
d0dfae6e 554 PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
3fc6c082
FB		 555/* PowerPC 601 */
556#define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)
d0dfae6e
JM		 557#define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601 | \
558 PPC_FLAGS_INPUT_6xx)
3fc6c082
FB		 559/* PowerPC 602 */
560#define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
76a66253 561 PPC_MEM_TLBSYNC | PPC_TB | PPC_602_SPEC)
d0dfae6e
JM		 562#define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602 | \
563 PPC_FLAGS_INPUT_6xx)
3fc6c082
FB		 564/* PowerPC 603 */
565#define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
566 PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
d0dfae6e
JM		 567#define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603 | \
568 PPC_FLAGS_INPUT_6xx)
3fc6c082
FB		 569/* PowerPC G2 */
570#define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
571 PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
d0dfae6e
JM		 572#define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603 | \
573 PPC_FLAGS_INPUT_6xx)
3fc6c082
FB		 574/* PowerPC 604 */
575#define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
576 PPC_MEM_TLBSYNC | PPC_TB)
d0dfae6e
JM		 577#define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604 | \
578 PPC_FLAGS_INPUT_6xx)
3fc6c082
FB		 579/* PowerPC 740/750 (aka G3) */
580#define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
581 PPC_MEM_TLBSYNC | PPC_TB)
d0dfae6e
JM		 582#define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0 | \
583 PPC_FLAGS_INPUT_6xx)
3fc6c082
FB		 584/* PowerPC 745/755 */
585#define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
586 PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB)
d0dfae6e
JM		 587#define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5 | \
588 PPC_FLAGS_INPUT_6xx)
3fc6c082
FB		 589/* PowerPC 74xx (aka G4) */
590#define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC | \
591 PPC_MEM_TLBSYNC | PPC_TB)
d0dfae6e
JM		 592#define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx | \
593 PPC_FLAGS_INPUT_6xx)
426613db
JM		 594/* PowerPC 970 (aka G5) */
595#define PPC_INSNS_970 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_FLOAT_OPT | \
596 PPC_ALTIVEC | PPC_MEM_TLBSYNC | PPC_TB | \
597 PPC_64B | PPC_64_BRIDGE | PPC_SLBI)
d0dfae6e
JM		 598#define PPC_FLAGS_970 (PPC_FLAGS_MMU_64BRIDGE | PPC_FLAGS_EXCP_970 | \
599 PPC_FLAGS_INPUT_970)
3fc6c082
FB		 600
601/* Default PowerPC will be 604/970 */
602#define PPC_INSNS_PPC32 PPC_INSNS_604
603#define PPC_FLAGS_PPC32 PPC_FLAGS_604
3fc6c082
FB		 604#define PPC_INSNS_PPC64 PPC_INSNS_970
605#define PPC_FLAGS_PPC64 PPC_FLAGS_970
3fc6c082
FB		 606#define PPC_INSNS_DEFAULT PPC_INSNS_604
607#define PPC_FLAGS_DEFAULT PPC_FLAGS_604
608typedef struct ppc_def_t ppc_def_t;
79aceca5 609
3fc6c082
FB		 610/*****************************************************************************/
611/* Types used to describe some PowerPC registers */
612typedef struct CPUPPCState CPUPPCState;
613typedef struct opc_handler_t opc_handler_t;
9fddaa0c 614typedef struct ppc_tb_t ppc_tb_t;
3fc6c082
FB		 615typedef struct ppc_spr_t ppc_spr_t;
616typedef struct ppc_dcr_t ppc_dcr_t;
617typedef struct ppc_avr_t ppc_avr_t;
1d0a48fb 618typedef union ppc_tlb_t ppc_tlb_t;
76a66253 619
3fc6c082
FB		 620/* SPR access micro-ops generations callbacks */
621struct ppc_spr_t {
622 void (*uea_read)(void *opaque, int spr_num);
623 void (*uea_write)(void *opaque, int spr_num);
76a66253 624#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 625 void (*oea_read)(void *opaque, int spr_num);
626 void (*oea_write)(void *opaque, int spr_num);
76a66253 627#endif
3fc6c082
FB		 628 const unsigned char *name;
629};
630
631/* Altivec registers (128 bits) */
632struct ppc_avr_t {
633 uint32_t u[4];
634};
9fddaa0c 635
3fc6c082 636/* Software TLB cache */
1d0a48fb
JM		 637typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
638struct ppc6xx_tlb_t {
76a66253
JM		 639 target_ulong pte0;
640 target_ulong pte1;
641 target_ulong EPN;
1d0a48fb
JM		 642};
643
644typedef struct ppcemb_tlb_t ppcemb_tlb_t;
645struct ppcemb_tlb_t {
c55e9aef 646 target_phys_addr_t RPN;
1d0a48fb 647 target_ulong EPN;
76a66253 648 target_ulong PID;
c55e9aef
JM		 649 target_ulong size;
650 uint32_t prot;
651 uint32_t attr; /* Storage attributes */
1d0a48fb
JM		 652};
653
654union ppc_tlb_t {
655 ppc6xx_tlb_t tlb6;
656 ppcemb_tlb_t tlbe;
3fc6c082
FB		 657};
658
659/*****************************************************************************/
660/* Machine state register bits definition */
76a66253 661#define MSR_SF 63 /* Sixty-four-bit mode hflags */
3fc6c082 662#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
76a66253 663#define MSR_HV 60 /* hypervisor state hflags */
363be49c
JM		 664#define MSR_CM 31 /* Computation mode for BookE hflags */
665#define MSR_ICM 30 /* Interrupt computation mode for BookE */
666#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
76a66253 667#define MSR_VR 25 /* altivec available hflags */
363be49c 668#define MSR_SPE 25 /* SPE enable for BookE hflags */
76a66253
JM		 669#define MSR_AP 23 /* Access privilege state on 602 hflags */
670#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
3fc6c082
FB		 671#define MSR_KEY 19 /* key bit on 603e */
672#define MSR_POW 18 /* Power management */
673#define MSR_WE 18 /* Wait state enable on embedded PowerPC */
674#define MSR_TGPR 17 /* TGPR usage on 602/603 */
76a66253 675#define MSR_TLB 17 /* TLB update on ? */
3fc6c082
FB		 676#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC */
677#define MSR_ILE 16 /* Interrupt little-endian mode */
678#define MSR_EE 15 /* External interrupt enable */
76a66253
JM		 679#define MSR_PR 14 /* Problem state hflags */
680#define MSR_FP 13 /* Floating point available hflags */
3fc6c082 681#define MSR_ME 12 /* Machine check interrupt enable */
76a66253
JM		 682#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
683#define MSR_SE 10 /* Single-step trace enable hflags */
3fc6c082 684#define MSR_DWE 10 /* Debug wait enable on 405 */
76a66253
JM		 685#define MSR_UBLE 10 /* User BTB lock enable on e500 */
686#define MSR_BE 9 /* Branch trace enable hflags */
3fc6c082 687#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC */
76a66253 688#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
3fc6c082
FB		 689#define MSR_AL 7 /* AL bit on POWER */
690#define MSR_IP 6 /* Interrupt prefix */
691#define MSR_IR 5 /* Instruction relocate */
692#define MSR_IS 5 /* Instruction address space on embedded PowerPC */
693#define MSR_DR 4 /* Data relocate */
694#define MSR_DS 4 /* Data address space on embedded PowerPC */
695#define MSR_PE 3 /* Protection enable on 403 */
696#define MSR_EP 3 /* Exception prefix on 601 */
697#define MSR_PX 2 /* Protection exclusive on 403 */
698#define MSR_PMM 2 /* Performance monitor mark on POWER */
699#define MSR_RI 1 /* Recoverable interrupt */
76a66253 700#define MSR_LE 0 /* Little-endian mode hflags */
3fc6c082
FB		 701#define msr_sf env->msr[MSR_SF]
702#define msr_isf env->msr[MSR_ISF]
703#define msr_hv env->msr[MSR_HV]
363be49c
JM		 704#define msr_cm env->msr[MSR_CM]
705#define msr_icm env->msr[MSR_ICM]
76a66253 706#define msr_ucle env->msr[MSR_UCLE]
3fc6c082 707#define msr_vr env->msr[MSR_VR]
76a66253 708#define msr_spe env->msr[MSR_SPE]
3fc6c082
FB		 709#define msr_ap env->msr[MSR_AP]
710#define msr_sa env->msr[MSR_SA]
711#define msr_key env->msr[MSR_KEY]
76a66253 712#define msr_pow env->msr[MSR_POW]
3fc6c082
FB		 713#define msr_we env->msr[MSR_WE]
714#define msr_tgpr env->msr[MSR_TGPR]
715#define msr_tlb env->msr[MSR_TLB]
716#define msr_ce env->msr[MSR_CE]
76a66253
JM		 717#define msr_ile env->msr[MSR_ILE]
718#define msr_ee env->msr[MSR_EE]
719#define msr_pr env->msr[MSR_PR]
720#define msr_fp env->msr[MSR_FP]
721#define msr_me env->msr[MSR_ME]
722#define msr_fe0 env->msr[MSR_FE0]
723#define msr_se env->msr[MSR_SE]
3fc6c082 724#define msr_dwe env->msr[MSR_DWE]
76a66253
JM		 725#define msr_uble env->msr[MSR_UBLE]
726#define msr_be env->msr[MSR_BE]
3fc6c082 727#define msr_de env->msr[MSR_DE]
76a66253 728#define msr_fe1 env->msr[MSR_FE1]
3fc6c082 729#define msr_al env->msr[MSR_AL]
76a66253
JM		 730#define msr_ip env->msr[MSR_IP]
731#define msr_ir env->msr[MSR_IR]
3fc6c082 732#define msr_is env->msr[MSR_IS]
76a66253 733#define msr_dr env->msr[MSR_DR]
3fc6c082
FB		 734#define msr_ds env->msr[MSR_DS]
735#define msr_pe env->msr[MSR_PE]
736#define msr_ep env->msr[MSR_EP]
737#define msr_px env->msr[MSR_PX]
738#define msr_pmm env->msr[MSR_PMM]
76a66253
JM		 739#define msr_ri env->msr[MSR_RI]
740#define msr_le env->msr[MSR_LE]
79aceca5 741
3fc6c082
FB		 742/*****************************************************************************/
743/* The whole PowerPC CPU context */
744struct CPUPPCState {
745 /* First are the most commonly used resources
746 * during translated code execution
747 */
0487d6a8 748#if TARGET_GPR_BITS > HOST_LONG_BITS
3fc6c082
FB		 749 /* temporary fixed-point registers
750 * used to emulate 64 bits target on 32 bits hosts
5fafdf24 751 */
3c4c9f9f 752 ppc_gpr_t t0, t1, t2;
3fc6c082 753#endif
d9bce9d9
JM		 754 ppc_avr_t t0_avr, t1_avr, t2_avr;
755
79aceca5 756 /* general purpose registers */
76a66253 757 ppc_gpr_t gpr[32];
3fc6c082
FB		 758 /* LR */
759 target_ulong lr;
760 /* CTR */
761 target_ulong ctr;
762 /* condition register */
763 uint8_t crf[8];
79aceca5 764 /* XER */
3fc6c082
FB		 765 /* XXX: We use only 5 fields, but we want to keep the structure aligned */
766 uint8_t xer[8];
79aceca5 767 /* Reservation address */
3fc6c082
FB		 768 target_ulong reserve;
769
770 /* Those ones are used in supervisor mode only */
79aceca5 771 /* machine state register */
3fc6c082
FB		 772 uint8_t msr[64];
773 /* temporary general purpose registers */
76a66253 774 ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
3fc6c082
FB		 775
776 /* Floating point execution context */
76a66253 777 /* temporary float registers */
4ecc3190
FB		 778 float64 ft0;
779 float64 ft1;
780 float64 ft2;
781 float_status fp_status;
3fc6c082
FB		 782 /* floating point registers */
783 float64 fpr[32];
784 /* floating point status and control register */
785 uint8_t fpscr[8];
4ecc3190 786
a316d335
FB		 787 CPU_COMMON
788
50443c98
FB		 789 int halted; /* TRUE if the CPU is in suspend state */
790
ac9eb073
FB		 791 int access_type; /* when a memory exception occurs, the access
792 type is stored here */
a541f297 793
3fc6c082
FB		 794 /* MMU context */
795 /* Address space register */
796 target_ulong asr;
797 /* segment registers */
798 target_ulong sdr1;
799 target_ulong sr[16];
800 /* BATs */
801 int nb_BATs;
802 target_ulong DBAT[2][8];
803 target_ulong IBAT[2][8];
9fddaa0c 804
3fc6c082
FB		 805 /* Other registers */
806 /* Special purpose registers */
807 target_ulong spr[1024];
808 /* Altivec registers */
809 ppc_avr_t avr[32];
810 uint32_t vscr;
d9bce9d9
JM		 811 /* SPE registers */
812 ppc_gpr_t spe_acc;
0487d6a8 813 float_status spe_status;
d9bce9d9 814 uint32_t spe_fscr;
3fc6c082
FB		 815
816 /* Internal devices resources */
9fddaa0c
FB		 817 /* Time base and decrementer */
818 ppc_tb_t *tb_env;
3fc6c082 819 /* Device control registers */
3fc6c082
FB		 820 ppc_dcr_t *dcr_env;
821
822 /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
76a66253
JM		 823 int nb_tlb; /* Total number of TLB */
824 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
825 int nb_ways; /* Number of ways in the TLB set */
826 int last_way; /* Last used way used to allocate TLB in a LRU way */
827 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
363be49c 828 int nb_pids; /* Number of available PID registers */
76a66253 829 ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
3fc6c082
FB		 830 /* 403 dedicated access protection registers */
831 target_ulong pb[4];
832
833 /* Those resources are used during exception processing */
834 /* CPU model definition */
835 uint64_t msr_mask;
836 uint32_t flags;
837
838 int exception_index;
839 int error_code;
840 int interrupt_request;
47103572 841 uint32_t pending_interrupts;
e9df014c
JM		 842#if !defined(CONFIG_USER_ONLY)
843 /* This is the IRQ controller, which is implementation dependant
844 * and only relevant when emulating a complete machine.
845 */
846 uint32_t irq_input_state;
847 void **irq_inputs;
848#endif
3fc6c082
FB		 849
850 /* Those resources are used only during code translation */
851 /* Next instruction pointer */
852 target_ulong nip;
853 /* SPR translation callbacks */
854 ppc_spr_t spr_cb[1024];
855 /* opcode handlers */
856 opc_handler_t *opcodes[0x40];
857
858 /* Those resources are used only in Qemu core */
859 jmp_buf jmp_env;
860 int user_mode_only; /* user mode only simulation */
4296f459 861 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
3fc6c082 862
9fddaa0c
FB		 863 /* Power management */
864 int power_mode;
a541f297 865
6d506e6d
FB		 866 /* temporary hack to handle OSI calls (only used if non NULL) */
867 int (*osi_call)(struct CPUPPCState *env);
3fc6c082 868};
79aceca5 869
76a66253
JM		 870/* Context used internally during MMU translations */
871typedef struct mmu_ctx_t mmu_ctx_t;
872struct mmu_ctx_t {
873 target_phys_addr_t raddr; /* Real address */
874 int prot; /* Protection bits */
875 target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
876 target_ulong ptem; /* Virtual segment ID | API */
877 int key; /* Access key */
878};
879
3fc6c082 880/*****************************************************************************/
36081602
JM		 881CPUPPCState *cpu_ppc_init (void);
882int cpu_ppc_exec (CPUPPCState *s);
883void cpu_ppc_close (CPUPPCState *s);
79aceca5
FB		 884/* you can call this signal handler from your SIGBUS and SIGSEGV
885 signal handlers to inform the virtual CPU of exceptions. non zero
886 is returned if the signal was handled by the virtual CPU. */
36081602
JM		 887int cpu_ppc_signal_handler (int host_signum, void *pinfo,
888 void *puc);
79aceca5 889
a541f297 890void do_interrupt (CPUPPCState *env);
e9df014c 891void ppc_hw_interrupt (CPUPPCState *env);
36081602 892void cpu_loop_exit (void);
a541f297 893
9a64fbe4 894void dump_stack (CPUPPCState *env);
a541f297 895
76a66253 896#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 897target_ulong do_load_ibatu (CPUPPCState *env, int nr);
898target_ulong do_load_ibatl (CPUPPCState *env, int nr);
899void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
900void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
901target_ulong do_load_dbatu (CPUPPCState *env, int nr);
902target_ulong do_load_dbatl (CPUPPCState *env, int nr);
903void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
904void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
3fc6c082
FB		 905target_ulong do_load_sdr1 (CPUPPCState *env);
906void do_store_sdr1 (CPUPPCState *env, target_ulong value);
d9bce9d9
JM		 907#if defined(TARGET_PPC64)
908target_ulong ppc_load_asr (CPUPPCState *env);
909void ppc_store_asr (CPUPPCState *env, target_ulong value);
910#endif
3fc6c082
FB		 911target_ulong do_load_sr (CPUPPCState *env, int srnum);
912void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
76a66253
JM		 913#endif
914uint32_t ppc_load_xer (CPUPPCState *env);
915void ppc_store_xer (CPUPPCState *env, uint32_t value);
3fc6c082
FB		 916target_ulong do_load_msr (CPUPPCState *env);
917void do_store_msr (CPUPPCState *env, target_ulong value);
426613db 918void ppc_store_msr_32 (CPUPPCState *env, uint32_t value);
3fc6c082
FB		 919
920void do_compute_hflags (CPUPPCState *env);
0a032cbe
JM		 921void cpu_ppc_reset (void *opaque);
922CPUPPCState *cpu_ppc_init (void);
923void cpu_ppc_close(CPUPPCState *env);
a541f297 924
3fc6c082
FB		 925int ppc_find_by_name (const unsigned char *name, ppc_def_t **def);
926int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
927void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
928int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);
85c4adf6 929
9fddaa0c
FB		 930/* Time-base and decrementer management */
931#ifndef NO_CPU_IO_DEFS
932uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
933uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
934void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
935void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
936uint32_t cpu_ppc_load_decr (CPUPPCState *env);
937void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
d9bce9d9
JM		 938uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
939uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
940#if !defined(CONFIG_USER_ONLY)
941void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
942void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
943target_ulong load_40x_pit (CPUPPCState *env);
944void store_40x_pit (CPUPPCState *env, target_ulong val);
8ecc7913 945void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
c294fc58 946void store_40x_sler (CPUPPCState *env, uint32_t val);
d9bce9d9
JM		 947void store_booke_tcr (CPUPPCState *env, target_ulong val);
948void store_booke_tsr (CPUPPCState *env, target_ulong val);
0a032cbe 949void ppc_tlb_invalidate_all (CPUPPCState *env);
36081602 950int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
d9bce9d9 951#endif
9fddaa0c 952#endif
79aceca5 953
2e719ba3
JM		 954/* Device control registers */
955int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
956int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
957
9467d44c
TS		 958#define CPUState CPUPPCState
959#define cpu_init cpu_ppc_init
960#define cpu_exec cpu_ppc_exec
961#define cpu_gen_code cpu_ppc_gen_code
962#define cpu_signal_handler cpu_ppc_signal_handler
963
79aceca5
FB		 964#include "cpu-all.h"
965
3fc6c082
FB		 966/*****************************************************************************/
967/* Registers definitions */
79aceca5
FB		 968#define XER_SO 31
969#define XER_OV 30
970#define XER_CA 29
3fc6c082 971#define XER_CMP 8
36081602 972#define XER_BC 0
3fc6c082
FB		 973#define xer_so env->xer[4]
974#define xer_ov env->xer[6]
975#define xer_ca env->xer[2]
976#define xer_cmp env->xer[1]
36081602 977#define xer_bc env->xer[0]
79aceca5 978
3fc6c082 979/* SPR definitions */
76a66253
JM		 980#define SPR_MQ (0x000)
981#define SPR_XER (0x001)
982#define SPR_601_VRTCU (0x004)
983#define SPR_601_VRTCL (0x005)
984#define SPR_601_UDECR (0x006)
985#define SPR_LR (0x008)
986#define SPR_CTR (0x009)
987#define SPR_DSISR (0x012)
988#define SPR_DAR (0x013)
989#define SPR_601_RTCU (0x014)
990#define SPR_601_RTCL (0x015)
991#define SPR_DECR (0x016)
992#define SPR_SDR1 (0x019)
993#define SPR_SRR0 (0x01A)
994#define SPR_SRR1 (0x01B)
2662a059 995#define SPR_AMR (0x01D)
76a66253
JM		 996#define SPR_BOOKE_PID (0x030)
997#define SPR_BOOKE_DECAR (0x036)
363be49c
JM		 998#define SPR_BOOKE_CSRR0 (0x03A)
999#define SPR_BOOKE_CSRR1 (0x03B)
76a66253
JM		 1000#define SPR_BOOKE_DEAR (0x03D)
1001#define SPR_BOOKE_ESR (0x03E)
363be49c 1002#define SPR_BOOKE_IVPR (0x03F)
76a66253
JM		 1003#define SPR_8xx_EIE (0x050)
1004#define SPR_8xx_EID (0x051)
1005#define SPR_8xx_NRE (0x052)
2662a059 1006#define SPR_CTRL (0x088)
76a66253
JM		 1007#define SPR_58x_CMPA (0x090)
1008#define SPR_58x_CMPB (0x091)
1009#define SPR_58x_CMPC (0x092)
1010#define SPR_58x_CMPD (0x093)
1011#define SPR_58x_ICR (0x094)
1012#define SPR_58x_DER (0x094)
1013#define SPR_58x_COUNTA (0x096)
1014#define SPR_58x_COUNTB (0x097)
2662a059 1015#define SPR_UCTRL (0x098)
76a66253
JM		 1016#define SPR_58x_CMPE (0x098)
1017#define SPR_58x_CMPF (0x099)
1018#define SPR_58x_CMPG (0x09A)
1019#define SPR_58x_CMPH (0x09B)
1020#define SPR_58x_LCTRL1 (0x09C)
1021#define SPR_58x_LCTRL2 (0x09D)
1022#define SPR_58x_ICTRL (0x09E)
1023#define SPR_58x_BAR (0x09F)
1024#define SPR_VRSAVE (0x100)
1025#define SPR_USPRG0 (0x100)
363be49c
JM		 1026#define SPR_USPRG1 (0x101)
1027#define SPR_USPRG2 (0x102)
1028#define SPR_USPRG3 (0x103)
76a66253
JM		 1029#define SPR_USPRG4 (0x104)
1030#define SPR_USPRG5 (0x105)
1031#define SPR_USPRG6 (0x106)
1032#define SPR_USPRG7 (0x107)
1033#define SPR_VTBL (0x10C)
1034#define SPR_VTBU (0x10D)
1035#define SPR_SPRG0 (0x110)
1036#define SPR_SPRG1 (0x111)
1037#define SPR_SPRG2 (0x112)
1038#define SPR_SPRG3 (0x113)
1039#define SPR_SPRG4 (0x114)
1040#define SPR_SCOMC (0x114)
1041#define SPR_SPRG5 (0x115)
1042#define SPR_SCOMD (0x115)
1043#define SPR_SPRG6 (0x116)
1044#define SPR_SPRG7 (0x117)
1045#define SPR_ASR (0x118)
1046#define SPR_EAR (0x11A)
1047#define SPR_TBL (0x11C)
1048#define SPR_TBU (0x11D)
2662a059 1049#define SPR_TBU40 (0x11E)
76a66253
JM		 1050#define SPR_SVR (0x11E)
1051#define SPR_BOOKE_PIR (0x11E)
1052#define SPR_PVR (0x11F)
1053#define SPR_HSPRG0 (0x130)
1054#define SPR_BOOKE_DBSR (0x130)
1055#define SPR_HSPRG1 (0x131)
2662a059
JM		 1056#define SPR_HDSISR (0x132)
1057#define SPR_HDAR (0x133)
76a66253
JM		 1058#define SPR_BOOKE_DBCR0 (0x134)
1059#define SPR_IBCR (0x135)
2662a059 1060#define SPR_PURR (0x135)
76a66253
JM		 1061#define SPR_BOOKE_DBCR1 (0x135)
1062#define SPR_DBCR (0x136)
1063#define SPR_HDEC (0x136)
1064#define SPR_BOOKE_DBCR2 (0x136)
1065#define SPR_HIOR (0x137)
1066#define SPR_MBAR (0x137)
1067#define SPR_RMOR (0x138)
1068#define SPR_BOOKE_IAC1 (0x138)
1069#define SPR_HRMOR (0x139)
1070#define SPR_BOOKE_IAC2 (0x139)
1071#define SPR_HSSR0 (0x13A)
1072#define SPR_BOOKE_IAC3 (0x13A)
1073#define SPR_HSSR1 (0x13B)
1074#define SPR_BOOKE_IAC4 (0x13B)
1075#define SPR_LPCR (0x13C)
1076#define SPR_BOOKE_DAC1 (0x13C)
1077#define SPR_LPIDR (0x13D)
1078#define SPR_DABR2 (0x13D)
1079#define SPR_BOOKE_DAC2 (0x13D)
1080#define SPR_BOOKE_DVC1 (0x13E)
1081#define SPR_BOOKE_DVC2 (0x13F)
1082#define SPR_BOOKE_TSR (0x150)
1083#define SPR_BOOKE_TCR (0x154)
1084#define SPR_BOOKE_IVOR0 (0x190)
1085#define SPR_BOOKE_IVOR1 (0x191)
1086#define SPR_BOOKE_IVOR2 (0x192)
1087#define SPR_BOOKE_IVOR3 (0x193)
1088#define SPR_BOOKE_IVOR4 (0x194)
1089#define SPR_BOOKE_IVOR5 (0x195)
1090#define SPR_BOOKE_IVOR6 (0x196)
1091#define SPR_BOOKE_IVOR7 (0x197)
1092#define SPR_BOOKE_IVOR8 (0x198)
1093#define SPR_BOOKE_IVOR9 (0x199)
1094#define SPR_BOOKE_IVOR10 (0x19A)
1095#define SPR_BOOKE_IVOR11 (0x19B)
1096#define SPR_BOOKE_IVOR12 (0x19C)
1097#define SPR_BOOKE_IVOR13 (0x19D)
1098#define SPR_BOOKE_IVOR14 (0x19E)
1099#define SPR_BOOKE_IVOR15 (0x19F)
2662a059 1100#define SPR_BOOKE_SPEFSCR (0x200)
76a66253
JM		 1101#define SPR_E500_BBEAR (0x201)
1102#define SPR_E500_BBTAR (0x202)
1103#define SPR_BOOKE_ATBL (0x20E)
1104#define SPR_BOOKE_ATBU (0x20F)
1105#define SPR_IBAT0U (0x210)
363be49c 1106#define SPR_BOOKE_IVOR32 (0x210)
76a66253 1107#define SPR_IBAT0L (0x211)
363be49c 1108#define SPR_BOOKE_IVOR33 (0x211)
76a66253 1109#define SPR_IBAT1U (0x212)
363be49c 1110#define SPR_BOOKE_IVOR34 (0x212)
76a66253 1111#define SPR_IBAT1L (0x213)
363be49c 1112#define SPR_BOOKE_IVOR35 (0x213)
76a66253 1113#define SPR_IBAT2U (0x214)
363be49c 1114#define SPR_BOOKE_IVOR36 (0x214)
76a66253
JM		 1115#define SPR_IBAT2L (0x215)
1116#define SPR_E500_L1CFG0 (0x215)
363be49c 1117#define SPR_BOOKE_IVOR37 (0x215)
76a66253
JM		 1118#define SPR_IBAT3U (0x216)
1119#define SPR_E500_L1CFG1 (0x216)
1120#define SPR_IBAT3L (0x217)
1121#define SPR_DBAT0U (0x218)
1122#define SPR_DBAT0L (0x219)
1123#define SPR_DBAT1U (0x21A)
1124#define SPR_DBAT1L (0x21B)
1125#define SPR_DBAT2U (0x21C)
1126#define SPR_DBAT2L (0x21D)
1127#define SPR_DBAT3U (0x21E)
1128#define SPR_DBAT3L (0x21F)
1129#define SPR_IBAT4U (0x230)
1130#define SPR_IBAT4L (0x231)
1131#define SPR_IBAT5U (0x232)
1132#define SPR_IBAT5L (0x233)
1133#define SPR_IBAT6U (0x234)
1134#define SPR_IBAT6L (0x235)
1135#define SPR_IBAT7U (0x236)
1136#define SPR_IBAT7L (0x237)
1137#define SPR_DBAT4U (0x238)
1138#define SPR_DBAT4L (0x239)
1139#define SPR_DBAT5U (0x23A)
363be49c 1140#define SPR_BOOKE_MCSRR0 (0x23A)
76a66253 1141#define SPR_DBAT5L (0x23B)
363be49c 1142#define SPR_BOOKE_MCSRR1 (0x23B)
76a66253 1143#define SPR_DBAT6U (0x23C)
363be49c 1144#define SPR_BOOKE_MCSR (0x23C)
76a66253
JM		 1145#define SPR_DBAT6L (0x23D)
1146#define SPR_E500_MCAR (0x23D)
1147#define SPR_DBAT7U (0x23E)
363be49c 1148#define SPR_BOOKE_DSRR0 (0x23E)
76a66253 1149#define SPR_DBAT7L (0x23F)
363be49c
JM		 1150#define SPR_BOOKE_DSRR1 (0x23F)
1151#define SPR_BOOKE_SPRG8 (0x25C)
1152#define SPR_BOOKE_SPRG9 (0x25D)
1153#define SPR_BOOKE_MAS0 (0x270)
1154#define SPR_BOOKE_MAS1 (0x271)
1155#define SPR_BOOKE_MAS2 (0x272)
1156#define SPR_BOOKE_MAS3 (0x273)
1157#define SPR_BOOKE_MAS4 (0x274)
1158#define SPR_BOOKE_MAS6 (0x276)
1159#define SPR_BOOKE_PID1 (0x279)
1160#define SPR_BOOKE_PID2 (0x27A)
1161#define SPR_BOOKE_TLB0CFG (0x2B0)
1162#define SPR_BOOKE_TLB1CFG (0x2B1)
1163#define SPR_BOOKE_TLB2CFG (0x2B2)
1164#define SPR_BOOKE_TLB3CFG (0x2B3)
1165#define SPR_BOOKE_EPR (0x2BE)
2662a059
JM		 1166#define SPR_PERF0 (0x300)
1167#define SPR_PERF1 (0x301)
1168#define SPR_PERF2 (0x302)
1169#define SPR_PERF3 (0x303)
1170#define SPR_PERF4 (0x304)
1171#define SPR_PERF5 (0x305)
1172#define SPR_PERF6 (0x306)
1173#define SPR_PERF7 (0x307)
1174#define SPR_PERF8 (0x308)
1175#define SPR_PERF9 (0x309)
1176#define SPR_PERFA (0x30A)
1177#define SPR_PERFB (0x30B)
1178#define SPR_PERFC (0x30C)
1179#define SPR_PERFD (0x30D)
1180#define SPR_PERFE (0x30E)
1181#define SPR_PERFF (0x30F)
1182#define SPR_UPERF0 (0x310)
1183#define SPR_UPERF1 (0x311)
1184#define SPR_UPERF2 (0x312)
1185#define SPR_UPERF3 (0x313)
1186#define SPR_UPERF4 (0x314)
1187#define SPR_UPERF5 (0x315)
1188#define SPR_UPERF6 (0x316)
1189#define SPR_UPERF7 (0x317)
1190#define SPR_UPERF8 (0x318)
1191#define SPR_UPERF9 (0x319)
1192#define SPR_UPERFA (0x31A)
1193#define SPR_UPERFB (0x31B)
1194#define SPR_UPERFC (0x31C)
1195#define SPR_UPERFD (0x31D)
1196#define SPR_UPERFE (0x31E)
1197#define SPR_UPERFF (0x31F)
76a66253
JM		 1198#define SPR_440_INV0 (0x370)
1199#define SPR_440_INV1 (0x371)
1200#define SPR_440_INV2 (0x372)
1201#define SPR_440_INV3 (0x373)
2662a059
JM		 1202#define SPR_440_ITV0 (0x374)
1203#define SPR_440_ITV1 (0x375)
1204#define SPR_440_ITV2 (0x376)
1205#define SPR_440_ITV3 (0x377)
1206#define SPR_PPR (0x380)
76a66253
JM		 1207#define SPR_440_DNV0 (0x390)
1208#define SPR_440_DNV1 (0x391)
1209#define SPR_440_DNV2 (0x392)
1210#define SPR_440_DNV3 (0x393)
2662a059
JM		 1211#define SPR_440_DTV0 (0x394)
1212#define SPR_440_DTV1 (0x395)
1213#define SPR_440_DTV2 (0x396)
1214#define SPR_440_DTV3 (0x397)
76a66253
JM		 1215#define SPR_440_DVLIM (0x398)
1216#define SPR_440_IVLIM (0x399)
1217#define SPR_440_RSTCFG (0x39B)
2662a059
JM		 1218#define SPR_BOOKE_DCDBTRL (0x39C)
1219#define SPR_BOOKE_DCDBTRH (0x39D)
1220#define SPR_BOOKE_ICDBTRL (0x39E)
1221#define SPR_BOOKE_ICDBTRH (0x39F)
76a66253
JM		 1222#define SPR_UMMCR0 (0x3A8)
1223#define SPR_UPMC1 (0x3A9)
1224#define SPR_UPMC2 (0x3AA)
1225#define SPR_USIA (0x3AB)
1226#define SPR_UMMCR1 (0x3AC)
1227#define SPR_UPMC3 (0x3AD)
1228#define SPR_UPMC4 (0x3AE)
1229#define SPR_USDA (0x3AF)
1230#define SPR_40x_ZPR (0x3B0)
363be49c 1231#define SPR_BOOKE_MAS7 (0x3B0)
76a66253
JM		 1232#define SPR_40x_PID (0x3B1)
1233#define SPR_440_MMUCR (0x3B2)
1234#define SPR_4xx_CCR0 (0x3B3)
363be49c 1235#define SPR_BOOKE_EPLC (0x3B3)
76a66253 1236#define SPR_405_IAC3 (0x3B4)
363be49c 1237#define SPR_BOOKE_EPSC (0x3B4)
76a66253
JM		 1238#define SPR_405_IAC4 (0x3B5)
1239#define SPR_405_DVC1 (0x3B6)
1240#define SPR_405_DVC2 (0x3B7)
1241#define SPR_MMCR0 (0x3B8)
1242#define SPR_PMC1 (0x3B9)
1243#define SPR_40x_SGR (0x3B9)
1244#define SPR_PMC2 (0x3BA)
1245#define SPR_40x_DCWR (0x3BA)
1246#define SPR_SIA (0x3BB)
1247#define SPR_405_SLER (0x3BB)
1248#define SPR_MMCR1 (0x3BC)
1249#define SPR_405_SU0R (0x3BC)
1250#define SPR_PMC3 (0x3BD)
1251#define SPR_405_DBCR1 (0x3BD)
1252#define SPR_PMC4 (0x3BE)
1253#define SPR_SDA (0x3BF)
1254#define SPR_403_VTBL (0x3CC)
1255#define SPR_403_VTBU (0x3CD)
1256#define SPR_DMISS (0x3D0)
1257#define SPR_DCMP (0x3D1)
1258#define SPR_HASH1 (0x3D2)
1259#define SPR_HASH2 (0x3D3)
2662a059 1260#define SPR_BOOKE_ICDBDR (0x3D3)
76a66253
JM		 1261#define SPR_IMISS (0x3D4)
1262#define SPR_40x_ESR (0x3D4)
1263#define SPR_ICMP (0x3D5)
1264#define SPR_40x_DEAR (0x3D5)
1265#define SPR_RPA (0x3D6)
1266#define SPR_40x_EVPR (0x3D6)
1267#define SPR_403_CDBCR (0x3D7)
1268#define SPR_TCR (0x3D8)
1269#define SPR_40x_TSR (0x3D8)
1270#define SPR_IBR (0x3DA)
1271#define SPR_40x_TCR (0x3DA)
1272#define SPR_ESASR (0x3DB)
1273#define SPR_40x_PIT (0x3DB)
1274#define SPR_403_TBL (0x3DC)
1275#define SPR_403_TBU (0x3DD)
1276#define SPR_SEBR (0x3DE)
1277#define SPR_40x_SRR2 (0x3DE)
1278#define SPR_SER (0x3DF)
1279#define SPR_40x_SRR3 (0x3DF)
1280#define SPR_HID0 (0x3F0)
1281#define SPR_40x_DBSR (0x3F0)
1282#define SPR_HID1 (0x3F1)
1283#define SPR_IABR (0x3F2)
1284#define SPR_40x_DBCR0 (0x3F2)
1285#define SPR_601_HID2 (0x3F2)
1286#define SPR_E500_L1CSR0 (0x3F2)
1287#define SPR_HID2 (0x3F3)
1288#define SPR_E500_L1CSR1 (0x3F3)
1289#define SPR_440_DBDR (0x3F3)
1290#define SPR_40x_IAC1 (0x3F4)
363be49c 1291#define SPR_BOOKE_MMUCSR0 (0x3F4)
76a66253 1292#define SPR_DABR (0x3F5)
3fc6c082 1293#define DABR_MASK (~(target_ulong)0x7)
76a66253
JM		 1294#define SPR_E500_BUCSR (0x3F5)
1295#define SPR_40x_IAC2 (0x3F5)
1296#define SPR_601_HID5 (0x3F5)
1297#define SPR_40x_DAC1 (0x3F6)
2662a059 1298#define SPR_DABRX (0x3F7)
76a66253 1299#define SPR_40x_DAC2 (0x3F7)
363be49c 1300#define SPR_BOOKE_MMUCFG (0x3F7)
76a66253
JM		 1301#define SPR_L2PM (0x3F8)
1302#define SPR_750_HID2 (0x3F8)
1303#define SPR_L2CR (0x3F9)
1304#define SPR_IABR2 (0x3FA)
1305#define SPR_40x_DCCR (0x3FA)
1306#define SPR_ICTC (0x3FB)
1307#define SPR_40x_ICCR (0x3FB)
1308#define SPR_THRM1 (0x3FC)
1309#define SPR_403_PBL1 (0x3FC)
1310#define SPR_SP (0x3FD)
1311#define SPR_THRM2 (0x3FD)
1312#define SPR_403_PBU1 (0x3FD)
1313#define SPR_LT (0x3FE)
1314#define SPR_THRM3 (0x3FE)
1315#define SPR_FPECR (0x3FE)
1316#define SPR_403_PBL2 (0x3FE)
1317#define SPR_PIR (0x3FF)
1318#define SPR_403_PBU2 (0x3FF)
1319#define SPR_601_HID15 (0x3FF)
1320#define SPR_E500_SVR (0x3FF)
79aceca5 1321
76a66253 1322/*****************************************************************************/
9a64fbe4
FB		 1323/* Memory access type :
1324 * may be needed for precise access rights control and precise exceptions.
1325 */
79aceca5 1326enum {
9a64fbe4
FB		 1327 /* 1 bit to define user level / supervisor access */
1328 ACCESS_USER = 0x00,
1329 ACCESS_SUPER = 0x01,
1330 /* Type of instruction that generated the access */
1331 ACCESS_CODE = 0x10, /* Code fetch access */
1332 ACCESS_INT = 0x20, /* Integer load/store access */
1333 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1334 ACCESS_RES = 0x40, /* load/store with reservation */
1335 ACCESS_EXT = 0x50, /* external access */
1336 ACCESS_CACHE = 0x60, /* Cache manipulation */
1337};
1338
1339/*****************************************************************************/
1340/* Exceptions */
2be0071f
FB		 1341#define EXCP_NONE -1
1342/* PowerPC hardware exceptions : exception vectors defined in PowerPC book 3 */
1343#define EXCP_RESET 0x0100 /* System reset */
1344#define EXCP_MACHINE_CHECK 0x0200 /* Machine check exception */
1345#define EXCP_DSI 0x0300 /* Data storage exception */
1346#define EXCP_DSEG 0x0380 /* Data segment exception */
1347#define EXCP_ISI 0x0400 /* Instruction storage exception */
1348#define EXCP_ISEG 0x0480 /* Instruction segment exception */
1349#define EXCP_EXTERNAL 0x0500 /* External interruption */
1350#define EXCP_ALIGN 0x0600 /* Alignment exception */
1351#define EXCP_PROGRAM 0x0700 /* Program exception */
1352#define EXCP_NO_FP 0x0800 /* Floating point unavailable exception */
1353#define EXCP_DECR 0x0900 /* Decrementer exception */
1354#define EXCP_HDECR 0x0980 /* Hypervisor decrementer exception */
1355#define EXCP_SYSCALL 0x0C00 /* System call */
1356#define EXCP_TRACE 0x0D00 /* Trace exception */
1357#define EXCP_PERF 0x0F00 /* Performance monitor exception */
1358/* Exceptions defined in PowerPC 32 bits programming environment manual */
1359#define EXCP_FP_ASSIST 0x0E00 /* Floating-point assist */
1360/* Implementation specific exceptions */
1361/* 40x exceptions */
1362#define EXCP_40x_PIT 0x1000 /* Programmable interval timer interrupt */
1363#define EXCP_40x_FIT 0x1010 /* Fixed interval timer interrupt */
1364#define EXCP_40x_WATCHDOG 0x1020 /* Watchdog timer exception */
1365#define EXCP_40x_DTLBMISS 0x1100 /* Data TLB miss exception */
1366#define EXCP_40x_ITLBMISS 0x1200 /* Instruction TLB miss exception */
1367#define EXCP_40x_DEBUG 0x2000 /* Debug exception */
1368/* 405 specific exceptions */
1369#define EXCP_405_APU 0x0F20 /* APU unavailable exception */
1370/* TLB assist exceptions (602/603) */
1371#define EXCP_I_TLBMISS 0x1000 /* Instruction TLB miss */
1372#define EXCP_DL_TLBMISS 0x1100 /* Data load TLB miss */
1373#define EXCP_DS_TLBMISS 0x1200 /* Data store TLB miss */
1374/* Breakpoint exceptions (602/603/604/620/740/745/750/755...) */
1375#define EXCP_IABR 0x1300 /* Instruction address breakpoint */
1376#define EXCP_SMI 0x1400 /* System management interrupt */
1377/* Altivec related exceptions */
1378#define EXCP_VPU 0x0F20 /* VPU unavailable exception */
1379/* 601 specific exceptions */
1380#define EXCP_601_IO 0x0600 /* IO error exception */
1381#define EXCP_601_RUNM 0x2000 /* Run mode exception */
1382/* 602 specific exceptions */
1383#define EXCP_602_WATCHDOG 0x1500 /* Watchdog exception */
1384#define EXCP_602_EMUL 0x1600 /* Emulation trap exception */
1385/* G2 specific exceptions */
1386#define EXCP_G2_CRIT 0x0A00 /* Critical interrupt */
1387/* MPC740/745/750 & IBM 750 specific exceptions */
1388#define EXCP_THRM 0x1700 /* Thermal management interrupt */
1389/* 74xx specific exceptions */
1390#define EXCP_74xx_VPUA 0x1600 /* VPU assist exception */
1391/* 970FX specific exceptions */
1392#define EXCP_970_SOFTP 0x1500 /* Soft patch exception */
1393#define EXCP_970_MAINT 0x1600 /* Maintenance exception */
1394#define EXCP_970_THRM 0x1800 /* Thermal exception */
1395#define EXCP_970_VPUA 0x1700 /* VPU assist exception */
0487d6a8
JM		 1396/* SPE related exceptions */
1397#define EXCP_NO_SPE 0x0F20 /* SPE unavailable exception */
2be0071f
FB		 1398/* End of exception vectors area */
1399#define EXCP_PPC_MAX 0x4000
1400/* Qemu exceptions: special cases we want to stop translation */
1401#define EXCP_MTMSR 0x11000 /* mtmsr instruction: */
76a66253 1402 /* may change privilege level */
2be0071f
FB		 1403#define EXCP_BRANCH 0x11001 /* branch instruction */
1404#define EXCP_SYSCALL_USER 0x12000 /* System call in user mode only */
2be0071f 1405
9a64fbe4
FB		 1406/* Error codes */
1407enum {
9a64fbe4
FB		 1408 /* Exception subtypes for EXCP_ALIGN */
1409 EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
1410 EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
1411 EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
1412 EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
1413 EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
1414 EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
1415 /* Exception subtypes for EXCP_PROGRAM */
79aceca5 1416 /* FP exceptions */
9a64fbe4
FB		 1417 EXCP_FP = 0x10,
1418 EXCP_FP_OX = 0x01, /* FP overflow */
1419 EXCP_FP_UX = 0x02, /* FP underflow */
1420 EXCP_FP_ZX = 0x03, /* FP divide by zero */
1421 EXCP_FP_XX = 0x04, /* FP inexact */
1422 EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */
0cfec834 1423 EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
9a64fbe4
FB		 1424 EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
1425 EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
1426 EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
1427 EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
1428 EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
1429 EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
1430 EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
79aceca5 1431 /* Invalid instruction */
9a64fbe4
FB		 1432 EXCP_INVAL = 0x20,
1433 EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
1434 EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
1435 EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
1436 EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
79aceca5 1437 /* Privileged instruction */
9a64fbe4 1438 EXCP_PRIV = 0x30,
8b67546f
JM		 1439 EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
1440 EXCP_PRIV_REG = 0x02, /* Privileged register exception */
79aceca5 1441 /* Trap */
9a64fbe4 1442 EXCP_TRAP = 0x40,
79aceca5
FB		 1443};
1444
47103572
JM		 1445/* Hardware interruption sources:
1446 * all those exception can be raised simulteaneously
1447 */
e9df014c
JM		 1448/* Input pins definitions */
1449enum {
1450 /* 6xx bus input pins */
24be5ae3
JM		 1451 PPC6xx_INPUT_HRESET = 0,
1452 PPC6xx_INPUT_SRESET = 1,
1453 PPC6xx_INPUT_CKSTP_IN = 2,
1454 PPC6xx_INPUT_MCP = 3,
1455 PPC6xx_INPUT_SMI = 4,
1456 PPC6xx_INPUT_INT = 5,
1457};
1458
1459enum {
e9df014c 1460 /* Embedded PowerPC input pins */
24be5ae3
JM		 1461 PPCBookE_INPUT_HRESET = 0,
1462 PPCBookE_INPUT_SRESET = 1,
1463 PPCBookE_INPUT_CKSTP_IN = 2,
1464 PPCBookE_INPUT_MCP = 3,
1465 PPCBookE_INPUT_SMI = 4,
1466 PPCBookE_INPUT_INT = 5,
1467 PPCBookE_INPUT_CINT = 6,
1468};
1469
1470enum {
1471 /* PowerPC 405 input pins */
1472 PPC405_INPUT_RESET_CORE = 0,
1473 PPC405_INPUT_RESET_CHIP = 1,
1474 PPC405_INPUT_RESET_SYS = 2,
1475 PPC405_INPUT_CINT = 3,
1476 PPC405_INPUT_INT = 4,
1477 PPC405_INPUT_HALT = 5,
1478 PPC405_INPUT_DEBUG = 6,
e9df014c
JM		 1479};
1480
d0dfae6e
JM		 1481enum {
1482 /* PowerPC 970 input pins */
1483 PPC970_INPUT_HRESET = 0,
1484 PPC970_INPUT_SRESET = 1,
1485 PPC970_INPUT_CKSTP = 2,
1486 PPC970_INPUT_TBEN = 3,
1487 PPC970_INPUT_MCP = 4,
1488 PPC970_INPUT_INT = 5,
1489 PPC970_INPUT_THINT = 6,
1490};
1491
e9df014c 1492/* Hardware exceptions definitions */
47103572 1493enum {
e9df014c
JM		 1494 /* External hardware exception sources */
1495 PPC_INTERRUPT_RESET = 0, /* Reset exception */
1496 PPC_INTERRUPT_MCK = 1, /* Machine check exception */
1497 PPC_INTERRUPT_EXT = 2, /* External interrupt */
1498 PPC_INTERRUPT_SMI = 3, /* System management interrupt */
1499 PPC_INTERRUPT_CEXT = 4, /* Critical external interrupt */
1500 PPC_INTERRUPT_DEBUG = 5, /* External debug exception */
d0dfae6e 1501 PPC_INTERRUPT_THERM = 6, /* Thermal exception */
e9df014c 1502 /* Internal hardware exception sources */
d0dfae6e
JM		 1503 PPC_INTERRUPT_DECR = 7, /* Decrementer exception */
1504 PPC_INTERRUPT_HDECR = 8, /* Hypervisor decrementer exception */
1505 PPC_INTERRUPT_PIT = 9, /* Programmable inteval timer interrupt */
1506 PPC_INTERRUPT_FIT = 10, /* Fixed interval timer interrupt */
1507 PPC_INTERRUPT_WDT = 11, /* Watchdog timer interrupt */
47103572
JM		 1508};
1509
9a64fbe4
FB		 1510/*****************************************************************************/
1511
79aceca5 1512#endif /* !defined (__CPU_PPC_H__) */
Qemu copy for testing