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79aceca5 1/*
3fc6c082 2 * PowerPC emulation cpu definitions for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#if !defined (__CPU_PPC_H__)
21#define __CPU_PPC_H__
22
3fc6c082 23#include "config.h"
de270b3c 24#include <inttypes.h>
3fc6c082 25
76a66253
JM		 26#if defined (TARGET_PPC64)
27typedef uint64_t ppc_gpr_t;
0487d6a8 28#define TARGET_GPR_BITS 64
d9d7210c 29#define TARGET_LONG_BITS 64
76a66253 30#define REGX "%016" PRIx64
35cdaad6
JM		 31#define TARGET_PAGE_BITS 12
32#elif defined(TARGET_PPCEMB)
8b67546f 33/* BookE have 36 bits physical address space */
e96efcfc 34#define TARGET_PHYS_ADDR_BITS 64
76a66253
JM		 35/* GPR are 64 bits: used by vector extension */
36typedef uint64_t ppc_gpr_t;
0487d6a8 37#define TARGET_GPR_BITS 64
d9d7210c 38#define TARGET_LONG_BITS 32
1b9eb036 39#define REGX "%016" PRIx64
d9d7210c
JM		 40#if defined(CONFIG_USER_ONLY)
41/* It looks like a lot of Linux programs assume page size
42 * is 4kB long. This is evil, but we have to deal with it...
43 */
44#define TARGET_PAGE_BITS 12
45#else
35cdaad6
JM		 46/* Pages can be 1 kB small */
47#define TARGET_PAGE_BITS 10
d9d7210c
JM		 48#endif
49#else
50#if (HOST_LONG_BITS >= 64)
51/* When using 64 bits temporary registers,
52 * we can use 64 bits GPR with no extra cost
53 * It's even an optimization as it will prevent
54 * the compiler to do unuseful masking in the micro-ops.
55 */
56typedef uint64_t ppc_gpr_t;
57#define TARGET_GPR_BITS 64
71c8b8fd 58#define REGX "%08" PRIx64
76a66253
JM		 59#else
60typedef uint32_t ppc_gpr_t;
0487d6a8 61#define TARGET_GPR_BITS 32
71c8b8fd 62#define REGX "%08" PRIx32
d9d7210c
JM		 63#endif
64#define TARGET_LONG_BITS 32
35cdaad6 65#define TARGET_PAGE_BITS 12
76a66253 66#endif
3cf1e035 67
79aceca5
FB		 68#include "cpu-defs.h"
69
e96efcfc
JM		 70#define ADDRX TARGET_FMT_lx
71#define PADDRX TARGET_FMT_plx
72
79aceca5
FB		 73#include <setjmp.h>
74
4ecc3190
FB		 75#include "softfloat.h"
76
1fddef4b
FB		 77#define TARGET_HAS_ICE 1
78
76a66253
JM		 79#if defined (TARGET_PPC64)
80#define ELF_MACHINE EM_PPC64
81#else
82#define ELF_MACHINE EM_PPC
83#endif
9042c0e2 84
fdabc366
FB		 85/* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC
86 * have different cache line sizes
87 */
88#define ICACHE_LINE_SIZE 32
89#define DCACHE_LINE_SIZE 32
90
3fc6c082 91/*****************************************************************************/
a750fc0b 92/* MMU model */
3fc6c082 93enum {
a750fc0b
JM		 94 POWERPC_MMU_UNKNOWN = 0,
95 /* Standard 32 bits PowerPC MMU */
96 POWERPC_MMU_32B,
97 /* Standard 64 bits PowerPC MMU */
98 POWERPC_MMU_64B,
99 /* PowerPC 601 MMU */
100 POWERPC_MMU_601,
101 /* PowerPC 6xx MMU with software TLB */
102 POWERPC_MMU_SOFT_6xx,
103 /* PowerPC 74xx MMU with software TLB */
104 POWERPC_MMU_SOFT_74xx,
105 /* PowerPC 4xx MMU with software TLB */
106 POWERPC_MMU_SOFT_4xx,
107 /* PowerPC 4xx MMU with software TLB and zones protections */
108 POWERPC_MMU_SOFT_4xx_Z,
109 /* PowerPC 4xx MMU in real mode only */
110 POWERPC_MMU_REAL_4xx,
111 /* BookE MMU model */
112 POWERPC_MMU_BOOKE,
113 /* BookE FSL MMU model */
114 POWERPC_MMU_BOOKE_FSL,
115 /* 64 bits "bridge" PowerPC MMU */
116 POWERPC_MMU_64BRIDGE,
3fc6c082
FB		 117};
118
119/*****************************************************************************/
a750fc0b 120/* Exception model */
3fc6c082 121enum {
a750fc0b 122 POWERPC_EXCP_UNKNOWN = 0,
3fc6c082 123 /* Standard PowerPC exception model */
a750fc0b 124 POWERPC_EXCP_STD,
2662a059 125 /* PowerPC 40x exception model */
a750fc0b 126 POWERPC_EXCP_40x,
2662a059 127 /* PowerPC 601 exception model */
a750fc0b 128 POWERPC_EXCP_601,
2662a059 129 /* PowerPC 602 exception model */
a750fc0b 130 POWERPC_EXCP_602,
2662a059 131 /* PowerPC 603 exception model */
a750fc0b
JM		 132 POWERPC_EXCP_603,
133 /* PowerPC 603e exception model */
134 POWERPC_EXCP_603E,
135 /* PowerPC G2 exception model */
136 POWERPC_EXCP_G2,
2662a059 137 /* PowerPC 604 exception model */
a750fc0b 138 POWERPC_EXCP_604,
2662a059 139 /* PowerPC 7x0 exception model */
a750fc0b 140 POWERPC_EXCP_7x0,
2662a059 141 /* PowerPC 7x5 exception model */
a750fc0b 142 POWERPC_EXCP_7x5,
2662a059 143 /* PowerPC 74xx exception model */
a750fc0b 144 POWERPC_EXCP_74xx,
2662a059 145 /* PowerPC 970 exception model */
a750fc0b 146 POWERPC_EXCP_970,
2662a059 147 /* BookE exception model */
a750fc0b
JM		 148 POWERPC_EXCP_BOOKE,
149};
150
e1833e1f
JM		 151/*****************************************************************************/
152/* Exception vectors definitions */
153enum {
154 POWERPC_EXCP_NONE = -1,
155 /* The 64 first entries are used by the PowerPC embedded specification */
156 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
157 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
158 POWERPC_EXCP_DSI = 2, /* Data storage exception */
159 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
160 POWERPC_EXCP_EXTERNAL = 4, /* External input */
161 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
162 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
163 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
164 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
165 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
166 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
167 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
168 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
169 POWERPC_EXCP_DTLB = 13, /* Data TLB error */
170 POWERPC_EXCP_ITLB = 14, /* Instruction TLB error */
171 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
172 /* Vectors 16 to 31 are reserved */
173#if defined(TARGET_PPCEMB)
174 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
175 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
176 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
177 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
178 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
179 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
180#endif /* defined(TARGET_PPCEMB) */
181 /* Vectors 38 to 63 are reserved */
182 /* Exceptions defined in the PowerPC server specification */
183 POWERPC_EXCP_RESET = 64, /* System reset exception */
184#if defined(TARGET_PPC64) /* PowerPC 64 */
185 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
186 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
187#endif /* defined(TARGET_PPC64) */
188#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
189 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
190#endif /* defined(TARGET_PPC64H) */
191 POWERPC_EXCP_TRACE = 68, /* Trace exception */
192#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
193 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
194 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
195 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
196 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
197#endif /* defined(TARGET_PPC64H) */
198 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
199 /* 40x specific exceptions */
200 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
201 /* 601 specific exceptions */
202 POWERPC_EXCP_IO = 75, /* IO error exception */
203 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
204 /* 602 specific exceptions */
205 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
206 /* 602/603 specific exceptions */
207 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB error */
208 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
209 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
210 /* Exceptions available on most PowerPC */
211 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
212 POWERPC_EXCP_IABR = 82, /* Instruction address breakpoint */
213 POWERPC_EXCP_SMI = 83, /* System management interrupt */
214 POWERPC_EXCP_PERFM = 84, /* Embedded performance monitor interrupt */
215 /* 7xx/74xx specific exceptions */
216 POWERPC_EXCP_THERM = 85, /* Thermal interrupt */
217 /* 74xx specific exceptions */
218 POWERPC_EXCP_VPUA = 86, /* Vector assist exception */
219 /* 970FX specific exceptions */
220 POWERPC_EXCP_SOFTP = 87, /* Soft patch exception */
221 POWERPC_EXCP_MAINT = 88, /* Maintenance exception */
222 /* EOL */
223 POWERPC_EXCP_NB = 96,
224 /* Qemu exceptions: used internally during code translation */
225 POWERPC_EXCP_STOP = 0x200, /* stop translation */
226 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
227 /* Qemu exceptions: special cases we want to stop translation */
228 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
229 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
230};
231
232
233/* Exceptions error codes */
234enum {
235 /* Exception subtypes for POWERPC_EXCP_ALIGN */
236 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
237 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
238 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
239 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
240 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
241 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
242 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
243 /* FP exceptions */
244 POWERPC_EXCP_FP = 0x10,
245 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
246 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
247 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
248 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
249 POWERPC_EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */
250 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
251 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
252 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
253 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
254 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
255 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
256 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
257 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
258 /* Invalid instruction */
259 POWERPC_EXCP_INVAL = 0x20,
260 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
261 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
262 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
263 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
264 /* Privileged instruction */
265 POWERPC_EXCP_PRIV = 0x30,
266 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
267 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
268 /* Trap */
269 POWERPC_EXCP_TRAP = 0x40,
270};
271
a750fc0b
JM		 272/*****************************************************************************/
273/* Input pins model */
274enum {
275 PPC_FLAGS_INPUT_UNKNOWN = 0,
2662a059 276 /* PowerPC 6xx bus */
a750fc0b 277 PPC_FLAGS_INPUT_6xx,
2662a059 278 /* BookE bus */
a750fc0b
JM		 279 PPC_FLAGS_INPUT_BookE,
280 /* PowerPC 405 bus */
281 PPC_FLAGS_INPUT_405,
2662a059 282 /* PowerPC 970 bus */
a750fc0b
JM		 283 PPC_FLAGS_INPUT_970,
284 /* PowerPC 401 bus */
285 PPC_FLAGS_INPUT_401,
3fc6c082
FB		 286};
287
a750fc0b 288#define PPC_INPUT(env) (env->bus_model)
3fc6c082 289
3fc6c082 290typedef struct ppc_def_t ppc_def_t;
a750fc0b 291typedef struct opc_handler_t opc_handler_t;
79aceca5 292
3fc6c082
FB		 293/*****************************************************************************/
294/* Types used to describe some PowerPC registers */
295typedef struct CPUPPCState CPUPPCState;
9fddaa0c 296typedef struct ppc_tb_t ppc_tb_t;
3fc6c082
FB		 297typedef struct ppc_spr_t ppc_spr_t;
298typedef struct ppc_dcr_t ppc_dcr_t;
299typedef struct ppc_avr_t ppc_avr_t;
1d0a48fb 300typedef union ppc_tlb_t ppc_tlb_t;
76a66253 301
3fc6c082
FB		 302/* SPR access micro-ops generations callbacks */
303struct ppc_spr_t {
304 void (*uea_read)(void *opaque, int spr_num);
305 void (*uea_write)(void *opaque, int spr_num);
76a66253 306#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 307 void (*oea_read)(void *opaque, int spr_num);
308 void (*oea_write)(void *opaque, int spr_num);
76a66253 309#endif
3fc6c082
FB		 310 const unsigned char *name;
311};
312
313/* Altivec registers (128 bits) */
314struct ppc_avr_t {
315 uint32_t u[4];
316};
9fddaa0c 317
3fc6c082 318/* Software TLB cache */
1d0a48fb
JM		 319typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
320struct ppc6xx_tlb_t {
76a66253
JM		 321 target_ulong pte0;
322 target_ulong pte1;
323 target_ulong EPN;
1d0a48fb
JM		 324};
325
326typedef struct ppcemb_tlb_t ppcemb_tlb_t;
327struct ppcemb_tlb_t {
c55e9aef 328 target_phys_addr_t RPN;
1d0a48fb 329 target_ulong EPN;
76a66253 330 target_ulong PID;
c55e9aef
JM		 331 target_ulong size;
332 uint32_t prot;
333 uint32_t attr; /* Storage attributes */
1d0a48fb
JM		 334};
335
336union ppc_tlb_t {
337 ppc6xx_tlb_t tlb6;
338 ppcemb_tlb_t tlbe;
3fc6c082
FB		 339};
340
341/*****************************************************************************/
342/* Machine state register bits definition */
76a66253 343#define MSR_SF 63 /* Sixty-four-bit mode hflags */
3fc6c082 344#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
76a66253 345#define MSR_HV 60 /* hypervisor state hflags */
363be49c
JM		 346#define MSR_CM 31 /* Computation mode for BookE hflags */
347#define MSR_ICM 30 /* Interrupt computation mode for BookE */
348#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
76a66253 349#define MSR_VR 25 /* altivec available hflags */
363be49c 350#define MSR_SPE 25 /* SPE enable for BookE hflags */
76a66253
JM		 351#define MSR_AP 23 /* Access privilege state on 602 hflags */
352#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
3fc6c082
FB		 353#define MSR_KEY 19 /* key bit on 603e */
354#define MSR_POW 18 /* Power management */
355#define MSR_WE 18 /* Wait state enable on embedded PowerPC */
356#define MSR_TGPR 17 /* TGPR usage on 602/603 */
76a66253 357#define MSR_TLB 17 /* TLB update on ? */
3fc6c082
FB		 358#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC */
359#define MSR_ILE 16 /* Interrupt little-endian mode */
360#define MSR_EE 15 /* External interrupt enable */
76a66253
JM		 361#define MSR_PR 14 /* Problem state hflags */
362#define MSR_FP 13 /* Floating point available hflags */
3fc6c082 363#define MSR_ME 12 /* Machine check interrupt enable */
76a66253
JM		 364#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
365#define MSR_SE 10 /* Single-step trace enable hflags */
3fc6c082 366#define MSR_DWE 10 /* Debug wait enable on 405 */
76a66253
JM		 367#define MSR_UBLE 10 /* User BTB lock enable on e500 */
368#define MSR_BE 9 /* Branch trace enable hflags */
3fc6c082 369#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC */
76a66253 370#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
3fc6c082
FB		 371#define MSR_AL 7 /* AL bit on POWER */
372#define MSR_IP 6 /* Interrupt prefix */
373#define MSR_IR 5 /* Instruction relocate */
374#define MSR_IS 5 /* Instruction address space on embedded PowerPC */
375#define MSR_DR 4 /* Data relocate */
376#define MSR_DS 4 /* Data address space on embedded PowerPC */
377#define MSR_PE 3 /* Protection enable on 403 */
378#define MSR_EP 3 /* Exception prefix on 601 */
379#define MSR_PX 2 /* Protection exclusive on 403 */
380#define MSR_PMM 2 /* Performance monitor mark on POWER */
381#define MSR_RI 1 /* Recoverable interrupt */
76a66253 382#define MSR_LE 0 /* Little-endian mode hflags */
3fc6c082
FB		 383#define msr_sf env->msr[MSR_SF]
384#define msr_isf env->msr[MSR_ISF]
385#define msr_hv env->msr[MSR_HV]
363be49c
JM		 386#define msr_cm env->msr[MSR_CM]
387#define msr_icm env->msr[MSR_ICM]
76a66253 388#define msr_ucle env->msr[MSR_UCLE]
3fc6c082 389#define msr_vr env->msr[MSR_VR]
76a66253 390#define msr_spe env->msr[MSR_SPE]
3fc6c082
FB		 391#define msr_ap env->msr[MSR_AP]
392#define msr_sa env->msr[MSR_SA]
393#define msr_key env->msr[MSR_KEY]
76a66253 394#define msr_pow env->msr[MSR_POW]
3fc6c082
FB		 395#define msr_we env->msr[MSR_WE]
396#define msr_tgpr env->msr[MSR_TGPR]
397#define msr_tlb env->msr[MSR_TLB]
398#define msr_ce env->msr[MSR_CE]
76a66253
JM		 399#define msr_ile env->msr[MSR_ILE]
400#define msr_ee env->msr[MSR_EE]
401#define msr_pr env->msr[MSR_PR]
402#define msr_fp env->msr[MSR_FP]
403#define msr_me env->msr[MSR_ME]
404#define msr_fe0 env->msr[MSR_FE0]
405#define msr_se env->msr[MSR_SE]
3fc6c082 406#define msr_dwe env->msr[MSR_DWE]
76a66253
JM		 407#define msr_uble env->msr[MSR_UBLE]
408#define msr_be env->msr[MSR_BE]
3fc6c082 409#define msr_de env->msr[MSR_DE]
76a66253 410#define msr_fe1 env->msr[MSR_FE1]
3fc6c082 411#define msr_al env->msr[MSR_AL]
76a66253
JM		 412#define msr_ip env->msr[MSR_IP]
413#define msr_ir env->msr[MSR_IR]
3fc6c082 414#define msr_is env->msr[MSR_IS]
76a66253 415#define msr_dr env->msr[MSR_DR]
3fc6c082
FB		 416#define msr_ds env->msr[MSR_DS]
417#define msr_pe env->msr[MSR_PE]
418#define msr_ep env->msr[MSR_EP]
419#define msr_px env->msr[MSR_PX]
420#define msr_pmm env->msr[MSR_PMM]
76a66253
JM		 421#define msr_ri env->msr[MSR_RI]
422#define msr_le env->msr[MSR_LE]
79aceca5 423
3fc6c082
FB		 424/*****************************************************************************/
425/* The whole PowerPC CPU context */
426struct CPUPPCState {
427 /* First are the most commonly used resources
428 * during translated code execution
429 */
0487d6a8 430#if TARGET_GPR_BITS > HOST_LONG_BITS
3fc6c082
FB		 431 /* temporary fixed-point registers
432 * used to emulate 64 bits target on 32 bits hosts
5fafdf24 433 */
3c4c9f9f 434 ppc_gpr_t t0, t1, t2;
3fc6c082 435#endif
d9bce9d9
JM		 436 ppc_avr_t t0_avr, t1_avr, t2_avr;
437
79aceca5 438 /* general purpose registers */
76a66253 439 ppc_gpr_t gpr[32];
3fc6c082
FB		 440 /* LR */
441 target_ulong lr;
442 /* CTR */
443 target_ulong ctr;
444 /* condition register */
445 uint8_t crf[8];
79aceca5 446 /* XER */
3fc6c082
FB		 447 /* XXX: We use only 5 fields, but we want to keep the structure aligned */
448 uint8_t xer[8];
79aceca5 449 /* Reservation address */
3fc6c082
FB		 450 target_ulong reserve;
451
452 /* Those ones are used in supervisor mode only */
79aceca5 453 /* machine state register */
3fc6c082
FB		 454 uint8_t msr[64];
455 /* temporary general purpose registers */
76a66253 456 ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
3fc6c082
FB		 457
458 /* Floating point execution context */
76a66253 459 /* temporary float registers */
4ecc3190
FB		 460 float64 ft0;
461 float64 ft1;
462 float64 ft2;
463 float_status fp_status;
3fc6c082
FB		 464 /* floating point registers */
465 float64 fpr[32];
466 /* floating point status and control register */
467 uint8_t fpscr[8];
4ecc3190 468
a316d335
FB		 469 CPU_COMMON
470
50443c98
FB		 471 int halted; /* TRUE if the CPU is in suspend state */
472
ac9eb073
FB		 473 int access_type; /* when a memory exception occurs, the access
474 type is stored here */
a541f297 475
3fc6c082
FB		 476 /* MMU context */
477 /* Address space register */
478 target_ulong asr;
479 /* segment registers */
480 target_ulong sdr1;
481 target_ulong sr[16];
482 /* BATs */
483 int nb_BATs;
484 target_ulong DBAT[2][8];
485 target_ulong IBAT[2][8];
9fddaa0c 486
3fc6c082
FB		 487 /* Other registers */
488 /* Special purpose registers */
489 target_ulong spr[1024];
490 /* Altivec registers */
491 ppc_avr_t avr[32];
492 uint32_t vscr;
d9bce9d9
JM		 493 /* SPE registers */
494 ppc_gpr_t spe_acc;
0487d6a8 495 float_status spe_status;
d9bce9d9 496 uint32_t spe_fscr;
3fc6c082
FB		 497
498 /* Internal devices resources */
9fddaa0c
FB		 499 /* Time base and decrementer */
500 ppc_tb_t *tb_env;
3fc6c082 501 /* Device control registers */
3fc6c082
FB		 502 ppc_dcr_t *dcr_env;
503
504 /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
76a66253
JM		 505 int nb_tlb; /* Total number of TLB */
506 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
507 int nb_ways; /* Number of ways in the TLB set */
508 int last_way; /* Last used way used to allocate TLB in a LRU way */
509 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
363be49c 510 int nb_pids; /* Number of available PID registers */
76a66253 511 ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
3fc6c082
FB		 512 /* 403 dedicated access protection registers */
513 target_ulong pb[4];
514
515 /* Those resources are used during exception processing */
516 /* CPU model definition */
a750fc0b
JM		 517 target_ulong msr_mask;
518 uint8_t mmu_model;
519 uint8_t excp_model;
520 uint8_t bus_model;
521 uint8_t pad;
237c0af0 522 int bfd_mach;
3fc6c082
FB		 523 uint32_t flags;
524
525 int exception_index;
526 int error_code;
527 int interrupt_request;
47103572 528 uint32_t pending_interrupts;
e9df014c
JM		 529#if !defined(CONFIG_USER_ONLY)
530 /* This is the IRQ controller, which is implementation dependant
531 * and only relevant when emulating a complete machine.
532 */
533 uint32_t irq_input_state;
534 void **irq_inputs;
e1833e1f
JM		 535 /* Exception vectors */
536 target_ulong excp_vectors[POWERPC_EXCP_NB];
537 target_ulong excp_prefix;
538 target_ulong ivor_mask;
539 target_ulong ivpr_mask;
e9df014c 540#endif
3fc6c082
FB		 541
542 /* Those resources are used only during code translation */
543 /* Next instruction pointer */
544 target_ulong nip;
545 /* SPR translation callbacks */
546 ppc_spr_t spr_cb[1024];
547 /* opcode handlers */
548 opc_handler_t *opcodes[0x40];
549
550 /* Those resources are used only in Qemu core */
551 jmp_buf jmp_env;
552 int user_mode_only; /* user mode only simulation */
4296f459 553 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
3fc6c082 554
9fddaa0c
FB		 555 /* Power management */
556 int power_mode;
a541f297 557
6d506e6d
FB		 558 /* temporary hack to handle OSI calls (only used if non NULL) */
559 int (*osi_call)(struct CPUPPCState *env);
3fc6c082 560};
79aceca5 561
76a66253
JM		 562/* Context used internally during MMU translations */
563typedef struct mmu_ctx_t mmu_ctx_t;
564struct mmu_ctx_t {
565 target_phys_addr_t raddr; /* Real address */
566 int prot; /* Protection bits */
567 target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
568 target_ulong ptem; /* Virtual segment ID | API */
569 int key; /* Access key */
570};
571
3fc6c082 572/*****************************************************************************/
36081602
JM		 573CPUPPCState *cpu_ppc_init (void);
574int cpu_ppc_exec (CPUPPCState *s);
575void cpu_ppc_close (CPUPPCState *s);
79aceca5
FB		 576/* you can call this signal handler from your SIGBUS and SIGSEGV
577 signal handlers to inform the virtual CPU of exceptions. non zero
578 is returned if the signal was handled by the virtual CPU. */
36081602
JM		 579int cpu_ppc_signal_handler (int host_signum, void *pinfo,
580 void *puc);
79aceca5 581
a541f297 582void do_interrupt (CPUPPCState *env);
e9df014c 583void ppc_hw_interrupt (CPUPPCState *env);
36081602 584void cpu_loop_exit (void);
a541f297 585
9a64fbe4 586void dump_stack (CPUPPCState *env);
a541f297 587
76a66253 588#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 589target_ulong do_load_ibatu (CPUPPCState *env, int nr);
590target_ulong do_load_ibatl (CPUPPCState *env, int nr);
591void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
592void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
593target_ulong do_load_dbatu (CPUPPCState *env, int nr);
594target_ulong do_load_dbatl (CPUPPCState *env, int nr);
595void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
596void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
3fc6c082
FB		 597target_ulong do_load_sdr1 (CPUPPCState *env);
598void do_store_sdr1 (CPUPPCState *env, target_ulong value);
d9bce9d9
JM		 599#if defined(TARGET_PPC64)
600target_ulong ppc_load_asr (CPUPPCState *env);
601void ppc_store_asr (CPUPPCState *env, target_ulong value);
602#endif
3fc6c082
FB		 603target_ulong do_load_sr (CPUPPCState *env, int srnum);
604void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
76a66253
JM		 605#endif
606uint32_t ppc_load_xer (CPUPPCState *env);
607void ppc_store_xer (CPUPPCState *env, uint32_t value);
3fc6c082
FB		 608target_ulong do_load_msr (CPUPPCState *env);
609void do_store_msr (CPUPPCState *env, target_ulong value);
426613db 610void ppc_store_msr_32 (CPUPPCState *env, uint32_t value);
3fc6c082
FB		 611
612void do_compute_hflags (CPUPPCState *env);
0a032cbe
JM		 613void cpu_ppc_reset (void *opaque);
614CPUPPCState *cpu_ppc_init (void);
615void cpu_ppc_close(CPUPPCState *env);
a541f297 616
3fc6c082
FB		 617int ppc_find_by_name (const unsigned char *name, ppc_def_t **def);
618int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
619void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
620int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);
85c4adf6 621
9fddaa0c
FB		 622/* Time-base and decrementer management */
623#ifndef NO_CPU_IO_DEFS
624uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
625uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
626void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
627void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
628uint32_t cpu_ppc_load_decr (CPUPPCState *env);
629void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
58a7d328
JM		 630#if defined(TARGET_PPC64H)
631uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
632void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
633uint64_t cpu_ppc_load_purr (CPUPPCState *env);
634void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
635#endif
d9bce9d9
JM		 636uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
637uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
638#if !defined(CONFIG_USER_ONLY)
639void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
640void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
641target_ulong load_40x_pit (CPUPPCState *env);
642void store_40x_pit (CPUPPCState *env, target_ulong val);
8ecc7913 643void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
c294fc58 644void store_40x_sler (CPUPPCState *env, uint32_t val);
d9bce9d9
JM		 645void store_booke_tcr (CPUPPCState *env, target_ulong val);
646void store_booke_tsr (CPUPPCState *env, target_ulong val);
0a032cbe 647void ppc_tlb_invalidate_all (CPUPPCState *env);
36081602 648int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
d9bce9d9 649#endif
9fddaa0c 650#endif
79aceca5 651
2e719ba3
JM		 652/* Device control registers */
653int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
654int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
655
9467d44c
TS		 656#define CPUState CPUPPCState
657#define cpu_init cpu_ppc_init
658#define cpu_exec cpu_ppc_exec
659#define cpu_gen_code cpu_ppc_gen_code
660#define cpu_signal_handler cpu_ppc_signal_handler
661
79aceca5
FB		 662#include "cpu-all.h"
663
3fc6c082
FB		 664/*****************************************************************************/
665/* Registers definitions */
79aceca5
FB		 666#define XER_SO 31
667#define XER_OV 30
668#define XER_CA 29
3fc6c082 669#define XER_CMP 8
36081602 670#define XER_BC 0
3fc6c082
FB		 671#define xer_so env->xer[4]
672#define xer_ov env->xer[6]
673#define xer_ca env->xer[2]
674#define xer_cmp env->xer[1]
36081602 675#define xer_bc env->xer[0]
79aceca5 676
3fc6c082 677/* SPR definitions */
76a66253
JM		 678#define SPR_MQ (0x000)
679#define SPR_XER (0x001)
680#define SPR_601_VRTCU (0x004)
681#define SPR_601_VRTCL (0x005)
682#define SPR_601_UDECR (0x006)
683#define SPR_LR (0x008)
684#define SPR_CTR (0x009)
685#define SPR_DSISR (0x012)
a750fc0b 686#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
76a66253
JM		 687#define SPR_601_RTCU (0x014)
688#define SPR_601_RTCL (0x015)
689#define SPR_DECR (0x016)
690#define SPR_SDR1 (0x019)
691#define SPR_SRR0 (0x01A)
692#define SPR_SRR1 (0x01B)
2662a059 693#define SPR_AMR (0x01D)
76a66253
JM		 694#define SPR_BOOKE_PID (0x030)
695#define SPR_BOOKE_DECAR (0x036)
363be49c
JM		 696#define SPR_BOOKE_CSRR0 (0x03A)
697#define SPR_BOOKE_CSRR1 (0x03B)
76a66253
JM		 698#define SPR_BOOKE_DEAR (0x03D)
699#define SPR_BOOKE_ESR (0x03E)
363be49c 700#define SPR_BOOKE_IVPR (0x03F)
76a66253
JM		 701#define SPR_8xx_EIE (0x050)
702#define SPR_8xx_EID (0x051)
703#define SPR_8xx_NRE (0x052)
2662a059 704#define SPR_CTRL (0x088)
76a66253
JM		 705#define SPR_58x_CMPA (0x090)
706#define SPR_58x_CMPB (0x091)
707#define SPR_58x_CMPC (0x092)
708#define SPR_58x_CMPD (0x093)
709#define SPR_58x_ICR (0x094)
710#define SPR_58x_DER (0x094)
711#define SPR_58x_COUNTA (0x096)
712#define SPR_58x_COUNTB (0x097)
2662a059 713#define SPR_UCTRL (0x098)
76a66253
JM		 714#define SPR_58x_CMPE (0x098)
715#define SPR_58x_CMPF (0x099)
716#define SPR_58x_CMPG (0x09A)
717#define SPR_58x_CMPH (0x09B)
718#define SPR_58x_LCTRL1 (0x09C)
719#define SPR_58x_LCTRL2 (0x09D)
720#define SPR_58x_ICTRL (0x09E)
721#define SPR_58x_BAR (0x09F)
722#define SPR_VRSAVE (0x100)
723#define SPR_USPRG0 (0x100)
363be49c
JM		 724#define SPR_USPRG1 (0x101)
725#define SPR_USPRG2 (0x102)
726#define SPR_USPRG3 (0x103)
76a66253
JM		 727#define SPR_USPRG4 (0x104)
728#define SPR_USPRG5 (0x105)
729#define SPR_USPRG6 (0x106)
730#define SPR_USPRG7 (0x107)
731#define SPR_VTBL (0x10C)
732#define SPR_VTBU (0x10D)
733#define SPR_SPRG0 (0x110)
734#define SPR_SPRG1 (0x111)
735#define SPR_SPRG2 (0x112)
736#define SPR_SPRG3 (0x113)
737#define SPR_SPRG4 (0x114)
738#define SPR_SCOMC (0x114)
739#define SPR_SPRG5 (0x115)
740#define SPR_SCOMD (0x115)
741#define SPR_SPRG6 (0x116)
742#define SPR_SPRG7 (0x117)
743#define SPR_ASR (0x118)
744#define SPR_EAR (0x11A)
745#define SPR_TBL (0x11C)
746#define SPR_TBU (0x11D)
2662a059 747#define SPR_TBU40 (0x11E)
76a66253
JM		 748#define SPR_SVR (0x11E)
749#define SPR_BOOKE_PIR (0x11E)
750#define SPR_PVR (0x11F)
751#define SPR_HSPRG0 (0x130)
752#define SPR_BOOKE_DBSR (0x130)
753#define SPR_HSPRG1 (0x131)
2662a059
JM		 754#define SPR_HDSISR (0x132)
755#define SPR_HDAR (0x133)
76a66253
JM		 756#define SPR_BOOKE_DBCR0 (0x134)
757#define SPR_IBCR (0x135)
2662a059 758#define SPR_PURR (0x135)
76a66253
JM		 759#define SPR_BOOKE_DBCR1 (0x135)
760#define SPR_DBCR (0x136)
761#define SPR_HDEC (0x136)
762#define SPR_BOOKE_DBCR2 (0x136)
763#define SPR_HIOR (0x137)
764#define SPR_MBAR (0x137)
765#define SPR_RMOR (0x138)
766#define SPR_BOOKE_IAC1 (0x138)
767#define SPR_HRMOR (0x139)
768#define SPR_BOOKE_IAC2 (0x139)
e1833e1f 769#define SPR_HSRR0 (0x13A)
76a66253 770#define SPR_BOOKE_IAC3 (0x13A)
e1833e1f 771#define SPR_HSRR1 (0x13B)
76a66253
JM		 772#define SPR_BOOKE_IAC4 (0x13B)
773#define SPR_LPCR (0x13C)
774#define SPR_BOOKE_DAC1 (0x13C)
775#define SPR_LPIDR (0x13D)
776#define SPR_DABR2 (0x13D)
777#define SPR_BOOKE_DAC2 (0x13D)
778#define SPR_BOOKE_DVC1 (0x13E)
779#define SPR_BOOKE_DVC2 (0x13F)
780#define SPR_BOOKE_TSR (0x150)
781#define SPR_BOOKE_TCR (0x154)
782#define SPR_BOOKE_IVOR0 (0x190)
783#define SPR_BOOKE_IVOR1 (0x191)
784#define SPR_BOOKE_IVOR2 (0x192)
785#define SPR_BOOKE_IVOR3 (0x193)
786#define SPR_BOOKE_IVOR4 (0x194)
787#define SPR_BOOKE_IVOR5 (0x195)
788#define SPR_BOOKE_IVOR6 (0x196)
789#define SPR_BOOKE_IVOR7 (0x197)
790#define SPR_BOOKE_IVOR8 (0x198)
791#define SPR_BOOKE_IVOR9 (0x199)
792#define SPR_BOOKE_IVOR10 (0x19A)
793#define SPR_BOOKE_IVOR11 (0x19B)
794#define SPR_BOOKE_IVOR12 (0x19C)
795#define SPR_BOOKE_IVOR13 (0x19D)
796#define SPR_BOOKE_IVOR14 (0x19E)
797#define SPR_BOOKE_IVOR15 (0x19F)
2662a059 798#define SPR_BOOKE_SPEFSCR (0x200)
76a66253
JM		 799#define SPR_E500_BBEAR (0x201)
800#define SPR_E500_BBTAR (0x202)
801#define SPR_BOOKE_ATBL (0x20E)
802#define SPR_BOOKE_ATBU (0x20F)
803#define SPR_IBAT0U (0x210)
363be49c 804#define SPR_BOOKE_IVOR32 (0x210)
76a66253 805#define SPR_IBAT0L (0x211)
363be49c 806#define SPR_BOOKE_IVOR33 (0x211)
76a66253 807#define SPR_IBAT1U (0x212)
363be49c 808#define SPR_BOOKE_IVOR34 (0x212)
76a66253 809#define SPR_IBAT1L (0x213)
363be49c 810#define SPR_BOOKE_IVOR35 (0x213)
76a66253 811#define SPR_IBAT2U (0x214)
363be49c 812#define SPR_BOOKE_IVOR36 (0x214)
76a66253
JM		 813#define SPR_IBAT2L (0x215)
814#define SPR_E500_L1CFG0 (0x215)
363be49c 815#define SPR_BOOKE_IVOR37 (0x215)
76a66253
JM		 816#define SPR_IBAT3U (0x216)
817#define SPR_E500_L1CFG1 (0x216)
818#define SPR_IBAT3L (0x217)
819#define SPR_DBAT0U (0x218)
820#define SPR_DBAT0L (0x219)
821#define SPR_DBAT1U (0x21A)
822#define SPR_DBAT1L (0x21B)
823#define SPR_DBAT2U (0x21C)
824#define SPR_DBAT2L (0x21D)
825#define SPR_DBAT3U (0x21E)
826#define SPR_DBAT3L (0x21F)
827#define SPR_IBAT4U (0x230)
828#define SPR_IBAT4L (0x231)
829#define SPR_IBAT5U (0x232)
830#define SPR_IBAT5L (0x233)
831#define SPR_IBAT6U (0x234)
832#define SPR_IBAT6L (0x235)
833#define SPR_IBAT7U (0x236)
834#define SPR_IBAT7L (0x237)
835#define SPR_DBAT4U (0x238)
836#define SPR_DBAT4L (0x239)
837#define SPR_DBAT5U (0x23A)
363be49c 838#define SPR_BOOKE_MCSRR0 (0x23A)
76a66253 839#define SPR_DBAT5L (0x23B)
363be49c 840#define SPR_BOOKE_MCSRR1 (0x23B)
76a66253 841#define SPR_DBAT6U (0x23C)
363be49c 842#define SPR_BOOKE_MCSR (0x23C)
76a66253
JM		 843#define SPR_DBAT6L (0x23D)
844#define SPR_E500_MCAR (0x23D)
845#define SPR_DBAT7U (0x23E)
363be49c 846#define SPR_BOOKE_DSRR0 (0x23E)
76a66253 847#define SPR_DBAT7L (0x23F)
363be49c
JM		 848#define SPR_BOOKE_DSRR1 (0x23F)
849#define SPR_BOOKE_SPRG8 (0x25C)
850#define SPR_BOOKE_SPRG9 (0x25D)
851#define SPR_BOOKE_MAS0 (0x270)
852#define SPR_BOOKE_MAS1 (0x271)
853#define SPR_BOOKE_MAS2 (0x272)
854#define SPR_BOOKE_MAS3 (0x273)
855#define SPR_BOOKE_MAS4 (0x274)
856#define SPR_BOOKE_MAS6 (0x276)
857#define SPR_BOOKE_PID1 (0x279)
858#define SPR_BOOKE_PID2 (0x27A)
859#define SPR_BOOKE_TLB0CFG (0x2B0)
860#define SPR_BOOKE_TLB1CFG (0x2B1)
861#define SPR_BOOKE_TLB2CFG (0x2B2)
862#define SPR_BOOKE_TLB3CFG (0x2B3)
863#define SPR_BOOKE_EPR (0x2BE)
2662a059
JM		 864#define SPR_PERF0 (0x300)
865#define SPR_PERF1 (0x301)
866#define SPR_PERF2 (0x302)
867#define SPR_PERF3 (0x303)
868#define SPR_PERF4 (0x304)
869#define SPR_PERF5 (0x305)
870#define SPR_PERF6 (0x306)
871#define SPR_PERF7 (0x307)
872#define SPR_PERF8 (0x308)
873#define SPR_PERF9 (0x309)
874#define SPR_PERFA (0x30A)
875#define SPR_PERFB (0x30B)
876#define SPR_PERFC (0x30C)
877#define SPR_PERFD (0x30D)
878#define SPR_PERFE (0x30E)
879#define SPR_PERFF (0x30F)
880#define SPR_UPERF0 (0x310)
881#define SPR_UPERF1 (0x311)
882#define SPR_UPERF2 (0x312)
883#define SPR_UPERF3 (0x313)
884#define SPR_UPERF4 (0x314)
885#define SPR_UPERF5 (0x315)
886#define SPR_UPERF6 (0x316)
887#define SPR_UPERF7 (0x317)
888#define SPR_UPERF8 (0x318)
889#define SPR_UPERF9 (0x319)
890#define SPR_UPERFA (0x31A)
891#define SPR_UPERFB (0x31B)
892#define SPR_UPERFC (0x31C)
893#define SPR_UPERFD (0x31D)
894#define SPR_UPERFE (0x31E)
895#define SPR_UPERFF (0x31F)
76a66253
JM		 896#define SPR_440_INV0 (0x370)
897#define SPR_440_INV1 (0x371)
898#define SPR_440_INV2 (0x372)
899#define SPR_440_INV3 (0x373)
2662a059
JM		 900#define SPR_440_ITV0 (0x374)
901#define SPR_440_ITV1 (0x375)
902#define SPR_440_ITV2 (0x376)
903#define SPR_440_ITV3 (0x377)
a750fc0b
JM		 904#define SPR_440_CCR1 (0x378)
905#define SPR_DCRIPR (0x37B)
2662a059 906#define SPR_PPR (0x380)
76a66253
JM		 907#define SPR_440_DNV0 (0x390)
908#define SPR_440_DNV1 (0x391)
909#define SPR_440_DNV2 (0x392)
910#define SPR_440_DNV3 (0x393)
2662a059
JM		 911#define SPR_440_DTV0 (0x394)
912#define SPR_440_DTV1 (0x395)
913#define SPR_440_DTV2 (0x396)
914#define SPR_440_DTV3 (0x397)
76a66253
JM		 915#define SPR_440_DVLIM (0x398)
916#define SPR_440_IVLIM (0x399)
917#define SPR_440_RSTCFG (0x39B)
2662a059
JM		 918#define SPR_BOOKE_DCDBTRL (0x39C)
919#define SPR_BOOKE_DCDBTRH (0x39D)
920#define SPR_BOOKE_ICDBTRL (0x39E)
921#define SPR_BOOKE_ICDBTRH (0x39F)
a750fc0b
JM		 922#define SPR_UMMCR2 (0x3A0)
923#define SPR_UPMC5 (0x3A1)
924#define SPR_UPMC6 (0x3A2)
925#define SPR_UBAMR (0x3A7)
76a66253
JM		 926#define SPR_UMMCR0 (0x3A8)
927#define SPR_UPMC1 (0x3A9)
928#define SPR_UPMC2 (0x3AA)
a750fc0b 929#define SPR_USIAR (0x3AB)
76a66253
JM		 930#define SPR_UMMCR1 (0x3AC)
931#define SPR_UPMC3 (0x3AD)
932#define SPR_UPMC4 (0x3AE)
933#define SPR_USDA (0x3AF)
934#define SPR_40x_ZPR (0x3B0)
363be49c 935#define SPR_BOOKE_MAS7 (0x3B0)
a750fc0b
JM		 936#define SPR_620_PMR0 (0x3B0)
937#define SPR_MMCR2 (0x3B0)
938#define SPR_PMC5 (0x3B1)
76a66253 939#define SPR_40x_PID (0x3B1)
a750fc0b
JM		 940#define SPR_620_PMR1 (0x3B1)
941#define SPR_PMC6 (0x3B2)
76a66253 942#define SPR_440_MMUCR (0x3B2)
a750fc0b 943#define SPR_620_PMR2 (0x3B2)
76a66253 944#define SPR_4xx_CCR0 (0x3B3)
363be49c 945#define SPR_BOOKE_EPLC (0x3B3)
a750fc0b 946#define SPR_620_PMR3 (0x3B3)
76a66253 947#define SPR_405_IAC3 (0x3B4)
363be49c 948#define SPR_BOOKE_EPSC (0x3B4)
a750fc0b 949#define SPR_620_PMR4 (0x3B4)
76a66253 950#define SPR_405_IAC4 (0x3B5)
a750fc0b 951#define SPR_620_PMR5 (0x3B5)
76a66253 952#define SPR_405_DVC1 (0x3B6)
a750fc0b 953#define SPR_620_PMR6 (0x3B6)
76a66253 954#define SPR_405_DVC2 (0x3B7)
a750fc0b
JM		 955#define SPR_620_PMR7 (0x3B7)
956#define SPR_BAMR (0x3B7)
76a66253 957#define SPR_MMCR0 (0x3B8)
a750fc0b 958#define SPR_620_PMR8 (0x3B8)
76a66253
JM		 959#define SPR_PMC1 (0x3B9)
960#define SPR_40x_SGR (0x3B9)
a750fc0b 961#define SPR_620_PMR9 (0x3B9)
76a66253
JM		 962#define SPR_PMC2 (0x3BA)
963#define SPR_40x_DCWR (0x3BA)
a750fc0b
JM		 964#define SPR_620_PMRA (0x3BA)
965#define SPR_SIAR (0x3BB)
76a66253 966#define SPR_405_SLER (0x3BB)
a750fc0b 967#define SPR_620_PMRB (0x3BB)
76a66253
JM		 968#define SPR_MMCR1 (0x3BC)
969#define SPR_405_SU0R (0x3BC)
a750fc0b
JM		 970#define SPR_620_PMRC (0x3BC)
971#define SPR_401_SKR (0x3BC)
76a66253
JM		 972#define SPR_PMC3 (0x3BD)
973#define SPR_405_DBCR1 (0x3BD)
a750fc0b 974#define SPR_620_PMRD (0x3BD)
76a66253 975#define SPR_PMC4 (0x3BE)
a750fc0b 976#define SPR_620_PMRE (0x3BE)
76a66253 977#define SPR_SDA (0x3BF)
a750fc0b 978#define SPR_620_PMRF (0x3BF)
76a66253
JM		 979#define SPR_403_VTBL (0x3CC)
980#define SPR_403_VTBU (0x3CD)
981#define SPR_DMISS (0x3D0)
982#define SPR_DCMP (0x3D1)
983#define SPR_HASH1 (0x3D2)
984#define SPR_HASH2 (0x3D3)
2662a059 985#define SPR_BOOKE_ICDBDR (0x3D3)
a750fc0b 986#define SPR_TLBMISS (0x3D4)
76a66253
JM		 987#define SPR_IMISS (0x3D4)
988#define SPR_40x_ESR (0x3D4)
a750fc0b 989#define SPR_PTEHI (0x3D5)
76a66253
JM		 990#define SPR_ICMP (0x3D5)
991#define SPR_40x_DEAR (0x3D5)
a750fc0b 992#define SPR_PTELO (0x3D6)
76a66253
JM		 993#define SPR_RPA (0x3D6)
994#define SPR_40x_EVPR (0x3D6)
a750fc0b 995#define SPR_L3PM (0x3D7)
76a66253 996#define SPR_403_CDBCR (0x3D7)
a750fc0b 997#define SPR_L3OHCR (0x3D8)
76a66253
JM		 998#define SPR_TCR (0x3D8)
999#define SPR_40x_TSR (0x3D8)
1000#define SPR_IBR (0x3DA)
1001#define SPR_40x_TCR (0x3DA)
a750fc0b 1002#define SPR_ESASRR (0x3DB)
76a66253
JM		 1003#define SPR_40x_PIT (0x3DB)
1004#define SPR_403_TBL (0x3DC)
1005#define SPR_403_TBU (0x3DD)
1006#define SPR_SEBR (0x3DE)
1007#define SPR_40x_SRR2 (0x3DE)
1008#define SPR_SER (0x3DF)
1009#define SPR_40x_SRR3 (0x3DF)
a750fc0b
JM		 1010#define SPR_L3ITCR0 (0x3E8)
1011#define SPR_L3ITCR1 (0x3E9)
1012#define SPR_L3ITCR2 (0x3EA)
1013#define SPR_L3ITCR3 (0x3EB)
76a66253
JM		 1014#define SPR_HID0 (0x3F0)
1015#define SPR_40x_DBSR (0x3F0)
1016#define SPR_HID1 (0x3F1)
1017#define SPR_IABR (0x3F2)
1018#define SPR_40x_DBCR0 (0x3F2)
1019#define SPR_601_HID2 (0x3F2)
1020#define SPR_E500_L1CSR0 (0x3F2)
a750fc0b 1021#define SPR_ICTRL (0x3F3)
76a66253
JM		 1022#define SPR_HID2 (0x3F3)
1023#define SPR_E500_L1CSR1 (0x3F3)
1024#define SPR_440_DBDR (0x3F3)
a750fc0b 1025#define SPR_LDSTDB (0x3F4)
76a66253 1026#define SPR_40x_IAC1 (0x3F4)
363be49c 1027#define SPR_BOOKE_MMUCSR0 (0x3F4)
76a66253 1028#define SPR_DABR (0x3F5)
3fc6c082 1029#define DABR_MASK (~(target_ulong)0x7)
76a66253
JM		 1030#define SPR_E500_BUCSR (0x3F5)
1031#define SPR_40x_IAC2 (0x3F5)
1032#define SPR_601_HID5 (0x3F5)
1033#define SPR_40x_DAC1 (0x3F6)
a750fc0b
JM		 1034#define SPR_MSSCR0 (0x3F6)
1035#define SPR_MSSSR0 (0x3F7)
2662a059 1036#define SPR_DABRX (0x3F7)
76a66253 1037#define SPR_40x_DAC2 (0x3F7)
363be49c 1038#define SPR_BOOKE_MMUCFG (0x3F7)
a750fc0b
JM		 1039#define SPR_LDSTCR (0x3F8)
1040#define SPR_L2PMCR (0x3F8)
76a66253 1041#define SPR_750_HID2 (0x3F8)
a750fc0b 1042#define SPR_620_HID8 (0x3F8)
76a66253 1043#define SPR_L2CR (0x3F9)
a750fc0b
JM		 1044#define SPR_620_HID9 (0x3F9)
1045#define SPR_L3CR (0x3FA)
76a66253
JM		 1046#define SPR_IABR2 (0x3FA)
1047#define SPR_40x_DCCR (0x3FA)
1048#define SPR_ICTC (0x3FB)
1049#define SPR_40x_ICCR (0x3FB)
1050#define SPR_THRM1 (0x3FC)
1051#define SPR_403_PBL1 (0x3FC)
1052#define SPR_SP (0x3FD)
1053#define SPR_THRM2 (0x3FD)
1054#define SPR_403_PBU1 (0x3FD)
a750fc0b 1055#define SPR_604_HID13 (0x3FD)
76a66253
JM		 1056#define SPR_LT (0x3FE)
1057#define SPR_THRM3 (0x3FE)
1058#define SPR_FPECR (0x3FE)
1059#define SPR_403_PBL2 (0x3FE)
1060#define SPR_PIR (0x3FF)
1061#define SPR_403_PBU2 (0x3FF)
1062#define SPR_601_HID15 (0x3FF)
a750fc0b 1063#define SPR_604_HID15 (0x3FF)
76a66253 1064#define SPR_E500_SVR (0x3FF)
79aceca5 1065
76a66253 1066/*****************************************************************************/
9a64fbe4
FB		 1067/* Memory access type :
1068 * may be needed for precise access rights control and precise exceptions.
1069 */
79aceca5 1070enum {
9a64fbe4
FB		 1071 /* 1 bit to define user level / supervisor access */
1072 ACCESS_USER = 0x00,
1073 ACCESS_SUPER = 0x01,
1074 /* Type of instruction that generated the access */
1075 ACCESS_CODE = 0x10, /* Code fetch access */
1076 ACCESS_INT = 0x20, /* Integer load/store access */
1077 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1078 ACCESS_RES = 0x40, /* load/store with reservation */
1079 ACCESS_EXT = 0x50, /* external access */
1080 ACCESS_CACHE = 0x60, /* Cache manipulation */
1081};
1082
47103572
JM		 1083/* Hardware interruption sources:
1084 * all those exception can be raised simulteaneously
1085 */
e9df014c
JM		 1086/* Input pins definitions */
1087enum {
1088 /* 6xx bus input pins */
24be5ae3
JM		 1089 PPC6xx_INPUT_HRESET = 0,
1090 PPC6xx_INPUT_SRESET = 1,
1091 PPC6xx_INPUT_CKSTP_IN = 2,
1092 PPC6xx_INPUT_MCP = 3,
1093 PPC6xx_INPUT_SMI = 4,
1094 PPC6xx_INPUT_INT = 5,
1095};
1096
1097enum {
e9df014c 1098 /* Embedded PowerPC input pins */
24be5ae3
JM		 1099 PPCBookE_INPUT_HRESET = 0,
1100 PPCBookE_INPUT_SRESET = 1,
1101 PPCBookE_INPUT_CKSTP_IN = 2,
1102 PPCBookE_INPUT_MCP = 3,
1103 PPCBookE_INPUT_SMI = 4,
1104 PPCBookE_INPUT_INT = 5,
1105 PPCBookE_INPUT_CINT = 6,
1106};
1107
a750fc0b
JM		 1108enum {
1109 /* PowerPC 401/403 input pins */
1110 PPC401_INPUT_RESET = 0,
1111 PPC401_INPUT_CINT = 1,
1112 PPC401_INPUT_INT = 2,
1113 PPC401_INPUT_BERR = 3,
1114 PPC401_INPUT_HALT = 4,
1115};
1116
24be5ae3
JM		 1117enum {
1118 /* PowerPC 405 input pins */
1119 PPC405_INPUT_RESET_CORE = 0,
1120 PPC405_INPUT_RESET_CHIP = 1,
1121 PPC405_INPUT_RESET_SYS = 2,
1122 PPC405_INPUT_CINT = 3,
1123 PPC405_INPUT_INT = 4,
1124 PPC405_INPUT_HALT = 5,
1125 PPC405_INPUT_DEBUG = 6,
e9df014c
JM		 1126};
1127
a750fc0b
JM		 1128enum {
1129 /* PowerPC 620 (and probably others) input pins */
1130 PPC620_INPUT_HRESET = 0,
1131 PPC620_INPUT_SRESET = 1,
1132 PPC620_INPUT_CKSTP = 2,
1133 PPC620_INPUT_TBEN = 3,
1134 PPC620_INPUT_WAKEUP = 4,
1135 PPC620_INPUT_MCP = 5,
1136 PPC620_INPUT_SMI = 6,
1137 PPC620_INPUT_INT = 7,
1138};
1139
d0dfae6e
JM		 1140enum {
1141 /* PowerPC 970 input pins */
1142 PPC970_INPUT_HRESET = 0,
1143 PPC970_INPUT_SRESET = 1,
1144 PPC970_INPUT_CKSTP = 2,
1145 PPC970_INPUT_TBEN = 3,
1146 PPC970_INPUT_MCP = 4,
1147 PPC970_INPUT_INT = 5,
1148 PPC970_INPUT_THINT = 6,
1149};
1150
e9df014c 1151/* Hardware exceptions definitions */
47103572 1152enum {
e9df014c 1153 /* External hardware exception sources */
e1833e1f
JM		 1154 PPC_INTERRUPT_RESET = 0, /* Reset exception */
1155 PPC_INTERRUPT_MCK = 1, /* Machine check exception */
1156 PPC_INTERRUPT_EXT = 2, /* External interrupt */
1157 PPC_INTERRUPT_SMI = 3, /* System management interrupt */
1158 PPC_INTERRUPT_CEXT = 4, /* Critical external interrupt */
1159 PPC_INTERRUPT_DEBUG = 5, /* External debug exception */
1160 PPC_INTERRUPT_THERM = 6, /* Thermal exception */
e9df014c 1161 /* Internal hardware exception sources */
e1833e1f
JM		 1162 PPC_INTERRUPT_DECR = 7, /* Decrementer exception */
1163 PPC_INTERRUPT_HDECR = 8, /* Hypervisor decrementer exception */
1164 PPC_INTERRUPT_PIT = 9, /* Programmable inteval timer interrupt */
1165 PPC_INTERRUPT_FIT = 10, /* Fixed interval timer interrupt */
1166 PPC_INTERRUPT_WDT = 11, /* Watchdog timer interrupt */
1167 PPC_INTERRUPT_CDOORBELL = 12, /* Critical doorbell interrupt */
1168 PPC_INTERRUPT_DOORBELL = 13, /* Doorbell interrupt */
1169 PPC_INTERRUPT_PERFM = 14, /* Performance monitor interrupt */
47103572
JM		 1170};
1171
9a64fbe4
FB		 1172/*****************************************************************************/
1173
79aceca5 1174#endif /* !defined (__CPU_PPC_H__) */
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