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ARM register index+writeback fix (Lauro Ramos Venancio).
[qemu.git] / target-ppc / cpu.h
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation cpu definitions for qemu.
79aceca5 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#if !defined (__CPU_PPC_H__)
21#define __CPU_PPC_H__
22
3fc6c082 23#include "config.h"
76a66253 24#include <stdint.h>
3fc6c082 25
76a66253
JM		 26#if defined (TARGET_PPC64)
27typedef uint64_t ppc_gpr_t;
28#define TARGET_LONG_BITS 64
29#define REGX "%016" PRIx64
30#elif defined(TARGET_E500)
31/* GPR are 64 bits: used by vector extension */
32typedef uint64_t ppc_gpr_t;
3cf1e035 33#define TARGET_LONG_BITS 32
76a66253
JM		 34#define REGX "%08" PRIx32
35#else
36typedef uint32_t ppc_gpr_t;
37#define TARGET_LONG_BITS 32
38#define REGX "%08" PRIx32
39#endif
3cf1e035 40
79aceca5
FB		 41#include "cpu-defs.h"
42
79aceca5
FB		 43#include <setjmp.h>
44
4ecc3190
FB		 45#include "softfloat.h"
46
1fddef4b
FB		 47#define TARGET_HAS_ICE 1
48
76a66253
JM		 49#if defined (TARGET_PPC64)
50#define ELF_MACHINE EM_PPC64
51#else
52#define ELF_MACHINE EM_PPC
53#endif
9042c0e2 54
fdabc366
FB		 55/* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC
56 * have different cache line sizes
57 */
58#define ICACHE_LINE_SIZE 32
59#define DCACHE_LINE_SIZE 32
60
61/* XXX: put this in a common place */
62#define likely(x) __builtin_expect(!!(x), 1)
76a66253 63#define unlikely(x) __builtin_expect(!!(x), 0)
fdabc366 64
3fc6c082
FB		 65/*****************************************************************************/
66/* PVR definitions for most known PowerPC */
67enum {
68 /* PowerPC 401 cores */
69 CPU_PPC_401A1 = 0x00210000,
70 CPU_PPC_401B2 = 0x00220000,
71 CPU_PPC_401C2 = 0x00230000,
72 CPU_PPC_401D2 = 0x00240000,
73 CPU_PPC_401E2 = 0x00250000,
74 CPU_PPC_401F2 = 0x00260000,
75 CPU_PPC_401G2 = 0x00270000,
76a66253
JM		 76#define CPU_PPC_401 CPU_PPC_401G2
77 CPU_PPC_IOP480 = 0x40100000, /* 401B2 ? */
78 CPU_PPC_COBRA = 0x10100000, /* IBM Processor for Network Resources */
3fc6c082 79 /* PowerPC 403 cores */
76a66253 80 CPU_PPC_403GA = 0x00200011,
3fc6c082
FB		 81 CPU_PPC_403GB = 0x00200100,
82 CPU_PPC_403GC = 0x00200200,
83 CPU_PPC_403GCX = 0x00201400,
76a66253 84#define CPU_PPC_403 CPU_PPC_403GCX
3fc6c082 85 /* PowerPC 405 cores */
76a66253
JM		 86 CPU_PPC_405CR = 0x40110145,
87#define CPU_PPC_405GP CPU_PPC_405CR
88 CPU_PPC_405EP = 0x51210950,
89 CPU_PPC_405GPR = 0x50910951,
3fc6c082
FB		 90 CPU_PPC_405D2 = 0x20010000,
91 CPU_PPC_405D4 = 0x41810000,
76a66253
JM		 92#define CPU_PPC_405 CPU_PPC_405D4
93 CPU_PPC_NPE405H = 0x414100C0,
94 CPU_PPC_NPE405H2 = 0x41410140,
95 CPU_PPC_NPE405L = 0x416100C0,
96 /* XXX: missing 405LP, LC77700 */
97 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
98#if 0
99 CPU_PPC_STB01000 = xxx,
100#endif
3fc6c082 101#if 0
76a66253
JM		 102 CPU_PPC_STB01010 = xxx,
103#endif
104#if 0
105 CPU_PPC_STB0210 = xxx,
3fc6c082
FB		 106#endif
107 CPU_PPC_STB03 = 0x40310000,
108#if 0
76a66253 109 CPU_PPC_STB043 = xxx,
3fc6c082 110#endif
76a66253
JM		 111#if 0
112 CPU_PPC_STB045 = xxx,
113#endif
114 CPU_PPC_STB25 = 0x51510950,
3fc6c082
FB		 115#if 0
116 CPU_PPC_STB130 = xxx,
117#endif
76a66253
JM		 118 /* Xilinx cores */
119 CPU_PPC_X2VP4 = 0x20010820,
120#define CPU_PPC_X2VP7 CPU_PPC_X2VP4
121 CPU_PPC_X2VP20 = 0x20010860,
122#define CPU_PPC_X2VP50 CPU_PPC_X2VP20
3fc6c082 123 /* PowerPC 440 cores */
76a66253
JM		 124 CPU_PPC_440EP = 0x422218D3,
125#define CPU_PPC_440GR CPU_PPC_440EP
126 CPU_PPC_440GP = 0x40120481,
127 CPU_PPC_440GX = 0x51B21850,
128 CPU_PPC_440GXc = 0x51B21892,
129 CPU_PPC_440GXf = 0x51B21894,
130 CPU_PPC_440SP = 0x53221850,
131 CPU_PPC_440SP2 = 0x53221891,
132 CPU_PPC_440SPE = 0x53421890,
133 /* XXX: missing 440GRX */
134 /* PowerPC 460 cores - TODO */
135 /* PowerPC MPC 5xx cores */
136 CPU_PPC_5xx = 0x00020020,
137 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
3fc6c082 138 CPU_PPC_8xx = 0x00500000,
76a66253
JM		 139 /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
140 CPU_PPC_82xx_HIP3 = 0x00810101,
141 CPU_PPC_82xx_HIP4 = 0x80811014,
142 CPU_PPC_827x = 0x80822013,
143 /* eCores */
144 CPU_PPC_e200 = 0x81120000,
145 CPU_PPC_e500v110 = 0x80200010,
146 CPU_PPC_e500v120 = 0x80200020,
147 CPU_PPC_e500v210 = 0x80210010,
148 CPU_PPC_e500v220 = 0x80210020,
149#define CPU_PPC_e500 CPU_PPC_e500v220
150 CPU_PPC_e600 = 0x80040010,
3fc6c082 151 /* PowerPC 6xx cores */
76a66253
JM		 152 CPU_PPC_601 = 0x00010001,
153 CPU_PPC_602 = 0x00050100,
154 CPU_PPC_603 = 0x00030100,
155 CPU_PPC_603E = 0x00060101,
156 CPU_PPC_603P = 0x00070000,
157 CPU_PPC_603E7v = 0x00070100,
158 CPU_PPC_603E7v2 = 0x00070201,
159 CPU_PPC_603E7 = 0x00070200,
160 CPU_PPC_603R = 0x00071201,
161 CPU_PPC_G2 = 0x00810011,
162 CPU_PPC_G2H4 = 0x80811010,
163 CPU_PPC_G2gp = 0x80821010,
164 CPU_PPC_G2ls = 0x90810010,
165 CPU_PPC_G2LE = 0x80820010,
166 CPU_PPC_G2LEgp = 0x80822010,
167 CPU_PPC_G2LEls = 0xA0822010,
3fc6c082 168 CPU_PPC_604 = 0x00040000,
76a66253
JM		 169 CPU_PPC_604E = 0x00090100, /* Also 2110 & 2120 */
170 CPU_PPC_604R = 0x000a0101,
3fc6c082
FB		 171 /* PowerPC 74x/75x cores (aka G3) */
172 CPU_PPC_74x = 0x00080000,
76a66253
JM		 173 CPU_PPC_740E = 0x00080100,
174 CPU_PPC_750E = 0x00080200,
175 CPU_PPC_755_10 = 0x00083100,
176 CPU_PPC_755_11 = 0x00083101,
177 CPU_PPC_755_20 = 0x00083200,
178 CPU_PPC_755D = 0x00083202,
179 CPU_PPC_755E = 0x00083203,
180#define CPU_PPC_755 CPU_PPC_755E
3fc6c082 181 CPU_PPC_74xP = 0x10080000,
76a66253
JM		 182 CPU_PPC_750CXE21 = 0x00082201,
183 CPU_PPC_750CXE22 = 0x00082212,
184 CPU_PPC_750CXE23 = 0x00082203,
3fc6c082
FB		 185 CPU_PPC_750CXE24 = 0x00082214,
186 CPU_PPC_750CXE24b = 0x00083214,
187 CPU_PPC_750CXE31 = 0x00083211,
188 CPU_PPC_750CXE31b = 0x00083311,
189#define CPU_PPC_750CXE CPU_PPC_750CXE31b
76a66253
JM		 190 CPU_PPC_750CXR = 0x00083410,
191 CPU_PPC_750FX10 = 0x70000100,
192 CPU_PPC_750FX20 = 0x70000200,
193 CPU_PPC_750FX21 = 0x70000201,
194 CPU_PPC_750FX22 = 0x70000202,
195 CPU_PPC_750FX23 = 0x70000203,
196#define CPU_PPC_750FX CPU_PPC_750FX23
197 CPU_PPC_750FL = 0x700A0203,
198 CPU_PPC_750GX10 = 0x70020100,
199 CPU_PPC_750GX11 = 0x70020101,
200 CPU_PPC_750GX12 = 0x70020102,
201#define CPU_PPC_750GX CPU_PPC_750GX12
202 CPU_PPC_750GL = 0x70020102,
203 CPU_PPC_750L30 = 0x00088300,
204 CPU_PPC_750L32 = 0x00088302,
205 CPU_PPC_750CL = 0x00087200,
3fc6c082 206 /* PowerPC 74xx cores (aka G4) */
76a66253
JM		 207 CPU_PPC_7400 = 0x000C0100,
208 CPU_PPC_7410C = 0x800C1102,
209 CPU_PPC_7410D = 0x800C1103,
210 CPU_PPC_7410E = 0x800C1104,
211 CPU_PPC_7441 = 0x80000210,
212 CPU_PPC_7445 = 0x80010100,
213 CPU_PPC_7447 = 0x80020100,
214 CPU_PPC_7447A = 0x80030101,
215 CPU_PPC_7448 = 0x80040100,
216 CPU_PPC_7450 = 0x80000200,
217 CPU_PPC_7450b = 0x80000201,
3fc6c082 218 CPU_PPC_7451 = 0x80000203,
76a66253
JM		 219 CPU_PPC_7451G = 0x80000210,
220 CPU_PPC_7455 = 0x80010201,
221 CPU_PPC_7455F = 0x80010303,
222 CPU_PPC_7455G = 0x80010304,
223 CPU_PPC_7457 = 0x80020101,
224 CPU_PPC_7457C = 0x80020102,
3fc6c082
FB		 225 CPU_PPC_7457A = 0x80030000,
226 /* 64 bits PowerPC */
227 CPU_PPC_620 = 0x00140000,
228 CPU_PPC_630 = 0x00400000,
229 CPU_PPC_631 = 0x00410000,
230 CPU_PPC_POWER4 = 0x00350000,
231 CPU_PPC_POWER4P = 0x00380000,
232 CPU_PPC_POWER5 = 0x003A0000,
233 CPU_PPC_POWER5P = 0x003B0000,
234 CPU_PPC_970 = 0x00390000,
76a66253
JM		 235 CPU_PPC_970FX10 = 0x00391100,
236 CPU_PPC_970FX20 = 0x003C0200,
237 CPU_PPC_970FX21 = 0x003C0201,
238 CPU_PPC_970FX30 = 0x003C0300,
239 CPU_PPC_970FX31 = 0x003C0301,
240#define CPU_PPC_970FX CPU_PPC_970FX31
241 CPU_PPC_970MP10 = 0x00440100,
242 CPU_PPC_970MP11 = 0x00440101,
243#define CPU_PPC_970MP CPU_PPC_970MP11
244 CPU_PPC_CELL10 = 0x00700100,
245 CPU_PPC_CELL20 = 0x00700400,
246 CPU_PPC_CELL30 = 0x00700500,
247 CPU_PPC_CELL31 = 0x00700501,
248#define CPU_PPC_CELL32 CPU_PPC_CELL31
249#define CPU_PPC_CELL CPU_PPC_CELL32
3fc6c082
FB		 250 CPU_PPC_RS64 = 0x00330000,
251 CPU_PPC_RS64II = 0x00340000,
252 CPU_PPC_RS64III = 0x00360000,
253 CPU_PPC_RS64IV = 0x00370000,
254 /* Original POWER */
255 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
256 * POWER2 (RIOS2) & RSC2 (P2SC) here
257 */
258#if 0
259 CPU_POWER = xxx,
260#endif
261#if 0
262 CPU_POWER2 = xxx,
263#endif
264};
265
76a66253 266/* System version register (used on MPC 8xxx) */
3fc6c082
FB		 267enum {
268 PPC_SVR_8540 = 0x80300000,
76a66253
JM		 269 PPC_SVR_8541E = 0x807A0010,
270 PPC_SVR_8543v10 = 0x80320010,
271 PPC_SVR_8543v11 = 0x80320011,
272 PPC_SVR_8543v20 = 0x80320020,
273 PPC_SVR_8543Ev10 = 0x803A0010,
274 PPC_SVR_8543Ev11 = 0x803A0011,
275 PPC_SVR_8543Ev20 = 0x803A0020,
276 PPC_SVR_8545 = 0x80310220,
277 PPC_SVR_8545E = 0x80390220,
278 PPC_SVR_8547E = 0x80390120,
279 PPC_SCR_8548v10 = 0x80310010,
280 PPC_SCR_8548v11 = 0x80310011,
281 PPC_SCR_8548v20 = 0x80310020,
282 PPC_SVR_8548Ev10 = 0x80390010,
283 PPC_SVR_8548Ev11 = 0x80390011,
284 PPC_SVR_8548Ev20 = 0x80390020,
285 PPC_SVR_8555E = 0x80790010,
286 PPC_SVR_8560v10 = 0x80700010,
287 PPC_SVR_8560v20 = 0x80700020,
3fc6c082
FB		 288};
289
290/*****************************************************************************/
9a64fbe4
FB		 291/* Instruction types */
292enum {
3fc6c082
FB		 293 PPC_NONE = 0x00000000,
294 /* integer operations instructions */
295 /* flow control instructions */
296 /* virtual memory instructions */
297 /* ld/st with reservation instructions */
298 /* cache control instructions */
299 /* spr/msr access instructions */
300 PPC_INSNS_BASE = 0x00000001,
301#define PPC_INTEGER PPC_INSNS_BASE
302#define PPC_FLOW PPC_INSNS_BASE
303#define PPC_MEM PPC_INSNS_BASE
304#define PPC_RES PPC_INSNS_BASE
305#define PPC_CACHE PPC_INSNS_BASE
306#define PPC_MISC PPC_INSNS_BASE
307 /* floating point operations instructions */
308 PPC_FLOAT = 0x00000002,
309 /* more floating point operations instructions */
310 PPC_FLOAT_EXT = 0x00000004,
311 /* external control instructions */
312 PPC_EXTERN = 0x00000008,
313 /* segment register access instructions */
314 PPC_SEGMENT = 0x00000010,
315 /* Optional cache control instructions */
316 PPC_CACHE_OPT = 0x00000020,
317 /* Optional floating point op instructions */
318 PPC_FLOAT_OPT = 0x00000040,
319 /* Optional memory control instructions */
320 PPC_MEM_TLBIA = 0x00000080,
321 PPC_MEM_TLBIE = 0x00000100,
322 PPC_MEM_TLBSYNC = 0x00000200,
323 /* eieio & sync */
324 PPC_MEM_SYNC = 0x00000400,
325 /* PowerPC 6xx TLB management instructions */
326 PPC_6xx_TLB = 0x00000800,
327 /* Altivec support */
328 PPC_ALTIVEC = 0x00001000,
329 /* Time base support */
330 PPC_TB = 0x00002000,
331 /* Embedded PowerPC dedicated instructions */
76a66253 332 PPC_EMB_COMMON = 0x00004000,
3fc6c082
FB		 333 /* PowerPC 40x exception model */
334 PPC_40x_EXCP = 0x00008000,
335 /* PowerPC 40x specific instructions */
336 PPC_40x_SPEC = 0x00010000,
337 /* PowerPC 405 Mac instructions */
338 PPC_405_MAC = 0x00020000,
339 /* PowerPC 440 specific instructions */
340 PPC_440_SPEC = 0x00040000,
341 /* Specific extensions */
342 /* Power-to-PowerPC bridge (601) */
343 PPC_POWER_BR = 0x00080000,
344 /* PowerPC 602 specific */
345 PPC_602_SPEC = 0x00100000,
346 /* Deprecated instructions */
347 /* Original POWER instruction set */
348 PPC_POWER = 0x00200000,
349 /* POWER2 instruction set extension */
350 PPC_POWER2 = 0x00400000,
351 /* Power RTC support */
352 PPC_POWER_RTC = 0x00800000,
353 /* 64 bits PowerPC instructions */
354 /* 64 bits PowerPC instruction set */
355 PPC_64B = 0x01000000,
356 /* 64 bits hypervisor extensions */
357 PPC_64H = 0x02000000,
358 /* 64 bits PowerPC "bridge" features */
359 PPC_64_BRIDGE = 0x04000000,
76a66253
JM		 360 /* BookE (embedded) PowerPC specification */
361 PPC_BOOKE = 0x08000000,
362 /* eieio */
363 PPC_MEM_EIEIO = 0x10000000,
364 /* e500 vector instructions */
365 PPC_E500_VECTOR = 0x20000000,
366 /* PowerPC 4xx dedicated instructions */
367 PPC_4xx_COMMON = 0x40000000,
9a64fbe4 368};
79aceca5 369
3fc6c082
FB		 370/* CPU run-time flags (MMU and exception model) */
371enum {
372 /* MMU model */
76a66253 373 PPC_FLAGS_MMU_MASK = 0x0000000F,
3fc6c082
FB		 374 /* Standard 32 bits PowerPC MMU */
375 PPC_FLAGS_MMU_32B = 0x00000000,
376 /* Standard 64 bits PowerPC MMU */
377 PPC_FLAGS_MMU_64B = 0x00000001,
378 /* PowerPC 601 MMU */
379 PPC_FLAGS_MMU_601 = 0x00000002,
380 /* PowerPC 6xx MMU with software TLB */
381 PPC_FLAGS_MMU_SOFT_6xx = 0x00000003,
382 /* PowerPC 4xx MMU with software TLB */
383 PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,
384 /* PowerPC 403 MMU */
385 PPC_FLAGS_MMU_403 = 0x00000005,
76a66253
JM		 386 /* Freescale e500 MMU model */
387 PPC_FLAGS_MMU_e500 = 0x00000006,
3fc6c082 388 /* Exception model */
76a66253 389 PPC_FLAGS_EXCP_MASK = 0x000000F0,
3fc6c082
FB		 390 /* Standard PowerPC exception model */
391 PPC_FLAGS_EXCP_STD = 0x00000000,
392 /* PowerPC 40x exception model */
393 PPC_FLAGS_EXCP_40x = 0x00000010,
394 /* PowerPC 601 exception model */
395 PPC_FLAGS_EXCP_601 = 0x00000020,
396 /* PowerPC 602 exception model */
397 PPC_FLAGS_EXCP_602 = 0x00000030,
398 /* PowerPC 603 exception model */
399 PPC_FLAGS_EXCP_603 = 0x00000040,
400 /* PowerPC 604 exception model */
401 PPC_FLAGS_EXCP_604 = 0x00000050,
402 /* PowerPC 7x0 exception model */
403 PPC_FLAGS_EXCP_7x0 = 0x00000060,
404 /* PowerPC 7x5 exception model */
405 PPC_FLAGS_EXCP_7x5 = 0x00000070,
406 /* PowerPC 74xx exception model */
407 PPC_FLAGS_EXCP_74xx = 0x00000080,
408 /* PowerPC 970 exception model */
409 PPC_FLAGS_EXCP_970 = 0x00000090,
410};
411
412#define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK)
413#define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK)
414
415/*****************************************************************************/
416/* Supported instruction set definitions */
417/* This generates an empty opcode table... */
418#define PPC_INSNS_TODO (PPC_NONE)
419#define PPC_FLAGS_TODO (0x00000000)
420
421/* PowerPC 40x instruction set */
76a66253 422#define PPC_INSNS_EMB (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_EMB_COMMON)
3fc6c082
FB		 423/* PowerPC 401 */
424#define PPC_INSNS_401 (PPC_INSNS_TODO)
425#define PPC_FLAGS_401 (PPC_FLAGS_TODO)
426/* PowerPC 403 */
76a66253
JM		 427#define PPC_INSNS_403 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
428 PPC_MEM_TLBIA | PPC_4xx_COMMON | PPC_40x_EXCP | \
429 PPC_40x_SPEC)
3fc6c082
FB		 430#define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x)
431/* PowerPC 405 */
76a66253
JM		 432#define PPC_INSNS_405 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
433 PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_TB | \
434 PPC_4xx_COMMON | PPC_40x_SPEC | PPC_40x_EXCP | \
3fc6c082
FB		 435 PPC_405_MAC)
436#define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
437/* PowerPC 440 */
76a66253
JM		 438#define PPC_INSNS_440 (PPC_INSNS_EMB | PPC_CACHE_OPT | PPC_BOOKE | \
439 PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
3fc6c082 440#define PPC_FLAGS_440 (PPC_FLAGS_TODO)
76a66253
JM		 441/* Generic BookE PowerPC */
442#define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \
443 PPC_FLOAT | PPC_FLOAT_OPT | PPC_CACHE_OPT)
444#define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
445/* e500 core */
446#define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \
447 PPC_CACHE_OPT | PPC_E500_VECTOR)
448#define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
3fc6c082
FB		 449/* Non-embedded PowerPC */
450#define PPC_INSNS_COMMON (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
76a66253 451 PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
3fc6c082
FB		 452/* PowerPC 601 */
453#define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)
454#define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601)
455/* PowerPC 602 */
456#define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
76a66253 457 PPC_MEM_TLBSYNC | PPC_TB | PPC_602_SPEC)
3fc6c082
FB		 458#define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602)
459/* PowerPC 603 */
460#define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
461 PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
462#define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
463/* PowerPC G2 */
464#define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
465 PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
466#define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
467/* PowerPC 604 */
468#define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
469 PPC_MEM_TLBSYNC | PPC_TB)
470#define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604)
471/* PowerPC 740/750 (aka G3) */
472#define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
473 PPC_MEM_TLBSYNC | PPC_TB)
474#define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0)
475/* PowerPC 745/755 */
476#define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
477 PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB)
478#define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5)
479/* PowerPC 74xx (aka G4) */
480#define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC | \
481 PPC_MEM_TLBSYNC | PPC_TB)
482#define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx)
483
484/* Default PowerPC will be 604/970 */
485#define PPC_INSNS_PPC32 PPC_INSNS_604
486#define PPC_FLAGS_PPC32 PPC_FLAGS_604
487#if 0
488#define PPC_INSNS_PPC64 PPC_INSNS_970
489#define PPC_FLAGS_PPC64 PPC_FLAGS_970
490#endif
491#define PPC_INSNS_DEFAULT PPC_INSNS_604
492#define PPC_FLAGS_DEFAULT PPC_FLAGS_604
493typedef struct ppc_def_t ppc_def_t;
79aceca5 494
3fc6c082
FB		 495/*****************************************************************************/
496/* Types used to describe some PowerPC registers */
497typedef struct CPUPPCState CPUPPCState;
498typedef struct opc_handler_t opc_handler_t;
9fddaa0c 499typedef struct ppc_tb_t ppc_tb_t;
3fc6c082
FB		 500typedef struct ppc_spr_t ppc_spr_t;
501typedef struct ppc_dcr_t ppc_dcr_t;
502typedef struct ppc_avr_t ppc_avr_t;
76a66253
JM		 503typedef struct ppc_tlb_t ppc_tlb_t;
504
3fc6c082
FB		 505
506/* SPR access micro-ops generations callbacks */
507struct ppc_spr_t {
508 void (*uea_read)(void *opaque, int spr_num);
509 void (*uea_write)(void *opaque, int spr_num);
76a66253 510#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 511 void (*oea_read)(void *opaque, int spr_num);
512 void (*oea_write)(void *opaque, int spr_num);
76a66253 513#endif
3fc6c082
FB		 514 const unsigned char *name;
515};
516
517/* Altivec registers (128 bits) */
518struct ppc_avr_t {
519 uint32_t u[4];
520};
9fddaa0c 521
3fc6c082 522/* Software TLB cache */
3fc6c082 523struct ppc_tlb_t {
76a66253
JM		 524 target_ulong pte0;
525 target_ulong pte1;
526 target_ulong EPN;
527 target_ulong PID;
528 int size;
3fc6c082
FB		 529};
530
531/*****************************************************************************/
532/* Machine state register bits definition */
76a66253 533#define MSR_SF 63 /* Sixty-four-bit mode hflags */
3fc6c082 534#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
76a66253
JM		 535#define MSR_HV 60 /* hypervisor state hflags */
536#define MSR_UCLE 26 /* User-mode cache lock enable on e500 */
537#define MSR_VR 25 /* altivec available hflags */
538#define MSR_SPE 25 /* SPE enable on e500 hflags */
539#define MSR_AP 23 /* Access privilege state on 602 hflags */
540#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
3fc6c082
FB		 541#define MSR_KEY 19 /* key bit on 603e */
542#define MSR_POW 18 /* Power management */
543#define MSR_WE 18 /* Wait state enable on embedded PowerPC */
544#define MSR_TGPR 17 /* TGPR usage on 602/603 */
76a66253 545#define MSR_TLB 17 /* TLB update on ? */
3fc6c082
FB		 546#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC */
547#define MSR_ILE 16 /* Interrupt little-endian mode */
548#define MSR_EE 15 /* External interrupt enable */
76a66253
JM		 549#define MSR_PR 14 /* Problem state hflags */
550#define MSR_FP 13 /* Floating point available hflags */
3fc6c082 551#define MSR_ME 12 /* Machine check interrupt enable */
76a66253
JM		 552#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
553#define MSR_SE 10 /* Single-step trace enable hflags */
3fc6c082 554#define MSR_DWE 10 /* Debug wait enable on 405 */
76a66253
JM		 555#define MSR_UBLE 10 /* User BTB lock enable on e500 */
556#define MSR_BE 9 /* Branch trace enable hflags */
3fc6c082 557#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC */
76a66253 558#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
3fc6c082
FB		 559#define MSR_AL 7 /* AL bit on POWER */
560#define MSR_IP 6 /* Interrupt prefix */
561#define MSR_IR 5 /* Instruction relocate */
562#define MSR_IS 5 /* Instruction address space on embedded PowerPC */
563#define MSR_DR 4 /* Data relocate */
564#define MSR_DS 4 /* Data address space on embedded PowerPC */
565#define MSR_PE 3 /* Protection enable on 403 */
566#define MSR_EP 3 /* Exception prefix on 601 */
567#define MSR_PX 2 /* Protection exclusive on 403 */
568#define MSR_PMM 2 /* Performance monitor mark on POWER */
569#define MSR_RI 1 /* Recoverable interrupt */
76a66253 570#define MSR_LE 0 /* Little-endian mode hflags */
3fc6c082
FB		 571#define msr_sf env->msr[MSR_SF]
572#define msr_isf env->msr[MSR_ISF]
573#define msr_hv env->msr[MSR_HV]
76a66253 574#define msr_ucle env->msr[MSR_UCLE]
3fc6c082 575#define msr_vr env->msr[MSR_VR]
76a66253 576#define msr_spe env->msr[MSR_SPE]
3fc6c082
FB		 577#define msr_ap env->msr[MSR_AP]
578#define msr_sa env->msr[MSR_SA]
579#define msr_key env->msr[MSR_KEY]
76a66253 580#define msr_pow env->msr[MSR_POW]
3fc6c082
FB		 581#define msr_we env->msr[MSR_WE]
582#define msr_tgpr env->msr[MSR_TGPR]
583#define msr_tlb env->msr[MSR_TLB]
584#define msr_ce env->msr[MSR_CE]
76a66253
JM		 585#define msr_ile env->msr[MSR_ILE]
586#define msr_ee env->msr[MSR_EE]
587#define msr_pr env->msr[MSR_PR]
588#define msr_fp env->msr[MSR_FP]
589#define msr_me env->msr[MSR_ME]
590#define msr_fe0 env->msr[MSR_FE0]
591#define msr_se env->msr[MSR_SE]
3fc6c082 592#define msr_dwe env->msr[MSR_DWE]
76a66253
JM		 593#define msr_uble env->msr[MSR_UBLE]
594#define msr_be env->msr[MSR_BE]
3fc6c082 595#define msr_de env->msr[MSR_DE]
76a66253 596#define msr_fe1 env->msr[MSR_FE1]
3fc6c082 597#define msr_al env->msr[MSR_AL]
76a66253
JM		 598#define msr_ip env->msr[MSR_IP]
599#define msr_ir env->msr[MSR_IR]
3fc6c082 600#define msr_is env->msr[MSR_IS]
76a66253 601#define msr_dr env->msr[MSR_DR]
3fc6c082
FB		 602#define msr_ds env->msr[MSR_DS]
603#define msr_pe env->msr[MSR_PE]
604#define msr_ep env->msr[MSR_EP]
605#define msr_px env->msr[MSR_PX]
606#define msr_pmm env->msr[MSR_PMM]
76a66253
JM		 607#define msr_ri env->msr[MSR_RI]
608#define msr_le env->msr[MSR_LE]
79aceca5 609
3fc6c082
FB		 610/*****************************************************************************/
611/* The whole PowerPC CPU context */
612struct CPUPPCState {
613 /* First are the most commonly used resources
614 * during translated code execution
615 */
616#if TARGET_LONG_BITS > HOST_LONG_BITS
617 /* temporary fixed-point registers
618 * used to emulate 64 bits target on 32 bits hosts
619 */
620 target_ulong t0, t1, t2;
621#endif
79aceca5 622 /* general purpose registers */
76a66253 623 ppc_gpr_t gpr[32];
3fc6c082
FB		 624 /* LR */
625 target_ulong lr;
626 /* CTR */
627 target_ulong ctr;
628 /* condition register */
629 uint8_t crf[8];
79aceca5 630 /* XER */
3fc6c082
FB		 631 /* XXX: We use only 5 fields, but we want to keep the structure aligned */
632 uint8_t xer[8];
79aceca5 633 /* Reservation address */
3fc6c082
FB		 634 target_ulong reserve;
635
636 /* Those ones are used in supervisor mode only */
79aceca5 637 /* machine state register */
3fc6c082
FB		 638 uint8_t msr[64];
639 /* temporary general purpose registers */
76a66253 640 ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
3fc6c082
FB		 641
642 /* Floating point execution context */
76a66253 643 /* temporary float registers */
4ecc3190
FB		 644 float64 ft0;
645 float64 ft1;
646 float64 ft2;
647 float_status fp_status;
3fc6c082
FB		 648 /* floating point registers */
649 float64 fpr[32];
650 /* floating point status and control register */
651 uint8_t fpscr[8];
4ecc3190 652
a316d335
FB		 653 CPU_COMMON
654
50443c98
FB		 655 int halted; /* TRUE if the CPU is in suspend state */
656
ac9eb073
FB		 657 int access_type; /* when a memory exception occurs, the access
658 type is stored here */
a541f297 659
3fc6c082
FB		 660 /* MMU context */
661 /* Address space register */
662 target_ulong asr;
663 /* segment registers */
664 target_ulong sdr1;
665 target_ulong sr[16];
666 /* BATs */
667 int nb_BATs;
668 target_ulong DBAT[2][8];
669 target_ulong IBAT[2][8];
9fddaa0c 670
3fc6c082
FB		 671 /* Other registers */
672 /* Special purpose registers */
673 target_ulong spr[1024];
674 /* Altivec registers */
675 ppc_avr_t avr[32];
676 uint32_t vscr;
677
678 /* Internal devices resources */
9fddaa0c
FB		 679 /* Time base and decrementer */
680 ppc_tb_t *tb_env;
3fc6c082
FB		 681 /* Device control registers */
682 int (*dcr_read)(ppc_dcr_t *dcr_env, int dcr_num, target_ulong *val);
683 int (*dcr_write)(ppc_dcr_t *dcr_env, int dcr_num, target_ulong val);
684 ppc_dcr_t *dcr_env;
685
686 /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
76a66253
JM		 687 int nb_tlb; /* Total number of TLB */
688 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
689 int nb_ways; /* Number of ways in the TLB set */
690 int last_way; /* Last used way used to allocate TLB in a LRU way */
691 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
692 ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
3fc6c082
FB		 693 /* Callbacks for specific checks on some implementations */
694 int (*tlb_check_more)(CPUPPCState *env, struct ppc_tlb_t *tlb, int *prot,
695 target_ulong vaddr, int rw, int acc_type,
696 int is_user);
697 /* 403 dedicated access protection registers */
698 target_ulong pb[4];
699
700 /* Those resources are used during exception processing */
701 /* CPU model definition */
702 uint64_t msr_mask;
703 uint32_t flags;
704
705 int exception_index;
706 int error_code;
707 int interrupt_request;
708
709 /* Those resources are used only during code translation */
710 /* Next instruction pointer */
711 target_ulong nip;
712 /* SPR translation callbacks */
713 ppc_spr_t spr_cb[1024];
714 /* opcode handlers */
715 opc_handler_t *opcodes[0x40];
716
717 /* Those resources are used only in Qemu core */
718 jmp_buf jmp_env;
719 int user_mode_only; /* user mode only simulation */
3fc6c082
FB		 720 uint32_t hflags;
721
9fddaa0c
FB		 722 /* Power management */
723 int power_mode;
a541f297 724
6d506e6d
FB		 725 /* temporary hack to handle OSI calls (only used if non NULL) */
726 int (*osi_call)(struct CPUPPCState *env);
3fc6c082 727};
79aceca5 728
76a66253
JM		 729/* Context used internally during MMU translations */
730typedef struct mmu_ctx_t mmu_ctx_t;
731struct mmu_ctx_t {
732 target_phys_addr_t raddr; /* Real address */
733 int prot; /* Protection bits */
734 target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
735 target_ulong ptem; /* Virtual segment ID | API */
736 int key; /* Access key */
737};
738
3fc6c082 739/*****************************************************************************/
79aceca5
FB		 740CPUPPCState *cpu_ppc_init(void);
741int cpu_ppc_exec(CPUPPCState *s);
742void cpu_ppc_close(CPUPPCState *s);
743/* you can call this signal handler from your SIGBUS and SIGSEGV
744 signal handlers to inform the virtual CPU of exceptions. non zero
745 is returned if the signal was handled by the virtual CPU. */
5a7b542b 746int cpu_ppc_signal_handler(int host_signum, void *pinfo,
79aceca5
FB		 747 void *puc);
748
a541f297 749void do_interrupt (CPUPPCState *env);
9a64fbe4 750void cpu_loop_exit(void);
a541f297 751
9a64fbe4 752void dump_stack (CPUPPCState *env);
a541f297 753
76a66253 754#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 755target_ulong do_load_ibatu (CPUPPCState *env, int nr);
756target_ulong do_load_ibatl (CPUPPCState *env, int nr);
757void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
758void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
759target_ulong do_load_dbatu (CPUPPCState *env, int nr);
760target_ulong do_load_dbatl (CPUPPCState *env, int nr);
761void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
762void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
3fc6c082
FB		 763target_ulong do_load_sdr1 (CPUPPCState *env);
764void do_store_sdr1 (CPUPPCState *env, target_ulong value);
765target_ulong do_load_asr (CPUPPCState *env);
766void do_store_asr (CPUPPCState *env, target_ulong value);
767target_ulong do_load_sr (CPUPPCState *env, int srnum);
768void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
76a66253
JM		 769#endif
770uint32_t ppc_load_xer (CPUPPCState *env);
771void ppc_store_xer (CPUPPCState *env, uint32_t value);
3fc6c082
FB		 772target_ulong do_load_msr (CPUPPCState *env);
773void do_store_msr (CPUPPCState *env, target_ulong value);
3fc6c082
FB		 774
775void do_compute_hflags (CPUPPCState *env);
a541f297 776
3fc6c082
FB		 777int ppc_find_by_name (const unsigned char *name, ppc_def_t **def);
778int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
779void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
780int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);
85c4adf6 781
9fddaa0c
FB		 782/* Time-base and decrementer management */
783#ifndef NO_CPU_IO_DEFS
784uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
785uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
786void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
787void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
788uint32_t cpu_ppc_load_decr (CPUPPCState *env);
789void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
790#endif
79aceca5
FB		 791
792#define TARGET_PAGE_BITS 12
793#include "cpu-all.h"
794
3fc6c082
FB		 795/*****************************************************************************/
796/* Registers definitions */
79aceca5 797#define ugpr(n) (env->gpr[n])
79aceca5 798
79aceca5
FB		 799#define XER_SO 31
800#define XER_OV 30
801#define XER_CA 29
3fc6c082 802#define XER_CMP 8
79aceca5 803#define XER_BC 0
3fc6c082
FB		 804#define xer_so env->xer[4]
805#define xer_ov env->xer[6]
806#define xer_ca env->xer[2]
807#define xer_cmp env->xer[1]
9a64fbe4 808#define xer_bc env->xer[0]
79aceca5 809
3fc6c082 810/* SPR definitions */
76a66253
JM		 811#define SPR_MQ (0x000)
812#define SPR_XER (0x001)
813#define SPR_601_VRTCU (0x004)
814#define SPR_601_VRTCL (0x005)
815#define SPR_601_UDECR (0x006)
816#define SPR_LR (0x008)
817#define SPR_CTR (0x009)
818#define SPR_DSISR (0x012)
819#define SPR_DAR (0x013)
820#define SPR_601_RTCU (0x014)
821#define SPR_601_RTCL (0x015)
822#define SPR_DECR (0x016)
823#define SPR_SDR1 (0x019)
824#define SPR_SRR0 (0x01A)
825#define SPR_SRR1 (0x01B)
826#define SPR_BOOKE_PID (0x030)
827#define SPR_BOOKE_DECAR (0x036)
828#define SPR_CSRR0 (0x03A)
829#define SPR_CSRR1 (0x03B)
830#define SPR_BOOKE_DEAR (0x03D)
831#define SPR_BOOKE_ESR (0x03E)
832#define SPR_BOOKE_EVPR (0x03F)
833#define SPR_8xx_EIE (0x050)
834#define SPR_8xx_EID (0x051)
835#define SPR_8xx_NRE (0x052)
836#define SPR_58x_CMPA (0x090)
837#define SPR_58x_CMPB (0x091)
838#define SPR_58x_CMPC (0x092)
839#define SPR_58x_CMPD (0x093)
840#define SPR_58x_ICR (0x094)
841#define SPR_58x_DER (0x094)
842#define SPR_58x_COUNTA (0x096)
843#define SPR_58x_COUNTB (0x097)
844#define SPR_58x_CMPE (0x098)
845#define SPR_58x_CMPF (0x099)
846#define SPR_58x_CMPG (0x09A)
847#define SPR_58x_CMPH (0x09B)
848#define SPR_58x_LCTRL1 (0x09C)
849#define SPR_58x_LCTRL2 (0x09D)
850#define SPR_58x_ICTRL (0x09E)
851#define SPR_58x_BAR (0x09F)
852#define SPR_VRSAVE (0x100)
853#define SPR_USPRG0 (0x100)
854#define SPR_USPRG4 (0x104)
855#define SPR_USPRG5 (0x105)
856#define SPR_USPRG6 (0x106)
857#define SPR_USPRG7 (0x107)
858#define SPR_VTBL (0x10C)
859#define SPR_VTBU (0x10D)
860#define SPR_SPRG0 (0x110)
861#define SPR_SPRG1 (0x111)
862#define SPR_SPRG2 (0x112)
863#define SPR_SPRG3 (0x113)
864#define SPR_SPRG4 (0x114)
865#define SPR_SCOMC (0x114)
866#define SPR_SPRG5 (0x115)
867#define SPR_SCOMD (0x115)
868#define SPR_SPRG6 (0x116)
869#define SPR_SPRG7 (0x117)
870#define SPR_ASR (0x118)
871#define SPR_EAR (0x11A)
872#define SPR_TBL (0x11C)
873#define SPR_TBU (0x11D)
874#define SPR_SVR (0x11E)
875#define SPR_BOOKE_PIR (0x11E)
876#define SPR_PVR (0x11F)
877#define SPR_HSPRG0 (0x130)
878#define SPR_BOOKE_DBSR (0x130)
879#define SPR_HSPRG1 (0x131)
880#define SPR_BOOKE_DBCR0 (0x134)
881#define SPR_IBCR (0x135)
882#define SPR_BOOKE_DBCR1 (0x135)
883#define SPR_DBCR (0x136)
884#define SPR_HDEC (0x136)
885#define SPR_BOOKE_DBCR2 (0x136)
886#define SPR_HIOR (0x137)
887#define SPR_MBAR (0x137)
888#define SPR_RMOR (0x138)
889#define SPR_BOOKE_IAC1 (0x138)
890#define SPR_HRMOR (0x139)
891#define SPR_BOOKE_IAC2 (0x139)
892#define SPR_HSSR0 (0x13A)
893#define SPR_BOOKE_IAC3 (0x13A)
894#define SPR_HSSR1 (0x13B)
895#define SPR_BOOKE_IAC4 (0x13B)
896#define SPR_LPCR (0x13C)
897#define SPR_BOOKE_DAC1 (0x13C)
898#define SPR_LPIDR (0x13D)
899#define SPR_DABR2 (0x13D)
900#define SPR_BOOKE_DAC2 (0x13D)
901#define SPR_BOOKE_DVC1 (0x13E)
902#define SPR_BOOKE_DVC2 (0x13F)
903#define SPR_BOOKE_TSR (0x150)
904#define SPR_BOOKE_TCR (0x154)
905#define SPR_BOOKE_IVOR0 (0x190)
906#define SPR_BOOKE_IVOR1 (0x191)
907#define SPR_BOOKE_IVOR2 (0x192)
908#define SPR_BOOKE_IVOR3 (0x193)
909#define SPR_BOOKE_IVOR4 (0x194)
910#define SPR_BOOKE_IVOR5 (0x195)
911#define SPR_BOOKE_IVOR6 (0x196)
912#define SPR_BOOKE_IVOR7 (0x197)
913#define SPR_BOOKE_IVOR8 (0x198)
914#define SPR_BOOKE_IVOR9 (0x199)
915#define SPR_BOOKE_IVOR10 (0x19A)
916#define SPR_BOOKE_IVOR11 (0x19B)
917#define SPR_BOOKE_IVOR12 (0x19C)
918#define SPR_BOOKE_IVOR13 (0x19D)
919#define SPR_BOOKE_IVOR14 (0x19E)
920#define SPR_BOOKE_IVOR15 (0x19F)
921#define SPR_E500_SPEFSCR (0x200)
922#define SPR_E500_BBEAR (0x201)
923#define SPR_E500_BBTAR (0x202)
924#define SPR_BOOKE_ATBL (0x20E)
925#define SPR_BOOKE_ATBU (0x20F)
926#define SPR_IBAT0U (0x210)
927#define SPR_E500_IVOR32 (0x210)
928#define SPR_IBAT0L (0x211)
929#define SPR_E500_IVOR33 (0x211)
930#define SPR_IBAT1U (0x212)
931#define SPR_E500_IVOR34 (0x212)
932#define SPR_IBAT1L (0x213)
933#define SPR_E500_IVOR35 (0x213)
934#define SPR_IBAT2U (0x214)
935#define SPR_IBAT2L (0x215)
936#define SPR_E500_L1CFG0 (0x215)
937#define SPR_IBAT3U (0x216)
938#define SPR_E500_L1CFG1 (0x216)
939#define SPR_IBAT3L (0x217)
940#define SPR_DBAT0U (0x218)
941#define SPR_DBAT0L (0x219)
942#define SPR_DBAT1U (0x21A)
943#define SPR_DBAT1L (0x21B)
944#define SPR_DBAT2U (0x21C)
945#define SPR_DBAT2L (0x21D)
946#define SPR_DBAT3U (0x21E)
947#define SPR_DBAT3L (0x21F)
948#define SPR_IBAT4U (0x230)
949#define SPR_IBAT4L (0x231)
950#define SPR_IBAT5U (0x232)
951#define SPR_IBAT5L (0x233)
952#define SPR_IBAT6U (0x234)
953#define SPR_IBAT6L (0x235)
954#define SPR_IBAT7U (0x236)
955#define SPR_IBAT7L (0x237)
956#define SPR_DBAT4U (0x238)
957#define SPR_DBAT4L (0x239)
958#define SPR_DBAT5U (0x23A)
959#define SPR_E500_MCSRR0 (0x23A)
960#define SPR_DBAT5L (0x23B)
961#define SPR_E500_MCSRR1 (0x23B)
962#define SPR_DBAT6U (0x23C)
963#define SPR_E500_MCSR (0x23C)
964#define SPR_DBAT6L (0x23D)
965#define SPR_E500_MCAR (0x23D)
966#define SPR_DBAT7U (0x23E)
967#define SPR_DBAT7L (0x23F)
968#define SPR_E500_MAS0 (0x270)
969#define SPR_E500_MAS1 (0x271)
970#define SPR_E500_MAS2 (0x272)
971#define SPR_E500_MAS3 (0x273)
972#define SPR_E500_MAS4 (0x274)
973#define SPR_E500_MAS6 (0x276)
974#define SPR_E500_PID1 (0x279)
975#define SPR_E500_PID2 (0x27A)
976#define SPR_E500_TLB0CFG (0x2B0)
977#define SPR_E500_TLB1CFG (0x2B1)
978#define SPR_440_INV0 (0x370)
979#define SPR_440_INV1 (0x371)
980#define SPR_440_INV2 (0x372)
981#define SPR_440_INV3 (0x373)
982#define SPR_440_IVT0 (0x374)
983#define SPR_440_IVT1 (0x375)
984#define SPR_440_IVT2 (0x376)
985#define SPR_440_IVT3 (0x377)
986#define SPR_440_DNV0 (0x390)
987#define SPR_440_DNV1 (0x391)
988#define SPR_440_DNV2 (0x392)
989#define SPR_440_DNV3 (0x393)
990#define SPR_440_DVT0 (0x394)
991#define SPR_440_DVT1 (0x395)
992#define SPR_440_DVT2 (0x396)
993#define SPR_440_DVT3 (0x397)
994#define SPR_440_DVLIM (0x398)
995#define SPR_440_IVLIM (0x399)
996#define SPR_440_RSTCFG (0x39B)
997#define SPR_440_DCBTRL (0x39C)
998#define SPR_440_DCBTRH (0x39D)
999#define SPR_440_ICBTRL (0x39E)
1000#define SPR_440_ICBTRH (0x39F)
1001#define SPR_UMMCR0 (0x3A8)
1002#define SPR_UPMC1 (0x3A9)
1003#define SPR_UPMC2 (0x3AA)
1004#define SPR_USIA (0x3AB)
1005#define SPR_UMMCR1 (0x3AC)
1006#define SPR_UPMC3 (0x3AD)
1007#define SPR_UPMC4 (0x3AE)
1008#define SPR_USDA (0x3AF)
1009#define SPR_40x_ZPR (0x3B0)
1010#define SPR_E500_MAS7 (0x3B0)
1011#define SPR_40x_PID (0x3B1)
1012#define SPR_440_MMUCR (0x3B2)
1013#define SPR_4xx_CCR0 (0x3B3)
1014#define SPR_405_IAC3 (0x3B4)
1015#define SPR_405_IAC4 (0x3B5)
1016#define SPR_405_DVC1 (0x3B6)
1017#define SPR_405_DVC2 (0x3B7)
1018#define SPR_MMCR0 (0x3B8)
1019#define SPR_PMC1 (0x3B9)
1020#define SPR_40x_SGR (0x3B9)
1021#define SPR_PMC2 (0x3BA)
1022#define SPR_40x_DCWR (0x3BA)
1023#define SPR_SIA (0x3BB)
1024#define SPR_405_SLER (0x3BB)
1025#define SPR_MMCR1 (0x3BC)
1026#define SPR_405_SU0R (0x3BC)
1027#define SPR_PMC3 (0x3BD)
1028#define SPR_405_DBCR1 (0x3BD)
1029#define SPR_PMC4 (0x3BE)
1030#define SPR_SDA (0x3BF)
1031#define SPR_403_VTBL (0x3CC)
1032#define SPR_403_VTBU (0x3CD)
1033#define SPR_DMISS (0x3D0)
1034#define SPR_DCMP (0x3D1)
1035#define SPR_HASH1 (0x3D2)
1036#define SPR_HASH2 (0x3D3)
1037#define SPR_4xx_ICDBDR (0x3D3)
1038#define SPR_IMISS (0x3D4)
1039#define SPR_40x_ESR (0x3D4)
1040#define SPR_ICMP (0x3D5)
1041#define SPR_40x_DEAR (0x3D5)
1042#define SPR_RPA (0x3D6)
1043#define SPR_40x_EVPR (0x3D6)
1044#define SPR_403_CDBCR (0x3D7)
1045#define SPR_TCR (0x3D8)
1046#define SPR_40x_TSR (0x3D8)
1047#define SPR_IBR (0x3DA)
1048#define SPR_40x_TCR (0x3DA)
1049#define SPR_ESASR (0x3DB)
1050#define SPR_40x_PIT (0x3DB)
1051#define SPR_403_TBL (0x3DC)
1052#define SPR_403_TBU (0x3DD)
1053#define SPR_SEBR (0x3DE)
1054#define SPR_40x_SRR2 (0x3DE)
1055#define SPR_SER (0x3DF)
1056#define SPR_40x_SRR3 (0x3DF)
1057#define SPR_HID0 (0x3F0)
1058#define SPR_40x_DBSR (0x3F0)
1059#define SPR_HID1 (0x3F1)
1060#define SPR_IABR (0x3F2)
1061#define SPR_40x_DBCR0 (0x3F2)
1062#define SPR_601_HID2 (0x3F2)
1063#define SPR_E500_L1CSR0 (0x3F2)
1064#define SPR_HID2 (0x3F3)
1065#define SPR_E500_L1CSR1 (0x3F3)
1066#define SPR_440_DBDR (0x3F3)
1067#define SPR_40x_IAC1 (0x3F4)
1068#define SPR_E500_MMUCSR0 (0x3F4)
1069#define SPR_DABR (0x3F5)
3fc6c082 1070#define DABR_MASK (~(target_ulong)0x7)
76a66253
JM		 1071#define SPR_E500_BUCSR (0x3F5)
1072#define SPR_40x_IAC2 (0x3F5)
1073#define SPR_601_HID5 (0x3F5)
1074#define SPR_40x_DAC1 (0x3F6)
1075#define SPR_40x_DAC2 (0x3F7)
1076#define SPR_E500_MMUCFG (0x3F7)
1077#define SPR_L2PM (0x3F8)
1078#define SPR_750_HID2 (0x3F8)
1079#define SPR_L2CR (0x3F9)
1080#define SPR_IABR2 (0x3FA)
1081#define SPR_40x_DCCR (0x3FA)
1082#define SPR_ICTC (0x3FB)
1083#define SPR_40x_ICCR (0x3FB)
1084#define SPR_THRM1 (0x3FC)
1085#define SPR_403_PBL1 (0x3FC)
1086#define SPR_SP (0x3FD)
1087#define SPR_THRM2 (0x3FD)
1088#define SPR_403_PBU1 (0x3FD)
1089#define SPR_LT (0x3FE)
1090#define SPR_THRM3 (0x3FE)
1091#define SPR_FPECR (0x3FE)
1092#define SPR_403_PBL2 (0x3FE)
1093#define SPR_PIR (0x3FF)
1094#define SPR_403_PBU2 (0x3FF)
1095#define SPR_601_HID15 (0x3FF)
1096#define SPR_E500_SVR (0x3FF)
79aceca5 1097
76a66253 1098/*****************************************************************************/
9a64fbe4
FB		 1099/* Memory access type :
1100 * may be needed for precise access rights control and precise exceptions.
1101 */
79aceca5 1102enum {
9a64fbe4
FB		 1103 /* 1 bit to define user level / supervisor access */
1104 ACCESS_USER = 0x00,
1105 ACCESS_SUPER = 0x01,
1106 /* Type of instruction that generated the access */
1107 ACCESS_CODE = 0x10, /* Code fetch access */
1108 ACCESS_INT = 0x20, /* Integer load/store access */
1109 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1110 ACCESS_RES = 0x40, /* load/store with reservation */
1111 ACCESS_EXT = 0x50, /* external access */
1112 ACCESS_CACHE = 0x60, /* Cache manipulation */
1113};
1114
1115/*****************************************************************************/
1116/* Exceptions */
2be0071f
FB		 1117#define EXCP_NONE -1
1118/* PowerPC hardware exceptions : exception vectors defined in PowerPC book 3 */
1119#define EXCP_RESET 0x0100 /* System reset */
1120#define EXCP_MACHINE_CHECK 0x0200 /* Machine check exception */
1121#define EXCP_DSI 0x0300 /* Data storage exception */
1122#define EXCP_DSEG 0x0380 /* Data segment exception */
1123#define EXCP_ISI 0x0400 /* Instruction storage exception */
1124#define EXCP_ISEG 0x0480 /* Instruction segment exception */
1125#define EXCP_EXTERNAL 0x0500 /* External interruption */
1126#define EXCP_ALIGN 0x0600 /* Alignment exception */
1127#define EXCP_PROGRAM 0x0700 /* Program exception */
1128#define EXCP_NO_FP 0x0800 /* Floating point unavailable exception */
1129#define EXCP_DECR 0x0900 /* Decrementer exception */
1130#define EXCP_HDECR 0x0980 /* Hypervisor decrementer exception */
1131#define EXCP_SYSCALL 0x0C00 /* System call */
1132#define EXCP_TRACE 0x0D00 /* Trace exception */
1133#define EXCP_PERF 0x0F00 /* Performance monitor exception */
1134/* Exceptions defined in PowerPC 32 bits programming environment manual */
1135#define EXCP_FP_ASSIST 0x0E00 /* Floating-point assist */
1136/* Implementation specific exceptions */
1137/* 40x exceptions */
1138#define EXCP_40x_PIT 0x1000 /* Programmable interval timer interrupt */
1139#define EXCP_40x_FIT 0x1010 /* Fixed interval timer interrupt */
1140#define EXCP_40x_WATCHDOG 0x1020 /* Watchdog timer exception */
1141#define EXCP_40x_DTLBMISS 0x1100 /* Data TLB miss exception */
1142#define EXCP_40x_ITLBMISS 0x1200 /* Instruction TLB miss exception */
1143#define EXCP_40x_DEBUG 0x2000 /* Debug exception */
1144/* 405 specific exceptions */
1145#define EXCP_405_APU 0x0F20 /* APU unavailable exception */
1146/* TLB assist exceptions (602/603) */
1147#define EXCP_I_TLBMISS 0x1000 /* Instruction TLB miss */
1148#define EXCP_DL_TLBMISS 0x1100 /* Data load TLB miss */
1149#define EXCP_DS_TLBMISS 0x1200 /* Data store TLB miss */
1150/* Breakpoint exceptions (602/603/604/620/740/745/750/755...) */
1151#define EXCP_IABR 0x1300 /* Instruction address breakpoint */
1152#define EXCP_SMI 0x1400 /* System management interrupt */
1153/* Altivec related exceptions */
1154#define EXCP_VPU 0x0F20 /* VPU unavailable exception */
1155/* 601 specific exceptions */
1156#define EXCP_601_IO 0x0600 /* IO error exception */
1157#define EXCP_601_RUNM 0x2000 /* Run mode exception */
1158/* 602 specific exceptions */
1159#define EXCP_602_WATCHDOG 0x1500 /* Watchdog exception */
1160#define EXCP_602_EMUL 0x1600 /* Emulation trap exception */
1161/* G2 specific exceptions */
1162#define EXCP_G2_CRIT 0x0A00 /* Critical interrupt */
1163/* MPC740/745/750 & IBM 750 specific exceptions */
1164#define EXCP_THRM 0x1700 /* Thermal management interrupt */
1165/* 74xx specific exceptions */
1166#define EXCP_74xx_VPUA 0x1600 /* VPU assist exception */
1167/* 970FX specific exceptions */
1168#define EXCP_970_SOFTP 0x1500 /* Soft patch exception */
1169#define EXCP_970_MAINT 0x1600 /* Maintenance exception */
1170#define EXCP_970_THRM 0x1800 /* Thermal exception */
1171#define EXCP_970_VPUA 0x1700 /* VPU assist exception */
1172/* End of exception vectors area */
1173#define EXCP_PPC_MAX 0x4000
1174/* Qemu exceptions: special cases we want to stop translation */
1175#define EXCP_MTMSR 0x11000 /* mtmsr instruction: */
76a66253 1176 /* may change privilege level */
2be0071f
FB		 1177#define EXCP_BRANCH 0x11001 /* branch instruction */
1178#define EXCP_SYSCALL_USER 0x12000 /* System call in user mode only */
1179#define EXCP_INTERRUPT_CRITICAL 0x13000 /* critical IRQ */
1180
9a64fbe4
FB		 1181/* Error codes */
1182enum {
9a64fbe4
FB		 1183 /* Exception subtypes for EXCP_ALIGN */
1184 EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
1185 EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
1186 EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
1187 EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
1188 EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
1189 EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
1190 /* Exception subtypes for EXCP_PROGRAM */
79aceca5 1191 /* FP exceptions */
9a64fbe4
FB		 1192 EXCP_FP = 0x10,
1193 EXCP_FP_OX = 0x01, /* FP overflow */
1194 EXCP_FP_UX = 0x02, /* FP underflow */
1195 EXCP_FP_ZX = 0x03, /* FP divide by zero */
1196 EXCP_FP_XX = 0x04, /* FP inexact */
1197 EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */
1198 EXCP_FP_VXISI = 0x06, /* FP invalid infinite substraction */
1199 EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
1200 EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
1201 EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
1202 EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
1203 EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
1204 EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
1205 EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
79aceca5 1206 /* Invalid instruction */
9a64fbe4
FB		 1207 EXCP_INVAL = 0x20,
1208 EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
1209 EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
1210 EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
1211 EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
79aceca5 1212 /* Privileged instruction */
9a64fbe4
FB		 1213 EXCP_PRIV = 0x30,
1214 EXCP_PRIV_OPC = 0x01,
1215 EXCP_PRIV_REG = 0x02,
79aceca5 1216 /* Trap */
9a64fbe4 1217 EXCP_TRAP = 0x40,
79aceca5
FB		 1218};
1219
9a64fbe4
FB		 1220/*****************************************************************************/
1221
79aceca5 1222#endif /* !defined (__CPU_PPC_H__) */
Qemu copy for testing