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Fix monitor disasm output for Sparc64 target
[qemu.git] / target-ppc / cpu.h
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation cpu definitions for qemu.
79aceca5 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#if !defined (__CPU_PPC_H__)
21#define __CPU_PPC_H__
22
3fc6c082 23#include "config.h"
de270b3c 24#include <inttypes.h>
3fc6c082 25
51789c41
JM		 26#if defined(TARGET_PPC64) || (HOST_LONG_BITS >= 64)
27/* When using 64 bits temporary registers,
28 * we can use 64 bits GPR with no extra cost
29 */
30#define TARGET_PPCSPE
31#endif
32
76a66253
JM		 33#if defined (TARGET_PPC64)
34typedef uint64_t ppc_gpr_t;
35#define TARGET_LONG_BITS 64
0487d6a8 36#define TARGET_GPR_BITS 64
76a66253 37#define REGX "%016" PRIx64
1b9eb036 38#define ADDRX "%016" PRIx64
0487d6a8 39#elif defined(TARGET_PPCSPE)
76a66253
JM		 40/* GPR are 64 bits: used by vector extension */
41typedef uint64_t ppc_gpr_t;
3cf1e035 42#define TARGET_LONG_BITS 32
0487d6a8 43#define TARGET_GPR_BITS 64
1b9eb036
JM		 44#define REGX "%016" PRIx64
45#define ADDRX "%08" PRIx32
76a66253
JM		 46#else
47typedef uint32_t ppc_gpr_t;
48#define TARGET_LONG_BITS 32
0487d6a8 49#define TARGET_GPR_BITS 32
76a66253 50#define REGX "%08" PRIx32
1b9eb036 51#define ADDRX "%08" PRIx32
76a66253 52#endif
3cf1e035 53
79aceca5
FB		 54#include "cpu-defs.h"
55
79aceca5
FB		 56#include <setjmp.h>
57
4ecc3190
FB		 58#include "softfloat.h"
59
1fddef4b
FB		 60#define TARGET_HAS_ICE 1
61
76a66253
JM		 62#if defined (TARGET_PPC64)
63#define ELF_MACHINE EM_PPC64
64#else
65#define ELF_MACHINE EM_PPC
66#endif
9042c0e2 67
fdabc366
FB		 68/* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC
69 * have different cache line sizes
70 */
71#define ICACHE_LINE_SIZE 32
72#define DCACHE_LINE_SIZE 32
73
74/* XXX: put this in a common place */
75#define likely(x) __builtin_expect(!!(x), 1)
76a66253 76#define unlikely(x) __builtin_expect(!!(x), 0)
fdabc366 77
3fc6c082
FB		 78/*****************************************************************************/
79/* PVR definitions for most known PowerPC */
80enum {
81 /* PowerPC 401 cores */
82 CPU_PPC_401A1 = 0x00210000,
83 CPU_PPC_401B2 = 0x00220000,
84 CPU_PPC_401C2 = 0x00230000,
85 CPU_PPC_401D2 = 0x00240000,
86 CPU_PPC_401E2 = 0x00250000,
87 CPU_PPC_401F2 = 0x00260000,
88 CPU_PPC_401G2 = 0x00270000,
76a66253
JM		 89#define CPU_PPC_401 CPU_PPC_401G2
90 CPU_PPC_IOP480 = 0x40100000, /* 401B2 ? */
91 CPU_PPC_COBRA = 0x10100000, /* IBM Processor for Network Resources */
3fc6c082 92 /* PowerPC 403 cores */
76a66253 93 CPU_PPC_403GA = 0x00200011,
3fc6c082
FB		 94 CPU_PPC_403GB = 0x00200100,
95 CPU_PPC_403GC = 0x00200200,
96 CPU_PPC_403GCX = 0x00201400,
76a66253 97#define CPU_PPC_403 CPU_PPC_403GCX
3fc6c082 98 /* PowerPC 405 cores */
76a66253
JM		 99 CPU_PPC_405CR = 0x40110145,
100#define CPU_PPC_405GP CPU_PPC_405CR
101 CPU_PPC_405EP = 0x51210950,
102 CPU_PPC_405GPR = 0x50910951,
3fc6c082
FB		 103 CPU_PPC_405D2 = 0x20010000,
104 CPU_PPC_405D4 = 0x41810000,
76a66253
JM		 105#define CPU_PPC_405 CPU_PPC_405D4
106 CPU_PPC_NPE405H = 0x414100C0,
107 CPU_PPC_NPE405H2 = 0x41410140,
108 CPU_PPC_NPE405L = 0x416100C0,
109 /* XXX: missing 405LP, LC77700 */
110 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
111#if 0
112 CPU_PPC_STB01000 = xxx,
113#endif
3fc6c082 114#if 0
76a66253
JM		 115 CPU_PPC_STB01010 = xxx,
116#endif
117#if 0
118 CPU_PPC_STB0210 = xxx,
3fc6c082
FB		 119#endif
120 CPU_PPC_STB03 = 0x40310000,
121#if 0
76a66253 122 CPU_PPC_STB043 = xxx,
3fc6c082 123#endif
76a66253
JM		 124#if 0
125 CPU_PPC_STB045 = xxx,
126#endif
127 CPU_PPC_STB25 = 0x51510950,
3fc6c082
FB		 128#if 0
129 CPU_PPC_STB130 = xxx,
130#endif
76a66253
JM		 131 /* Xilinx cores */
132 CPU_PPC_X2VP4 = 0x20010820,
133#define CPU_PPC_X2VP7 CPU_PPC_X2VP4
134 CPU_PPC_X2VP20 = 0x20010860,
135#define CPU_PPC_X2VP50 CPU_PPC_X2VP20
3fc6c082 136 /* PowerPC 440 cores */
76a66253
JM		 137 CPU_PPC_440EP = 0x422218D3,
138#define CPU_PPC_440GR CPU_PPC_440EP
139 CPU_PPC_440GP = 0x40120481,
140 CPU_PPC_440GX = 0x51B21850,
141 CPU_PPC_440GXc = 0x51B21892,
142 CPU_PPC_440GXf = 0x51B21894,
143 CPU_PPC_440SP = 0x53221850,
144 CPU_PPC_440SP2 = 0x53221891,
145 CPU_PPC_440SPE = 0x53421890,
146 /* XXX: missing 440GRX */
147 /* PowerPC 460 cores - TODO */
148 /* PowerPC MPC 5xx cores */
149 CPU_PPC_5xx = 0x00020020,
150 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
3fc6c082 151 CPU_PPC_8xx = 0x00500000,
76a66253
JM		 152 /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
153 CPU_PPC_82xx_HIP3 = 0x00810101,
154 CPU_PPC_82xx_HIP4 = 0x80811014,
155 CPU_PPC_827x = 0x80822013,
156 /* eCores */
157 CPU_PPC_e200 = 0x81120000,
158 CPU_PPC_e500v110 = 0x80200010,
159 CPU_PPC_e500v120 = 0x80200020,
160 CPU_PPC_e500v210 = 0x80210010,
161 CPU_PPC_e500v220 = 0x80210020,
162#define CPU_PPC_e500 CPU_PPC_e500v220
163 CPU_PPC_e600 = 0x80040010,
3fc6c082 164 /* PowerPC 6xx cores */
76a66253
JM		 165 CPU_PPC_601 = 0x00010001,
166 CPU_PPC_602 = 0x00050100,
167 CPU_PPC_603 = 0x00030100,
168 CPU_PPC_603E = 0x00060101,
169 CPU_PPC_603P = 0x00070000,
170 CPU_PPC_603E7v = 0x00070100,
171 CPU_PPC_603E7v2 = 0x00070201,
172 CPU_PPC_603E7 = 0x00070200,
173 CPU_PPC_603R = 0x00071201,
174 CPU_PPC_G2 = 0x00810011,
175 CPU_PPC_G2H4 = 0x80811010,
176 CPU_PPC_G2gp = 0x80821010,
177 CPU_PPC_G2ls = 0x90810010,
178 CPU_PPC_G2LE = 0x80820010,
179 CPU_PPC_G2LEgp = 0x80822010,
180 CPU_PPC_G2LEls = 0xA0822010,
3fc6c082 181 CPU_PPC_604 = 0x00040000,
76a66253
JM		 182 CPU_PPC_604E = 0x00090100, /* Also 2110 & 2120 */
183 CPU_PPC_604R = 0x000a0101,
3fc6c082
FB		 184 /* PowerPC 74x/75x cores (aka G3) */
185 CPU_PPC_74x = 0x00080000,
76a66253
JM		 186 CPU_PPC_740E = 0x00080100,
187 CPU_PPC_750E = 0x00080200,
188 CPU_PPC_755_10 = 0x00083100,
189 CPU_PPC_755_11 = 0x00083101,
190 CPU_PPC_755_20 = 0x00083200,
191 CPU_PPC_755D = 0x00083202,
192 CPU_PPC_755E = 0x00083203,
193#define CPU_PPC_755 CPU_PPC_755E
3fc6c082 194 CPU_PPC_74xP = 0x10080000,
76a66253
JM		 195 CPU_PPC_750CXE21 = 0x00082201,
196 CPU_PPC_750CXE22 = 0x00082212,
197 CPU_PPC_750CXE23 = 0x00082203,
3fc6c082
FB		 198 CPU_PPC_750CXE24 = 0x00082214,
199 CPU_PPC_750CXE24b = 0x00083214,
200 CPU_PPC_750CXE31 = 0x00083211,
201 CPU_PPC_750CXE31b = 0x00083311,
202#define CPU_PPC_750CXE CPU_PPC_750CXE31b
76a66253
JM		 203 CPU_PPC_750CXR = 0x00083410,
204 CPU_PPC_750FX10 = 0x70000100,
205 CPU_PPC_750FX20 = 0x70000200,
206 CPU_PPC_750FX21 = 0x70000201,
207 CPU_PPC_750FX22 = 0x70000202,
208 CPU_PPC_750FX23 = 0x70000203,
209#define CPU_PPC_750FX CPU_PPC_750FX23
210 CPU_PPC_750FL = 0x700A0203,
211 CPU_PPC_750GX10 = 0x70020100,
212 CPU_PPC_750GX11 = 0x70020101,
213 CPU_PPC_750GX12 = 0x70020102,
214#define CPU_PPC_750GX CPU_PPC_750GX12
215 CPU_PPC_750GL = 0x70020102,
216 CPU_PPC_750L30 = 0x00088300,
217 CPU_PPC_750L32 = 0x00088302,
218 CPU_PPC_750CL = 0x00087200,
3fc6c082 219 /* PowerPC 74xx cores (aka G4) */
76a66253
JM		 220 CPU_PPC_7400 = 0x000C0100,
221 CPU_PPC_7410C = 0x800C1102,
222 CPU_PPC_7410D = 0x800C1103,
223 CPU_PPC_7410E = 0x800C1104,
224 CPU_PPC_7441 = 0x80000210,
225 CPU_PPC_7445 = 0x80010100,
226 CPU_PPC_7447 = 0x80020100,
227 CPU_PPC_7447A = 0x80030101,
228 CPU_PPC_7448 = 0x80040100,
229 CPU_PPC_7450 = 0x80000200,
230 CPU_PPC_7450b = 0x80000201,
3fc6c082 231 CPU_PPC_7451 = 0x80000203,
76a66253
JM		 232 CPU_PPC_7451G = 0x80000210,
233 CPU_PPC_7455 = 0x80010201,
234 CPU_PPC_7455F = 0x80010303,
235 CPU_PPC_7455G = 0x80010304,
236 CPU_PPC_7457 = 0x80020101,
237 CPU_PPC_7457C = 0x80020102,
3fc6c082
FB		 238 CPU_PPC_7457A = 0x80030000,
239 /* 64 bits PowerPC */
240 CPU_PPC_620 = 0x00140000,
241 CPU_PPC_630 = 0x00400000,
242 CPU_PPC_631 = 0x00410000,
243 CPU_PPC_POWER4 = 0x00350000,
244 CPU_PPC_POWER4P = 0x00380000,
245 CPU_PPC_POWER5 = 0x003A0000,
246 CPU_PPC_POWER5P = 0x003B0000,
247 CPU_PPC_970 = 0x00390000,
76a66253
JM		 248 CPU_PPC_970FX10 = 0x00391100,
249 CPU_PPC_970FX20 = 0x003C0200,
250 CPU_PPC_970FX21 = 0x003C0201,
251 CPU_PPC_970FX30 = 0x003C0300,
252 CPU_PPC_970FX31 = 0x003C0301,
253#define CPU_PPC_970FX CPU_PPC_970FX31
254 CPU_PPC_970MP10 = 0x00440100,
255 CPU_PPC_970MP11 = 0x00440101,
256#define CPU_PPC_970MP CPU_PPC_970MP11
257 CPU_PPC_CELL10 = 0x00700100,
258 CPU_PPC_CELL20 = 0x00700400,
259 CPU_PPC_CELL30 = 0x00700500,
260 CPU_PPC_CELL31 = 0x00700501,
261#define CPU_PPC_CELL32 CPU_PPC_CELL31
262#define CPU_PPC_CELL CPU_PPC_CELL32
3fc6c082
FB		 263 CPU_PPC_RS64 = 0x00330000,
264 CPU_PPC_RS64II = 0x00340000,
265 CPU_PPC_RS64III = 0x00360000,
266 CPU_PPC_RS64IV = 0x00370000,
267 /* Original POWER */
268 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
269 * POWER2 (RIOS2) & RSC2 (P2SC) here
270 */
271#if 0
272 CPU_POWER = xxx,
273#endif
274#if 0
275 CPU_POWER2 = xxx,
276#endif
277};
278
76a66253 279/* System version register (used on MPC 8xxx) */
3fc6c082
FB		 280enum {
281 PPC_SVR_8540 = 0x80300000,
76a66253
JM		 282 PPC_SVR_8541E = 0x807A0010,
283 PPC_SVR_8543v10 = 0x80320010,
284 PPC_SVR_8543v11 = 0x80320011,
285 PPC_SVR_8543v20 = 0x80320020,
286 PPC_SVR_8543Ev10 = 0x803A0010,
287 PPC_SVR_8543Ev11 = 0x803A0011,
288 PPC_SVR_8543Ev20 = 0x803A0020,
289 PPC_SVR_8545 = 0x80310220,
290 PPC_SVR_8545E = 0x80390220,
291 PPC_SVR_8547E = 0x80390120,
292 PPC_SCR_8548v10 = 0x80310010,
293 PPC_SCR_8548v11 = 0x80310011,
294 PPC_SCR_8548v20 = 0x80310020,
295 PPC_SVR_8548Ev10 = 0x80390010,
296 PPC_SVR_8548Ev11 = 0x80390011,
297 PPC_SVR_8548Ev20 = 0x80390020,
298 PPC_SVR_8555E = 0x80790010,
299 PPC_SVR_8560v10 = 0x80700010,
300 PPC_SVR_8560v20 = 0x80700020,
3fc6c082
FB		 301};
302
303/*****************************************************************************/
9a64fbe4
FB		 304/* Instruction types */
305enum {
3fc6c082
FB		 306 PPC_NONE = 0x00000000,
307 /* integer operations instructions */
308 /* flow control instructions */
309 /* virtual memory instructions */
310 /* ld/st with reservation instructions */
311 /* cache control instructions */
312 /* spr/msr access instructions */
0487d6a8 313 PPC_INSNS_BASE = 0x0000000000000001ULL,
3fc6c082
FB		 314#define PPC_INTEGER PPC_INSNS_BASE
315#define PPC_FLOW PPC_INSNS_BASE
316#define PPC_MEM PPC_INSNS_BASE
317#define PPC_RES PPC_INSNS_BASE
318#define PPC_CACHE PPC_INSNS_BASE
319#define PPC_MISC PPC_INSNS_BASE
320 /* floating point operations instructions */
0487d6a8 321 PPC_FLOAT = 0x0000000000000002ULL,
3fc6c082 322 /* more floating point operations instructions */
0487d6a8 323 PPC_FLOAT_EXT = 0x0000000000000004ULL,
3fc6c082 324 /* external control instructions */
0487d6a8 325 PPC_EXTERN = 0x0000000000000008ULL,
3fc6c082 326 /* segment register access instructions */
0487d6a8 327 PPC_SEGMENT = 0x0000000000000010ULL,
3fc6c082 328 /* Optional cache control instructions */
0487d6a8 329 PPC_CACHE_OPT = 0x0000000000000020ULL,
3fc6c082 330 /* Optional floating point op instructions */
0487d6a8 331 PPC_FLOAT_OPT = 0x0000000000000040ULL,
3fc6c082 332 /* Optional memory control instructions */
0487d6a8
JM		 333 PPC_MEM_TLBIA = 0x0000000000000080ULL,
334 PPC_MEM_TLBIE = 0x0000000000000100ULL,
335 PPC_MEM_TLBSYNC = 0x0000000000000200ULL,
3fc6c082 336 /* eieio & sync */
0487d6a8 337 PPC_MEM_SYNC = 0x0000000000000400ULL,
3fc6c082 338 /* PowerPC 6xx TLB management instructions */
0487d6a8 339 PPC_6xx_TLB = 0x0000000000000800ULL,
3fc6c082 340 /* Altivec support */
0487d6a8 341 PPC_ALTIVEC = 0x0000000000001000ULL,
3fc6c082 342 /* Time base support */
0487d6a8 343 PPC_TB = 0x0000000000002000ULL,
3fc6c082 344 /* Embedded PowerPC dedicated instructions */
0487d6a8 345 PPC_EMB_COMMON = 0x0000000000004000ULL,
3fc6c082 346 /* PowerPC 40x exception model */
0487d6a8 347 PPC_40x_EXCP = 0x0000000000008000ULL,
3fc6c082 348 /* PowerPC 40x specific instructions */
0487d6a8 349 PPC_40x_SPEC = 0x0000000000010000ULL,
3fc6c082 350 /* PowerPC 405 Mac instructions */
0487d6a8 351 PPC_405_MAC = 0x0000000000020000ULL,
3fc6c082 352 /* PowerPC 440 specific instructions */
0487d6a8 353 PPC_440_SPEC = 0x0000000000040000ULL,
3fc6c082
FB		 354 /* Specific extensions */
355 /* Power-to-PowerPC bridge (601) */
0487d6a8 356 PPC_POWER_BR = 0x0000000000080000ULL,
3fc6c082 357 /* PowerPC 602 specific */
0487d6a8 358 PPC_602_SPEC = 0x0000000000100000ULL,
3fc6c082
FB		 359 /* Deprecated instructions */
360 /* Original POWER instruction set */
0487d6a8 361 PPC_POWER = 0x0000000000200000ULL,
3fc6c082 362 /* POWER2 instruction set extension */
0487d6a8 363 PPC_POWER2 = 0x0000000000400000ULL,
3fc6c082 364 /* Power RTC support */
0487d6a8 365 PPC_POWER_RTC = 0x0000000000800000ULL,
3fc6c082
FB		 366 /* 64 bits PowerPC instructions */
367 /* 64 bits PowerPC instruction set */
0487d6a8 368 PPC_64B = 0x0000000001000000ULL,
3fc6c082 369 /* 64 bits hypervisor extensions */
0487d6a8 370 PPC_64H = 0x0000000002000000ULL,
3fc6c082 371 /* 64 bits PowerPC "bridge" features */
0487d6a8 372 PPC_64_BRIDGE = 0x0000000004000000ULL,
76a66253 373 /* BookE (embedded) PowerPC specification */
0487d6a8 374 PPC_BOOKE = 0x0000000008000000ULL,
76a66253 375 /* eieio */
0487d6a8 376 PPC_MEM_EIEIO = 0x0000000010000000ULL,
76a66253 377 /* e500 vector instructions */
0487d6a8 378 PPC_E500_VECTOR = 0x0000000020000000ULL,
76a66253 379 /* PowerPC 4xx dedicated instructions */
0487d6a8 380 PPC_4xx_COMMON = 0x0000000040000000ULL,
d9bce9d9 381 /* PowerPC 2.03 specification extensions */
0487d6a8
JM		 382 PPC_203 = 0x0000000080000000ULL,
383 /* PowerPC 2.03 SPE extension */
384 PPC_SPE = 0x0000000100000000ULL,
385 /* PowerPC 2.03 SPE floating-point extension */
386 PPC_SPEFPU = 0x0000000200000000ULL,
426613db
JM		 387 /* SLB management */
388 PPC_SLBI = 0x0000000400000000ULL,
9a64fbe4 389};
79aceca5 390
3fc6c082
FB		 391/* CPU run-time flags (MMU and exception model) */
392enum {
393 /* MMU model */
76a66253 394 PPC_FLAGS_MMU_MASK = 0x0000000F,
3fc6c082
FB		 395 /* Standard 32 bits PowerPC MMU */
396 PPC_FLAGS_MMU_32B = 0x00000000,
397 /* Standard 64 bits PowerPC MMU */
398 PPC_FLAGS_MMU_64B = 0x00000001,
399 /* PowerPC 601 MMU */
400 PPC_FLAGS_MMU_601 = 0x00000002,
401 /* PowerPC 6xx MMU with software TLB */
402 PPC_FLAGS_MMU_SOFT_6xx = 0x00000003,
403 /* PowerPC 4xx MMU with software TLB */
404 PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,
405 /* PowerPC 403 MMU */
406 PPC_FLAGS_MMU_403 = 0x00000005,
76a66253
JM		 407 /* Freescale e500 MMU model */
408 PPC_FLAGS_MMU_e500 = 0x00000006,
d9bce9d9
JM		 409 /* BookE MMU model */
410 PPC_FLAGS_MMU_BOOKE = 0x00000007,
3fc6c082 411 /* Exception model */
76a66253 412 PPC_FLAGS_EXCP_MASK = 0x000000F0,
3fc6c082
FB		 413 /* Standard PowerPC exception model */
414 PPC_FLAGS_EXCP_STD = 0x00000000,
415 /* PowerPC 40x exception model */
416 PPC_FLAGS_EXCP_40x = 0x00000010,
417 /* PowerPC 601 exception model */
418 PPC_FLAGS_EXCP_601 = 0x00000020,
419 /* PowerPC 602 exception model */
420 PPC_FLAGS_EXCP_602 = 0x00000030,
421 /* PowerPC 603 exception model */
422 PPC_FLAGS_EXCP_603 = 0x00000040,
423 /* PowerPC 604 exception model */
424 PPC_FLAGS_EXCP_604 = 0x00000050,
425 /* PowerPC 7x0 exception model */
426 PPC_FLAGS_EXCP_7x0 = 0x00000060,
427 /* PowerPC 7x5 exception model */
428 PPC_FLAGS_EXCP_7x5 = 0x00000070,
429 /* PowerPC 74xx exception model */
430 PPC_FLAGS_EXCP_74xx = 0x00000080,
431 /* PowerPC 970 exception model */
432 PPC_FLAGS_EXCP_970 = 0x00000090,
d9bce9d9
JM		 433 /* BookE exception model */
434 PPC_FLAGS_EXCP_BOOKE = 0x000000A0,
3fc6c082
FB		 435};
436
437#define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK)
438#define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK)
439
440/*****************************************************************************/
441/* Supported instruction set definitions */
442/* This generates an empty opcode table... */
443#define PPC_INSNS_TODO (PPC_NONE)
444#define PPC_FLAGS_TODO (0x00000000)
445
446/* PowerPC 40x instruction set */
76a66253 447#define PPC_INSNS_EMB (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_EMB_COMMON)
3fc6c082
FB		 448/* PowerPC 401 */
449#define PPC_INSNS_401 (PPC_INSNS_TODO)
450#define PPC_FLAGS_401 (PPC_FLAGS_TODO)
451/* PowerPC 403 */
76a66253
JM		 452#define PPC_INSNS_403 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
453 PPC_MEM_TLBIA | PPC_4xx_COMMON | PPC_40x_EXCP | \
454 PPC_40x_SPEC)
3fc6c082
FB		 455#define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x)
456/* PowerPC 405 */
76a66253
JM		 457#define PPC_INSNS_405 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
458 PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_TB | \
459 PPC_4xx_COMMON | PPC_40x_SPEC | PPC_40x_EXCP | \
3fc6c082
FB		 460 PPC_405_MAC)
461#define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
462/* PowerPC 440 */
76a66253
JM		 463#define PPC_INSNS_440 (PPC_INSNS_EMB | PPC_CACHE_OPT | PPC_BOOKE | \
464 PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
d9bce9d9 465#define PPC_FLAGS_440 (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE)
76a66253
JM		 466/* Generic BookE PowerPC */
467#define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \
468 PPC_FLOAT | PPC_FLOAT_OPT | PPC_CACHE_OPT)
d9bce9d9 469#define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE)
76a66253
JM		 470/* e500 core */
471#define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \
472 PPC_CACHE_OPT | PPC_E500_VECTOR)
473#define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
3fc6c082
FB		 474/* Non-embedded PowerPC */
475#define PPC_INSNS_COMMON (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
76a66253 476 PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
3fc6c082
FB		 477/* PowerPC 601 */
478#define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)
479#define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601)
480/* PowerPC 602 */
481#define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
76a66253 482 PPC_MEM_TLBSYNC | PPC_TB | PPC_602_SPEC)
3fc6c082
FB		 483#define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602)
484/* PowerPC 603 */
485#define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
486 PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
487#define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
488/* PowerPC G2 */
489#define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
490 PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
491#define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
492/* PowerPC 604 */
493#define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
494 PPC_MEM_TLBSYNC | PPC_TB)
495#define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604)
496/* PowerPC 740/750 (aka G3) */
497#define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
498 PPC_MEM_TLBSYNC | PPC_TB)
499#define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0)
500/* PowerPC 745/755 */
501#define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
502 PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB)
503#define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5)
504/* PowerPC 74xx (aka G4) */
505#define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC | \
506 PPC_MEM_TLBSYNC | PPC_TB)
507#define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx)
426613db
JM		 508/* PowerPC 970 (aka G5) */
509#define PPC_INSNS_970 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_FLOAT_OPT | \
510 PPC_ALTIVEC | PPC_MEM_TLBSYNC | PPC_TB | \
511 PPC_64B | PPC_64_BRIDGE | PPC_SLBI)
512#define PPC_FLAGS_970 (PPC_FLAGS_MMU_64B | PPC_FLAGS_EXCP_970)
3fc6c082
FB		 513
514/* Default PowerPC will be 604/970 */
515#define PPC_INSNS_PPC32 PPC_INSNS_604
516#define PPC_FLAGS_PPC32 PPC_FLAGS_604
3fc6c082
FB		 517#define PPC_INSNS_PPC64 PPC_INSNS_970
518#define PPC_FLAGS_PPC64 PPC_FLAGS_970
3fc6c082
FB		 519#define PPC_INSNS_DEFAULT PPC_INSNS_604
520#define PPC_FLAGS_DEFAULT PPC_FLAGS_604
521typedef struct ppc_def_t ppc_def_t;
79aceca5 522
3fc6c082
FB		 523/*****************************************************************************/
524/* Types used to describe some PowerPC registers */
525typedef struct CPUPPCState CPUPPCState;
526typedef struct opc_handler_t opc_handler_t;
9fddaa0c 527typedef struct ppc_tb_t ppc_tb_t;
3fc6c082
FB		 528typedef struct ppc_spr_t ppc_spr_t;
529typedef struct ppc_dcr_t ppc_dcr_t;
530typedef struct ppc_avr_t ppc_avr_t;
1d0a48fb 531typedef union ppc_tlb_t ppc_tlb_t;
76a66253 532
3fc6c082
FB		 533/* SPR access micro-ops generations callbacks */
534struct ppc_spr_t {
535 void (*uea_read)(void *opaque, int spr_num);
536 void (*uea_write)(void *opaque, int spr_num);
76a66253 537#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 538 void (*oea_read)(void *opaque, int spr_num);
539 void (*oea_write)(void *opaque, int spr_num);
76a66253 540#endif
3fc6c082
FB		 541 const unsigned char *name;
542};
543
544/* Altivec registers (128 bits) */
545struct ppc_avr_t {
546 uint32_t u[4];
547};
9fddaa0c 548
3fc6c082 549/* Software TLB cache */
1d0a48fb
JM		 550typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
551struct ppc6xx_tlb_t {
76a66253
JM		 552 target_ulong pte0;
553 target_ulong pte1;
554 target_ulong EPN;
1d0a48fb
JM		 555};
556
557typedef struct ppcemb_tlb_t ppcemb_tlb_t;
558struct ppcemb_tlb_t {
559 target_ulong RPN;
560 target_ulong EPN;
76a66253
JM		 561 target_ulong PID;
562 int size;
1d0a48fb
JM		 563 int prot;
564 int attr; /* Storage attributes */
565};
566
567union ppc_tlb_t {
568 ppc6xx_tlb_t tlb6;
569 ppcemb_tlb_t tlbe;
3fc6c082
FB		 570};
571
572/*****************************************************************************/
573/* Machine state register bits definition */
76a66253 574#define MSR_SF 63 /* Sixty-four-bit mode hflags */
3fc6c082 575#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
76a66253 576#define MSR_HV 60 /* hypervisor state hflags */
363be49c
JM		 577#define MSR_CM 31 /* Computation mode for BookE hflags */
578#define MSR_ICM 30 /* Interrupt computation mode for BookE */
579#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
76a66253 580#define MSR_VR 25 /* altivec available hflags */
363be49c 581#define MSR_SPE 25 /* SPE enable for BookE hflags */
76a66253
JM		 582#define MSR_AP 23 /* Access privilege state on 602 hflags */
583#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
3fc6c082
FB		 584#define MSR_KEY 19 /* key bit on 603e */
585#define MSR_POW 18 /* Power management */
586#define MSR_WE 18 /* Wait state enable on embedded PowerPC */
587#define MSR_TGPR 17 /* TGPR usage on 602/603 */
76a66253 588#define MSR_TLB 17 /* TLB update on ? */
3fc6c082
FB		 589#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC */
590#define MSR_ILE 16 /* Interrupt little-endian mode */
591#define MSR_EE 15 /* External interrupt enable */
76a66253
JM		 592#define MSR_PR 14 /* Problem state hflags */
593#define MSR_FP 13 /* Floating point available hflags */
3fc6c082 594#define MSR_ME 12 /* Machine check interrupt enable */
76a66253
JM		 595#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
596#define MSR_SE 10 /* Single-step trace enable hflags */
3fc6c082 597#define MSR_DWE 10 /* Debug wait enable on 405 */
76a66253
JM		 598#define MSR_UBLE 10 /* User BTB lock enable on e500 */
599#define MSR_BE 9 /* Branch trace enable hflags */
3fc6c082 600#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC */
76a66253 601#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
3fc6c082
FB		 602#define MSR_AL 7 /* AL bit on POWER */
603#define MSR_IP 6 /* Interrupt prefix */
604#define MSR_IR 5 /* Instruction relocate */
605#define MSR_IS 5 /* Instruction address space on embedded PowerPC */
606#define MSR_DR 4 /* Data relocate */
607#define MSR_DS 4 /* Data address space on embedded PowerPC */
608#define MSR_PE 3 /* Protection enable on 403 */
609#define MSR_EP 3 /* Exception prefix on 601 */
610#define MSR_PX 2 /* Protection exclusive on 403 */
611#define MSR_PMM 2 /* Performance monitor mark on POWER */
612#define MSR_RI 1 /* Recoverable interrupt */
76a66253 613#define MSR_LE 0 /* Little-endian mode hflags */
3fc6c082
FB		 614#define msr_sf env->msr[MSR_SF]
615#define msr_isf env->msr[MSR_ISF]
616#define msr_hv env->msr[MSR_HV]
363be49c
JM		 617#define msr_cm env->msr[MSR_CM]
618#define msr_icm env->msr[MSR_ICM]
76a66253 619#define msr_ucle env->msr[MSR_UCLE]
3fc6c082 620#define msr_vr env->msr[MSR_VR]
76a66253 621#define msr_spe env->msr[MSR_SPE]
3fc6c082
FB		 622#define msr_ap env->msr[MSR_AP]
623#define msr_sa env->msr[MSR_SA]
624#define msr_key env->msr[MSR_KEY]
76a66253 625#define msr_pow env->msr[MSR_POW]
3fc6c082
FB		 626#define msr_we env->msr[MSR_WE]
627#define msr_tgpr env->msr[MSR_TGPR]
628#define msr_tlb env->msr[MSR_TLB]
629#define msr_ce env->msr[MSR_CE]
76a66253
JM		 630#define msr_ile env->msr[MSR_ILE]
631#define msr_ee env->msr[MSR_EE]
632#define msr_pr env->msr[MSR_PR]
633#define msr_fp env->msr[MSR_FP]
634#define msr_me env->msr[MSR_ME]
635#define msr_fe0 env->msr[MSR_FE0]
636#define msr_se env->msr[MSR_SE]
3fc6c082 637#define msr_dwe env->msr[MSR_DWE]
76a66253
JM		 638#define msr_uble env->msr[MSR_UBLE]
639#define msr_be env->msr[MSR_BE]
3fc6c082 640#define msr_de env->msr[MSR_DE]
76a66253 641#define msr_fe1 env->msr[MSR_FE1]
3fc6c082 642#define msr_al env->msr[MSR_AL]
76a66253
JM		 643#define msr_ip env->msr[MSR_IP]
644#define msr_ir env->msr[MSR_IR]
3fc6c082 645#define msr_is env->msr[MSR_IS]
76a66253 646#define msr_dr env->msr[MSR_DR]
3fc6c082
FB		 647#define msr_ds env->msr[MSR_DS]
648#define msr_pe env->msr[MSR_PE]
649#define msr_ep env->msr[MSR_EP]
650#define msr_px env->msr[MSR_PX]
651#define msr_pmm env->msr[MSR_PMM]
76a66253
JM		 652#define msr_ri env->msr[MSR_RI]
653#define msr_le env->msr[MSR_LE]
79aceca5 654
3fc6c082
FB		 655/*****************************************************************************/
656/* The whole PowerPC CPU context */
657struct CPUPPCState {
658 /* First are the most commonly used resources
659 * during translated code execution
660 */
0487d6a8 661#if TARGET_GPR_BITS > HOST_LONG_BITS
3fc6c082
FB		 662 /* temporary fixed-point registers
663 * used to emulate 64 bits target on 32 bits hosts
0487d6a8 664 */
3fc6c082
FB		 665 target_ulong t0, t1, t2;
666#endif
d9bce9d9
JM		 667 ppc_avr_t t0_avr, t1_avr, t2_avr;
668
79aceca5 669 /* general purpose registers */
76a66253 670 ppc_gpr_t gpr[32];
3fc6c082
FB		 671 /* LR */
672 target_ulong lr;
673 /* CTR */
674 target_ulong ctr;
675 /* condition register */
676 uint8_t crf[8];
79aceca5 677 /* XER */
3fc6c082
FB		 678 /* XXX: We use only 5 fields, but we want to keep the structure aligned */
679 uint8_t xer[8];
79aceca5 680 /* Reservation address */
3fc6c082
FB		 681 target_ulong reserve;
682
683 /* Those ones are used in supervisor mode only */
79aceca5 684 /* machine state register */
3fc6c082
FB		 685 uint8_t msr[64];
686 /* temporary general purpose registers */
76a66253 687 ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
3fc6c082
FB		 688
689 /* Floating point execution context */
76a66253 690 /* temporary float registers */
4ecc3190
FB		 691 float64 ft0;
692 float64 ft1;
693 float64 ft2;
694 float_status fp_status;
3fc6c082
FB		 695 /* floating point registers */
696 float64 fpr[32];
697 /* floating point status and control register */
698 uint8_t fpscr[8];
4ecc3190 699
a316d335
FB		 700 CPU_COMMON
701
50443c98
FB		 702 int halted; /* TRUE if the CPU is in suspend state */
703
ac9eb073
FB		 704 int access_type; /* when a memory exception occurs, the access
705 type is stored here */
a541f297 706
3fc6c082
FB		 707 /* MMU context */
708 /* Address space register */
709 target_ulong asr;
710 /* segment registers */
711 target_ulong sdr1;
712 target_ulong sr[16];
713 /* BATs */
714 int nb_BATs;
715 target_ulong DBAT[2][8];
716 target_ulong IBAT[2][8];
9fddaa0c 717
3fc6c082
FB		 718 /* Other registers */
719 /* Special purpose registers */
720 target_ulong spr[1024];
721 /* Altivec registers */
722 ppc_avr_t avr[32];
723 uint32_t vscr;
d9bce9d9
JM		 724 /* SPE registers */
725 ppc_gpr_t spe_acc;
0487d6a8 726 float_status spe_status;
d9bce9d9 727 uint32_t spe_fscr;
3fc6c082
FB		 728
729 /* Internal devices resources */
9fddaa0c
FB		 730 /* Time base and decrementer */
731 ppc_tb_t *tb_env;
3fc6c082
FB		 732 /* Device control registers */
733 int (*dcr_read)(ppc_dcr_t *dcr_env, int dcr_num, target_ulong *val);
734 int (*dcr_write)(ppc_dcr_t *dcr_env, int dcr_num, target_ulong val);
735 ppc_dcr_t *dcr_env;
736
737 /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
76a66253
JM		 738 int nb_tlb; /* Total number of TLB */
739 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
740 int nb_ways; /* Number of ways in the TLB set */
741 int last_way; /* Last used way used to allocate TLB in a LRU way */
742 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
363be49c 743 int nb_pids; /* Number of available PID registers */
76a66253 744 ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
3fc6c082 745 /* Callbacks for specific checks on some implementations */
1d0a48fb 746 int (*tlb_check_more)(CPUPPCState *env, ppc_tlb_t *tlb, int *prot,
3fc6c082
FB		 747 target_ulong vaddr, int rw, int acc_type,
748 int is_user);
749 /* 403 dedicated access protection registers */
750 target_ulong pb[4];
751
752 /* Those resources are used during exception processing */
753 /* CPU model definition */
754 uint64_t msr_mask;
755 uint32_t flags;
756
757 int exception_index;
758 int error_code;
759 int interrupt_request;
47103572 760 uint32_t pending_interrupts;
d537cf6c 761 void *irq[32];
3fc6c082
FB		 762
763 /* Those resources are used only during code translation */
764 /* Next instruction pointer */
765 target_ulong nip;
766 /* SPR translation callbacks */
767 ppc_spr_t spr_cb[1024];
768 /* opcode handlers */
769 opc_handler_t *opcodes[0x40];
770
771 /* Those resources are used only in Qemu core */
772 jmp_buf jmp_env;
773 int user_mode_only; /* user mode only simulation */
3fc6c082
FB		 774 uint32_t hflags;
775
9fddaa0c
FB		 776 /* Power management */
777 int power_mode;
a541f297 778
6d506e6d
FB		 779 /* temporary hack to handle OSI calls (only used if non NULL) */
780 int (*osi_call)(struct CPUPPCState *env);
3fc6c082 781};
79aceca5 782
76a66253
JM		 783/* Context used internally during MMU translations */
784typedef struct mmu_ctx_t mmu_ctx_t;
785struct mmu_ctx_t {
786 target_phys_addr_t raddr; /* Real address */
787 int prot; /* Protection bits */
788 target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
789 target_ulong ptem; /* Virtual segment ID | API */
790 int key; /* Access key */
791};
792
3fc6c082 793/*****************************************************************************/
79aceca5
FB		 794CPUPPCState *cpu_ppc_init(void);
795int cpu_ppc_exec(CPUPPCState *s);
796void cpu_ppc_close(CPUPPCState *s);
797/* you can call this signal handler from your SIGBUS and SIGSEGV
798 signal handlers to inform the virtual CPU of exceptions. non zero
799 is returned if the signal was handled by the virtual CPU. */
5a7b542b 800int cpu_ppc_signal_handler(int host_signum, void *pinfo,
79aceca5
FB		 801 void *puc);
802
a541f297 803void do_interrupt (CPUPPCState *env);
9a64fbe4 804void cpu_loop_exit(void);
a541f297 805
9a64fbe4 806void dump_stack (CPUPPCState *env);
a541f297 807
76a66253 808#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 809target_ulong do_load_ibatu (CPUPPCState *env, int nr);
810target_ulong do_load_ibatl (CPUPPCState *env, int nr);
811void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
812void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
813target_ulong do_load_dbatu (CPUPPCState *env, int nr);
814target_ulong do_load_dbatl (CPUPPCState *env, int nr);
815void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
816void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
3fc6c082
FB		 817target_ulong do_load_sdr1 (CPUPPCState *env);
818void do_store_sdr1 (CPUPPCState *env, target_ulong value);
d9bce9d9
JM		 819#if defined(TARGET_PPC64)
820target_ulong ppc_load_asr (CPUPPCState *env);
821void ppc_store_asr (CPUPPCState *env, target_ulong value);
822#endif
3fc6c082
FB		 823target_ulong do_load_sr (CPUPPCState *env, int srnum);
824void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
76a66253
JM		 825#endif
826uint32_t ppc_load_xer (CPUPPCState *env);
827void ppc_store_xer (CPUPPCState *env, uint32_t value);
3fc6c082
FB		 828target_ulong do_load_msr (CPUPPCState *env);
829void do_store_msr (CPUPPCState *env, target_ulong value);
426613db 830void ppc_store_msr_32 (CPUPPCState *env, uint32_t value);
3fc6c082
FB		 831
832void do_compute_hflags (CPUPPCState *env);
a541f297 833
3fc6c082
FB		 834int ppc_find_by_name (const unsigned char *name, ppc_def_t **def);
835int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
836void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
837int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);
85c4adf6 838
9fddaa0c
FB		 839/* Time-base and decrementer management */
840#ifndef NO_CPU_IO_DEFS
841uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
842uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
843void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
844void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
845uint32_t cpu_ppc_load_decr (CPUPPCState *env);
846void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
d9bce9d9
JM		 847uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
848uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
849#if !defined(CONFIG_USER_ONLY)
850void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
851void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
852target_ulong load_40x_pit (CPUPPCState *env);
853void store_40x_pit (CPUPPCState *env, target_ulong val);
854void store_booke_tcr (CPUPPCState *env, target_ulong val);
855void store_booke_tsr (CPUPPCState *env, target_ulong val);
856#endif
9fddaa0c 857#endif
79aceca5
FB		 858
859#define TARGET_PAGE_BITS 12
860#include "cpu-all.h"
861
3fc6c082
FB		 862/*****************************************************************************/
863/* Registers definitions */
79aceca5 864#define ugpr(n) (env->gpr[n])
79aceca5 865
79aceca5
FB		 866#define XER_SO 31
867#define XER_OV 30
868#define XER_CA 29
3fc6c082 869#define XER_CMP 8
79aceca5 870#define XER_BC 0
3fc6c082
FB		 871#define xer_so env->xer[4]
872#define xer_ov env->xer[6]
873#define xer_ca env->xer[2]
874#define xer_cmp env->xer[1]
9a64fbe4 875#define xer_bc env->xer[0]
79aceca5 876
3fc6c082 877/* SPR definitions */
76a66253
JM		 878#define SPR_MQ (0x000)
879#define SPR_XER (0x001)
880#define SPR_601_VRTCU (0x004)
881#define SPR_601_VRTCL (0x005)
882#define SPR_601_UDECR (0x006)
883#define SPR_LR (0x008)
884#define SPR_CTR (0x009)
885#define SPR_DSISR (0x012)
886#define SPR_DAR (0x013)
887#define SPR_601_RTCU (0x014)
888#define SPR_601_RTCL (0x015)
889#define SPR_DECR (0x016)
890#define SPR_SDR1 (0x019)
891#define SPR_SRR0 (0x01A)
892#define SPR_SRR1 (0x01B)
893#define SPR_BOOKE_PID (0x030)
894#define SPR_BOOKE_DECAR (0x036)
363be49c
JM		 895#define SPR_BOOKE_CSRR0 (0x03A)
896#define SPR_BOOKE_CSRR1 (0x03B)
76a66253
JM		 897#define SPR_BOOKE_DEAR (0x03D)
898#define SPR_BOOKE_ESR (0x03E)
363be49c 899#define SPR_BOOKE_IVPR (0x03F)
76a66253
JM		 900#define SPR_8xx_EIE (0x050)
901#define SPR_8xx_EID (0x051)
902#define SPR_8xx_NRE (0x052)
903#define SPR_58x_CMPA (0x090)
904#define SPR_58x_CMPB (0x091)
905#define SPR_58x_CMPC (0x092)
906#define SPR_58x_CMPD (0x093)
907#define SPR_58x_ICR (0x094)
908#define SPR_58x_DER (0x094)
909#define SPR_58x_COUNTA (0x096)
910#define SPR_58x_COUNTB (0x097)
911#define SPR_58x_CMPE (0x098)
912#define SPR_58x_CMPF (0x099)
913#define SPR_58x_CMPG (0x09A)
914#define SPR_58x_CMPH (0x09B)
915#define SPR_58x_LCTRL1 (0x09C)
916#define SPR_58x_LCTRL2 (0x09D)
917#define SPR_58x_ICTRL (0x09E)
918#define SPR_58x_BAR (0x09F)
919#define SPR_VRSAVE (0x100)
920#define SPR_USPRG0 (0x100)
363be49c
JM		 921#define SPR_USPRG1 (0x101)
922#define SPR_USPRG2 (0x102)
923#define SPR_USPRG3 (0x103)
76a66253
JM		 924#define SPR_USPRG4 (0x104)
925#define SPR_USPRG5 (0x105)
926#define SPR_USPRG6 (0x106)
927#define SPR_USPRG7 (0x107)
928#define SPR_VTBL (0x10C)
929#define SPR_VTBU (0x10D)
930#define SPR_SPRG0 (0x110)
931#define SPR_SPRG1 (0x111)
932#define SPR_SPRG2 (0x112)
933#define SPR_SPRG3 (0x113)
934#define SPR_SPRG4 (0x114)
935#define SPR_SCOMC (0x114)
936#define SPR_SPRG5 (0x115)
937#define SPR_SCOMD (0x115)
938#define SPR_SPRG6 (0x116)
939#define SPR_SPRG7 (0x117)
940#define SPR_ASR (0x118)
941#define SPR_EAR (0x11A)
942#define SPR_TBL (0x11C)
943#define SPR_TBU (0x11D)
944#define SPR_SVR (0x11E)
945#define SPR_BOOKE_PIR (0x11E)
946#define SPR_PVR (0x11F)
947#define SPR_HSPRG0 (0x130)
948#define SPR_BOOKE_DBSR (0x130)
949#define SPR_HSPRG1 (0x131)
950#define SPR_BOOKE_DBCR0 (0x134)
951#define SPR_IBCR (0x135)
952#define SPR_BOOKE_DBCR1 (0x135)
953#define SPR_DBCR (0x136)
954#define SPR_HDEC (0x136)
955#define SPR_BOOKE_DBCR2 (0x136)
956#define SPR_HIOR (0x137)
957#define SPR_MBAR (0x137)
958#define SPR_RMOR (0x138)
959#define SPR_BOOKE_IAC1 (0x138)
960#define SPR_HRMOR (0x139)
961#define SPR_BOOKE_IAC2 (0x139)
962#define SPR_HSSR0 (0x13A)
963#define SPR_BOOKE_IAC3 (0x13A)
964#define SPR_HSSR1 (0x13B)
965#define SPR_BOOKE_IAC4 (0x13B)
966#define SPR_LPCR (0x13C)
967#define SPR_BOOKE_DAC1 (0x13C)
968#define SPR_LPIDR (0x13D)
969#define SPR_DABR2 (0x13D)
970#define SPR_BOOKE_DAC2 (0x13D)
971#define SPR_BOOKE_DVC1 (0x13E)
972#define SPR_BOOKE_DVC2 (0x13F)
973#define SPR_BOOKE_TSR (0x150)
974#define SPR_BOOKE_TCR (0x154)
975#define SPR_BOOKE_IVOR0 (0x190)
976#define SPR_BOOKE_IVOR1 (0x191)
977#define SPR_BOOKE_IVOR2 (0x192)
978#define SPR_BOOKE_IVOR3 (0x193)
979#define SPR_BOOKE_IVOR4 (0x194)
980#define SPR_BOOKE_IVOR5 (0x195)
981#define SPR_BOOKE_IVOR6 (0x196)
982#define SPR_BOOKE_IVOR7 (0x197)
983#define SPR_BOOKE_IVOR8 (0x198)
984#define SPR_BOOKE_IVOR9 (0x199)
985#define SPR_BOOKE_IVOR10 (0x19A)
986#define SPR_BOOKE_IVOR11 (0x19B)
987#define SPR_BOOKE_IVOR12 (0x19C)
988#define SPR_BOOKE_IVOR13 (0x19D)
989#define SPR_BOOKE_IVOR14 (0x19E)
990#define SPR_BOOKE_IVOR15 (0x19F)
991#define SPR_E500_SPEFSCR (0x200)
992#define SPR_E500_BBEAR (0x201)
993#define SPR_E500_BBTAR (0x202)
994#define SPR_BOOKE_ATBL (0x20E)
995#define SPR_BOOKE_ATBU (0x20F)
996#define SPR_IBAT0U (0x210)
363be49c 997#define SPR_BOOKE_IVOR32 (0x210)
76a66253 998#define SPR_IBAT0L (0x211)
363be49c 999#define SPR_BOOKE_IVOR33 (0x211)
76a66253 1000#define SPR_IBAT1U (0x212)
363be49c 1001#define SPR_BOOKE_IVOR34 (0x212)
76a66253 1002#define SPR_IBAT1L (0x213)
363be49c 1003#define SPR_BOOKE_IVOR35 (0x213)
76a66253 1004#define SPR_IBAT2U (0x214)
363be49c 1005#define SPR_BOOKE_IVOR36 (0x214)
76a66253
JM		 1006#define SPR_IBAT2L (0x215)
1007#define SPR_E500_L1CFG0 (0x215)
363be49c 1008#define SPR_BOOKE_IVOR37 (0x215)
76a66253
JM		 1009#define SPR_IBAT3U (0x216)
1010#define SPR_E500_L1CFG1 (0x216)
1011#define SPR_IBAT3L (0x217)
1012#define SPR_DBAT0U (0x218)
1013#define SPR_DBAT0L (0x219)
1014#define SPR_DBAT1U (0x21A)
1015#define SPR_DBAT1L (0x21B)
1016#define SPR_DBAT2U (0x21C)
1017#define SPR_DBAT2L (0x21D)
1018#define SPR_DBAT3U (0x21E)
1019#define SPR_DBAT3L (0x21F)
1020#define SPR_IBAT4U (0x230)
1021#define SPR_IBAT4L (0x231)
1022#define SPR_IBAT5U (0x232)
1023#define SPR_IBAT5L (0x233)
1024#define SPR_IBAT6U (0x234)
1025#define SPR_IBAT6L (0x235)
1026#define SPR_IBAT7U (0x236)
1027#define SPR_IBAT7L (0x237)
1028#define SPR_DBAT4U (0x238)
1029#define SPR_DBAT4L (0x239)
1030#define SPR_DBAT5U (0x23A)
363be49c 1031#define SPR_BOOKE_MCSRR0 (0x23A)
76a66253 1032#define SPR_DBAT5L (0x23B)
363be49c 1033#define SPR_BOOKE_MCSRR1 (0x23B)
76a66253 1034#define SPR_DBAT6U (0x23C)
363be49c 1035#define SPR_BOOKE_MCSR (0x23C)
76a66253
JM		 1036#define SPR_DBAT6L (0x23D)
1037#define SPR_E500_MCAR (0x23D)
1038#define SPR_DBAT7U (0x23E)
363be49c 1039#define SPR_BOOKE_DSRR0 (0x23E)
76a66253 1040#define SPR_DBAT7L (0x23F)
363be49c
JM		 1041#define SPR_BOOKE_DSRR1 (0x23F)
1042#define SPR_BOOKE_SPRG8 (0x25C)
1043#define SPR_BOOKE_SPRG9 (0x25D)
1044#define SPR_BOOKE_MAS0 (0x270)
1045#define SPR_BOOKE_MAS1 (0x271)
1046#define SPR_BOOKE_MAS2 (0x272)
1047#define SPR_BOOKE_MAS3 (0x273)
1048#define SPR_BOOKE_MAS4 (0x274)
1049#define SPR_BOOKE_MAS6 (0x276)
1050#define SPR_BOOKE_PID1 (0x279)
1051#define SPR_BOOKE_PID2 (0x27A)
1052#define SPR_BOOKE_TLB0CFG (0x2B0)
1053#define SPR_BOOKE_TLB1CFG (0x2B1)
1054#define SPR_BOOKE_TLB2CFG (0x2B2)
1055#define SPR_BOOKE_TLB3CFG (0x2B3)
1056#define SPR_BOOKE_EPR (0x2BE)
76a66253
JM		 1057#define SPR_440_INV0 (0x370)
1058#define SPR_440_INV1 (0x371)
1059#define SPR_440_INV2 (0x372)
1060#define SPR_440_INV3 (0x373)
1061#define SPR_440_IVT0 (0x374)
1062#define SPR_440_IVT1 (0x375)
1063#define SPR_440_IVT2 (0x376)
1064#define SPR_440_IVT3 (0x377)
1065#define SPR_440_DNV0 (0x390)
1066#define SPR_440_DNV1 (0x391)
1067#define SPR_440_DNV2 (0x392)
1068#define SPR_440_DNV3 (0x393)
1069#define SPR_440_DVT0 (0x394)
1070#define SPR_440_DVT1 (0x395)
1071#define SPR_440_DVT2 (0x396)
1072#define SPR_440_DVT3 (0x397)
1073#define SPR_440_DVLIM (0x398)
1074#define SPR_440_IVLIM (0x399)
1075#define SPR_440_RSTCFG (0x39B)
363be49c
JM		 1076#define SPR_BOOKE_DCBTRL (0x39C)
1077#define SPR_BOOKE_DCBTRH (0x39D)
1078#define SPR_BOOKE_ICBTRL (0x39E)
1079#define SPR_BOOKE_ICBTRH (0x39F)
76a66253
JM		 1080#define SPR_UMMCR0 (0x3A8)
1081#define SPR_UPMC1 (0x3A9)
1082#define SPR_UPMC2 (0x3AA)
1083#define SPR_USIA (0x3AB)
1084#define SPR_UMMCR1 (0x3AC)
1085#define SPR_UPMC3 (0x3AD)
1086#define SPR_UPMC4 (0x3AE)
1087#define SPR_USDA (0x3AF)
1088#define SPR_40x_ZPR (0x3B0)
363be49c 1089#define SPR_BOOKE_MAS7 (0x3B0)
76a66253
JM		 1090#define SPR_40x_PID (0x3B1)
1091#define SPR_440_MMUCR (0x3B2)
1092#define SPR_4xx_CCR0 (0x3B3)
363be49c 1093#define SPR_BOOKE_EPLC (0x3B3)
76a66253 1094#define SPR_405_IAC3 (0x3B4)
363be49c 1095#define SPR_BOOKE_EPSC (0x3B4)
76a66253
JM		 1096#define SPR_405_IAC4 (0x3B5)
1097#define SPR_405_DVC1 (0x3B6)
1098#define SPR_405_DVC2 (0x3B7)
1099#define SPR_MMCR0 (0x3B8)
1100#define SPR_PMC1 (0x3B9)
1101#define SPR_40x_SGR (0x3B9)
1102#define SPR_PMC2 (0x3BA)
1103#define SPR_40x_DCWR (0x3BA)
1104#define SPR_SIA (0x3BB)
1105#define SPR_405_SLER (0x3BB)
1106#define SPR_MMCR1 (0x3BC)
1107#define SPR_405_SU0R (0x3BC)
1108#define SPR_PMC3 (0x3BD)
1109#define SPR_405_DBCR1 (0x3BD)
1110#define SPR_PMC4 (0x3BE)
1111#define SPR_SDA (0x3BF)
1112#define SPR_403_VTBL (0x3CC)
1113#define SPR_403_VTBU (0x3CD)
1114#define SPR_DMISS (0x3D0)
1115#define SPR_DCMP (0x3D1)
1116#define SPR_HASH1 (0x3D2)
1117#define SPR_HASH2 (0x3D3)
363be49c 1118#define SPR_BOOKE_ICBDR (0x3D3)
76a66253
JM		 1119#define SPR_IMISS (0x3D4)
1120#define SPR_40x_ESR (0x3D4)
1121#define SPR_ICMP (0x3D5)
1122#define SPR_40x_DEAR (0x3D5)
1123#define SPR_RPA (0x3D6)
1124#define SPR_40x_EVPR (0x3D6)
1125#define SPR_403_CDBCR (0x3D7)
1126#define SPR_TCR (0x3D8)
1127#define SPR_40x_TSR (0x3D8)
1128#define SPR_IBR (0x3DA)
1129#define SPR_40x_TCR (0x3DA)
1130#define SPR_ESASR (0x3DB)
1131#define SPR_40x_PIT (0x3DB)
1132#define SPR_403_TBL (0x3DC)
1133#define SPR_403_TBU (0x3DD)
1134#define SPR_SEBR (0x3DE)
1135#define SPR_40x_SRR2 (0x3DE)
1136#define SPR_SER (0x3DF)
1137#define SPR_40x_SRR3 (0x3DF)
1138#define SPR_HID0 (0x3F0)
1139#define SPR_40x_DBSR (0x3F0)
1140#define SPR_HID1 (0x3F1)
1141#define SPR_IABR (0x3F2)
1142#define SPR_40x_DBCR0 (0x3F2)
1143#define SPR_601_HID2 (0x3F2)
1144#define SPR_E500_L1CSR0 (0x3F2)
1145#define SPR_HID2 (0x3F3)
1146#define SPR_E500_L1CSR1 (0x3F3)
1147#define SPR_440_DBDR (0x3F3)
1148#define SPR_40x_IAC1 (0x3F4)
363be49c 1149#define SPR_BOOKE_MMUCSR0 (0x3F4)
76a66253 1150#define SPR_DABR (0x3F5)
3fc6c082 1151#define DABR_MASK (~(target_ulong)0x7)
76a66253
JM		 1152#define SPR_E500_BUCSR (0x3F5)
1153#define SPR_40x_IAC2 (0x3F5)
1154#define SPR_601_HID5 (0x3F5)
1155#define SPR_40x_DAC1 (0x3F6)
1156#define SPR_40x_DAC2 (0x3F7)
363be49c 1157#define SPR_BOOKE_MMUCFG (0x3F7)
76a66253
JM		 1158#define SPR_L2PM (0x3F8)
1159#define SPR_750_HID2 (0x3F8)
1160#define SPR_L2CR (0x3F9)
1161#define SPR_IABR2 (0x3FA)
1162#define SPR_40x_DCCR (0x3FA)
1163#define SPR_ICTC (0x3FB)
1164#define SPR_40x_ICCR (0x3FB)
1165#define SPR_THRM1 (0x3FC)
1166#define SPR_403_PBL1 (0x3FC)
1167#define SPR_SP (0x3FD)
1168#define SPR_THRM2 (0x3FD)
1169#define SPR_403_PBU1 (0x3FD)
1170#define SPR_LT (0x3FE)
1171#define SPR_THRM3 (0x3FE)
1172#define SPR_FPECR (0x3FE)
1173#define SPR_403_PBL2 (0x3FE)
1174#define SPR_PIR (0x3FF)
1175#define SPR_403_PBU2 (0x3FF)
1176#define SPR_601_HID15 (0x3FF)
1177#define SPR_E500_SVR (0x3FF)
79aceca5 1178
76a66253 1179/*****************************************************************************/
9a64fbe4
FB		 1180/* Memory access type :
1181 * may be needed for precise access rights control and precise exceptions.
1182 */
79aceca5 1183enum {
9a64fbe4
FB		 1184 /* 1 bit to define user level / supervisor access */
1185 ACCESS_USER = 0x00,
1186 ACCESS_SUPER = 0x01,
1187 /* Type of instruction that generated the access */
1188 ACCESS_CODE = 0x10, /* Code fetch access */
1189 ACCESS_INT = 0x20, /* Integer load/store access */
1190 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1191 ACCESS_RES = 0x40, /* load/store with reservation */
1192 ACCESS_EXT = 0x50, /* external access */
1193 ACCESS_CACHE = 0x60, /* Cache manipulation */
1194};
1195
1196/*****************************************************************************/
1197/* Exceptions */
2be0071f
FB		 1198#define EXCP_NONE -1
1199/* PowerPC hardware exceptions : exception vectors defined in PowerPC book 3 */
1200#define EXCP_RESET 0x0100 /* System reset */
1201#define EXCP_MACHINE_CHECK 0x0200 /* Machine check exception */
1202#define EXCP_DSI 0x0300 /* Data storage exception */
1203#define EXCP_DSEG 0x0380 /* Data segment exception */
1204#define EXCP_ISI 0x0400 /* Instruction storage exception */
1205#define EXCP_ISEG 0x0480 /* Instruction segment exception */
1206#define EXCP_EXTERNAL 0x0500 /* External interruption */
1207#define EXCP_ALIGN 0x0600 /* Alignment exception */
1208#define EXCP_PROGRAM 0x0700 /* Program exception */
1209#define EXCP_NO_FP 0x0800 /* Floating point unavailable exception */
1210#define EXCP_DECR 0x0900 /* Decrementer exception */
1211#define EXCP_HDECR 0x0980 /* Hypervisor decrementer exception */
1212#define EXCP_SYSCALL 0x0C00 /* System call */
1213#define EXCP_TRACE 0x0D00 /* Trace exception */
1214#define EXCP_PERF 0x0F00 /* Performance monitor exception */
1215/* Exceptions defined in PowerPC 32 bits programming environment manual */
1216#define EXCP_FP_ASSIST 0x0E00 /* Floating-point assist */
1217/* Implementation specific exceptions */
1218/* 40x exceptions */
1219#define EXCP_40x_PIT 0x1000 /* Programmable interval timer interrupt */
1220#define EXCP_40x_FIT 0x1010 /* Fixed interval timer interrupt */
1221#define EXCP_40x_WATCHDOG 0x1020 /* Watchdog timer exception */
1222#define EXCP_40x_DTLBMISS 0x1100 /* Data TLB miss exception */
1223#define EXCP_40x_ITLBMISS 0x1200 /* Instruction TLB miss exception */
1224#define EXCP_40x_DEBUG 0x2000 /* Debug exception */
1225/* 405 specific exceptions */
1226#define EXCP_405_APU 0x0F20 /* APU unavailable exception */
1227/* TLB assist exceptions (602/603) */
1228#define EXCP_I_TLBMISS 0x1000 /* Instruction TLB miss */
1229#define EXCP_DL_TLBMISS 0x1100 /* Data load TLB miss */
1230#define EXCP_DS_TLBMISS 0x1200 /* Data store TLB miss */
1231/* Breakpoint exceptions (602/603/604/620/740/745/750/755...) */
1232#define EXCP_IABR 0x1300 /* Instruction address breakpoint */
1233#define EXCP_SMI 0x1400 /* System management interrupt */
1234/* Altivec related exceptions */
1235#define EXCP_VPU 0x0F20 /* VPU unavailable exception */
1236/* 601 specific exceptions */
1237#define EXCP_601_IO 0x0600 /* IO error exception */
1238#define EXCP_601_RUNM 0x2000 /* Run mode exception */
1239/* 602 specific exceptions */
1240#define EXCP_602_WATCHDOG 0x1500 /* Watchdog exception */
1241#define EXCP_602_EMUL 0x1600 /* Emulation trap exception */
1242/* G2 specific exceptions */
1243#define EXCP_G2_CRIT 0x0A00 /* Critical interrupt */
1244/* MPC740/745/750 & IBM 750 specific exceptions */
1245#define EXCP_THRM 0x1700 /* Thermal management interrupt */
1246/* 74xx specific exceptions */
1247#define EXCP_74xx_VPUA 0x1600 /* VPU assist exception */
1248/* 970FX specific exceptions */
1249#define EXCP_970_SOFTP 0x1500 /* Soft patch exception */
1250#define EXCP_970_MAINT 0x1600 /* Maintenance exception */
1251#define EXCP_970_THRM 0x1800 /* Thermal exception */
1252#define EXCP_970_VPUA 0x1700 /* VPU assist exception */
0487d6a8
JM		 1253/* SPE related exceptions */
1254#define EXCP_NO_SPE 0x0F20 /* SPE unavailable exception */
2be0071f
FB		 1255/* End of exception vectors area */
1256#define EXCP_PPC_MAX 0x4000
1257/* Qemu exceptions: special cases we want to stop translation */
1258#define EXCP_MTMSR 0x11000 /* mtmsr instruction: */
76a66253 1259 /* may change privilege level */
2be0071f
FB		 1260#define EXCP_BRANCH 0x11001 /* branch instruction */
1261#define EXCP_SYSCALL_USER 0x12000 /* System call in user mode only */
1262#define EXCP_INTERRUPT_CRITICAL 0x13000 /* critical IRQ */
1263
9a64fbe4
FB		 1264/* Error codes */
1265enum {
9a64fbe4
FB		 1266 /* Exception subtypes for EXCP_ALIGN */
1267 EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
1268 EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
1269 EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
1270 EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
1271 EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
1272 EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
1273 /* Exception subtypes for EXCP_PROGRAM */
79aceca5 1274 /* FP exceptions */
9a64fbe4
FB		 1275 EXCP_FP = 0x10,
1276 EXCP_FP_OX = 0x01, /* FP overflow */
1277 EXCP_FP_UX = 0x02, /* FP underflow */
1278 EXCP_FP_ZX = 0x03, /* FP divide by zero */
1279 EXCP_FP_XX = 0x04, /* FP inexact */
1280 EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */
1281 EXCP_FP_VXISI = 0x06, /* FP invalid infinite substraction */
1282 EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
1283 EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
1284 EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
1285 EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
1286 EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
1287 EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
1288 EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
79aceca5 1289 /* Invalid instruction */
9a64fbe4
FB		 1290 EXCP_INVAL = 0x20,
1291 EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
1292 EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
1293 EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
1294 EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
79aceca5 1295 /* Privileged instruction */
9a64fbe4
FB		 1296 EXCP_PRIV = 0x30,
1297 EXCP_PRIV_OPC = 0x01,
1298 EXCP_PRIV_REG = 0x02,
79aceca5 1299 /* Trap */
9a64fbe4 1300 EXCP_TRAP = 0x40,
79aceca5
FB		 1301};
1302
47103572
JM		 1303/* Hardware interruption sources:
1304 * all those exception can be raised simulteaneously
1305 */
1306enum {
1307 PPC_INTERRUPT_RESET = 0, /* Reset / critical input */
1308 PPC_INTERRUPT_MCK = 1, /* Machine check exception */
1309 PPC_INTERRUPT_EXT = 2, /* External interrupt */
1310 PPC_INTERRUPT_DECR = 3, /* Decrementer exception */
1311 PPC_INTERRUPT_HDECR = 4, /* Hypervisor decrementer exception */
1312 PPC_INTERRUPT_PIT = 5, /* Programmable inteval timer interrupt */
1313 PPC_INTERRUPT_FIT = 6, /* Fixed interval timer interrupt */
1314 PPC_INTERRUPT_WDT = 7, /* Watchdog timer interrupt */
1315 PPC_INTERRUPT_DEBUG = 8, /* External debug exception */
1316};
1317
9a64fbe4
FB		 1318/*****************************************************************************/
1319
79aceca5 1320#endif /* !defined (__CPU_PPC_H__) */
Qemu copy for testing