[qemu.git] / target-ppc / cpu.h

/*
 *  PPC emulation cpu definitions for qemu.
 * 
 *  Copyright (c) 2003 Jocelyn Mayer
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#if !defined (__CPU_PPC_H__)
#define __CPU_PPC_H__

#include <endian.h>
#include <asm/byteorder.h>

#include "cpu-defs.h"

//#define USE_OPEN_FIRMWARE

/***                          Sign extend constants                        ***/
/* 8 to 32 bits */
static inline int32_t s_ext8 (uint8_t value)
{
    int8_t *tmp = &value;

    return *tmp;
}

/* 16 to 32 bits */
static inline int32_t s_ext16 (uint16_t value)
{
    int16_t *tmp = &value;

    return *tmp;
}

/* 24 to 32 bits */
static inline int32_t s_ext24 (uint32_t value)
{
    uint16_t utmp = (value >> 8) & 0xFFFF;
    int16_t *tmp = &utmp;

    return (*tmp << 8) | (value & 0xFF);
}

#include "config.h"
#include <setjmp.h>

/* Instruction types */
enum {
    PPC_NONE     = 0x0000,
    PPC_INTEGER  = 0x0001, /* CPU has integer operations instructions        */
    PPC_FLOAT    = 0x0002, /* CPU has floating point operations instructions */
    PPC_FLOW     = 0x0004, /* CPU has flow control instructions              */
    PPC_MEM      = 0x0008, /* CPU has virtual memory instructions            */
    PPC_RES      = 0x0010, /* CPU has ld/st with reservation instructions    */
    PPC_CACHE    = 0x0020, /* CPU has cache control instructions             */
    PPC_MISC     = 0x0040, /* CPU has spr/msr access instructions            */
    PPC_EXTERN   = 0x0080, /* CPU has external control instructions          */
    PPC_SEGMENT  = 0x0100, /* CPU has memory segment instructions            */
    PPC_CACHE_OPT= 0x0200,
    PPC_FLOAT_OPT= 0x0400,
    PPC_MEM_OPT  = 0x0800,
};

#define PPC_COMMON  (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM |           \
                     PPC_RES | PPC_CACHE | PPC_MISC | PPC_SEGMENT)
/* PPC 740/745/750/755 (aka G3) has external access instructions */
#define PPC_750 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM |               \
                 PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT)

/* Supervisor mode registers */
/* Machine state register */
#define MSR_POW 18
#define MSR_ILE 16
#define MSR_EE  15
#define MSR_PR  14
#define MSR_FP  13
#define MSR_ME  12
#define MSR_FE0 11
#define MSR_SE  10
#define MSR_BE  9
#define MSR_FE1 8
#define MSR_IP 6
#define MSR_IR 5
#define MSR_DR 4
#define MSR_RI 1
#define MSR_LE 0
#define msr_pow env->msr[MSR_POW]
#define msr_ile env->msr[MSR_ILE]
#define msr_ee  env->msr[MSR_EE]
#define msr_pr  env->msr[MSR_PR]
#define msr_fp  env->msr[MSR_FP]
#define msr_me  env->msr[MSR_ME]
#define msr_fe0 env->msr[MSR_FE0]
#define msr_se  env->msr[MSR_SE]
#define msr_be  env->msr[MSR_BE]
#define msr_fe1 env->msr[MSR_FE1]
#define msr_ip  env->msr[MSR_IP]
#define msr_ir  env->msr[MSR_IR]
#define msr_dr  env->msr[MSR_DR]
#define msr_ri  env->msr[MSR_RI]
#define msr_le  env->msr[MSR_LE]

/* Segment registers */
typedef struct CPUPPCState {
    /* general purpose registers */
    uint32_t gpr[32];
    /* floating point registers */
    double fpr[32];
    /* segment registers */
    uint32_t sdr1;
    uint32_t sr[16];
    /* XER */
    uint8_t xer[4];
    /* Reservation address */
    uint32_t reserve;
    /* machine state register */
    uint8_t msr[32];
    /* condition register */
    uint8_t crf[8];
    /* floating point status and control register */
    uint8_t fpscr[8];
    uint32_t nip;
    /* special purpose registers */
    uint32_t lr;
    uint32_t ctr;
    /* Time base */
    uint32_t tb[2];
    /* decrementer */
    uint32_t decr;
    /* BATs */
    uint32_t DBAT[2][8];
    uint32_t IBAT[2][8];
    /* all others */
    uint32_t spr[1024];
    /* qemu dedicated */
     /* temporary float registers */
    double ft0;
    double ft1;
    double ft2;
    int interrupt_request;
    jmp_buf jmp_env;
    int exception_index;
    int error_code;
    uint32_t exceptions; /* exception queue */
    uint32_t errors[16];
    int user_mode_only; /* user mode only simulation */
    struct TranslationBlock *current_tb; /* currently executing TB */
    /* soft mmu support */
    /* 0 = kernel, 1 = user */
    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
    /* user data */
    void *opaque;
} CPUPPCState;

CPUPPCState *cpu_ppc_init(void);
int cpu_ppc_exec(CPUPPCState *s);
void cpu_ppc_close(CPUPPCState *s);
/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
struct siginfo;
int cpu_ppc_signal_handler(int host_signum, struct siginfo *info, 
                           void *puc);

void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags);
void cpu_loop_exit(void);
void dump_stack (CPUPPCState *env);
uint32_t _load_xer (void);
void _store_xer (uint32_t value);
uint32_t _load_msr (void);
void _store_msr (uint32_t value);
void do_interrupt (CPUPPCState *env);

#define TARGET_PAGE_BITS 12
#include "cpu-all.h"

#define ugpr(n) (env->gpr[n])
#define fprd(n) (env->fpr[n])
#define fprs(n) ((float)env->fpr[n])
#define fpru(n) ((uint32_t)env->fpr[n])
#define fpri(n) ((int32_t)env->fpr[n])

#define SPR_ENCODE(sprn)                               \
(((sprn) >> 5) | (((sprn) & 0x1F) << 5))

/* User mode SPR */
#define spr(n) env->spr[n]
#define XER_SO 31
#define XER_OV 30
#define XER_CA 29
#define XER_BC 0
#define xer_so env->xer[3]
#define xer_ov env->xer[2]
#define xer_ca env->xer[1]
#define xer_bc env->xer[0]

#define XER    SPR_ENCODE(1)
#define LR     SPR_ENCODE(8)
#define CTR    SPR_ENCODE(9)
/* VEA mode SPR */
#define V_TBL  SPR_ENCODE(268)
#define V_TBU  SPR_ENCODE(269)
/* supervisor mode SPR */
#define DSISR  SPR_ENCODE(18)
#define DAR    SPR_ENCODE(19)
#define DECR   SPR_ENCODE(22)
#define SDR1   SPR_ENCODE(25)
#define SRR0   SPR_ENCODE(26)
#define SRR1   SPR_ENCODE(27)
#define SPRG0  SPR_ENCODE(272)
#define SPRG1  SPR_ENCODE(273)
#define SPRG2  SPR_ENCODE(274)
#define SPRG3  SPR_ENCODE(275)
#define SPRG4  SPR_ENCODE(276)
#define SPRG5  SPR_ENCODE(277)
#define SPRG6  SPR_ENCODE(278)
#define SPRG7  SPR_ENCODE(279)
#define ASR    SPR_ENCODE(280)
#define EAR    SPR_ENCODE(282)
#define O_TBL  SPR_ENCODE(284)
#define O_TBU  SPR_ENCODE(285)
#define PVR    SPR_ENCODE(287)
#define IBAT0U SPR_ENCODE(528)
#define IBAT0L SPR_ENCODE(529)
#define IBAT1U SPR_ENCODE(530)
#define IBAT1L SPR_ENCODE(531)
#define IBAT2U SPR_ENCODE(532)
#define IBAT2L SPR_ENCODE(533)
#define IBAT3U SPR_ENCODE(534)
#define IBAT3L SPR_ENCODE(535)
#define DBAT0U SPR_ENCODE(536)
#define DBAT0L SPR_ENCODE(537)
#define DBAT1U SPR_ENCODE(538)
#define DBAT1L SPR_ENCODE(539)
#define DBAT2U SPR_ENCODE(540)
#define DBAT2L SPR_ENCODE(541)
#define DBAT3U SPR_ENCODE(542)
#define DBAT3L SPR_ENCODE(543)
#define IBAT4U SPR_ENCODE(560)
#define IBAT4L SPR_ENCODE(561)
#define IBAT5U SPR_ENCODE(562)
#define IBAT5L SPR_ENCODE(563)
#define IBAT6U SPR_ENCODE(564)
#define IBAT6L SPR_ENCODE(565)
#define IBAT7U SPR_ENCODE(566)
#define IBAT7L SPR_ENCODE(567)
#define DBAT4U SPR_ENCODE(568)
#define DBAT4L SPR_ENCODE(569)
#define DBAT5U SPR_ENCODE(570)
#define DBAT5L SPR_ENCODE(571)
#define DBAT6U SPR_ENCODE(572)
#define DBAT6L SPR_ENCODE(573)
#define DBAT7U SPR_ENCODE(574)
#define DBAT7L SPR_ENCODE(575)
#define DABR   SPR_ENCODE(1013)
#define DABR_MASK 0xFFFFFFF8
#define FPECR  SPR_ENCODE(1022)
#define PIR    SPR_ENCODE(1023)

#define TARGET_PAGE_BITS 12
#include "cpu-all.h"

CPUPPCState *cpu_ppc_init(void);
int cpu_ppc_exec(CPUPPCState *s);
void cpu_ppc_close(CPUPPCState *s);
void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags);
void PPC_init_hw (CPUPPCState *env, uint32_t mem_size,
                  uint32_t kernel_addr, uint32_t kernel_size,
                  uint32_t stack_addr, int boot_device);

/* Memory access type :
 * may be needed for precise access rights control and precise exceptions.
 */
enum {
    /* 1 bit to define user level / supervisor access */
    ACCESS_USER  = 0x00,
    ACCESS_SUPER = 0x01,
    /* Type of instruction that generated the access */
    ACCESS_CODE  = 0x10, /* Code fetch access                */
    ACCESS_INT   = 0x20, /* Integer load/store access        */
    ACCESS_FLOAT = 0x30, /* floating point load/store access */
    ACCESS_RES   = 0x40, /* load/store with reservation      */
    ACCESS_EXT   = 0x50, /* external access                  */
    ACCESS_CACHE = 0x60, /* Cache manipulation               */
};

/*****************************************************************************/
/* Exceptions */
enum {
    EXCP_NONE          = -1,
    /* PPC hardware exceptions : exception vector / 0x100 */
    EXCP_RESET         = 0x01, /* System reset                     */
    EXCP_MACHINE_CHECK = 0x02, /* Machine check exception          */
    EXCP_DSI           = 0x03, /* Impossible memory access         */
    EXCP_ISI           = 0x04, /* Impossible instruction fetch     */
    EXCP_EXTERNAL      = 0x05, /* External interruption            */
    EXCP_ALIGN         = 0x06, /* Alignment exception              */
    EXCP_PROGRAM       = 0x07, /* Program exception                */
    EXCP_NO_FP         = 0x08, /* No floating point                */
    EXCP_DECR          = 0x09, /* Decrementer exception            */
    EXCP_RESA          = 0x0A, /* Implementation specific          */
    EXCP_RESB          = 0x0B, /* Implementation specific          */
    EXCP_SYSCALL       = 0x0C, /* System call                      */
    EXCP_TRACE         = 0x0D, /* Trace exception (optional)       */
    EXCP_FP_ASSIST     = 0x0E, /* Floating-point assist (optional) */
    /* MPC740/745/750 & IBM 750 */
    EXCP_PERF          = 0x0F,  /* Performance monitor              */
    EXCP_IABR          = 0x13,  /* Instruction address breakpoint   */
    EXCP_SMI           = 0x14,  /* System management interrupt      */
    EXCP_THRM          = 0x15,  /* Thermal management interrupt     */
    /* MPC755 */
    EXCP_TLBMISS       = 0x10,  /* Instruction TLB miss             */
    EXCP_TLBMISS_DL    = 0x11,  /* Data TLB miss for load           */
    EXCP_TLBMISS_DS    = 0x12,  /* Data TLB miss for store          */
    EXCP_PPC_MAX       = 0x16,
    /* Qemu exception */
    EXCP_OFCALL        = 0x20,  /* Call open-firmware emulator      */
    EXCP_RTASCALL      = 0x21,  /* Call RTAS emulator               */
    /* Special cases where we want to stop translation */
    EXCP_MTMSR         = 0x104, /* mtmsr instruction:               */
                                /* may change privilege level       */
    EXCP_BRANCH        = 0x108, /* branch instruction               */
    EXCP_RFI           = 0x10C, /* return from interrupt            */
    EXCP_SYSCALL_USER  = 0x110, /* System call in user mode only    */
};
/* Error codes */
enum {
    /* Exception subtypes for EXCP_DSI                              */
    EXCP_DSI_TRANSLATE = 0x01,  /* Data address can't be translated */
    EXCP_DSI_NOTSUP    = 0x02,  /* Access type not supported        */
    EXCP_DSI_PROT      = 0x03,  /* Memory protection violation      */
    EXCP_DSI_EXTERNAL  = 0x04,  /* External access disabled         */
    EXCP_DSI_DABR      = 0x05,  /* Data address breakpoint          */
    /* flags for EXCP_DSI */
    EXCP_DSI_DIRECT    = 0x10,
    EXCP_DSI_STORE     = 0x20,
    EXCP_ECXW          = 0x40,
    /* Exception subtypes for EXCP_ISI                              */
    EXCP_ISI_TRANSLATE = 0x01,  /* Code address can't be translated */
    EXCP_ISI_NOEXEC    = 0x02,  /* Try to fetch from a data segment */
    EXCP_ISI_GUARD     = 0x03,  /* Fetch from guarded memory        */
    EXCP_ISI_PROT      = 0x04,  /* Memory protection violation      */
    /* Exception subtypes for EXCP_ALIGN                            */
    EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception           */
    EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store */
    EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access    */
    EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary */
    EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary  */
    EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access           */
    /* Exception subtypes for EXCP_PROGRAM                          */
    /* FP exceptions */
    EXCP_FP            = 0x10,
    EXCP_FP_OX         = 0x01,  /* FP overflow                      */
    EXCP_FP_UX         = 0x02,  /* FP underflow                     */
    EXCP_FP_ZX         = 0x03,  /* FP divide by zero                */
    EXCP_FP_XX         = 0x04,  /* FP inexact                       */
    EXCP_FP_VXNAN      = 0x05,  /* FP invalid SNaN op               */
    EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite substraction */
    EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide       */
    EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide           */
    EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero       */
    EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare               */
    EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation             */
    EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root           */
    EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion    */
    /* Invalid instruction */
    EXCP_INVAL         = 0x20,
    EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction              */
    EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction         */
    EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access               */
    EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr */
    /* Privileged instruction */
    EXCP_PRIV          = 0x30,
    EXCP_PRIV_OPC      = 0x01,
    EXCP_PRIV_REG      = 0x02,
    /* Trap */
    EXCP_TRAP          = 0x40,
};

/*****************************************************************************/

#endif /* !defined (__CPU_PPC_H__) */
Commit	Line	Data
79aceca5 FB	1	/*
	2	* PPC emulation cpu definitions for qemu.
	3	*
	4	* Copyright (c) 2003 Jocelyn Mayer
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#if !defined (__CPU_PPC_H__)
	21	#define __CPU_PPC_H__
	22
	23	#include <endian.h>
	24	#include <asm/byteorder.h>
	25
	26	#include "cpu-defs.h"
	27
9a64fbe4 FB	28	//#define USE_OPEN_FIRMWARE
9a64fbe4 FB	29
79aceca5 FB	30	/* Sign extend constants */
	31	/* 8 to 32 bits */
	32	static inline int32_t s_ext8 (uint8_t value)
	33	{
	34	int8_t *tmp = &value;
	35
	36	return *tmp;
	37	}
	38
	39	/* 16 to 32 bits */
	40	static inline int32_t s_ext16 (uint16_t value)
	41	{
	42	int16_t *tmp = &value;
	43
	44	return *tmp;
	45	}
	46
	47	/* 24 to 32 bits */
	48	static inline int32_t s_ext24 (uint32_t value)
	49	{
	50	uint16_t utmp = (value >> 8) & 0xFFFF;
	51	int16_t *tmp = &utmp;
	52
	53	return (*tmp << 8) \| (value & 0xFF);
	54	}
	55
	56	#include "config.h"
	57	#include <setjmp.h>
	58
9a64fbe4 FB	59	/* Instruction types */
	60	enum {
	61	PPC_NONE = 0x0000,
	62	PPC_INTEGER = 0x0001, /* CPU has integer operations instructions */
	63	PPC_FLOAT = 0x0002, /* CPU has floating point operations instructions */
	64	PPC_FLOW = 0x0004, /* CPU has flow control instructions */
	65	PPC_MEM = 0x0008, /* CPU has virtual memory instructions */
	66	PPC_RES = 0x0010, /* CPU has ld/st with reservation instructions */
	67	PPC_CACHE = 0x0020, /* CPU has cache control instructions */
	68	PPC_MISC = 0x0040, /* CPU has spr/msr access instructions */
	69	PPC_EXTERN = 0x0080, /* CPU has external control instructions */
	70	PPC_SEGMENT = 0x0100, /* CPU has memory segment instructions */
	71	PPC_CACHE_OPT= 0x0200,
	72	PPC_FLOAT_OPT= 0x0400,
	73	PPC_MEM_OPT = 0x0800,
	74	};
79aceca5	75
9a64fbe4 FB	76	#define PPC_COMMON (PPC_INTEGER \| PPC_FLOAT \| PPC_FLOW \| PPC_MEM \| \
	77	PPC_RES \| PPC_CACHE \| PPC_MISC \| PPC_SEGMENT)
	78	/* PPC 740/745/750/755 (aka G3) has external access instructions */
	79	#define PPC_750 (PPC_INTEGER \| PPC_FLOAT \| PPC_FLOW \| PPC_MEM \| \
	80	PPC_RES \| PPC_CACHE \| PPC_MISC \| PPC_EXTERN \| PPC_SEGMENT)
79aceca5 FB	81
	82	/* Supervisor mode registers */
	83	/* Machine state register */
	84	#define MSR_POW 18
	85	#define MSR_ILE 16
	86	#define MSR_EE 15
	87	#define MSR_PR 14
	88	#define MSR_FP 13
	89	#define MSR_ME 12
	90	#define MSR_FE0 11
	91	#define MSR_SE 10
	92	#define MSR_BE 9
	93	#define MSR_FE1 8
	94	#define MSR_IP 6
	95	#define MSR_IR 5
	96	#define MSR_DR 4
	97	#define MSR_RI 1
	98	#define MSR_LE 0
	99	#define msr_pow env->msr[MSR_POW]
	100	#define msr_ile env->msr[MSR_ILE]
	101	#define msr_ee env->msr[MSR_EE]
	102	#define msr_pr env->msr[MSR_PR]
	103	#define msr_fp env->msr[MSR_FP]
	104	#define msr_me env->msr[MSR_ME]
	105	#define msr_fe0 env->msr[MSR_FE0]
	106	#define msr_se env->msr[MSR_SE]
	107	#define msr_be env->msr[MSR_BE]
	108	#define msr_fe1 env->msr[MSR_FE1]
	109	#define msr_ip env->msr[MSR_IP]
	110	#define msr_ir env->msr[MSR_IR]
	111	#define msr_dr env->msr[MSR_DR]
	112	#define msr_ri env->msr[MSR_RI]
	113	#define msr_le env->msr[MSR_LE]
	114
	115	/* Segment registers */
79aceca5 FB	116	typedef struct CPUPPCState {
	117	/* general purpose registers */
	118	uint32_t gpr[32];
	119	/* floating point registers */
fb0eaffc	120	double fpr[32];
79aceca5	121	/* segment registers */
9a64fbe4 FB	122	uint32_t sdr1;
9a64fbe4 FB	123	uint32_t sr[16];
79aceca5	124	/* XER */
9a64fbe4	125	uint8_t xer[4];
79aceca5 FB	126	/* Reservation address */
	127	uint32_t reserve;
	128	/* machine state register */
	129	uint8_t msr[32];
	130	/* condition register */
	131	uint8_t crf[8];
	132	/* floating point status and control register */
9a64fbe4	133	uint8_t fpscr[8];
79aceca5	134	uint32_t nip;
9a64fbe4 FB	135	/* special purpose registers */
	136	uint32_t lr;
	137	uint32_t ctr;
	138	/* Time base */
	139	uint32_t tb[2];
	140	/* decrementer */
	141	uint32_t decr;
	142	/* BATs */
	143	uint32_t DBAT[2][8];
	144	uint32_t IBAT[2][8];
	145	/* all others */
	146	uint32_t spr[1024];
79aceca5	147	/* qemu dedicated */
fb0eaffc FB	148	/* temporary float registers */
	149	double ft0;
	150	double ft1;
	151	double ft2;
79aceca5 FB	152	int interrupt_request;
	153	jmp_buf jmp_env;
	154	int exception_index;
	155	int error_code;
9a64fbe4 FB	156	uint32_t exceptions; /* exception queue */
9a64fbe4 FB	157	uint32_t errors[16];
79aceca5 FB	158	int user_mode_only; /* user mode only simulation */
79aceca5 FB	159	struct TranslationBlock current_tb; / currently executing TB */
9a64fbe4 FB	160	/* soft mmu support */
	161	/* 0 = kernel, 1 = user */
	162	CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
	163	CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
79aceca5 FB	164	/* user data */
	165	void *opaque;
	166	} CPUPPCState;
	167
	168	CPUPPCState *cpu_ppc_init(void);
	169	int cpu_ppc_exec(CPUPPCState *s);
	170	void cpu_ppc_close(CPUPPCState *s);
	171	/* you can call this signal handler from your SIGBUS and SIGSEGV
	172	signal handlers to inform the virtual CPU of exceptions. non zero
	173	is returned if the signal was handled by the virtual CPU. */
	174	struct siginfo;
	175	int cpu_ppc_signal_handler(int host_signum, struct siginfo *info,
	176	void *puc);
	177
	178	void cpu_ppc_dump_state(CPUPPCState env, FILE f, int flags);
9a64fbe4 FB	179	void cpu_loop_exit(void);
	180	void dump_stack (CPUPPCState *env);
	181	uint32_t _load_xer (void);
	182	void _store_xer (uint32_t value);
	183	uint32_t _load_msr (void);
	184	void _store_msr (uint32_t value);
	185	void do_interrupt (CPUPPCState *env);
79aceca5 FB	186
	187	#define TARGET_PAGE_BITS 12
	188	#include "cpu-all.h"
	189
	190	#define ugpr(n) (env->gpr[n])
9a64fbe4 FB	191	#define fprd(n) (env->fpr[n])
	192	#define fprs(n) ((float)env->fpr[n])
	193	#define fpru(n) ((uint32_t)env->fpr[n])
	194	#define fpri(n) ((int32_t)env->fpr[n])
79aceca5 FB	195
	196	#define SPR_ENCODE(sprn) \
	197	(((sprn) >> 5) \| (((sprn) & 0x1F) << 5))
	198
	199	/* User mode SPR */
	200	#define spr(n) env->spr[n]
79aceca5 FB	201	#define XER_SO 31
	202	#define XER_OV 30
	203	#define XER_CA 29
	204	#define XER_BC 0
9a64fbe4 FB	205	#define xer_so env->xer[3]
	206	#define xer_ov env->xer[2]
	207	#define xer_ca env->xer[1]
	208	#define xer_bc env->xer[0]
79aceca5	209
9a64fbe4 FB	210	#define XER SPR_ENCODE(1)
	211	#define LR SPR_ENCODE(8)
	212	#define CTR SPR_ENCODE(9)
79aceca5	213	/* VEA mode SPR */
9a64fbe4 FB	214	#define V_TBL SPR_ENCODE(268)
9a64fbe4 FB	215	#define V_TBU SPR_ENCODE(269)
79aceca5	216	/* supervisor mode SPR */
9a64fbe4 FB	217	#define DSISR SPR_ENCODE(18)
	218	#define DAR SPR_ENCODE(19)
	219	#define DECR SPR_ENCODE(22)
	220	#define SDR1 SPR_ENCODE(25)
	221	#define SRR0 SPR_ENCODE(26)
	222	#define SRR1 SPR_ENCODE(27)
	223	#define SPRG0 SPR_ENCODE(272)
	224	#define SPRG1 SPR_ENCODE(273)
	225	#define SPRG2 SPR_ENCODE(274)
	226	#define SPRG3 SPR_ENCODE(275)
	227	#define SPRG4 SPR_ENCODE(276)
	228	#define SPRG5 SPR_ENCODE(277)
	229	#define SPRG6 SPR_ENCODE(278)
	230	#define SPRG7 SPR_ENCODE(279)
	231	#define ASR SPR_ENCODE(280)
	232	#define EAR SPR_ENCODE(282)
	233	#define O_TBL SPR_ENCODE(284)
	234	#define O_TBU SPR_ENCODE(285)
	235	#define PVR SPR_ENCODE(287)
	236	#define IBAT0U SPR_ENCODE(528)
	237	#define IBAT0L SPR_ENCODE(529)
	238	#define IBAT1U SPR_ENCODE(530)
	239	#define IBAT1L SPR_ENCODE(531)
	240	#define IBAT2U SPR_ENCODE(532)
	241	#define IBAT2L SPR_ENCODE(533)
	242	#define IBAT3U SPR_ENCODE(534)
	243	#define IBAT3L SPR_ENCODE(535)
	244	#define DBAT0U SPR_ENCODE(536)
	245	#define DBAT0L SPR_ENCODE(537)
	246	#define DBAT1U SPR_ENCODE(538)
	247	#define DBAT1L SPR_ENCODE(539)
	248	#define DBAT2U SPR_ENCODE(540)
	249	#define DBAT2L SPR_ENCODE(541)
	250	#define DBAT3U SPR_ENCODE(542)
	251	#define DBAT3L SPR_ENCODE(543)
	252	#define IBAT4U SPR_ENCODE(560)
	253	#define IBAT4L SPR_ENCODE(561)
	254	#define IBAT5U SPR_ENCODE(562)
	255	#define IBAT5L SPR_ENCODE(563)
	256	#define IBAT6U SPR_ENCODE(564)
	257	#define IBAT6L SPR_ENCODE(565)
	258	#define IBAT7U SPR_ENCODE(566)
	259	#define IBAT7L SPR_ENCODE(567)
	260	#define DBAT4U SPR_ENCODE(568)
	261	#define DBAT4L SPR_ENCODE(569)
	262	#define DBAT5U SPR_ENCODE(570)
	263	#define DBAT5L SPR_ENCODE(571)
	264	#define DBAT6U SPR_ENCODE(572)
	265	#define DBAT6L SPR_ENCODE(573)
	266	#define DBAT7U SPR_ENCODE(574)
	267	#define DBAT7L SPR_ENCODE(575)
	268	#define DABR SPR_ENCODE(1013)
79aceca5	269	#define DABR_MASK 0xFFFFFFF8
9a64fbe4 FB	270	#define FPECR SPR_ENCODE(1022)
9a64fbe4 FB	271	#define PIR SPR_ENCODE(1023)
79aceca5 FB	272
	273	#define TARGET_PAGE_BITS 12
	274	#include "cpu-all.h"
	275
	276	CPUPPCState *cpu_ppc_init(void);
	277	int cpu_ppc_exec(CPUPPCState *s);
	278	void cpu_ppc_close(CPUPPCState *s);
	279	void cpu_ppc_dump_state(CPUPPCState env, FILE f, int flags);
9a64fbe4 FB	280	void PPC_init_hw (CPUPPCState *env, uint32_t mem_size,
	281	uint32_t kernel_addr, uint32_t kernel_size,
	282	uint32_t stack_addr, int boot_device);
79aceca5	283
9a64fbe4 FB	284	/* Memory access type :
	285	* may be needed for precise access rights control and precise exceptions.
	286	*/
79aceca5	287	enum {
9a64fbe4 FB	288	/* 1 bit to define user level / supervisor access */
	289	ACCESS_USER = 0x00,
	290	ACCESS_SUPER = 0x01,
	291	/* Type of instruction that generated the access */
	292	ACCESS_CODE = 0x10, /* Code fetch access */
	293	ACCESS_INT = 0x20, /* Integer load/store access */
	294	ACCESS_FLOAT = 0x30, /* floating point load/store access */
	295	ACCESS_RES = 0x40, /* load/store with reservation */
	296	ACCESS_EXT = 0x50, /* external access */
	297	ACCESS_CACHE = 0x60, /* Cache manipulation */
	298	};
	299
	300	/*****************************************************************************/
	301	/* Exceptions */
	302	enum {
	303	EXCP_NONE = -1,
79aceca5 FB	304	/* PPC hardware exceptions : exception vector / 0x100 */
	305	EXCP_RESET = 0x01, /* System reset */
	306	EXCP_MACHINE_CHECK = 0x02, /* Machine check exception */
	307	EXCP_DSI = 0x03, /* Impossible memory access */
	308	EXCP_ISI = 0x04, /* Impossible instruction fetch */
	309	EXCP_EXTERNAL = 0x05, /* External interruption */
	310	EXCP_ALIGN = 0x06, /* Alignment exception */
	311	EXCP_PROGRAM = 0x07, /* Program exception */
	312	EXCP_NO_FP = 0x08, /* No floating point */
	313	EXCP_DECR = 0x09, /* Decrementer exception */
	314	EXCP_RESA = 0x0A, /* Implementation specific */
	315	EXCP_RESB = 0x0B, /* Implementation specific */
	316	EXCP_SYSCALL = 0x0C, /* System call */
	317	EXCP_TRACE = 0x0D, /* Trace exception (optional) */
	318	EXCP_FP_ASSIST = 0x0E, /* Floating-point assist (optional) */
9a64fbe4 FB	319	/* MPC740/745/750 & IBM 750 */
	320	EXCP_PERF = 0x0F, /* Performance monitor */
	321	EXCP_IABR = 0x13, /* Instruction address breakpoint */
	322	EXCP_SMI = 0x14, /* System management interrupt */
	323	EXCP_THRM = 0x15, /* Thermal management interrupt */
	324	/* MPC755 */
	325	EXCP_TLBMISS = 0x10, /* Instruction TLB miss */
	326	EXCP_TLBMISS_DL = 0x11, /* Data TLB miss for load */
	327	EXCP_TLBMISS_DS = 0x12, /* Data TLB miss for store */
	328	EXCP_PPC_MAX = 0x16,
	329	/* Qemu exception */
	330	EXCP_OFCALL = 0x20, /* Call open-firmware emulator */
	331	EXCP_RTASCALL = 0x21, /* Call RTAS emulator */
	332	/* Special cases where we want to stop translation */
	333	EXCP_MTMSR = 0x104, /* mtmsr instruction: */
	334	/* may change privilege level */
	335	EXCP_BRANCH = 0x108, /* branch instruction */
	336	EXCP_RFI = 0x10C, /* return from interrupt */
	337	EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
	338	};
	339	/* Error codes */
	340	enum {
	341	/* Exception subtypes for EXCP_DSI */
	342	EXCP_DSI_TRANSLATE = 0x01, /* Data address can't be translated */
	343	EXCP_DSI_NOTSUP = 0x02, /* Access type not supported */
	344	EXCP_DSI_PROT = 0x03, /* Memory protection violation */
	345	EXCP_DSI_EXTERNAL = 0x04, /* External access disabled */
	346	EXCP_DSI_DABR = 0x05, /* Data address breakpoint */
	347	/* flags for EXCP_DSI */
	348	EXCP_DSI_DIRECT = 0x10,
	349	EXCP_DSI_STORE = 0x20,
	350	EXCP_ECXW = 0x40,
	351	/* Exception subtypes for EXCP_ISI */
	352	EXCP_ISI_TRANSLATE = 0x01, /* Code address can't be translated */
	353	EXCP_ISI_NOEXEC = 0x02, /* Try to fetch from a data segment */
	354	EXCP_ISI_GUARD = 0x03, /* Fetch from guarded memory */
	355	EXCP_ISI_PROT = 0x04, /* Memory protection violation */
	356	/* Exception subtypes for EXCP_ALIGN */
	357	EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
	358	EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
	359	EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
	360	EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
	361	EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
	362	EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
	363	/* Exception subtypes for EXCP_PROGRAM */
79aceca5	364	/* FP exceptions */
9a64fbe4 FB	365	EXCP_FP = 0x10,
	366	EXCP_FP_OX = 0x01, /* FP overflow */
	367	EXCP_FP_UX = 0x02, /* FP underflow */
	368	EXCP_FP_ZX = 0x03, /* FP divide by zero */
	369	EXCP_FP_XX = 0x04, /* FP inexact */
	370	EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */
	371	EXCP_FP_VXISI = 0x06, /* FP invalid infinite substraction */
	372	EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
	373	EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
	374	EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
	375	EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
	376	EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
	377	EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
	378	EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
79aceca5	379	/* Invalid instruction */
9a64fbe4 FB	380	EXCP_INVAL = 0x20,
	381	EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
	382	EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
	383	EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
	384	EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
79aceca5	385	/* Privileged instruction */
9a64fbe4 FB	386	EXCP_PRIV = 0x30,
	387	EXCP_PRIV_OPC = 0x01,
	388	EXCP_PRIV_REG = 0x02,
79aceca5	389	/* Trap */
9a64fbe4	390	EXCP_TRAP = 0x40,
79aceca5 FB	391	};
79aceca5 FB	392
9a64fbe4 FB	393	/*****************************************************************************/
9a64fbe4 FB	394
79aceca5	395	#endif /* !defined (__CPU_PPC_H__) */