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Rework PowerPC 440 TLB management (thanks to Hollis Blanchard)
[qemu.git] / target-ppc / cpu.h
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation cpu definitions for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#if !defined (__CPU_PPC_H__)
21#define __CPU_PPC_H__
22
3fc6c082 23#include "config.h"
de270b3c 24#include <inttypes.h>
3fc6c082 25
76a66253
JM		 26#if defined (TARGET_PPC64)
27typedef uint64_t ppc_gpr_t;
0487d6a8 28#define TARGET_GPR_BITS 64
d9d7210c 29#define TARGET_LONG_BITS 64
76a66253 30#define REGX "%016" PRIx64
35cdaad6
JM		 31#define TARGET_PAGE_BITS 12
32#elif defined(TARGET_PPCEMB)
8b67546f 33/* BookE have 36 bits physical address space */
e96efcfc 34#define TARGET_PHYS_ADDR_BITS 64
76a66253
JM		 35/* GPR are 64 bits: used by vector extension */
36typedef uint64_t ppc_gpr_t;
0487d6a8 37#define TARGET_GPR_BITS 64
d9d7210c 38#define TARGET_LONG_BITS 32
1b9eb036 39#define REGX "%016" PRIx64
d9d7210c
JM		 40#if defined(CONFIG_USER_ONLY)
41/* It looks like a lot of Linux programs assume page size
42 * is 4kB long. This is evil, but we have to deal with it...
43 */
44#define TARGET_PAGE_BITS 12
45#else
35cdaad6
JM		 46/* Pages can be 1 kB small */
47#define TARGET_PAGE_BITS 10
d9d7210c
JM		 48#endif
49#else
50#if (HOST_LONG_BITS >= 64)
51/* When using 64 bits temporary registers,
52 * we can use 64 bits GPR with no extra cost
53 * It's even an optimization as it will prevent
54 * the compiler to do unuseful masking in the micro-ops.
55 */
56typedef uint64_t ppc_gpr_t;
57#define TARGET_GPR_BITS 64
71c8b8fd 58#define REGX "%08" PRIx64
76a66253
JM		 59#else
60typedef uint32_t ppc_gpr_t;
0487d6a8 61#define TARGET_GPR_BITS 32
71c8b8fd 62#define REGX "%08" PRIx32
d9d7210c
JM		 63#endif
64#define TARGET_LONG_BITS 32
35cdaad6 65#define TARGET_PAGE_BITS 12
76a66253 66#endif
3cf1e035 67
79aceca5
FB		 68#include "cpu-defs.h"
69
e96efcfc
JM		 70#define ADDRX TARGET_FMT_lx
71#define PADDRX TARGET_FMT_plx
72
79aceca5
FB		 73#include <setjmp.h>
74
4ecc3190
FB		 75#include "softfloat.h"
76
1fddef4b
FB		 77#define TARGET_HAS_ICE 1
78
76a66253
JM		 79#if defined (TARGET_PPC64)
80#define ELF_MACHINE EM_PPC64
81#else
82#define ELF_MACHINE EM_PPC
83#endif
9042c0e2 84
fdabc366
FB		 85/* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC
86 * have different cache line sizes
87 */
88#define ICACHE_LINE_SIZE 32
89#define DCACHE_LINE_SIZE 32
90
3fc6c082
FB		 91/*****************************************************************************/
92/* PVR definitions for most known PowerPC */
93enum {
94 /* PowerPC 401 cores */
95 CPU_PPC_401A1 = 0x00210000,
96 CPU_PPC_401B2 = 0x00220000,
97 CPU_PPC_401C2 = 0x00230000,
98 CPU_PPC_401D2 = 0x00240000,
99 CPU_PPC_401E2 = 0x00250000,
100 CPU_PPC_401F2 = 0x00260000,
101 CPU_PPC_401G2 = 0x00270000,
76a66253
JM		 102#define CPU_PPC_401 CPU_PPC_401G2
103 CPU_PPC_IOP480 = 0x40100000, /* 401B2 ? */
104 CPU_PPC_COBRA = 0x10100000, /* IBM Processor for Network Resources */
3fc6c082 105 /* PowerPC 403 cores */
76a66253 106 CPU_PPC_403GA = 0x00200011,
3fc6c082
FB		 107 CPU_PPC_403GB = 0x00200100,
108 CPU_PPC_403GC = 0x00200200,
109 CPU_PPC_403GCX = 0x00201400,
76a66253 110#define CPU_PPC_403 CPU_PPC_403GCX
3fc6c082 111 /* PowerPC 405 cores */
76a66253
JM		 112 CPU_PPC_405CR = 0x40110145,
113#define CPU_PPC_405GP CPU_PPC_405CR
114 CPU_PPC_405EP = 0x51210950,
115 CPU_PPC_405GPR = 0x50910951,
3fc6c082
FB		 116 CPU_PPC_405D2 = 0x20010000,
117 CPU_PPC_405D4 = 0x41810000,
76a66253
JM		 118#define CPU_PPC_405 CPU_PPC_405D4
119 CPU_PPC_NPE405H = 0x414100C0,
120 CPU_PPC_NPE405H2 = 0x41410140,
121 CPU_PPC_NPE405L = 0x416100C0,
122 /* XXX: missing 405LP, LC77700 */
123 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
124#if 0
125 CPU_PPC_STB01000 = xxx,
126#endif
3fc6c082 127#if 0
76a66253
JM		 128 CPU_PPC_STB01010 = xxx,
129#endif
130#if 0
131 CPU_PPC_STB0210 = xxx,
3fc6c082
FB		 132#endif
133 CPU_PPC_STB03 = 0x40310000,
134#if 0
76a66253 135 CPU_PPC_STB043 = xxx,
3fc6c082 136#endif
76a66253
JM		 137#if 0
138 CPU_PPC_STB045 = xxx,
139#endif
140 CPU_PPC_STB25 = 0x51510950,
3fc6c082
FB		 141#if 0
142 CPU_PPC_STB130 = xxx,
143#endif
76a66253
JM		 144 /* Xilinx cores */
145 CPU_PPC_X2VP4 = 0x20010820,
146#define CPU_PPC_X2VP7 CPU_PPC_X2VP4
147 CPU_PPC_X2VP20 = 0x20010860,
148#define CPU_PPC_X2VP50 CPU_PPC_X2VP20
3fc6c082 149 /* PowerPC 440 cores */
76a66253
JM		 150 CPU_PPC_440EP = 0x422218D3,
151#define CPU_PPC_440GR CPU_PPC_440EP
152 CPU_PPC_440GP = 0x40120481,
153 CPU_PPC_440GX = 0x51B21850,
154 CPU_PPC_440GXc = 0x51B21892,
155 CPU_PPC_440GXf = 0x51B21894,
156 CPU_PPC_440SP = 0x53221850,
157 CPU_PPC_440SP2 = 0x53221891,
158 CPU_PPC_440SPE = 0x53421890,
159 /* XXX: missing 440GRX */
160 /* PowerPC 460 cores - TODO */
161 /* PowerPC MPC 5xx cores */
162 CPU_PPC_5xx = 0x00020020,
163 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
3fc6c082 164 CPU_PPC_8xx = 0x00500000,
76a66253
JM		 165 /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
166 CPU_PPC_82xx_HIP3 = 0x00810101,
167 CPU_PPC_82xx_HIP4 = 0x80811014,
168 CPU_PPC_827x = 0x80822013,
169 /* eCores */
170 CPU_PPC_e200 = 0x81120000,
171 CPU_PPC_e500v110 = 0x80200010,
172 CPU_PPC_e500v120 = 0x80200020,
173 CPU_PPC_e500v210 = 0x80210010,
174 CPU_PPC_e500v220 = 0x80210020,
175#define CPU_PPC_e500 CPU_PPC_e500v220
176 CPU_PPC_e600 = 0x80040010,
3fc6c082 177 /* PowerPC 6xx cores */
76a66253
JM		 178 CPU_PPC_601 = 0x00010001,
179 CPU_PPC_602 = 0x00050100,
180 CPU_PPC_603 = 0x00030100,
181 CPU_PPC_603E = 0x00060101,
182 CPU_PPC_603P = 0x00070000,
183 CPU_PPC_603E7v = 0x00070100,
184 CPU_PPC_603E7v2 = 0x00070201,
185 CPU_PPC_603E7 = 0x00070200,
186 CPU_PPC_603R = 0x00071201,
187 CPU_PPC_G2 = 0x00810011,
188 CPU_PPC_G2H4 = 0x80811010,
189 CPU_PPC_G2gp = 0x80821010,
190 CPU_PPC_G2ls = 0x90810010,
191 CPU_PPC_G2LE = 0x80820010,
192 CPU_PPC_G2LEgp = 0x80822010,
193 CPU_PPC_G2LEls = 0xA0822010,
3fc6c082 194 CPU_PPC_604 = 0x00040000,
76a66253
JM		 195 CPU_PPC_604E = 0x00090100, /* Also 2110 & 2120 */
196 CPU_PPC_604R = 0x000a0101,
3fc6c082
FB		 197 /* PowerPC 74x/75x cores (aka G3) */
198 CPU_PPC_74x = 0x00080000,
76a66253
JM		 199 CPU_PPC_740E = 0x00080100,
200 CPU_PPC_750E = 0x00080200,
201 CPU_PPC_755_10 = 0x00083100,
202 CPU_PPC_755_11 = 0x00083101,
203 CPU_PPC_755_20 = 0x00083200,
204 CPU_PPC_755D = 0x00083202,
205 CPU_PPC_755E = 0x00083203,
206#define CPU_PPC_755 CPU_PPC_755E
3fc6c082 207 CPU_PPC_74xP = 0x10080000,
76a66253
JM		 208 CPU_PPC_750CXE21 = 0x00082201,
209 CPU_PPC_750CXE22 = 0x00082212,
210 CPU_PPC_750CXE23 = 0x00082203,
3fc6c082
FB		 211 CPU_PPC_750CXE24 = 0x00082214,
212 CPU_PPC_750CXE24b = 0x00083214,
213 CPU_PPC_750CXE31 = 0x00083211,
214 CPU_PPC_750CXE31b = 0x00083311,
215#define CPU_PPC_750CXE CPU_PPC_750CXE31b
76a66253
JM		 216 CPU_PPC_750CXR = 0x00083410,
217 CPU_PPC_750FX10 = 0x70000100,
218 CPU_PPC_750FX20 = 0x70000200,
219 CPU_PPC_750FX21 = 0x70000201,
220 CPU_PPC_750FX22 = 0x70000202,
221 CPU_PPC_750FX23 = 0x70000203,
222#define CPU_PPC_750FX CPU_PPC_750FX23
223 CPU_PPC_750FL = 0x700A0203,
224 CPU_PPC_750GX10 = 0x70020100,
225 CPU_PPC_750GX11 = 0x70020101,
226 CPU_PPC_750GX12 = 0x70020102,
227#define CPU_PPC_750GX CPU_PPC_750GX12
228 CPU_PPC_750GL = 0x70020102,
229 CPU_PPC_750L30 = 0x00088300,
230 CPU_PPC_750L32 = 0x00088302,
231 CPU_PPC_750CL = 0x00087200,
3fc6c082 232 /* PowerPC 74xx cores (aka G4) */
76a66253
JM		 233 CPU_PPC_7400 = 0x000C0100,
234 CPU_PPC_7410C = 0x800C1102,
235 CPU_PPC_7410D = 0x800C1103,
236 CPU_PPC_7410E = 0x800C1104,
237 CPU_PPC_7441 = 0x80000210,
238 CPU_PPC_7445 = 0x80010100,
239 CPU_PPC_7447 = 0x80020100,
240 CPU_PPC_7447A = 0x80030101,
241 CPU_PPC_7448 = 0x80040100,
242 CPU_PPC_7450 = 0x80000200,
243 CPU_PPC_7450b = 0x80000201,
3fc6c082 244 CPU_PPC_7451 = 0x80000203,
76a66253
JM		 245 CPU_PPC_7451G = 0x80000210,
246 CPU_PPC_7455 = 0x80010201,
247 CPU_PPC_7455F = 0x80010303,
248 CPU_PPC_7455G = 0x80010304,
249 CPU_PPC_7457 = 0x80020101,
250 CPU_PPC_7457C = 0x80020102,
3fc6c082
FB		 251 CPU_PPC_7457A = 0x80030000,
252 /* 64 bits PowerPC */
253 CPU_PPC_620 = 0x00140000,
254 CPU_PPC_630 = 0x00400000,
255 CPU_PPC_631 = 0x00410000,
256 CPU_PPC_POWER4 = 0x00350000,
257 CPU_PPC_POWER4P = 0x00380000,
258 CPU_PPC_POWER5 = 0x003A0000,
259 CPU_PPC_POWER5P = 0x003B0000,
260 CPU_PPC_970 = 0x00390000,
76a66253
JM		 261 CPU_PPC_970FX10 = 0x00391100,
262 CPU_PPC_970FX20 = 0x003C0200,
263 CPU_PPC_970FX21 = 0x003C0201,
264 CPU_PPC_970FX30 = 0x003C0300,
265 CPU_PPC_970FX31 = 0x003C0301,
266#define CPU_PPC_970FX CPU_PPC_970FX31
267 CPU_PPC_970MP10 = 0x00440100,
268 CPU_PPC_970MP11 = 0x00440101,
269#define CPU_PPC_970MP CPU_PPC_970MP11
270 CPU_PPC_CELL10 = 0x00700100,
271 CPU_PPC_CELL20 = 0x00700400,
272 CPU_PPC_CELL30 = 0x00700500,
273 CPU_PPC_CELL31 = 0x00700501,
274#define CPU_PPC_CELL32 CPU_PPC_CELL31
275#define CPU_PPC_CELL CPU_PPC_CELL32
3fc6c082
FB		 276 CPU_PPC_RS64 = 0x00330000,
277 CPU_PPC_RS64II = 0x00340000,
278 CPU_PPC_RS64III = 0x00360000,
279 CPU_PPC_RS64IV = 0x00370000,
280 /* Original POWER */
281 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
282 * POWER2 (RIOS2) & RSC2 (P2SC) here
283 */
284#if 0
285 CPU_POWER = xxx,
286#endif
287#if 0
288 CPU_POWER2 = xxx,
289#endif
290};
291
76a66253 292/* System version register (used on MPC 8xxx) */
3fc6c082
FB		 293enum {
294 PPC_SVR_8540 = 0x80300000,
76a66253
JM		 295 PPC_SVR_8541E = 0x807A0010,
296 PPC_SVR_8543v10 = 0x80320010,
297 PPC_SVR_8543v11 = 0x80320011,
298 PPC_SVR_8543v20 = 0x80320020,
299 PPC_SVR_8543Ev10 = 0x803A0010,
300 PPC_SVR_8543Ev11 = 0x803A0011,
301 PPC_SVR_8543Ev20 = 0x803A0020,
302 PPC_SVR_8545 = 0x80310220,
303 PPC_SVR_8545E = 0x80390220,
304 PPC_SVR_8547E = 0x80390120,
305 PPC_SCR_8548v10 = 0x80310010,
306 PPC_SCR_8548v11 = 0x80310011,
307 PPC_SCR_8548v20 = 0x80310020,
308 PPC_SVR_8548Ev10 = 0x80390010,
309 PPC_SVR_8548Ev11 = 0x80390011,
310 PPC_SVR_8548Ev20 = 0x80390020,
311 PPC_SVR_8555E = 0x80790010,
312 PPC_SVR_8560v10 = 0x80700010,
313 PPC_SVR_8560v20 = 0x80700020,
3fc6c082
FB		 314};
315
316/*****************************************************************************/
9a64fbe4
FB		 317/* Instruction types */
318enum {
3fc6c082
FB		 319 PPC_NONE = 0x00000000,
320 /* integer operations instructions */
321 /* flow control instructions */
322 /* virtual memory instructions */
323 /* ld/st with reservation instructions */
324 /* cache control instructions */
325 /* spr/msr access instructions */
0487d6a8 326 PPC_INSNS_BASE = 0x0000000000000001ULL,
3fc6c082
FB		 327#define PPC_INTEGER PPC_INSNS_BASE
328#define PPC_FLOW PPC_INSNS_BASE
329#define PPC_MEM PPC_INSNS_BASE
330#define PPC_RES PPC_INSNS_BASE
331#define PPC_CACHE PPC_INSNS_BASE
332#define PPC_MISC PPC_INSNS_BASE
333 /* floating point operations instructions */
0487d6a8 334 PPC_FLOAT = 0x0000000000000002ULL,
3fc6c082 335 /* more floating point operations instructions */
0487d6a8 336 PPC_FLOAT_EXT = 0x0000000000000004ULL,
3fc6c082 337 /* external control instructions */
0487d6a8 338 PPC_EXTERN = 0x0000000000000008ULL,
3fc6c082 339 /* segment register access instructions */
0487d6a8 340 PPC_SEGMENT = 0x0000000000000010ULL,
3fc6c082 341 /* Optional cache control instructions */
0487d6a8 342 PPC_CACHE_OPT = 0x0000000000000020ULL,
3fc6c082 343 /* Optional floating point op instructions */
0487d6a8 344 PPC_FLOAT_OPT = 0x0000000000000040ULL,
3fc6c082 345 /* Optional memory control instructions */
0487d6a8
JM		 346 PPC_MEM_TLBIA = 0x0000000000000080ULL,
347 PPC_MEM_TLBIE = 0x0000000000000100ULL,
348 PPC_MEM_TLBSYNC = 0x0000000000000200ULL,
3fc6c082 349 /* eieio & sync */
0487d6a8 350 PPC_MEM_SYNC = 0x0000000000000400ULL,
3fc6c082 351 /* PowerPC 6xx TLB management instructions */
0487d6a8 352 PPC_6xx_TLB = 0x0000000000000800ULL,
3fc6c082 353 /* Altivec support */
0487d6a8 354 PPC_ALTIVEC = 0x0000000000001000ULL,
3fc6c082 355 /* Time base support */
0487d6a8 356 PPC_TB = 0x0000000000002000ULL,
3fc6c082 357 /* Embedded PowerPC dedicated instructions */
0487d6a8 358 PPC_EMB_COMMON = 0x0000000000004000ULL,
3fc6c082 359 /* PowerPC 40x exception model */
0487d6a8 360 PPC_40x_EXCP = 0x0000000000008000ULL,
3fc6c082 361 /* PowerPC 40x specific instructions */
0487d6a8 362 PPC_40x_SPEC = 0x0000000000010000ULL,
3fc6c082 363 /* PowerPC 405 Mac instructions */
0487d6a8 364 PPC_405_MAC = 0x0000000000020000ULL,
3fc6c082 365 /* PowerPC 440 specific instructions */
0487d6a8 366 PPC_440_SPEC = 0x0000000000040000ULL,
3fc6c082
FB		 367 /* Specific extensions */
368 /* Power-to-PowerPC bridge (601) */
0487d6a8 369 PPC_POWER_BR = 0x0000000000080000ULL,
3fc6c082 370 /* PowerPC 602 specific */
0487d6a8 371 PPC_602_SPEC = 0x0000000000100000ULL,
3fc6c082
FB		 372 /* Deprecated instructions */
373 /* Original POWER instruction set */
0487d6a8 374 PPC_POWER = 0x0000000000200000ULL,
3fc6c082 375 /* POWER2 instruction set extension */
0487d6a8 376 PPC_POWER2 = 0x0000000000400000ULL,
3fc6c082 377 /* Power RTC support */
0487d6a8 378 PPC_POWER_RTC = 0x0000000000800000ULL,
3fc6c082
FB		 379 /* 64 bits PowerPC instructions */
380 /* 64 bits PowerPC instruction set */
0487d6a8 381 PPC_64B = 0x0000000001000000ULL,
3fc6c082 382 /* 64 bits hypervisor extensions */
0487d6a8 383 PPC_64H = 0x0000000002000000ULL,
3fc6c082 384 /* 64 bits PowerPC "bridge" features */
0487d6a8 385 PPC_64_BRIDGE = 0x0000000004000000ULL,
76a66253 386 /* BookE (embedded) PowerPC specification */
0487d6a8 387 PPC_BOOKE = 0x0000000008000000ULL,
8b67546f 388 /* eieio */
0487d6a8 389 PPC_MEM_EIEIO = 0x0000000010000000ULL,
8b67546f 390 /* e500 vector instructions */
0487d6a8 391 PPC_E500_VECTOR = 0x0000000020000000ULL,
8b67546f 392 /* PowerPC 4xx dedicated instructions */
0487d6a8 393 PPC_4xx_COMMON = 0x0000000040000000ULL,
8b67546f 394 /* PowerPC 2.03 specification extensions */
0487d6a8 395 PPC_203 = 0x0000000080000000ULL,
8b67546f 396 /* PowerPC 2.03 SPE extension */
0487d6a8 397 PPC_SPE = 0x0000000100000000ULL,
8b67546f 398 /* PowerPC 2.03 SPE floating-point extension */
0487d6a8 399 PPC_SPEFPU = 0x0000000200000000ULL,
8b67546f 400 /* SLB management */
426613db 401 PPC_SLBI = 0x0000000400000000ULL,
9a64fbe4 402};
79aceca5 403
3fc6c082
FB		 404/* CPU run-time flags (MMU and exception model) */
405enum {
406 /* MMU model */
d0dfae6e 407 PPC_FLAGS_MMU_MASK = 0x000000FF,
3fc6c082 408 /* Standard 32 bits PowerPC MMU */
d0dfae6e 409 PPC_FLAGS_MMU_32B = 0x00000000,
3fc6c082 410 /* Standard 64 bits PowerPC MMU */
d0dfae6e 411 PPC_FLAGS_MMU_64B = 0x00000001,
3fc6c082 412 /* PowerPC 601 MMU */
d0dfae6e 413 PPC_FLAGS_MMU_601 = 0x00000002,
3fc6c082 414 /* PowerPC 6xx MMU with software TLB */
d0dfae6e 415 PPC_FLAGS_MMU_SOFT_6xx = 0x00000003,
3fc6c082 416 /* PowerPC 4xx MMU with software TLB */
d0dfae6e 417 PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,
3fc6c082 418 /* PowerPC 403 MMU */
d0dfae6e
JM		 419 PPC_FLAGS_MMU_403 = 0x00000005,
420 /* BookE FSL MMU model */
421 PPC_FLAGS_MMU_BOOKE_FSL = 0x00000006,
d9bce9d9 422 /* BookE MMU model */
d0dfae6e
JM		 423 PPC_FLAGS_MMU_BOOKE = 0x00000007,
424 /* 64 bits "bridge" PowerPC MMU */
425 PPC_FLAGS_MMU_64BRIDGE = 0x00000008,
3fc6c082 426 /* Exception model */
d0dfae6e 427 PPC_FLAGS_EXCP_MASK = 0x0000FF00,
3fc6c082 428 /* Standard PowerPC exception model */
d0dfae6e 429 PPC_FLAGS_EXCP_STD = 0x00000000,
3fc6c082 430 /* PowerPC 40x exception model */
d0dfae6e 431 PPC_FLAGS_EXCP_40x = 0x00000100,
3fc6c082 432 /* PowerPC 601 exception model */
d0dfae6e 433 PPC_FLAGS_EXCP_601 = 0x00000200,
3fc6c082 434 /* PowerPC 602 exception model */
d0dfae6e 435 PPC_FLAGS_EXCP_602 = 0x00000300,
3fc6c082 436 /* PowerPC 603 exception model */
d0dfae6e 437 PPC_FLAGS_EXCP_603 = 0x00000400,
3fc6c082 438 /* PowerPC 604 exception model */
d0dfae6e 439 PPC_FLAGS_EXCP_604 = 0x00000500,
3fc6c082 440 /* PowerPC 7x0 exception model */
d0dfae6e 441 PPC_FLAGS_EXCP_7x0 = 0x00000600,
3fc6c082 442 /* PowerPC 7x5 exception model */
d0dfae6e 443 PPC_FLAGS_EXCP_7x5 = 0x00000700,
3fc6c082 444 /* PowerPC 74xx exception model */
d0dfae6e 445 PPC_FLAGS_EXCP_74xx = 0x00000800,
3fc6c082 446 /* PowerPC 970 exception model */
d0dfae6e 447 PPC_FLAGS_EXCP_970 = 0x00000900,
d9bce9d9 448 /* BookE exception model */
d0dfae6e
JM		 449 PPC_FLAGS_EXCP_BOOKE = 0x00000A00,
450 /* Input pins model */
451 PPC_FLAGS_INPUT_MASK = 0x000F0000,
452 PPC_FLAGS_INPUT_6xx = 0x00000000,
453 PPC_FLAGS_INPUT_BookE = 0x00010000,
454 PPC_FLAGS_INPUT_40x = 0x00020000,
455 PPC_FLAGS_INPUT_970 = 0x00030000,
3fc6c082
FB		 456};
457
458#define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK)
459#define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK)
d0dfae6e 460#define PPC_INPUT(env) (env->flags & PPC_FLAGS_INPUT_MASK)
3fc6c082
FB		 461
462/*****************************************************************************/
463/* Supported instruction set definitions */
464/* This generates an empty opcode table... */
465#define PPC_INSNS_TODO (PPC_NONE)
466#define PPC_FLAGS_TODO (0x00000000)
467
468/* PowerPC 40x instruction set */
76a66253 469#define PPC_INSNS_EMB (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_EMB_COMMON)
3fc6c082
FB		 470/* PowerPC 401 */
471#define PPC_INSNS_401 (PPC_INSNS_TODO)
472#define PPC_FLAGS_401 (PPC_FLAGS_TODO)
473/* PowerPC 403 */
76a66253
JM		 474#define PPC_INSNS_403 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
475 PPC_MEM_TLBIA | PPC_4xx_COMMON | PPC_40x_EXCP | \
476 PPC_40x_SPEC)
d0dfae6e
JM		 477#define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x | \
478 PPC_FLAGS_INPUT_40x)
3fc6c082 479/* PowerPC 405 */
76a66253
JM		 480#define PPC_INSNS_405 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \
481 PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_TB | \
482 PPC_4xx_COMMON | PPC_40x_SPEC | PPC_40x_EXCP | \
3fc6c082 483 PPC_405_MAC)
d0dfae6e
JM		 484#define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \
485 PPC_FLAGS_INPUT_40x)
3fc6c082 486/* PowerPC 440 */
76a66253
JM		 487#define PPC_INSNS_440 (PPC_INSNS_EMB | PPC_CACHE_OPT | PPC_BOOKE | \
488 PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
d0dfae6e
JM		 489#define PPC_FLAGS_440 (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \
490 PPC_FLAGS_INPUT_BookE)
76a66253
JM		 491/* Generic BookE PowerPC */
492#define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \
493 PPC_FLOAT | PPC_FLOAT_OPT | PPC_CACHE_OPT)
d0dfae6e
JM		 494#define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \
495 PPC_FLAGS_INPUT_BookE)
76a66253
JM		 496/* e500 core */
497#define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \
498 PPC_CACHE_OPT | PPC_E500_VECTOR)
d0dfae6e
JM		 499#define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \
500 PPC_FLAGS_INPUT_BookE)
3fc6c082
FB		 501/* Non-embedded PowerPC */
502#define PPC_INSNS_COMMON (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
d0dfae6e 503 PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
3fc6c082
FB		 504/* PowerPC 601 */
505#define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)
d0dfae6e
JM		 506#define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601 | \
507 PPC_FLAGS_INPUT_6xx)
3fc6c082
FB		 508/* PowerPC 602 */
509#define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
76a66253 510 PPC_MEM_TLBSYNC | PPC_TB | PPC_602_SPEC)
d0dfae6e
JM		 511#define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602 | \
512 PPC_FLAGS_INPUT_6xx)
3fc6c082
FB		 513/* PowerPC 603 */
514#define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
515 PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
d0dfae6e
JM		 516#define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603 | \
517 PPC_FLAGS_INPUT_6xx)
3fc6c082
FB		 518/* PowerPC G2 */
519#define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
520 PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
d0dfae6e
JM		 521#define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603 | \
522 PPC_FLAGS_INPUT_6xx)
3fc6c082
FB		 523/* PowerPC 604 */
524#define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
525 PPC_MEM_TLBSYNC | PPC_TB)
d0dfae6e
JM		 526#define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604 | \
527 PPC_FLAGS_INPUT_6xx)
3fc6c082
FB		 528/* PowerPC 740/750 (aka G3) */
529#define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
530 PPC_MEM_TLBSYNC | PPC_TB)
d0dfae6e
JM		 531#define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0 | \
532 PPC_FLAGS_INPUT_6xx)
3fc6c082
FB		 533/* PowerPC 745/755 */
534#define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
535 PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB)
d0dfae6e
JM		 536#define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5 | \
537 PPC_FLAGS_INPUT_6xx)
3fc6c082
FB		 538/* PowerPC 74xx (aka G4) */
539#define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC | \
540 PPC_MEM_TLBSYNC | PPC_TB)
d0dfae6e
JM		 541#define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx | \
542 PPC_FLAGS_INPUT_6xx)
426613db
JM		 543/* PowerPC 970 (aka G5) */
544#define PPC_INSNS_970 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_FLOAT_OPT | \
545 PPC_ALTIVEC | PPC_MEM_TLBSYNC | PPC_TB | \
546 PPC_64B | PPC_64_BRIDGE | PPC_SLBI)
d0dfae6e
JM		 547#define PPC_FLAGS_970 (PPC_FLAGS_MMU_64BRIDGE | PPC_FLAGS_EXCP_970 | \
548 PPC_FLAGS_INPUT_970)
3fc6c082
FB		 549
550/* Default PowerPC will be 604/970 */
551#define PPC_INSNS_PPC32 PPC_INSNS_604
552#define PPC_FLAGS_PPC32 PPC_FLAGS_604
3fc6c082
FB		 553#define PPC_INSNS_PPC64 PPC_INSNS_970
554#define PPC_FLAGS_PPC64 PPC_FLAGS_970
3fc6c082
FB		 555#define PPC_INSNS_DEFAULT PPC_INSNS_604
556#define PPC_FLAGS_DEFAULT PPC_FLAGS_604
557typedef struct ppc_def_t ppc_def_t;
79aceca5 558
3fc6c082
FB		 559/*****************************************************************************/
560/* Types used to describe some PowerPC registers */
561typedef struct CPUPPCState CPUPPCState;
562typedef struct opc_handler_t opc_handler_t;
9fddaa0c 563typedef struct ppc_tb_t ppc_tb_t;
3fc6c082
FB		 564typedef struct ppc_spr_t ppc_spr_t;
565typedef struct ppc_dcr_t ppc_dcr_t;
566typedef struct ppc_avr_t ppc_avr_t;
1d0a48fb 567typedef union ppc_tlb_t ppc_tlb_t;
76a66253 568
3fc6c082
FB		 569/* SPR access micro-ops generations callbacks */
570struct ppc_spr_t {
571 void (*uea_read)(void *opaque, int spr_num);
572 void (*uea_write)(void *opaque, int spr_num);
76a66253 573#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 574 void (*oea_read)(void *opaque, int spr_num);
575 void (*oea_write)(void *opaque, int spr_num);
76a66253 576#endif
3fc6c082
FB		 577 const unsigned char *name;
578};
579
580/* Altivec registers (128 bits) */
581struct ppc_avr_t {
582 uint32_t u[4];
583};
9fddaa0c 584
3fc6c082 585/* Software TLB cache */
1d0a48fb
JM		 586typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
587struct ppc6xx_tlb_t {
76a66253
JM		 588 target_ulong pte0;
589 target_ulong pte1;
590 target_ulong EPN;
1d0a48fb
JM		 591};
592
593typedef struct ppcemb_tlb_t ppcemb_tlb_t;
594struct ppcemb_tlb_t {
c55e9aef 595 target_phys_addr_t RPN;
1d0a48fb 596 target_ulong EPN;
76a66253 597 target_ulong PID;
c55e9aef
JM		 598 target_ulong size;
599 uint32_t prot;
600 uint32_t attr; /* Storage attributes */
1d0a48fb
JM		 601};
602
603union ppc_tlb_t {
604 ppc6xx_tlb_t tlb6;
605 ppcemb_tlb_t tlbe;
3fc6c082
FB		 606};
607
608/*****************************************************************************/
609/* Machine state register bits definition */
76a66253 610#define MSR_SF 63 /* Sixty-four-bit mode hflags */
3fc6c082 611#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
76a66253 612#define MSR_HV 60 /* hypervisor state hflags */
363be49c
JM		 613#define MSR_CM 31 /* Computation mode for BookE hflags */
614#define MSR_ICM 30 /* Interrupt computation mode for BookE */
615#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
76a66253 616#define MSR_VR 25 /* altivec available hflags */
363be49c 617#define MSR_SPE 25 /* SPE enable for BookE hflags */
76a66253
JM		 618#define MSR_AP 23 /* Access privilege state on 602 hflags */
619#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
3fc6c082
FB		 620#define MSR_KEY 19 /* key bit on 603e */
621#define MSR_POW 18 /* Power management */
622#define MSR_WE 18 /* Wait state enable on embedded PowerPC */
623#define MSR_TGPR 17 /* TGPR usage on 602/603 */
76a66253 624#define MSR_TLB 17 /* TLB update on ? */
3fc6c082
FB		 625#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC */
626#define MSR_ILE 16 /* Interrupt little-endian mode */
627#define MSR_EE 15 /* External interrupt enable */
76a66253
JM		 628#define MSR_PR 14 /* Problem state hflags */
629#define MSR_FP 13 /* Floating point available hflags */
3fc6c082 630#define MSR_ME 12 /* Machine check interrupt enable */
76a66253
JM		 631#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
632#define MSR_SE 10 /* Single-step trace enable hflags */
3fc6c082 633#define MSR_DWE 10 /* Debug wait enable on 405 */
76a66253
JM		 634#define MSR_UBLE 10 /* User BTB lock enable on e500 */
635#define MSR_BE 9 /* Branch trace enable hflags */
3fc6c082 636#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC */
76a66253 637#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
3fc6c082
FB		 638#define MSR_AL 7 /* AL bit on POWER */
639#define MSR_IP 6 /* Interrupt prefix */
640#define MSR_IR 5 /* Instruction relocate */
641#define MSR_IS 5 /* Instruction address space on embedded PowerPC */
642#define MSR_DR 4 /* Data relocate */
643#define MSR_DS 4 /* Data address space on embedded PowerPC */
644#define MSR_PE 3 /* Protection enable on 403 */
645#define MSR_EP 3 /* Exception prefix on 601 */
646#define MSR_PX 2 /* Protection exclusive on 403 */
647#define MSR_PMM 2 /* Performance monitor mark on POWER */
648#define MSR_RI 1 /* Recoverable interrupt */
76a66253 649#define MSR_LE 0 /* Little-endian mode hflags */
3fc6c082
FB		 650#define msr_sf env->msr[MSR_SF]
651#define msr_isf env->msr[MSR_ISF]
652#define msr_hv env->msr[MSR_HV]
363be49c
JM		 653#define msr_cm env->msr[MSR_CM]
654#define msr_icm env->msr[MSR_ICM]
76a66253 655#define msr_ucle env->msr[MSR_UCLE]
3fc6c082 656#define msr_vr env->msr[MSR_VR]
76a66253 657#define msr_spe env->msr[MSR_SPE]
3fc6c082
FB		 658#define msr_ap env->msr[MSR_AP]
659#define msr_sa env->msr[MSR_SA]
660#define msr_key env->msr[MSR_KEY]
76a66253 661#define msr_pow env->msr[MSR_POW]
3fc6c082
FB		 662#define msr_we env->msr[MSR_WE]
663#define msr_tgpr env->msr[MSR_TGPR]
664#define msr_tlb env->msr[MSR_TLB]
665#define msr_ce env->msr[MSR_CE]
76a66253
JM		 666#define msr_ile env->msr[MSR_ILE]
667#define msr_ee env->msr[MSR_EE]
668#define msr_pr env->msr[MSR_PR]
669#define msr_fp env->msr[MSR_FP]
670#define msr_me env->msr[MSR_ME]
671#define msr_fe0 env->msr[MSR_FE0]
672#define msr_se env->msr[MSR_SE]
3fc6c082 673#define msr_dwe env->msr[MSR_DWE]
76a66253
JM		 674#define msr_uble env->msr[MSR_UBLE]
675#define msr_be env->msr[MSR_BE]
3fc6c082 676#define msr_de env->msr[MSR_DE]
76a66253 677#define msr_fe1 env->msr[MSR_FE1]
3fc6c082 678#define msr_al env->msr[MSR_AL]
76a66253
JM		 679#define msr_ip env->msr[MSR_IP]
680#define msr_ir env->msr[MSR_IR]
3fc6c082 681#define msr_is env->msr[MSR_IS]
76a66253 682#define msr_dr env->msr[MSR_DR]
3fc6c082
FB		 683#define msr_ds env->msr[MSR_DS]
684#define msr_pe env->msr[MSR_PE]
685#define msr_ep env->msr[MSR_EP]
686#define msr_px env->msr[MSR_PX]
687#define msr_pmm env->msr[MSR_PMM]
76a66253
JM		 688#define msr_ri env->msr[MSR_RI]
689#define msr_le env->msr[MSR_LE]
79aceca5 690
3fc6c082
FB		 691/*****************************************************************************/
692/* The whole PowerPC CPU context */
693struct CPUPPCState {
694 /* First are the most commonly used resources
695 * during translated code execution
696 */
0487d6a8 697#if TARGET_GPR_BITS > HOST_LONG_BITS
3fc6c082
FB		 698 /* temporary fixed-point registers
699 * used to emulate 64 bits target on 32 bits hosts
5fafdf24 700 */
3c4c9f9f 701 ppc_gpr_t t0, t1, t2;
3fc6c082 702#endif
d9bce9d9
JM		 703 ppc_avr_t t0_avr, t1_avr, t2_avr;
704
79aceca5 705 /* general purpose registers */
76a66253 706 ppc_gpr_t gpr[32];
3fc6c082
FB		 707 /* LR */
708 target_ulong lr;
709 /* CTR */
710 target_ulong ctr;
711 /* condition register */
712 uint8_t crf[8];
79aceca5 713 /* XER */
3fc6c082
FB		 714 /* XXX: We use only 5 fields, but we want to keep the structure aligned */
715 uint8_t xer[8];
79aceca5 716 /* Reservation address */
3fc6c082
FB		 717 target_ulong reserve;
718
719 /* Those ones are used in supervisor mode only */
79aceca5 720 /* machine state register */
3fc6c082
FB		 721 uint8_t msr[64];
722 /* temporary general purpose registers */
76a66253 723 ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
3fc6c082
FB		 724
725 /* Floating point execution context */
76a66253 726 /* temporary float registers */
4ecc3190
FB		 727 float64 ft0;
728 float64 ft1;
729 float64 ft2;
730 float_status fp_status;
3fc6c082
FB		 731 /* floating point registers */
732 float64 fpr[32];
733 /* floating point status and control register */
734 uint8_t fpscr[8];
4ecc3190 735
a316d335
FB		 736 CPU_COMMON
737
50443c98
FB		 738 int halted; /* TRUE if the CPU is in suspend state */
739
ac9eb073
FB		 740 int access_type; /* when a memory exception occurs, the access
741 type is stored here */
a541f297 742
3fc6c082
FB		 743 /* MMU context */
744 /* Address space register */
745 target_ulong asr;
746 /* segment registers */
747 target_ulong sdr1;
748 target_ulong sr[16];
749 /* BATs */
750 int nb_BATs;
751 target_ulong DBAT[2][8];
752 target_ulong IBAT[2][8];
9fddaa0c 753
3fc6c082
FB		 754 /* Other registers */
755 /* Special purpose registers */
756 target_ulong spr[1024];
757 /* Altivec registers */
758 ppc_avr_t avr[32];
759 uint32_t vscr;
d9bce9d9
JM		 760 /* SPE registers */
761 ppc_gpr_t spe_acc;
0487d6a8 762 float_status spe_status;
d9bce9d9 763 uint32_t spe_fscr;
3fc6c082
FB		 764
765 /* Internal devices resources */
9fddaa0c
FB		 766 /* Time base and decrementer */
767 ppc_tb_t *tb_env;
3fc6c082 768 /* Device control registers */
3fc6c082
FB		 769 ppc_dcr_t *dcr_env;
770
771 /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
76a66253
JM		 772 int nb_tlb; /* Total number of TLB */
773 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
774 int nb_ways; /* Number of ways in the TLB set */
775 int last_way; /* Last used way used to allocate TLB in a LRU way */
776 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
363be49c 777 int nb_pids; /* Number of available PID registers */
76a66253 778 ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
3fc6c082
FB		 779 /* 403 dedicated access protection registers */
780 target_ulong pb[4];
781
782 /* Those resources are used during exception processing */
783 /* CPU model definition */
784 uint64_t msr_mask;
785 uint32_t flags;
786
787 int exception_index;
788 int error_code;
789 int interrupt_request;
47103572 790 uint32_t pending_interrupts;
e9df014c
JM		 791#if !defined(CONFIG_USER_ONLY)
792 /* This is the IRQ controller, which is implementation dependant
793 * and only relevant when emulating a complete machine.
794 */
795 uint32_t irq_input_state;
796 void **irq_inputs;
797#endif
3fc6c082
FB		 798
799 /* Those resources are used only during code translation */
800 /* Next instruction pointer */
801 target_ulong nip;
802 /* SPR translation callbacks */
803 ppc_spr_t spr_cb[1024];
804 /* opcode handlers */
805 opc_handler_t *opcodes[0x40];
806
807 /* Those resources are used only in Qemu core */
808 jmp_buf jmp_env;
809 int user_mode_only; /* user mode only simulation */
4296f459 810 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
3fc6c082 811
9fddaa0c
FB		 812 /* Power management */
813 int power_mode;
a541f297 814
6d506e6d
FB		 815 /* temporary hack to handle OSI calls (only used if non NULL) */
816 int (*osi_call)(struct CPUPPCState *env);
3fc6c082 817};
79aceca5 818
76a66253
JM		 819/* Context used internally during MMU translations */
820typedef struct mmu_ctx_t mmu_ctx_t;
821struct mmu_ctx_t {
822 target_phys_addr_t raddr; /* Real address */
823 int prot; /* Protection bits */
824 target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
825 target_ulong ptem; /* Virtual segment ID | API */
826 int key; /* Access key */
827};
828
3fc6c082 829/*****************************************************************************/
36081602
JM		 830CPUPPCState *cpu_ppc_init (void);
831int cpu_ppc_exec (CPUPPCState *s);
832void cpu_ppc_close (CPUPPCState *s);
79aceca5
FB		 833/* you can call this signal handler from your SIGBUS and SIGSEGV
834 signal handlers to inform the virtual CPU of exceptions. non zero
835 is returned if the signal was handled by the virtual CPU. */
36081602
JM		 836int cpu_ppc_signal_handler (int host_signum, void *pinfo,
837 void *puc);
79aceca5 838
a541f297 839void do_interrupt (CPUPPCState *env);
e9df014c 840void ppc_hw_interrupt (CPUPPCState *env);
36081602 841void cpu_loop_exit (void);
a541f297 842
9a64fbe4 843void dump_stack (CPUPPCState *env);
a541f297 844
76a66253 845#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 846target_ulong do_load_ibatu (CPUPPCState *env, int nr);
847target_ulong do_load_ibatl (CPUPPCState *env, int nr);
848void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
849void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
850target_ulong do_load_dbatu (CPUPPCState *env, int nr);
851target_ulong do_load_dbatl (CPUPPCState *env, int nr);
852void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
853void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
3fc6c082
FB		 854target_ulong do_load_sdr1 (CPUPPCState *env);
855void do_store_sdr1 (CPUPPCState *env, target_ulong value);
d9bce9d9
JM		 856#if defined(TARGET_PPC64)
857target_ulong ppc_load_asr (CPUPPCState *env);
858void ppc_store_asr (CPUPPCState *env, target_ulong value);
859#endif
3fc6c082
FB		 860target_ulong do_load_sr (CPUPPCState *env, int srnum);
861void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
76a66253
JM		 862#endif
863uint32_t ppc_load_xer (CPUPPCState *env);
864void ppc_store_xer (CPUPPCState *env, uint32_t value);
3fc6c082
FB		 865target_ulong do_load_msr (CPUPPCState *env);
866void do_store_msr (CPUPPCState *env, target_ulong value);
426613db 867void ppc_store_msr_32 (CPUPPCState *env, uint32_t value);
3fc6c082
FB		 868
869void do_compute_hflags (CPUPPCState *env);
0a032cbe
JM		 870void cpu_ppc_reset (void *opaque);
871CPUPPCState *cpu_ppc_init (void);
872void cpu_ppc_close(CPUPPCState *env);
a541f297 873
3fc6c082
FB		 874int ppc_find_by_name (const unsigned char *name, ppc_def_t **def);
875int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
876void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
877int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);
85c4adf6 878
9fddaa0c
FB		 879/* Time-base and decrementer management */
880#ifndef NO_CPU_IO_DEFS
881uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
882uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
883void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
884void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
885uint32_t cpu_ppc_load_decr (CPUPPCState *env);
886void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
d9bce9d9
JM		 887uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
888uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
889#if !defined(CONFIG_USER_ONLY)
890void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
891void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
892target_ulong load_40x_pit (CPUPPCState *env);
893void store_40x_pit (CPUPPCState *env, target_ulong val);
8ecc7913 894void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
c294fc58 895void store_40x_sler (CPUPPCState *env, uint32_t val);
d9bce9d9
JM		 896void store_booke_tcr (CPUPPCState *env, target_ulong val);
897void store_booke_tsr (CPUPPCState *env, target_ulong val);
0a032cbe 898void ppc_tlb_invalidate_all (CPUPPCState *env);
36081602 899int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
d9bce9d9 900#endif
9fddaa0c 901#endif
79aceca5 902
2e719ba3
JM		 903/* Device control registers */
904int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
905int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
906
9467d44c
TS		 907#define CPUState CPUPPCState
908#define cpu_init cpu_ppc_init
909#define cpu_exec cpu_ppc_exec
910#define cpu_gen_code cpu_ppc_gen_code
911#define cpu_signal_handler cpu_ppc_signal_handler
912
79aceca5
FB		 913#include "cpu-all.h"
914
3fc6c082
FB		 915/*****************************************************************************/
916/* Registers definitions */
79aceca5
FB		 917#define XER_SO 31
918#define XER_OV 30
919#define XER_CA 29
3fc6c082 920#define XER_CMP 8
36081602 921#define XER_BC 0
3fc6c082
FB		 922#define xer_so env->xer[4]
923#define xer_ov env->xer[6]
924#define xer_ca env->xer[2]
925#define xer_cmp env->xer[1]
36081602 926#define xer_bc env->xer[0]
79aceca5 927
3fc6c082 928/* SPR definitions */
76a66253
JM		 929#define SPR_MQ (0x000)
930#define SPR_XER (0x001)
931#define SPR_601_VRTCU (0x004)
932#define SPR_601_VRTCL (0x005)
933#define SPR_601_UDECR (0x006)
934#define SPR_LR (0x008)
935#define SPR_CTR (0x009)
936#define SPR_DSISR (0x012)
937#define SPR_DAR (0x013)
938#define SPR_601_RTCU (0x014)
939#define SPR_601_RTCL (0x015)
940#define SPR_DECR (0x016)
941#define SPR_SDR1 (0x019)
942#define SPR_SRR0 (0x01A)
943#define SPR_SRR1 (0x01B)
944#define SPR_BOOKE_PID (0x030)
945#define SPR_BOOKE_DECAR (0x036)
363be49c
JM		 946#define SPR_BOOKE_CSRR0 (0x03A)
947#define SPR_BOOKE_CSRR1 (0x03B)
76a66253
JM		 948#define SPR_BOOKE_DEAR (0x03D)
949#define SPR_BOOKE_ESR (0x03E)
363be49c 950#define SPR_BOOKE_IVPR (0x03F)
76a66253
JM		 951#define SPR_8xx_EIE (0x050)
952#define SPR_8xx_EID (0x051)
953#define SPR_8xx_NRE (0x052)
954#define SPR_58x_CMPA (0x090)
955#define SPR_58x_CMPB (0x091)
956#define SPR_58x_CMPC (0x092)
957#define SPR_58x_CMPD (0x093)
958#define SPR_58x_ICR (0x094)
959#define SPR_58x_DER (0x094)
960#define SPR_58x_COUNTA (0x096)
961#define SPR_58x_COUNTB (0x097)
962#define SPR_58x_CMPE (0x098)
963#define SPR_58x_CMPF (0x099)
964#define SPR_58x_CMPG (0x09A)
965#define SPR_58x_CMPH (0x09B)
966#define SPR_58x_LCTRL1 (0x09C)
967#define SPR_58x_LCTRL2 (0x09D)
968#define SPR_58x_ICTRL (0x09E)
969#define SPR_58x_BAR (0x09F)
970#define SPR_VRSAVE (0x100)
971#define SPR_USPRG0 (0x100)
363be49c
JM		 972#define SPR_USPRG1 (0x101)
973#define SPR_USPRG2 (0x102)
974#define SPR_USPRG3 (0x103)
76a66253
JM		 975#define SPR_USPRG4 (0x104)
976#define SPR_USPRG5 (0x105)
977#define SPR_USPRG6 (0x106)
978#define SPR_USPRG7 (0x107)
979#define SPR_VTBL (0x10C)
980#define SPR_VTBU (0x10D)
981#define SPR_SPRG0 (0x110)
982#define SPR_SPRG1 (0x111)
983#define SPR_SPRG2 (0x112)
984#define SPR_SPRG3 (0x113)
985#define SPR_SPRG4 (0x114)
986#define SPR_SCOMC (0x114)
987#define SPR_SPRG5 (0x115)
988#define SPR_SCOMD (0x115)
989#define SPR_SPRG6 (0x116)
990#define SPR_SPRG7 (0x117)
991#define SPR_ASR (0x118)
992#define SPR_EAR (0x11A)
993#define SPR_TBL (0x11C)
994#define SPR_TBU (0x11D)
995#define SPR_SVR (0x11E)
996#define SPR_BOOKE_PIR (0x11E)
997#define SPR_PVR (0x11F)
998#define SPR_HSPRG0 (0x130)
999#define SPR_BOOKE_DBSR (0x130)
1000#define SPR_HSPRG1 (0x131)
1001#define SPR_BOOKE_DBCR0 (0x134)
1002#define SPR_IBCR (0x135)
1003#define SPR_BOOKE_DBCR1 (0x135)
1004#define SPR_DBCR (0x136)
1005#define SPR_HDEC (0x136)
1006#define SPR_BOOKE_DBCR2 (0x136)
1007#define SPR_HIOR (0x137)
1008#define SPR_MBAR (0x137)
1009#define SPR_RMOR (0x138)
1010#define SPR_BOOKE_IAC1 (0x138)
1011#define SPR_HRMOR (0x139)
1012#define SPR_BOOKE_IAC2 (0x139)
1013#define SPR_HSSR0 (0x13A)
1014#define SPR_BOOKE_IAC3 (0x13A)
1015#define SPR_HSSR1 (0x13B)
1016#define SPR_BOOKE_IAC4 (0x13B)
1017#define SPR_LPCR (0x13C)
1018#define SPR_BOOKE_DAC1 (0x13C)
1019#define SPR_LPIDR (0x13D)
1020#define SPR_DABR2 (0x13D)
1021#define SPR_BOOKE_DAC2 (0x13D)
1022#define SPR_BOOKE_DVC1 (0x13E)
1023#define SPR_BOOKE_DVC2 (0x13F)
1024#define SPR_BOOKE_TSR (0x150)
1025#define SPR_BOOKE_TCR (0x154)
1026#define SPR_BOOKE_IVOR0 (0x190)
1027#define SPR_BOOKE_IVOR1 (0x191)
1028#define SPR_BOOKE_IVOR2 (0x192)
1029#define SPR_BOOKE_IVOR3 (0x193)
1030#define SPR_BOOKE_IVOR4 (0x194)
1031#define SPR_BOOKE_IVOR5 (0x195)
1032#define SPR_BOOKE_IVOR6 (0x196)
1033#define SPR_BOOKE_IVOR7 (0x197)
1034#define SPR_BOOKE_IVOR8 (0x198)
1035#define SPR_BOOKE_IVOR9 (0x199)
1036#define SPR_BOOKE_IVOR10 (0x19A)
1037#define SPR_BOOKE_IVOR11 (0x19B)
1038#define SPR_BOOKE_IVOR12 (0x19C)
1039#define SPR_BOOKE_IVOR13 (0x19D)
1040#define SPR_BOOKE_IVOR14 (0x19E)
1041#define SPR_BOOKE_IVOR15 (0x19F)
1042#define SPR_E500_SPEFSCR (0x200)
1043#define SPR_E500_BBEAR (0x201)
1044#define SPR_E500_BBTAR (0x202)
1045#define SPR_BOOKE_ATBL (0x20E)
1046#define SPR_BOOKE_ATBU (0x20F)
1047#define SPR_IBAT0U (0x210)
363be49c 1048#define SPR_BOOKE_IVOR32 (0x210)
76a66253 1049#define SPR_IBAT0L (0x211)
363be49c 1050#define SPR_BOOKE_IVOR33 (0x211)
76a66253 1051#define SPR_IBAT1U (0x212)
363be49c 1052#define SPR_BOOKE_IVOR34 (0x212)
76a66253 1053#define SPR_IBAT1L (0x213)
363be49c 1054#define SPR_BOOKE_IVOR35 (0x213)
76a66253 1055#define SPR_IBAT2U (0x214)
363be49c 1056#define SPR_BOOKE_IVOR36 (0x214)
76a66253
JM		 1057#define SPR_IBAT2L (0x215)
1058#define SPR_E500_L1CFG0 (0x215)
363be49c 1059#define SPR_BOOKE_IVOR37 (0x215)
76a66253
JM		 1060#define SPR_IBAT3U (0x216)
1061#define SPR_E500_L1CFG1 (0x216)
1062#define SPR_IBAT3L (0x217)
1063#define SPR_DBAT0U (0x218)
1064#define SPR_DBAT0L (0x219)
1065#define SPR_DBAT1U (0x21A)
1066#define SPR_DBAT1L (0x21B)
1067#define SPR_DBAT2U (0x21C)
1068#define SPR_DBAT2L (0x21D)
1069#define SPR_DBAT3U (0x21E)
1070#define SPR_DBAT3L (0x21F)
1071#define SPR_IBAT4U (0x230)
1072#define SPR_IBAT4L (0x231)
1073#define SPR_IBAT5U (0x232)
1074#define SPR_IBAT5L (0x233)
1075#define SPR_IBAT6U (0x234)
1076#define SPR_IBAT6L (0x235)
1077#define SPR_IBAT7U (0x236)
1078#define SPR_IBAT7L (0x237)
1079#define SPR_DBAT4U (0x238)
1080#define SPR_DBAT4L (0x239)
1081#define SPR_DBAT5U (0x23A)
363be49c 1082#define SPR_BOOKE_MCSRR0 (0x23A)
76a66253 1083#define SPR_DBAT5L (0x23B)
363be49c 1084#define SPR_BOOKE_MCSRR1 (0x23B)
76a66253 1085#define SPR_DBAT6U (0x23C)
363be49c 1086#define SPR_BOOKE_MCSR (0x23C)
76a66253
JM		 1087#define SPR_DBAT6L (0x23D)
1088#define SPR_E500_MCAR (0x23D)
1089#define SPR_DBAT7U (0x23E)
363be49c 1090#define SPR_BOOKE_DSRR0 (0x23E)
76a66253 1091#define SPR_DBAT7L (0x23F)
363be49c
JM		 1092#define SPR_BOOKE_DSRR1 (0x23F)
1093#define SPR_BOOKE_SPRG8 (0x25C)
1094#define SPR_BOOKE_SPRG9 (0x25D)
1095#define SPR_BOOKE_MAS0 (0x270)
1096#define SPR_BOOKE_MAS1 (0x271)
1097#define SPR_BOOKE_MAS2 (0x272)
1098#define SPR_BOOKE_MAS3 (0x273)
1099#define SPR_BOOKE_MAS4 (0x274)
1100#define SPR_BOOKE_MAS6 (0x276)
1101#define SPR_BOOKE_PID1 (0x279)
1102#define SPR_BOOKE_PID2 (0x27A)
1103#define SPR_BOOKE_TLB0CFG (0x2B0)
1104#define SPR_BOOKE_TLB1CFG (0x2B1)
1105#define SPR_BOOKE_TLB2CFG (0x2B2)
1106#define SPR_BOOKE_TLB3CFG (0x2B3)
1107#define SPR_BOOKE_EPR (0x2BE)
76a66253
JM		 1108#define SPR_440_INV0 (0x370)
1109#define SPR_440_INV1 (0x371)
1110#define SPR_440_INV2 (0x372)
1111#define SPR_440_INV3 (0x373)
1112#define SPR_440_IVT0 (0x374)
1113#define SPR_440_IVT1 (0x375)
1114#define SPR_440_IVT2 (0x376)
1115#define SPR_440_IVT3 (0x377)
1116#define SPR_440_DNV0 (0x390)
1117#define SPR_440_DNV1 (0x391)
1118#define SPR_440_DNV2 (0x392)
1119#define SPR_440_DNV3 (0x393)
1120#define SPR_440_DVT0 (0x394)
1121#define SPR_440_DVT1 (0x395)
1122#define SPR_440_DVT2 (0x396)
1123#define SPR_440_DVT3 (0x397)
1124#define SPR_440_DVLIM (0x398)
1125#define SPR_440_IVLIM (0x399)
1126#define SPR_440_RSTCFG (0x39B)
363be49c
JM		 1127#define SPR_BOOKE_DCBTRL (0x39C)
1128#define SPR_BOOKE_DCBTRH (0x39D)
1129#define SPR_BOOKE_ICBTRL (0x39E)
1130#define SPR_BOOKE_ICBTRH (0x39F)
76a66253
JM		 1131#define SPR_UMMCR0 (0x3A8)
1132#define SPR_UPMC1 (0x3A9)
1133#define SPR_UPMC2 (0x3AA)
1134#define SPR_USIA (0x3AB)
1135#define SPR_UMMCR1 (0x3AC)
1136#define SPR_UPMC3 (0x3AD)
1137#define SPR_UPMC4 (0x3AE)
1138#define SPR_USDA (0x3AF)
1139#define SPR_40x_ZPR (0x3B0)
363be49c 1140#define SPR_BOOKE_MAS7 (0x3B0)
76a66253
JM		 1141#define SPR_40x_PID (0x3B1)
1142#define SPR_440_MMUCR (0x3B2)
1143#define SPR_4xx_CCR0 (0x3B3)
363be49c 1144#define SPR_BOOKE_EPLC (0x3B3)
76a66253 1145#define SPR_405_IAC3 (0x3B4)
363be49c 1146#define SPR_BOOKE_EPSC (0x3B4)
76a66253
JM		 1147#define SPR_405_IAC4 (0x3B5)
1148#define SPR_405_DVC1 (0x3B6)
1149#define SPR_405_DVC2 (0x3B7)
1150#define SPR_MMCR0 (0x3B8)
1151#define SPR_PMC1 (0x3B9)
1152#define SPR_40x_SGR (0x3B9)
1153#define SPR_PMC2 (0x3BA)
1154#define SPR_40x_DCWR (0x3BA)
1155#define SPR_SIA (0x3BB)
1156#define SPR_405_SLER (0x3BB)
1157#define SPR_MMCR1 (0x3BC)
1158#define SPR_405_SU0R (0x3BC)
1159#define SPR_PMC3 (0x3BD)
1160#define SPR_405_DBCR1 (0x3BD)
1161#define SPR_PMC4 (0x3BE)
1162#define SPR_SDA (0x3BF)
1163#define SPR_403_VTBL (0x3CC)
1164#define SPR_403_VTBU (0x3CD)
1165#define SPR_DMISS (0x3D0)
1166#define SPR_DCMP (0x3D1)
1167#define SPR_HASH1 (0x3D2)
1168#define SPR_HASH2 (0x3D3)
363be49c 1169#define SPR_BOOKE_ICBDR (0x3D3)
76a66253
JM		 1170#define SPR_IMISS (0x3D4)
1171#define SPR_40x_ESR (0x3D4)
1172#define SPR_ICMP (0x3D5)
1173#define SPR_40x_DEAR (0x3D5)
1174#define SPR_RPA (0x3D6)
1175#define SPR_40x_EVPR (0x3D6)
1176#define SPR_403_CDBCR (0x3D7)
1177#define SPR_TCR (0x3D8)
1178#define SPR_40x_TSR (0x3D8)
1179#define SPR_IBR (0x3DA)
1180#define SPR_40x_TCR (0x3DA)
1181#define SPR_ESASR (0x3DB)
1182#define SPR_40x_PIT (0x3DB)
1183#define SPR_403_TBL (0x3DC)
1184#define SPR_403_TBU (0x3DD)
1185#define SPR_SEBR (0x3DE)
1186#define SPR_40x_SRR2 (0x3DE)
1187#define SPR_SER (0x3DF)
1188#define SPR_40x_SRR3 (0x3DF)
1189#define SPR_HID0 (0x3F0)
1190#define SPR_40x_DBSR (0x3F0)
1191#define SPR_HID1 (0x3F1)
1192#define SPR_IABR (0x3F2)
1193#define SPR_40x_DBCR0 (0x3F2)
1194#define SPR_601_HID2 (0x3F2)
1195#define SPR_E500_L1CSR0 (0x3F2)
1196#define SPR_HID2 (0x3F3)
1197#define SPR_E500_L1CSR1 (0x3F3)
1198#define SPR_440_DBDR (0x3F3)
1199#define SPR_40x_IAC1 (0x3F4)
363be49c 1200#define SPR_BOOKE_MMUCSR0 (0x3F4)
76a66253 1201#define SPR_DABR (0x3F5)
3fc6c082 1202#define DABR_MASK (~(target_ulong)0x7)
76a66253
JM		 1203#define SPR_E500_BUCSR (0x3F5)
1204#define SPR_40x_IAC2 (0x3F5)
1205#define SPR_601_HID5 (0x3F5)
1206#define SPR_40x_DAC1 (0x3F6)
1207#define SPR_40x_DAC2 (0x3F7)
363be49c 1208#define SPR_BOOKE_MMUCFG (0x3F7)
76a66253
JM		 1209#define SPR_L2PM (0x3F8)
1210#define SPR_750_HID2 (0x3F8)
1211#define SPR_L2CR (0x3F9)
1212#define SPR_IABR2 (0x3FA)
1213#define SPR_40x_DCCR (0x3FA)
1214#define SPR_ICTC (0x3FB)
1215#define SPR_40x_ICCR (0x3FB)
1216#define SPR_THRM1 (0x3FC)
1217#define SPR_403_PBL1 (0x3FC)
1218#define SPR_SP (0x3FD)
1219#define SPR_THRM2 (0x3FD)
1220#define SPR_403_PBU1 (0x3FD)
1221#define SPR_LT (0x3FE)
1222#define SPR_THRM3 (0x3FE)
1223#define SPR_FPECR (0x3FE)
1224#define SPR_403_PBL2 (0x3FE)
1225#define SPR_PIR (0x3FF)
1226#define SPR_403_PBU2 (0x3FF)
1227#define SPR_601_HID15 (0x3FF)
1228#define SPR_E500_SVR (0x3FF)
79aceca5 1229
76a66253 1230/*****************************************************************************/
9a64fbe4
FB		 1231/* Memory access type :
1232 * may be needed for precise access rights control and precise exceptions.
1233 */
79aceca5 1234enum {
9a64fbe4
FB		 1235 /* 1 bit to define user level / supervisor access */
1236 ACCESS_USER = 0x00,
1237 ACCESS_SUPER = 0x01,
1238 /* Type of instruction that generated the access */
1239 ACCESS_CODE = 0x10, /* Code fetch access */
1240 ACCESS_INT = 0x20, /* Integer load/store access */
1241 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1242 ACCESS_RES = 0x40, /* load/store with reservation */
1243 ACCESS_EXT = 0x50, /* external access */
1244 ACCESS_CACHE = 0x60, /* Cache manipulation */
1245};
1246
1247/*****************************************************************************/
1248/* Exceptions */
2be0071f
FB		 1249#define EXCP_NONE -1
1250/* PowerPC hardware exceptions : exception vectors defined in PowerPC book 3 */
1251#define EXCP_RESET 0x0100 /* System reset */
1252#define EXCP_MACHINE_CHECK 0x0200 /* Machine check exception */
1253#define EXCP_DSI 0x0300 /* Data storage exception */
1254#define EXCP_DSEG 0x0380 /* Data segment exception */
1255#define EXCP_ISI 0x0400 /* Instruction storage exception */
1256#define EXCP_ISEG 0x0480 /* Instruction segment exception */
1257#define EXCP_EXTERNAL 0x0500 /* External interruption */
1258#define EXCP_ALIGN 0x0600 /* Alignment exception */
1259#define EXCP_PROGRAM 0x0700 /* Program exception */
1260#define EXCP_NO_FP 0x0800 /* Floating point unavailable exception */
1261#define EXCP_DECR 0x0900 /* Decrementer exception */
1262#define EXCP_HDECR 0x0980 /* Hypervisor decrementer exception */
1263#define EXCP_SYSCALL 0x0C00 /* System call */
1264#define EXCP_TRACE 0x0D00 /* Trace exception */
1265#define EXCP_PERF 0x0F00 /* Performance monitor exception */
1266/* Exceptions defined in PowerPC 32 bits programming environment manual */
1267#define EXCP_FP_ASSIST 0x0E00 /* Floating-point assist */
1268/* Implementation specific exceptions */
1269/* 40x exceptions */
1270#define EXCP_40x_PIT 0x1000 /* Programmable interval timer interrupt */
1271#define EXCP_40x_FIT 0x1010 /* Fixed interval timer interrupt */
1272#define EXCP_40x_WATCHDOG 0x1020 /* Watchdog timer exception */
1273#define EXCP_40x_DTLBMISS 0x1100 /* Data TLB miss exception */
1274#define EXCP_40x_ITLBMISS 0x1200 /* Instruction TLB miss exception */
1275#define EXCP_40x_DEBUG 0x2000 /* Debug exception */
1276/* 405 specific exceptions */
1277#define EXCP_405_APU 0x0F20 /* APU unavailable exception */
1278/* TLB assist exceptions (602/603) */
1279#define EXCP_I_TLBMISS 0x1000 /* Instruction TLB miss */
1280#define EXCP_DL_TLBMISS 0x1100 /* Data load TLB miss */
1281#define EXCP_DS_TLBMISS 0x1200 /* Data store TLB miss */
1282/* Breakpoint exceptions (602/603/604/620/740/745/750/755...) */
1283#define EXCP_IABR 0x1300 /* Instruction address breakpoint */
1284#define EXCP_SMI 0x1400 /* System management interrupt */
1285/* Altivec related exceptions */
1286#define EXCP_VPU 0x0F20 /* VPU unavailable exception */
1287/* 601 specific exceptions */
1288#define EXCP_601_IO 0x0600 /* IO error exception */
1289#define EXCP_601_RUNM 0x2000 /* Run mode exception */
1290/* 602 specific exceptions */
1291#define EXCP_602_WATCHDOG 0x1500 /* Watchdog exception */
1292#define EXCP_602_EMUL 0x1600 /* Emulation trap exception */
1293/* G2 specific exceptions */
1294#define EXCP_G2_CRIT 0x0A00 /* Critical interrupt */
1295/* MPC740/745/750 & IBM 750 specific exceptions */
1296#define EXCP_THRM 0x1700 /* Thermal management interrupt */
1297/* 74xx specific exceptions */
1298#define EXCP_74xx_VPUA 0x1600 /* VPU assist exception */
1299/* 970FX specific exceptions */
1300#define EXCP_970_SOFTP 0x1500 /* Soft patch exception */
1301#define EXCP_970_MAINT 0x1600 /* Maintenance exception */
1302#define EXCP_970_THRM 0x1800 /* Thermal exception */
1303#define EXCP_970_VPUA 0x1700 /* VPU assist exception */
0487d6a8
JM		 1304/* SPE related exceptions */
1305#define EXCP_NO_SPE 0x0F20 /* SPE unavailable exception */
2be0071f
FB		 1306/* End of exception vectors area */
1307#define EXCP_PPC_MAX 0x4000
1308/* Qemu exceptions: special cases we want to stop translation */
1309#define EXCP_MTMSR 0x11000 /* mtmsr instruction: */
76a66253 1310 /* may change privilege level */
2be0071f
FB		 1311#define EXCP_BRANCH 0x11001 /* branch instruction */
1312#define EXCP_SYSCALL_USER 0x12000 /* System call in user mode only */
2be0071f 1313
9a64fbe4
FB		 1314/* Error codes */
1315enum {
9a64fbe4
FB		 1316 /* Exception subtypes for EXCP_ALIGN */
1317 EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
1318 EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
1319 EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
1320 EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
1321 EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
1322 EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
1323 /* Exception subtypes for EXCP_PROGRAM */
79aceca5 1324 /* FP exceptions */
9a64fbe4
FB		 1325 EXCP_FP = 0x10,
1326 EXCP_FP_OX = 0x01, /* FP overflow */
1327 EXCP_FP_UX = 0x02, /* FP underflow */
1328 EXCP_FP_ZX = 0x03, /* FP divide by zero */
1329 EXCP_FP_XX = 0x04, /* FP inexact */
1330 EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */
0cfec834 1331 EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
9a64fbe4
FB		 1332 EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
1333 EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
1334 EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
1335 EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
1336 EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
1337 EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
1338 EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
79aceca5 1339 /* Invalid instruction */
9a64fbe4
FB		 1340 EXCP_INVAL = 0x20,
1341 EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
1342 EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
1343 EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
1344 EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
79aceca5 1345 /* Privileged instruction */
9a64fbe4 1346 EXCP_PRIV = 0x30,
8b67546f
JM		 1347 EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
1348 EXCP_PRIV_REG = 0x02, /* Privileged register exception */
79aceca5 1349 /* Trap */
9a64fbe4 1350 EXCP_TRAP = 0x40,
79aceca5
FB		 1351};
1352
47103572
JM		 1353/* Hardware interruption sources:
1354 * all those exception can be raised simulteaneously
1355 */
e9df014c
JM		 1356/* Input pins definitions */
1357enum {
1358 /* 6xx bus input pins */
24be5ae3
JM		 1359 PPC6xx_INPUT_HRESET = 0,
1360 PPC6xx_INPUT_SRESET = 1,
1361 PPC6xx_INPUT_CKSTP_IN = 2,
1362 PPC6xx_INPUT_MCP = 3,
1363 PPC6xx_INPUT_SMI = 4,
1364 PPC6xx_INPUT_INT = 5,
1365};
1366
1367enum {
e9df014c 1368 /* Embedded PowerPC input pins */
24be5ae3
JM		 1369 PPCBookE_INPUT_HRESET = 0,
1370 PPCBookE_INPUT_SRESET = 1,
1371 PPCBookE_INPUT_CKSTP_IN = 2,
1372 PPCBookE_INPUT_MCP = 3,
1373 PPCBookE_INPUT_SMI = 4,
1374 PPCBookE_INPUT_INT = 5,
1375 PPCBookE_INPUT_CINT = 6,
1376};
1377
1378enum {
1379 /* PowerPC 405 input pins */
1380 PPC405_INPUT_RESET_CORE = 0,
1381 PPC405_INPUT_RESET_CHIP = 1,
1382 PPC405_INPUT_RESET_SYS = 2,
1383 PPC405_INPUT_CINT = 3,
1384 PPC405_INPUT_INT = 4,
1385 PPC405_INPUT_HALT = 5,
1386 PPC405_INPUT_DEBUG = 6,
e9df014c
JM		 1387};
1388
d0dfae6e
JM		 1389enum {
1390 /* PowerPC 970 input pins */
1391 PPC970_INPUT_HRESET = 0,
1392 PPC970_INPUT_SRESET = 1,
1393 PPC970_INPUT_CKSTP = 2,
1394 PPC970_INPUT_TBEN = 3,
1395 PPC970_INPUT_MCP = 4,
1396 PPC970_INPUT_INT = 5,
1397 PPC970_INPUT_THINT = 6,
1398};
1399
e9df014c 1400/* Hardware exceptions definitions */
47103572 1401enum {
e9df014c
JM		 1402 /* External hardware exception sources */
1403 PPC_INTERRUPT_RESET = 0, /* Reset exception */
1404 PPC_INTERRUPT_MCK = 1, /* Machine check exception */
1405 PPC_INTERRUPT_EXT = 2, /* External interrupt */
1406 PPC_INTERRUPT_SMI = 3, /* System management interrupt */
1407 PPC_INTERRUPT_CEXT = 4, /* Critical external interrupt */
1408 PPC_INTERRUPT_DEBUG = 5, /* External debug exception */
d0dfae6e 1409 PPC_INTERRUPT_THERM = 6, /* Thermal exception */
e9df014c 1410 /* Internal hardware exception sources */
d0dfae6e
JM		 1411 PPC_INTERRUPT_DECR = 7, /* Decrementer exception */
1412 PPC_INTERRUPT_HDECR = 8, /* Hypervisor decrementer exception */
1413 PPC_INTERRUPT_PIT = 9, /* Programmable inteval timer interrupt */
1414 PPC_INTERRUPT_FIT = 10, /* Fixed interval timer interrupt */
1415 PPC_INTERRUPT_WDT = 11, /* Watchdog timer interrupt */
47103572
JM		 1416};
1417
9a64fbe4
FB		 1418/*****************************************************************************/
1419
79aceca5 1420#endif /* !defined (__CPU_PPC_H__) */
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