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Define Freescale cores specific MMU model, exceptions and input bus.
[qemu.git] / target-ppc / cpu.h
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation cpu definitions for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#if !defined (__CPU_PPC_H__)
21#define __CPU_PPC_H__
22
3fc6c082 23#include "config.h"
de270b3c 24#include <inttypes.h>
3fc6c082 25
a4f30719
JM		 26//#define PPC_EMULATE_32BITS_HYPV
27
76a66253 28#if defined (TARGET_PPC64)
3cd7d1dd 29/* PowerPC 64 definitions */
76a66253 30typedef uint64_t ppc_gpr_t;
0487d6a8 31#define TARGET_GPR_BITS 64
d9d7210c 32#define TARGET_LONG_BITS 64
76a66253 33#define REGX "%016" PRIx64
35cdaad6 34#define TARGET_PAGE_BITS 12
3cd7d1dd
JM		 35
36#else /* defined (TARGET_PPC64) */
37/* PowerPC 32 definitions */
d9d7210c
JM		 38#if (HOST_LONG_BITS >= 64)
39/* When using 64 bits temporary registers,
40 * we can use 64 bits GPR with no extra cost
3cd7d1dd 41 * It's even an optimization as this will prevent
d9d7210c
JM		 42 * the compiler to do unuseful masking in the micro-ops.
43 */
44typedef uint64_t ppc_gpr_t;
45#define TARGET_GPR_BITS 64
71c8b8fd 46#define REGX "%08" PRIx64
3cd7d1dd 47#else /* (HOST_LONG_BITS >= 64) */
76a66253 48typedef uint32_t ppc_gpr_t;
0487d6a8 49#define TARGET_GPR_BITS 32
71c8b8fd 50#define REGX "%08" PRIx32
3cd7d1dd
JM		 51#endif /* (HOST_LONG_BITS >= 64) */
52
d9d7210c 53#define TARGET_LONG_BITS 32
3cd7d1dd
JM		 54
55#if defined(TARGET_PPCEMB)
56/* Specific definitions for PowerPC embedded */
57/* BookE have 36 bits physical address space */
58#define TARGET_PHYS_ADDR_BITS 64
59#if defined(CONFIG_USER_ONLY)
60/* It looks like a lot of Linux programs assume page size
61 * is 4kB long. This is evil, but we have to deal with it...
62 */
35cdaad6 63#define TARGET_PAGE_BITS 12
3cd7d1dd
JM		 64#else /* defined(CONFIG_USER_ONLY) */
65/* Pages can be 1 kB small */
66#define TARGET_PAGE_BITS 10
67#endif /* defined(CONFIG_USER_ONLY) */
68#else /* defined(TARGET_PPCEMB) */
69/* "standard" PowerPC 32 definitions */
70#define TARGET_PAGE_BITS 12
71#endif /* defined(TARGET_PPCEMB) */
72
73#endif /* defined (TARGET_PPC64) */
3cf1e035 74
79aceca5
FB		 75#include "cpu-defs.h"
76
e96efcfc
JM		 77#define ADDRX TARGET_FMT_lx
78#define PADDRX TARGET_FMT_plx
79
79aceca5
FB		 80#include <setjmp.h>
81
4ecc3190
FB		 82#include "softfloat.h"
83
1fddef4b
FB		 84#define TARGET_HAS_ICE 1
85
76a66253
JM		 86#if defined (TARGET_PPC64)
87#define ELF_MACHINE EM_PPC64
88#else
89#define ELF_MACHINE EM_PPC
90#endif
9042c0e2 91
3fc6c082 92/*****************************************************************************/
a750fc0b 93/* MMU model */
7820dbf3
JM		 94typedef enum powerpc_mmu_t powerpc_mmu_t;
95enum powerpc_mmu_t {
a750fc0b
JM		 96 POWERPC_MMU_UNKNOWN = 0,
97 /* Standard 32 bits PowerPC MMU */
98 POWERPC_MMU_32B,
a750fc0b
JM		 99 /* PowerPC 6xx MMU with software TLB */
100 POWERPC_MMU_SOFT_6xx,
101 /* PowerPC 74xx MMU with software TLB */
102 POWERPC_MMU_SOFT_74xx,
103 /* PowerPC 4xx MMU with software TLB */
104 POWERPC_MMU_SOFT_4xx,
105 /* PowerPC 4xx MMU with software TLB and zones protections */
106 POWERPC_MMU_SOFT_4xx_Z,
b4095fed
JM		 107 /* PowerPC MMU in real mode only */
108 POWERPC_MMU_REAL,
109 /* Freescale MPC8xx MMU model */
110 POWERPC_MMU_MPC8xx,
a750fc0b
JM		 111 /* BookE MMU model */
112 POWERPC_MMU_BOOKE,
113 /* BookE FSL MMU model */
114 POWERPC_MMU_BOOKE_FSL,
faadf50e
JM		 115 /* PowerPC 601 MMU model (specific BATs format) */
116 POWERPC_MMU_601,
00af685f 117#if defined(TARGET_PPC64)
12de9a39 118 /* 64 bits PowerPC MMU */
00af685f 119 POWERPC_MMU_64B,
00af685f 120#endif /* defined(TARGET_PPC64) */
3fc6c082
FB		 121};
122
123/*****************************************************************************/
a750fc0b 124/* Exception model */
7820dbf3
JM		 125typedef enum powerpc_excp_t powerpc_excp_t;
126enum powerpc_excp_t {
a750fc0b 127 POWERPC_EXCP_UNKNOWN = 0,
3fc6c082 128 /* Standard PowerPC exception model */
a750fc0b 129 POWERPC_EXCP_STD,
2662a059 130 /* PowerPC 40x exception model */
a750fc0b 131 POWERPC_EXCP_40x,
2662a059 132 /* PowerPC 601 exception model */
a750fc0b 133 POWERPC_EXCP_601,
2662a059 134 /* PowerPC 602 exception model */
a750fc0b 135 POWERPC_EXCP_602,
2662a059 136 /* PowerPC 603 exception model */
a750fc0b
JM		 137 POWERPC_EXCP_603,
138 /* PowerPC 603e exception model */
139 POWERPC_EXCP_603E,
140 /* PowerPC G2 exception model */
141 POWERPC_EXCP_G2,
2662a059 142 /* PowerPC 604 exception model */
a750fc0b 143 POWERPC_EXCP_604,
2662a059 144 /* PowerPC 7x0 exception model */
a750fc0b 145 POWERPC_EXCP_7x0,
2662a059 146 /* PowerPC 7x5 exception model */
a750fc0b 147 POWERPC_EXCP_7x5,
2662a059 148 /* PowerPC 74xx exception model */
a750fc0b 149 POWERPC_EXCP_74xx,
2662a059 150 /* BookE exception model */
a750fc0b 151 POWERPC_EXCP_BOOKE,
00af685f
JM		 152#if defined(TARGET_PPC64)
153 /* PowerPC 970 exception model */
154 POWERPC_EXCP_970,
155#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 156};
157
e1833e1f
JM		 158/*****************************************************************************/
159/* Exception vectors definitions */
160enum {
161 POWERPC_EXCP_NONE = -1,
162 /* The 64 first entries are used by the PowerPC embedded specification */
163 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
164 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
165 POWERPC_EXCP_DSI = 2, /* Data storage exception */
166 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
167 POWERPC_EXCP_EXTERNAL = 4, /* External input */
168 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
169 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
170 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
171 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
172 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
173 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
174 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
175 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
b4095fed
JM		 176 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
177 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
e1833e1f
JM		 178 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
179 /* Vectors 16 to 31 are reserved */
e1833e1f
JM		 180 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
181 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
182 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
183 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
184 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
185 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
e1833e1f
JM		 186 /* Vectors 38 to 63 are reserved */
187 /* Exceptions defined in the PowerPC server specification */
188 POWERPC_EXCP_RESET = 64, /* System reset exception */
e1833e1f
JM		 189 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
190 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
e1833e1f 191 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
e1833e1f 192 POWERPC_EXCP_TRACE = 68, /* Trace exception */
e1833e1f
JM		 193 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
194 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
195 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
196 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
e1833e1f
JM		 197 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
198 /* 40x specific exceptions */
199 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
200 /* 601 specific exceptions */
201 POWERPC_EXCP_IO = 75, /* IO error exception */
202 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
203 /* 602 specific exceptions */
204 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
205 /* 602/603 specific exceptions */
b4095fed 206 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
e1833e1f
JM		 207 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
208 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
209 /* Exceptions available on most PowerPC */
210 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
b4095fed
JM		 211 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
212 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
213 POWERPC_EXCP_SMI = 84, /* System management interrupt */
214 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
e1833e1f 215 /* 7xx/74xx specific exceptions */
b4095fed 216 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
e1833e1f 217 /* 74xx specific exceptions */
b4095fed 218 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
e1833e1f 219 /* 970FX specific exceptions */
b4095fed
JM		 220 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
221 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
222 /* Freescale embeded cores specific exceptions */
223 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
224 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
225 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
226 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
e1833e1f
JM		 227 /* EOL */
228 POWERPC_EXCP_NB = 96,
229 /* Qemu exceptions: used internally during code translation */
230 POWERPC_EXCP_STOP = 0x200, /* stop translation */
231 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
232 /* Qemu exceptions: special cases we want to stop translation */
233 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
234 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
235};
236
e1833e1f
JM		 237/* Exceptions error codes */
238enum {
239 /* Exception subtypes for POWERPC_EXCP_ALIGN */
240 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
241 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
242 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
243 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
244 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
245 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
246 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
247 /* FP exceptions */
248 POWERPC_EXCP_FP = 0x10,
249 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
250 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
251 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
252 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
7c58044c 253 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
e1833e1f
JM		 254 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
255 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
256 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
257 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
258 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
259 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
260 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
261 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
262 /* Invalid instruction */
263 POWERPC_EXCP_INVAL = 0x20,
264 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
265 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
266 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
267 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
268 /* Privileged instruction */
269 POWERPC_EXCP_PRIV = 0x30,
270 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
271 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
272 /* Trap */
273 POWERPC_EXCP_TRAP = 0x40,
274};
275
a750fc0b
JM		 276/*****************************************************************************/
277/* Input pins model */
7820dbf3
JM		 278typedef enum powerpc_input_t powerpc_input_t;
279enum powerpc_input_t {
a750fc0b 280 PPC_FLAGS_INPUT_UNKNOWN = 0,
2662a059 281 /* PowerPC 6xx bus */
a750fc0b 282 PPC_FLAGS_INPUT_6xx,
2662a059 283 /* BookE bus */
a750fc0b
JM		 284 PPC_FLAGS_INPUT_BookE,
285 /* PowerPC 405 bus */
286 PPC_FLAGS_INPUT_405,
2662a059 287 /* PowerPC 970 bus */
a750fc0b
JM		 288 PPC_FLAGS_INPUT_970,
289 /* PowerPC 401 bus */
290 PPC_FLAGS_INPUT_401,
b4095fed
JM		 291 /* Freescale RCPU bus */
292 PPC_FLAGS_INPUT_RCPU,
3fc6c082
FB		 293};
294
a750fc0b 295#define PPC_INPUT(env) (env->bus_model)
3fc6c082 296
be147d08 297/*****************************************************************************/
3fc6c082 298typedef struct ppc_def_t ppc_def_t;
a750fc0b 299typedef struct opc_handler_t opc_handler_t;
79aceca5 300
3fc6c082
FB		 301/*****************************************************************************/
302/* Types used to describe some PowerPC registers */
303typedef struct CPUPPCState CPUPPCState;
9fddaa0c 304typedef struct ppc_tb_t ppc_tb_t;
3fc6c082
FB		 305typedef struct ppc_spr_t ppc_spr_t;
306typedef struct ppc_dcr_t ppc_dcr_t;
a9d9eb8f 307typedef union ppc_avr_t ppc_avr_t;
1d0a48fb 308typedef union ppc_tlb_t ppc_tlb_t;
76a66253 309
3fc6c082
FB		 310/* SPR access micro-ops generations callbacks */
311struct ppc_spr_t {
312 void (*uea_read)(void *opaque, int spr_num);
313 void (*uea_write)(void *opaque, int spr_num);
76a66253 314#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 315 void (*oea_read)(void *opaque, int spr_num);
316 void (*oea_write)(void *opaque, int spr_num);
be147d08
JM		 317 void (*hea_read)(void *opaque, int spr_num);
318 void (*hea_write)(void *opaque, int spr_num);
76a66253 319#endif
3fc6c082
FB		 320 const unsigned char *name;
321};
322
323/* Altivec registers (128 bits) */
a9d9eb8f
JM		 324union ppc_avr_t {
325 uint8_t u8[16];
326 uint16_t u16[8];
327 uint32_t u32[4];
328 uint64_t u64[2];
3fc6c082 329};
9fddaa0c 330
3fc6c082 331/* Software TLB cache */
1d0a48fb
JM		 332typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
333struct ppc6xx_tlb_t {
76a66253
JM		 334 target_ulong pte0;
335 target_ulong pte1;
336 target_ulong EPN;
1d0a48fb
JM		 337};
338
339typedef struct ppcemb_tlb_t ppcemb_tlb_t;
340struct ppcemb_tlb_t {
c55e9aef 341 target_phys_addr_t RPN;
1d0a48fb 342 target_ulong EPN;
76a66253 343 target_ulong PID;
c55e9aef
JM		 344 target_ulong size;
345 uint32_t prot;
346 uint32_t attr; /* Storage attributes */
1d0a48fb
JM		 347};
348
349union ppc_tlb_t {
350 ppc6xx_tlb_t tlb6;
351 ppcemb_tlb_t tlbe;
3fc6c082
FB		 352};
353
354/*****************************************************************************/
355/* Machine state register bits definition */
76a66253 356#define MSR_SF 63 /* Sixty-four-bit mode hflags */
3fc6c082 357#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
a4f30719 358#define MSR_SHV 60 /* hypervisor state hflags */
363be49c
JM		 359#define MSR_CM 31 /* Computation mode for BookE hflags */
360#define MSR_ICM 30 /* Interrupt computation mode for BookE */
a4f30719 361#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
363be49c 362#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
d26bfc9a
JM		 363#define MSR_VR 25 /* altivec available x hflags */
364#define MSR_SPE 25 /* SPE enable for BookE x hflags */
76a66253
JM		 365#define MSR_AP 23 /* Access privilege state on 602 hflags */
366#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
3fc6c082 367#define MSR_KEY 19 /* key bit on 603e */
25ba3a68 368#define MSR_POW 18 /* Power management */
d26bfc9a
JM		 369#define MSR_TGPR 17 /* TGPR usage on 602/603 x */
370#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
3fc6c082
FB		 371#define MSR_ILE 16 /* Interrupt little-endian mode */
372#define MSR_EE 15 /* External interrupt enable */
76a66253
JM		 373#define MSR_PR 14 /* Problem state hflags */
374#define MSR_FP 13 /* Floating point available hflags */
3fc6c082 375#define MSR_ME 12 /* Machine check interrupt enable */
76a66253 376#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
d26bfc9a
JM		 377#define MSR_SE 10 /* Single-step trace enable x hflags */
378#define MSR_DWE 10 /* Debug wait enable on 405 x */
379#define MSR_UBLE 10 /* User BTB lock enable on e500 x */
380#define MSR_BE 9 /* Branch trace enable x hflags */
381#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
76a66253 382#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
3fc6c082 383#define MSR_AL 7 /* AL bit on POWER */
0411a972 384#define MSR_EP 6 /* Exception prefix on 601 */
3fc6c082 385#define MSR_IR 5 /* Instruction relocate */
3fc6c082 386#define MSR_DR 4 /* Data relocate */
25ba3a68 387#define MSR_PE 3 /* Protection enable on 403 */
d26bfc9a
JM		 388#define MSR_PX 2 /* Protection exclusive on 403 x */
389#define MSR_PMM 2 /* Performance monitor mark on POWER x */
390#define MSR_RI 1 /* Recoverable interrupt 1 */
391#define MSR_LE 0 /* Little-endian mode 1 hflags */
0411a972
JM		 392
393#define msr_sf ((env->msr >> MSR_SF) & 1)
394#define msr_isf ((env->msr >> MSR_ISF) & 1)
a4f30719 395#define msr_shv ((env->msr >> MSR_SHV) & 1)
0411a972
JM		 396#define msr_cm ((env->msr >> MSR_CM) & 1)
397#define msr_icm ((env->msr >> MSR_ICM) & 1)
a4f30719 398#define msr_thv ((env->msr >> MSR_THV) & 1)
0411a972
JM		 399#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
400#define msr_vr ((env->msr >> MSR_VR) & 1)
401#define msr_spe ((env->msr >> MSR_SE) & 1)
402#define msr_ap ((env->msr >> MSR_AP) & 1)
403#define msr_sa ((env->msr >> MSR_SA) & 1)
404#define msr_key ((env->msr >> MSR_KEY) & 1)
405#define msr_pow ((env->msr >> MSR_POW) & 1)
406#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
407#define msr_ce ((env->msr >> MSR_CE) & 1)
408#define msr_ile ((env->msr >> MSR_ILE) & 1)
409#define msr_ee ((env->msr >> MSR_EE) & 1)
410#define msr_pr ((env->msr >> MSR_PR) & 1)
411#define msr_fp ((env->msr >> MSR_FP) & 1)
412#define msr_me ((env->msr >> MSR_ME) & 1)
413#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
414#define msr_se ((env->msr >> MSR_SE) & 1)
415#define msr_dwe ((env->msr >> MSR_DWE) & 1)
416#define msr_uble ((env->msr >> MSR_UBLE) & 1)
417#define msr_be ((env->msr >> MSR_BE) & 1)
418#define msr_de ((env->msr >> MSR_DE) & 1)
419#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
420#define msr_al ((env->msr >> MSR_AL) & 1)
421#define msr_ep ((env->msr >> MSR_EP) & 1)
422#define msr_ir ((env->msr >> MSR_IR) & 1)
423#define msr_dr ((env->msr >> MSR_DR) & 1)
424#define msr_pe ((env->msr >> MSR_PE) & 1)
425#define msr_px ((env->msr >> MSR_PX) & 1)
426#define msr_pmm ((env->msr >> MSR_PMM) & 1)
427#define msr_ri ((env->msr >> MSR_RI) & 1)
428#define msr_le ((env->msr >> MSR_LE) & 1)
a4f30719
JM		 429/* Hypervisor bit is more specific */
430#if defined(TARGET_PPC64)
431#define MSR_HVB (1ULL << MSR_SHV)
432#define msr_hv msr_shv
433#else
434#if defined(PPC_EMULATE_32BITS_HYPV)
435#define MSR_HVB (1ULL << MSR_THV)
436#define msr_hv msr_thv
437#define
438#else
439#define MSR_HVB (0ULL)
440#define msr_hv (0)
441#endif
442#endif
79aceca5 443
d26bfc9a 444enum {
d26bfc9a
JM		 445 POWERPC_FLAG_NONE = 0x00000000,
446 /* Flag for MSR bit 25 signification (VRE/SPE) */
447 POWERPC_FLAG_SPE = 0x00000001,
448 POWERPC_FLAG_VRE = 0x00000002,
d26bfc9a 449 /* Flag for MSR bit 17 signification (TGPR/CE) */
25ba3a68
JM		 450 POWERPC_FLAG_TGPR = 0x00000004,
451 POWERPC_FLAG_CE = 0x00000008,
d26bfc9a 452 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
25ba3a68
JM		 453 POWERPC_FLAG_SE = 0x00000010,
454 POWERPC_FLAG_DWE = 0x00000020,
455 POWERPC_FLAG_UBLE = 0x00000040,
d26bfc9a 456 /* Flag for MSR bit 9 signification (BE/DE) */
25ba3a68
JM		 457 POWERPC_FLAG_BE = 0x00000080,
458 POWERPC_FLAG_DE = 0x00000100,
a4f30719 459 /* Flag for MSR bit 2 signification (PX/PMM) */
25ba3a68
JM		 460 POWERPC_FLAG_PX = 0x00000200,
461 POWERPC_FLAG_PMM = 0x00000400,
d26bfc9a
JM		 462};
463
7c58044c
JM		 464/*****************************************************************************/
465/* Floating point status and control register */
466#define FPSCR_FX 31 /* Floating-point exception summary */
467#define FPSCR_FEX 30 /* Floating-point enabled exception summary */
468#define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
469#define FPSCR_OX 28 /* Floating-point overflow exception */
470#define FPSCR_UX 27 /* Floating-point underflow exception */
471#define FPSCR_ZX 26 /* Floating-point zero divide exception */
472#define FPSCR_XX 25 /* Floating-point inexact exception */
473#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
474#define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
475#define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
476#define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
477#define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
478#define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
479#define FPSCR_FR 18 /* Floating-point fraction rounded */
480#define FPSCR_FI 17 /* Floating-point fraction inexact */
481#define FPSCR_C 16 /* Floating-point result class descriptor */
482#define FPSCR_FL 15 /* Floating-point less than or negative */
483#define FPSCR_FG 14 /* Floating-point greater than or negative */
484#define FPSCR_FE 13 /* Floating-point equal or zero */
485#define FPSCR_FU 12 /* Floating-point unordered or NaN */
486#define FPSCR_FPCC 12 /* Floating-point condition code */
487#define FPSCR_FPRF 12 /* Floating-point result flags */
488#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
489#define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
490#define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
491#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
492#define FPSCR_OE 6 /* Floating-point overflow exception enable */
493#define FPSCR_UE 5 /* Floating-point undeflow exception enable */
494#define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
495#define FPSCR_XE 3 /* Floating-point inexact exception enable */
496#define FPSCR_NI 2 /* Floating-point non-IEEE mode */
497#define FPSCR_RN1 1
498#define FPSCR_RN 0 /* Floating-point rounding control */
499#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
500#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
501#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
502#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
503#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
504#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
505#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
506#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
507#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
508#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
509#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
510#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
511#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
512#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
513#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
514#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
515#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
516#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
517#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
518#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
519#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
520#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
521#define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
522/* Invalid operation exception summary */
523#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
524 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
525 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
526 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
527 (1 << FPSCR_VXCVI)))
528/* exception summary */
529#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
530/* enabled exception summary */
531#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
532 0x1F)
533
534/*****************************************************************************/
535/* The whole PowerPC CPU context */
6ebbf390 536#define NB_MMU_MODES 3
6ebbf390 537
3fc6c082
FB		 538struct CPUPPCState {
539 /* First are the most commonly used resources
540 * during translated code execution
541 */
57c26279 542#if (HOST_LONG_BITS == 32)
3fc6c082 543 /* temporary fixed-point registers
57c26279 544 * used to emulate 64 bits registers on 32 bits hosts
5fafdf24 545 */
57c26279 546 uint64_t t0, t1, t2;
3fc6c082 547#endif
a9d9eb8f 548 ppc_avr_t avr0, avr1, avr2;
d9bce9d9 549
79aceca5 550 /* general purpose registers */
76a66253 551 ppc_gpr_t gpr[32];
65d6c0f3 552#if !defined(TARGET_PPC64)
3cd7d1dd
JM		 553 /* Storage for GPR MSB, used by the SPE extension */
554 ppc_gpr_t gprh[32];
555#endif
3fc6c082
FB		 556 /* LR */
557 target_ulong lr;
558 /* CTR */
559 target_ulong ctr;
560 /* condition register */
561 uint8_t crf[8];
79aceca5 562 /* XER */
3fc6c082
FB		 563 /* XXX: We use only 5 fields, but we want to keep the structure aligned */
564 uint8_t xer[8];
79aceca5 565 /* Reservation address */
3fc6c082
FB		 566 target_ulong reserve;
567
568 /* Those ones are used in supervisor mode only */
79aceca5 569 /* machine state register */
0411a972 570 target_ulong msr;
3fc6c082 571 /* temporary general purpose registers */
76a66253 572 ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
3fc6c082
FB		 573
574 /* Floating point execution context */
76a66253 575 /* temporary float registers */
4ecc3190
FB		 576 float64 ft0;
577 float64 ft1;
578 float64 ft2;
579 float_status fp_status;
3fc6c082
FB		 580 /* floating point registers */
581 float64 fpr[32];
582 /* floating point status and control register */
7c58044c 583 uint32_t fpscr;
4ecc3190 584
a316d335
FB		 585 CPU_COMMON
586
50443c98
FB		 587 int halted; /* TRUE if the CPU is in suspend state */
588
ac9eb073
FB		 589 int access_type; /* when a memory exception occurs, the access
590 type is stored here */
a541f297 591
f2e63a42
JM		 592 /* MMU context - only relevant for full system emulation */
593#if !defined(CONFIG_USER_ONLY)
594#if defined(TARGET_PPC64)
3fc6c082
FB		 595 /* Address space register */
596 target_ulong asr;
f2e63a42
JM		 597 /* PowerPC 64 SLB area */
598 int slb_nr;
599#endif
3fc6c082
FB		 600 /* segment registers */
601 target_ulong sdr1;
602 target_ulong sr[16];
603 /* BATs */
604 int nb_BATs;
605 target_ulong DBAT[2][8];
606 target_ulong IBAT[2][8];
f2e63a42
JM		 607 /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
608 int nb_tlb; /* Total number of TLB */
609 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
610 int nb_ways; /* Number of ways in the TLB set */
611 int last_way; /* Last used way used to allocate TLB in a LRU way */
612 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
613 int nb_pids; /* Number of available PID registers */
614 ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
615 /* 403 dedicated access protection registers */
616 target_ulong pb[4];
617#endif
9fddaa0c 618
3fc6c082
FB		 619 /* Other registers */
620 /* Special purpose registers */
621 target_ulong spr[1024];
f2e63a42 622 ppc_spr_t spr_cb[1024];
3fc6c082
FB		 623 /* Altivec registers */
624 ppc_avr_t avr[32];
625 uint32_t vscr;
d9bce9d9
JM		 626 /* SPE registers */
627 ppc_gpr_t spe_acc;
0487d6a8 628 float_status spe_status;
d9bce9d9 629 uint32_t spe_fscr;
3fc6c082
FB		 630
631 /* Internal devices resources */
9fddaa0c
FB		 632 /* Time base and decrementer */
633 ppc_tb_t *tb_env;
3fc6c082 634 /* Device control registers */
3fc6c082
FB		 635 ppc_dcr_t *dcr_env;
636
d63001d1
JM		 637 int dcache_line_size;
638 int icache_line_size;
639
3fc6c082
FB		 640 /* Those resources are used during exception processing */
641 /* CPU model definition */
a750fc0b 642 target_ulong msr_mask;
7820dbf3
JM		 643 powerpc_mmu_t mmu_model;
644 powerpc_excp_t excp_model;
645 powerpc_input_t bus_model;
237c0af0 646 int bfd_mach;
3fc6c082
FB		 647 uint32_t flags;
648
649 int exception_index;
650 int error_code;
651 int interrupt_request;
47103572 652 uint32_t pending_interrupts;
e9df014c
JM		 653#if !defined(CONFIG_USER_ONLY)
654 /* This is the IRQ controller, which is implementation dependant
655 * and only relevant when emulating a complete machine.
656 */
657 uint32_t irq_input_state;
658 void **irq_inputs;
e1833e1f
JM		 659 /* Exception vectors */
660 target_ulong excp_vectors[POWERPC_EXCP_NB];
661 target_ulong excp_prefix;
662 target_ulong ivor_mask;
663 target_ulong ivpr_mask;
d63001d1 664 target_ulong hreset_vector;
e9df014c 665#endif
3fc6c082
FB		 666
667 /* Those resources are used only during code translation */
668 /* Next instruction pointer */
669 target_ulong nip;
f2e63a42 670
3fc6c082
FB		 671 /* opcode handlers */
672 opc_handler_t *opcodes[0x40];
673
674 /* Those resources are used only in Qemu core */
675 jmp_buf jmp_env;
676 int user_mode_only; /* user mode only simulation */
056401ea
JM		 677 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
678 target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
6ebbf390 679 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
3fc6c082 680
9fddaa0c
FB		 681 /* Power management */
682 int power_mode;
cd346349 683 int (*check_pow)(CPUPPCState *env);
a541f297 684
6d506e6d
FB		 685 /* temporary hack to handle OSI calls (only used if non NULL) */
686 int (*osi_call)(struct CPUPPCState *env);
3fc6c082 687};
79aceca5 688
76a66253
JM		 689/* Context used internally during MMU translations */
690typedef struct mmu_ctx_t mmu_ctx_t;
691struct mmu_ctx_t {
692 target_phys_addr_t raddr; /* Real address */
693 int prot; /* Protection bits */
694 target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
695 target_ulong ptem; /* Virtual segment ID | API */
696 int key; /* Access key */
b227a8e9 697 int nx; /* Non-execute area */
76a66253
JM		 698};
699
3fc6c082 700/*****************************************************************************/
aaed909a 701CPUPPCState *cpu_ppc_init (const char *cpu_model);
36081602
JM		 702int cpu_ppc_exec (CPUPPCState *s);
703void cpu_ppc_close (CPUPPCState *s);
79aceca5
FB		 704/* you can call this signal handler from your SIGBUS and SIGSEGV
705 signal handlers to inform the virtual CPU of exceptions. non zero
706 is returned if the signal was handled by the virtual CPU. */
36081602
JM		 707int cpu_ppc_signal_handler (int host_signum, void *pinfo,
708 void *puc);
79aceca5 709
a541f297 710void do_interrupt (CPUPPCState *env);
e9df014c 711void ppc_hw_interrupt (CPUPPCState *env);
36081602 712void cpu_loop_exit (void);
a541f297 713
9a64fbe4 714void dump_stack (CPUPPCState *env);
a541f297 715
76a66253 716#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 717target_ulong do_load_ibatu (CPUPPCState *env, int nr);
718target_ulong do_load_ibatl (CPUPPCState *env, int nr);
719void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
720void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
721target_ulong do_load_dbatu (CPUPPCState *env, int nr);
722target_ulong do_load_dbatl (CPUPPCState *env, int nr);
723void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
724void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
056401ea
JM		 725void do_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);
726void do_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);
3fc6c082
FB		 727target_ulong do_load_sdr1 (CPUPPCState *env);
728void do_store_sdr1 (CPUPPCState *env, target_ulong value);
d9bce9d9
JM		 729#if defined(TARGET_PPC64)
730target_ulong ppc_load_asr (CPUPPCState *env);
731void ppc_store_asr (CPUPPCState *env, target_ulong value);
12de9a39
JM		 732target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
733void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs);
734#endif /* defined(TARGET_PPC64) */
735#if 0 // Unused
3fc6c082 736target_ulong do_load_sr (CPUPPCState *env, int srnum);
76a66253 737#endif
12de9a39
JM		 738void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
739#endif /* !defined(CONFIG_USER_ONLY) */
bfa1e5cf
JM		 740target_ulong ppc_load_xer (CPUPPCState *env);
741void ppc_store_xer (CPUPPCState *env, target_ulong value);
0411a972 742void ppc_store_msr (CPUPPCState *env, target_ulong value);
3fc6c082 743
0a032cbe 744void cpu_ppc_reset (void *opaque);
a541f297 745
3fc6c082 746void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
aaed909a
FB		 747
748const ppc_def_t *cpu_ppc_find_by_name (const unsigned char *name);
aaed909a 749int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
85c4adf6 750
9fddaa0c
FB		 751/* Time-base and decrementer management */
752#ifndef NO_CPU_IO_DEFS
753uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
754uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
755void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
756void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
a062e36c
JM		 757uint32_t cpu_ppc_load_atbl (CPUPPCState *env);
758uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
759void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
760void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
9fddaa0c
FB		 761uint32_t cpu_ppc_load_decr (CPUPPCState *env);
762void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
58a7d328
JM		 763uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
764void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
765uint64_t cpu_ppc_load_purr (CPUPPCState *env);
766void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
d9bce9d9
JM		 767uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
768uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
769#if !defined(CONFIG_USER_ONLY)
770void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
771void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
772target_ulong load_40x_pit (CPUPPCState *env);
773void store_40x_pit (CPUPPCState *env, target_ulong val);
8ecc7913 774void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
c294fc58 775void store_40x_sler (CPUPPCState *env, uint32_t val);
d9bce9d9
JM		 776void store_booke_tcr (CPUPPCState *env, target_ulong val);
777void store_booke_tsr (CPUPPCState *env, target_ulong val);
0a032cbe 778void ppc_tlb_invalidate_all (CPUPPCState *env);
daf4f96e
JM		 779void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
780#if defined(TARGET_PPC64)
781void ppc_slb_invalidate_all (CPUPPCState *env);
782void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
783#endif
36081602 784int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
d9bce9d9 785#endif
9fddaa0c 786#endif
79aceca5 787
2e719ba3
JM		 788/* Device control registers */
789int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
790int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
791
9467d44c
TS		 792#define CPUState CPUPPCState
793#define cpu_init cpu_ppc_init
794#define cpu_exec cpu_ppc_exec
795#define cpu_gen_code cpu_ppc_gen_code
796#define cpu_signal_handler cpu_ppc_signal_handler
c732abe2 797#define cpu_list ppc_cpu_list
9467d44c 798
6ebbf390
JM		 799/* MMU modes definitions */
800#define MMU_MODE0_SUFFIX _user
801#define MMU_MODE1_SUFFIX _kernel
6ebbf390 802#define MMU_MODE2_SUFFIX _hypv
6ebbf390
JM		 803#define MMU_USER_IDX 0
804static inline int cpu_mmu_index (CPUState *env)
805{
806 return env->mmu_idx;
807}
808
79aceca5
FB		 809#include "cpu-all.h"
810
3fc6c082
FB		 811/*****************************************************************************/
812/* Registers definitions */
79aceca5
FB		 813#define XER_SO 31
814#define XER_OV 30
815#define XER_CA 29
3fc6c082 816#define XER_CMP 8
36081602 817#define XER_BC 0
3fc6c082
FB		 818#define xer_so env->xer[4]
819#define xer_ov env->xer[6]
820#define xer_ca env->xer[2]
821#define xer_cmp env->xer[1]
36081602 822#define xer_bc env->xer[0]
79aceca5 823
3fc6c082 824/* SPR definitions */
76a66253
JM		 825#define SPR_MQ (0x000)
826#define SPR_XER (0x001)
827#define SPR_601_VRTCU (0x004)
828#define SPR_601_VRTCL (0x005)
829#define SPR_601_UDECR (0x006)
830#define SPR_LR (0x008)
831#define SPR_CTR (0x009)
832#define SPR_DSISR (0x012)
a750fc0b 833#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
76a66253
JM		 834#define SPR_601_RTCU (0x014)
835#define SPR_601_RTCL (0x015)
836#define SPR_DECR (0x016)
837#define SPR_SDR1 (0x019)
838#define SPR_SRR0 (0x01A)
839#define SPR_SRR1 (0x01B)
2662a059 840#define SPR_AMR (0x01D)
76a66253
JM		 841#define SPR_BOOKE_PID (0x030)
842#define SPR_BOOKE_DECAR (0x036)
363be49c
JM		 843#define SPR_BOOKE_CSRR0 (0x03A)
844#define SPR_BOOKE_CSRR1 (0x03B)
76a66253
JM		 845#define SPR_BOOKE_DEAR (0x03D)
846#define SPR_BOOKE_ESR (0x03E)
363be49c 847#define SPR_BOOKE_IVPR (0x03F)
76a66253
JM		 848#define SPR_8xx_EIE (0x050)
849#define SPR_8xx_EID (0x051)
850#define SPR_8xx_NRE (0x052)
2662a059 851#define SPR_CTRL (0x088)
76a66253
JM		 852#define SPR_58x_CMPA (0x090)
853#define SPR_58x_CMPB (0x091)
854#define SPR_58x_CMPC (0x092)
855#define SPR_58x_CMPD (0x093)
856#define SPR_58x_ICR (0x094)
857#define SPR_58x_DER (0x094)
858#define SPR_58x_COUNTA (0x096)
859#define SPR_58x_COUNTB (0x097)
2662a059 860#define SPR_UCTRL (0x098)
76a66253
JM		 861#define SPR_58x_CMPE (0x098)
862#define SPR_58x_CMPF (0x099)
863#define SPR_58x_CMPG (0x09A)
864#define SPR_58x_CMPH (0x09B)
865#define SPR_58x_LCTRL1 (0x09C)
866#define SPR_58x_LCTRL2 (0x09D)
867#define SPR_58x_ICTRL (0x09E)
868#define SPR_58x_BAR (0x09F)
869#define SPR_VRSAVE (0x100)
870#define SPR_USPRG0 (0x100)
363be49c
JM		 871#define SPR_USPRG1 (0x101)
872#define SPR_USPRG2 (0x102)
873#define SPR_USPRG3 (0x103)
76a66253
JM		 874#define SPR_USPRG4 (0x104)
875#define SPR_USPRG5 (0x105)
876#define SPR_USPRG6 (0x106)
877#define SPR_USPRG7 (0x107)
878#define SPR_VTBL (0x10C)
879#define SPR_VTBU (0x10D)
880#define SPR_SPRG0 (0x110)
881#define SPR_SPRG1 (0x111)
882#define SPR_SPRG2 (0x112)
883#define SPR_SPRG3 (0x113)
884#define SPR_SPRG4 (0x114)
885#define SPR_SCOMC (0x114)
886#define SPR_SPRG5 (0x115)
887#define SPR_SCOMD (0x115)
888#define SPR_SPRG6 (0x116)
889#define SPR_SPRG7 (0x117)
890#define SPR_ASR (0x118)
891#define SPR_EAR (0x11A)
892#define SPR_TBL (0x11C)
893#define SPR_TBU (0x11D)
2662a059 894#define SPR_TBU40 (0x11E)
76a66253
JM		 895#define SPR_SVR (0x11E)
896#define SPR_BOOKE_PIR (0x11E)
897#define SPR_PVR (0x11F)
898#define SPR_HSPRG0 (0x130)
899#define SPR_BOOKE_DBSR (0x130)
900#define SPR_HSPRG1 (0x131)
2662a059
JM		 901#define SPR_HDSISR (0x132)
902#define SPR_HDAR (0x133)
76a66253
JM		 903#define SPR_BOOKE_DBCR0 (0x134)
904#define SPR_IBCR (0x135)
2662a059 905#define SPR_PURR (0x135)
76a66253
JM		 906#define SPR_BOOKE_DBCR1 (0x135)
907#define SPR_DBCR (0x136)
908#define SPR_HDEC (0x136)
909#define SPR_BOOKE_DBCR2 (0x136)
910#define SPR_HIOR (0x137)
911#define SPR_MBAR (0x137)
912#define SPR_RMOR (0x138)
913#define SPR_BOOKE_IAC1 (0x138)
914#define SPR_HRMOR (0x139)
915#define SPR_BOOKE_IAC2 (0x139)
e1833e1f 916#define SPR_HSRR0 (0x13A)
76a66253 917#define SPR_BOOKE_IAC3 (0x13A)
e1833e1f 918#define SPR_HSRR1 (0x13B)
76a66253
JM		 919#define SPR_BOOKE_IAC4 (0x13B)
920#define SPR_LPCR (0x13C)
921#define SPR_BOOKE_DAC1 (0x13C)
922#define SPR_LPIDR (0x13D)
923#define SPR_DABR2 (0x13D)
924#define SPR_BOOKE_DAC2 (0x13D)
925#define SPR_BOOKE_DVC1 (0x13E)
926#define SPR_BOOKE_DVC2 (0x13F)
927#define SPR_BOOKE_TSR (0x150)
928#define SPR_BOOKE_TCR (0x154)
929#define SPR_BOOKE_IVOR0 (0x190)
930#define SPR_BOOKE_IVOR1 (0x191)
931#define SPR_BOOKE_IVOR2 (0x192)
932#define SPR_BOOKE_IVOR3 (0x193)
933#define SPR_BOOKE_IVOR4 (0x194)
934#define SPR_BOOKE_IVOR5 (0x195)
935#define SPR_BOOKE_IVOR6 (0x196)
936#define SPR_BOOKE_IVOR7 (0x197)
937#define SPR_BOOKE_IVOR8 (0x198)
938#define SPR_BOOKE_IVOR9 (0x199)
939#define SPR_BOOKE_IVOR10 (0x19A)
940#define SPR_BOOKE_IVOR11 (0x19B)
941#define SPR_BOOKE_IVOR12 (0x19C)
942#define SPR_BOOKE_IVOR13 (0x19D)
943#define SPR_BOOKE_IVOR14 (0x19E)
944#define SPR_BOOKE_IVOR15 (0x19F)
2662a059 945#define SPR_BOOKE_SPEFSCR (0x200)
76a66253
JM		 946#define SPR_E500_BBEAR (0x201)
947#define SPR_E500_BBTAR (0x202)
a062e36c
JM		 948#define SPR_ATBL (0x20E)
949#define SPR_ATBU (0x20F)
76a66253 950#define SPR_IBAT0U (0x210)
363be49c 951#define SPR_BOOKE_IVOR32 (0x210)
76a66253 952#define SPR_IBAT0L (0x211)
363be49c 953#define SPR_BOOKE_IVOR33 (0x211)
76a66253 954#define SPR_IBAT1U (0x212)
363be49c 955#define SPR_BOOKE_IVOR34 (0x212)
76a66253 956#define SPR_IBAT1L (0x213)
363be49c 957#define SPR_BOOKE_IVOR35 (0x213)
76a66253 958#define SPR_IBAT2U (0x214)
363be49c 959#define SPR_BOOKE_IVOR36 (0x214)
76a66253
JM		 960#define SPR_IBAT2L (0x215)
961#define SPR_E500_L1CFG0 (0x215)
363be49c 962#define SPR_BOOKE_IVOR37 (0x215)
76a66253
JM		 963#define SPR_IBAT3U (0x216)
964#define SPR_E500_L1CFG1 (0x216)
965#define SPR_IBAT3L (0x217)
966#define SPR_DBAT0U (0x218)
967#define SPR_DBAT0L (0x219)
968#define SPR_DBAT1U (0x21A)
969#define SPR_DBAT1L (0x21B)
970#define SPR_DBAT2U (0x21C)
971#define SPR_DBAT2L (0x21D)
972#define SPR_DBAT3U (0x21E)
973#define SPR_DBAT3L (0x21F)
974#define SPR_IBAT4U (0x230)
975#define SPR_IBAT4L (0x231)
976#define SPR_IBAT5U (0x232)
977#define SPR_IBAT5L (0x233)
978#define SPR_IBAT6U (0x234)
979#define SPR_IBAT6L (0x235)
980#define SPR_IBAT7U (0x236)
981#define SPR_IBAT7L (0x237)
982#define SPR_DBAT4U (0x238)
983#define SPR_DBAT4L (0x239)
984#define SPR_DBAT5U (0x23A)
363be49c 985#define SPR_BOOKE_MCSRR0 (0x23A)
76a66253 986#define SPR_DBAT5L (0x23B)
363be49c 987#define SPR_BOOKE_MCSRR1 (0x23B)
76a66253 988#define SPR_DBAT6U (0x23C)
363be49c 989#define SPR_BOOKE_MCSR (0x23C)
76a66253
JM		 990#define SPR_DBAT6L (0x23D)
991#define SPR_E500_MCAR (0x23D)
992#define SPR_DBAT7U (0x23E)
363be49c 993#define SPR_BOOKE_DSRR0 (0x23E)
76a66253 994#define SPR_DBAT7L (0x23F)
363be49c
JM		 995#define SPR_BOOKE_DSRR1 (0x23F)
996#define SPR_BOOKE_SPRG8 (0x25C)
997#define SPR_BOOKE_SPRG9 (0x25D)
998#define SPR_BOOKE_MAS0 (0x270)
999#define SPR_BOOKE_MAS1 (0x271)
1000#define SPR_BOOKE_MAS2 (0x272)
1001#define SPR_BOOKE_MAS3 (0x273)
1002#define SPR_BOOKE_MAS4 (0x274)
1003#define SPR_BOOKE_MAS6 (0x276)
1004#define SPR_BOOKE_PID1 (0x279)
1005#define SPR_BOOKE_PID2 (0x27A)
1006#define SPR_BOOKE_TLB0CFG (0x2B0)
1007#define SPR_BOOKE_TLB1CFG (0x2B1)
1008#define SPR_BOOKE_TLB2CFG (0x2B2)
1009#define SPR_BOOKE_TLB3CFG (0x2B3)
1010#define SPR_BOOKE_EPR (0x2BE)
2662a059
JM		 1011#define SPR_PERF0 (0x300)
1012#define SPR_PERF1 (0x301)
1013#define SPR_PERF2 (0x302)
1014#define SPR_PERF3 (0x303)
1015#define SPR_PERF4 (0x304)
1016#define SPR_PERF5 (0x305)
1017#define SPR_PERF6 (0x306)
1018#define SPR_PERF7 (0x307)
1019#define SPR_PERF8 (0x308)
1020#define SPR_PERF9 (0x309)
1021#define SPR_PERFA (0x30A)
1022#define SPR_PERFB (0x30B)
1023#define SPR_PERFC (0x30C)
1024#define SPR_PERFD (0x30D)
1025#define SPR_PERFE (0x30E)
1026#define SPR_PERFF (0x30F)
1027#define SPR_UPERF0 (0x310)
1028#define SPR_UPERF1 (0x311)
1029#define SPR_UPERF2 (0x312)
1030#define SPR_UPERF3 (0x313)
1031#define SPR_UPERF4 (0x314)
1032#define SPR_UPERF5 (0x315)
1033#define SPR_UPERF6 (0x316)
1034#define SPR_UPERF7 (0x317)
1035#define SPR_UPERF8 (0x318)
1036#define SPR_UPERF9 (0x319)
1037#define SPR_UPERFA (0x31A)
1038#define SPR_UPERFB (0x31B)
1039#define SPR_UPERFC (0x31C)
1040#define SPR_UPERFD (0x31D)
1041#define SPR_UPERFE (0x31E)
1042#define SPR_UPERFF (0x31F)
76a66253
JM		 1043#define SPR_440_INV0 (0x370)
1044#define SPR_440_INV1 (0x371)
1045#define SPR_440_INV2 (0x372)
1046#define SPR_440_INV3 (0x373)
2662a059
JM		 1047#define SPR_440_ITV0 (0x374)
1048#define SPR_440_ITV1 (0x375)
1049#define SPR_440_ITV2 (0x376)
1050#define SPR_440_ITV3 (0x377)
a750fc0b
JM		 1051#define SPR_440_CCR1 (0x378)
1052#define SPR_DCRIPR (0x37B)
2662a059 1053#define SPR_PPR (0x380)
76a66253
JM		 1054#define SPR_440_DNV0 (0x390)
1055#define SPR_440_DNV1 (0x391)
1056#define SPR_440_DNV2 (0x392)
1057#define SPR_440_DNV3 (0x393)
2662a059
JM		 1058#define SPR_440_DTV0 (0x394)
1059#define SPR_440_DTV1 (0x395)
1060#define SPR_440_DTV2 (0x396)
1061#define SPR_440_DTV3 (0x397)
76a66253
JM		 1062#define SPR_440_DVLIM (0x398)
1063#define SPR_440_IVLIM (0x399)
1064#define SPR_440_RSTCFG (0x39B)
2662a059
JM		 1065#define SPR_BOOKE_DCDBTRL (0x39C)
1066#define SPR_BOOKE_DCDBTRH (0x39D)
1067#define SPR_BOOKE_ICDBTRL (0x39E)
1068#define SPR_BOOKE_ICDBTRH (0x39F)
a750fc0b
JM		 1069#define SPR_UMMCR2 (0x3A0)
1070#define SPR_UPMC5 (0x3A1)
1071#define SPR_UPMC6 (0x3A2)
1072#define SPR_UBAMR (0x3A7)
76a66253
JM		 1073#define SPR_UMMCR0 (0x3A8)
1074#define SPR_UPMC1 (0x3A9)
1075#define SPR_UPMC2 (0x3AA)
a750fc0b 1076#define SPR_USIAR (0x3AB)
76a66253
JM		 1077#define SPR_UMMCR1 (0x3AC)
1078#define SPR_UPMC3 (0x3AD)
1079#define SPR_UPMC4 (0x3AE)
1080#define SPR_USDA (0x3AF)
1081#define SPR_40x_ZPR (0x3B0)
363be49c 1082#define SPR_BOOKE_MAS7 (0x3B0)
a750fc0b
JM		 1083#define SPR_620_PMR0 (0x3B0)
1084#define SPR_MMCR2 (0x3B0)
1085#define SPR_PMC5 (0x3B1)
76a66253 1086#define SPR_40x_PID (0x3B1)
a750fc0b
JM		 1087#define SPR_620_PMR1 (0x3B1)
1088#define SPR_PMC6 (0x3B2)
76a66253 1089#define SPR_440_MMUCR (0x3B2)
a750fc0b 1090#define SPR_620_PMR2 (0x3B2)
76a66253 1091#define SPR_4xx_CCR0 (0x3B3)
363be49c 1092#define SPR_BOOKE_EPLC (0x3B3)
a750fc0b 1093#define SPR_620_PMR3 (0x3B3)
76a66253 1094#define SPR_405_IAC3 (0x3B4)
363be49c 1095#define SPR_BOOKE_EPSC (0x3B4)
a750fc0b 1096#define SPR_620_PMR4 (0x3B4)
76a66253 1097#define SPR_405_IAC4 (0x3B5)
a750fc0b 1098#define SPR_620_PMR5 (0x3B5)
76a66253 1099#define SPR_405_DVC1 (0x3B6)
a750fc0b 1100#define SPR_620_PMR6 (0x3B6)
76a66253 1101#define SPR_405_DVC2 (0x3B7)
a750fc0b
JM		 1102#define SPR_620_PMR7 (0x3B7)
1103#define SPR_BAMR (0x3B7)
76a66253 1104#define SPR_MMCR0 (0x3B8)
a750fc0b 1105#define SPR_620_PMR8 (0x3B8)
76a66253
JM		 1106#define SPR_PMC1 (0x3B9)
1107#define SPR_40x_SGR (0x3B9)
a750fc0b 1108#define SPR_620_PMR9 (0x3B9)
76a66253
JM		 1109#define SPR_PMC2 (0x3BA)
1110#define SPR_40x_DCWR (0x3BA)
a750fc0b
JM		 1111#define SPR_620_PMRA (0x3BA)
1112#define SPR_SIAR (0x3BB)
76a66253 1113#define SPR_405_SLER (0x3BB)
a750fc0b 1114#define SPR_620_PMRB (0x3BB)
76a66253
JM		 1115#define SPR_MMCR1 (0x3BC)
1116#define SPR_405_SU0R (0x3BC)
a750fc0b
JM		 1117#define SPR_620_PMRC (0x3BC)
1118#define SPR_401_SKR (0x3BC)
76a66253
JM		 1119#define SPR_PMC3 (0x3BD)
1120#define SPR_405_DBCR1 (0x3BD)
a750fc0b 1121#define SPR_620_PMRD (0x3BD)
76a66253 1122#define SPR_PMC4 (0x3BE)
a750fc0b 1123#define SPR_620_PMRE (0x3BE)
76a66253 1124#define SPR_SDA (0x3BF)
a750fc0b 1125#define SPR_620_PMRF (0x3BF)
76a66253
JM		 1126#define SPR_403_VTBL (0x3CC)
1127#define SPR_403_VTBU (0x3CD)
1128#define SPR_DMISS (0x3D0)
1129#define SPR_DCMP (0x3D1)
1130#define SPR_HASH1 (0x3D2)
1131#define SPR_HASH2 (0x3D3)
2662a059 1132#define SPR_BOOKE_ICDBDR (0x3D3)
a750fc0b 1133#define SPR_TLBMISS (0x3D4)
76a66253
JM		 1134#define SPR_IMISS (0x3D4)
1135#define SPR_40x_ESR (0x3D4)
a750fc0b 1136#define SPR_PTEHI (0x3D5)
76a66253
JM		 1137#define SPR_ICMP (0x3D5)
1138#define SPR_40x_DEAR (0x3D5)
a750fc0b 1139#define SPR_PTELO (0x3D6)
76a66253
JM		 1140#define SPR_RPA (0x3D6)
1141#define SPR_40x_EVPR (0x3D6)
a750fc0b 1142#define SPR_L3PM (0x3D7)
76a66253 1143#define SPR_403_CDBCR (0x3D7)
a750fc0b 1144#define SPR_L3OHCR (0x3D8)
76a66253
JM		 1145#define SPR_TCR (0x3D8)
1146#define SPR_40x_TSR (0x3D8)
1147#define SPR_IBR (0x3DA)
1148#define SPR_40x_TCR (0x3DA)
a750fc0b 1149#define SPR_ESASRR (0x3DB)
76a66253
JM		 1150#define SPR_40x_PIT (0x3DB)
1151#define SPR_403_TBL (0x3DC)
1152#define SPR_403_TBU (0x3DD)
1153#define SPR_SEBR (0x3DE)
1154#define SPR_40x_SRR2 (0x3DE)
1155#define SPR_SER (0x3DF)
1156#define SPR_40x_SRR3 (0x3DF)
a750fc0b
JM		 1157#define SPR_L3ITCR0 (0x3E8)
1158#define SPR_L3ITCR1 (0x3E9)
1159#define SPR_L3ITCR2 (0x3EA)
1160#define SPR_L3ITCR3 (0x3EB)
76a66253
JM		 1161#define SPR_HID0 (0x3F0)
1162#define SPR_40x_DBSR (0x3F0)
1163#define SPR_HID1 (0x3F1)
1164#define SPR_IABR (0x3F2)
1165#define SPR_40x_DBCR0 (0x3F2)
1166#define SPR_601_HID2 (0x3F2)
1167#define SPR_E500_L1CSR0 (0x3F2)
a750fc0b 1168#define SPR_ICTRL (0x3F3)
76a66253
JM		 1169#define SPR_HID2 (0x3F3)
1170#define SPR_E500_L1CSR1 (0x3F3)
1171#define SPR_440_DBDR (0x3F3)
a750fc0b 1172#define SPR_LDSTDB (0x3F4)
76a66253 1173#define SPR_40x_IAC1 (0x3F4)
65f9ee8d 1174#define SPR_MMUCSR0 (0x3F4)
76a66253 1175#define SPR_DABR (0x3F5)
3fc6c082 1176#define DABR_MASK (~(target_ulong)0x7)
76a66253
JM		 1177#define SPR_E500_BUCSR (0x3F5)
1178#define SPR_40x_IAC2 (0x3F5)
1179#define SPR_601_HID5 (0x3F5)
1180#define SPR_40x_DAC1 (0x3F6)
a750fc0b 1181#define SPR_MSSCR0 (0x3F6)
d63001d1 1182#define SPR_970_HID5 (0x3F6)
a750fc0b 1183#define SPR_MSSSR0 (0x3F7)
2662a059 1184#define SPR_DABRX (0x3F7)
76a66253 1185#define SPR_40x_DAC2 (0x3F7)
65f9ee8d 1186#define SPR_MMUCFG (0x3F7)
a750fc0b
JM		 1187#define SPR_LDSTCR (0x3F8)
1188#define SPR_L2PMCR (0x3F8)
76a66253 1189#define SPR_750_HID2 (0x3F8)
a750fc0b 1190#define SPR_620_HID8 (0x3F8)
76a66253 1191#define SPR_L2CR (0x3F9)
a750fc0b
JM		 1192#define SPR_620_HID9 (0x3F9)
1193#define SPR_L3CR (0x3FA)
76a66253
JM		 1194#define SPR_IABR2 (0x3FA)
1195#define SPR_40x_DCCR (0x3FA)
1196#define SPR_ICTC (0x3FB)
1197#define SPR_40x_ICCR (0x3FB)
1198#define SPR_THRM1 (0x3FC)
1199#define SPR_403_PBL1 (0x3FC)
1200#define SPR_SP (0x3FD)
1201#define SPR_THRM2 (0x3FD)
1202#define SPR_403_PBU1 (0x3FD)
a750fc0b 1203#define SPR_604_HID13 (0x3FD)
76a66253
JM		 1204#define SPR_LT (0x3FE)
1205#define SPR_THRM3 (0x3FE)
1206#define SPR_FPECR (0x3FE)
1207#define SPR_403_PBL2 (0x3FE)
1208#define SPR_PIR (0x3FF)
1209#define SPR_403_PBU2 (0x3FF)
1210#define SPR_601_HID15 (0x3FF)
a750fc0b 1211#define SPR_604_HID15 (0x3FF)
76a66253 1212#define SPR_E500_SVR (0x3FF)
79aceca5 1213
76a66253 1214/*****************************************************************************/
9a64fbe4
FB		 1215/* Memory access type :
1216 * may be needed for precise access rights control and precise exceptions.
1217 */
79aceca5 1218enum {
9a64fbe4
FB		 1219 /* 1 bit to define user level / supervisor access */
1220 ACCESS_USER = 0x00,
1221 ACCESS_SUPER = 0x01,
1222 /* Type of instruction that generated the access */
1223 ACCESS_CODE = 0x10, /* Code fetch access */
1224 ACCESS_INT = 0x20, /* Integer load/store access */
1225 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1226 ACCESS_RES = 0x40, /* load/store with reservation */
1227 ACCESS_EXT = 0x50, /* external access */
1228 ACCESS_CACHE = 0x60, /* Cache manipulation */
1229};
1230
47103572
JM		 1231/* Hardware interruption sources:
1232 * all those exception can be raised simulteaneously
1233 */
e9df014c
JM		 1234/* Input pins definitions */
1235enum {
1236 /* 6xx bus input pins */
24be5ae3
JM		 1237 PPC6xx_INPUT_HRESET = 0,
1238 PPC6xx_INPUT_SRESET = 1,
1239 PPC6xx_INPUT_CKSTP_IN = 2,
1240 PPC6xx_INPUT_MCP = 3,
1241 PPC6xx_INPUT_SMI = 4,
1242 PPC6xx_INPUT_INT = 5,
d68f1306
JM		 1243 PPC6xx_INPUT_TBEN = 6,
1244 PPC6xx_INPUT_WAKEUP = 7,
1245 PPC6xx_INPUT_NB,
24be5ae3
JM		 1246};
1247
1248enum {
e9df014c 1249 /* Embedded PowerPC input pins */
24be5ae3
JM		 1250 PPCBookE_INPUT_HRESET = 0,
1251 PPCBookE_INPUT_SRESET = 1,
1252 PPCBookE_INPUT_CKSTP_IN = 2,
1253 PPCBookE_INPUT_MCP = 3,
1254 PPCBookE_INPUT_SMI = 4,
1255 PPCBookE_INPUT_INT = 5,
1256 PPCBookE_INPUT_CINT = 6,
d68f1306 1257 PPCBookE_INPUT_NB,
24be5ae3
JM		 1258};
1259
a750fc0b 1260enum {
4e290a0b
JM		 1261 /* PowerPC 40x input pins */
1262 PPC40x_INPUT_RESET_CORE = 0,
1263 PPC40x_INPUT_RESET_CHIP = 1,
1264 PPC40x_INPUT_RESET_SYS = 2,
1265 PPC40x_INPUT_CINT = 3,
1266 PPC40x_INPUT_INT = 4,
1267 PPC40x_INPUT_HALT = 5,
1268 PPC40x_INPUT_DEBUG = 6,
1269 PPC40x_INPUT_NB,
e9df014c
JM		 1270};
1271
b4095fed
JM		 1272enum {
1273 /* RCPU input pins */
1274 PPCRCPU_INPUT_PORESET = 0,
1275 PPCRCPU_INPUT_HRESET = 1,
1276 PPCRCPU_INPUT_SRESET = 2,
1277 PPCRCPU_INPUT_IRQ0 = 3,
1278 PPCRCPU_INPUT_IRQ1 = 4,
1279 PPCRCPU_INPUT_IRQ2 = 5,
1280 PPCRCPU_INPUT_IRQ3 = 6,
1281 PPCRCPU_INPUT_IRQ4 = 7,
1282 PPCRCPU_INPUT_IRQ5 = 8,
1283 PPCRCPU_INPUT_IRQ6 = 9,
1284 PPCRCPU_INPUT_IRQ7 = 10,
1285 PPCRCPU_INPUT_NB,
1286};
1287
00af685f 1288#if defined(TARGET_PPC64)
d0dfae6e
JM		 1289enum {
1290 /* PowerPC 970 input pins */
1291 PPC970_INPUT_HRESET = 0,
1292 PPC970_INPUT_SRESET = 1,
1293 PPC970_INPUT_CKSTP = 2,
1294 PPC970_INPUT_TBEN = 3,
1295 PPC970_INPUT_MCP = 4,
1296 PPC970_INPUT_INT = 5,
1297 PPC970_INPUT_THINT = 6,
7b62a955 1298 PPC970_INPUT_NB,
d0dfae6e 1299};
00af685f 1300#endif
d0dfae6e 1301
e9df014c 1302/* Hardware exceptions definitions */
47103572 1303enum {
e9df014c 1304 /* External hardware exception sources */
e1833e1f 1305 PPC_INTERRUPT_RESET = 0, /* Reset exception */
d68f1306
JM		 1306 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
1307 PPC_INTERRUPT_MCK, /* Machine check exception */
1308 PPC_INTERRUPT_EXT, /* External interrupt */
1309 PPC_INTERRUPT_SMI, /* System management interrupt */
1310 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
1311 PPC_INTERRUPT_DEBUG, /* External debug exception */
1312 PPC_INTERRUPT_THERM, /* Thermal exception */
e9df014c 1313 /* Internal hardware exception sources */
d68f1306
JM		 1314 PPC_INTERRUPT_DECR, /* Decrementer exception */
1315 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
1316 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
1317 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
1318 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
1319 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
1320 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
1321 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
47103572
JM		 1322};
1323
9a64fbe4
FB		 1324/*****************************************************************************/
1325
79aceca5 1326#endif /* !defined (__CPU_PPC_H__) */
Qemu copy for testing