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mmu-hash*: Merge translate and fault handling functions
[qemu.git] / target-ppc / cpu.h
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation cpu definitions for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
79aceca5
FB		 18 */
19#if !defined (__CPU_PPC_H__)
20#define __CPU_PPC_H__
21
3fc6c082 22#include "config.h"
9a78eead 23#include "qemu-common.h"
3fc6c082 24
a4f30719
JM		 25//#define PPC_EMULATE_32BITS_HYPV
26
76a66253 27#if defined (TARGET_PPC64)
3cd7d1dd 28/* PowerPC 64 definitions */
d9d7210c 29#define TARGET_LONG_BITS 64
35cdaad6 30#define TARGET_PAGE_BITS 12
3cd7d1dd 31
52705890
RH		 32/* Note that the official physical address space bits is 62-M where M
33 is implementation dependent. I've not looked up M for the set of
34 cpus we emulate at the system level. */
35#define TARGET_PHYS_ADDR_SPACE_BITS 62
36
37/* Note that the PPC environment architecture talks about 80 bit virtual
38 addresses, with segmentation. Obviously that's not all visible to a
39 single process, which is all we're concerned with here. */
40#ifdef TARGET_ABI32
41# define TARGET_VIRT_ADDR_SPACE_BITS 32
42#else
43# define TARGET_VIRT_ADDR_SPACE_BITS 64
44#endif
45
81762d6d
DG		 46#define TARGET_PAGE_BITS_16M 24
47
3cd7d1dd
JM		 48#else /* defined (TARGET_PPC64) */
49/* PowerPC 32 definitions */
d9d7210c 50#define TARGET_LONG_BITS 32
3cd7d1dd
JM		 51
52#if defined(TARGET_PPCEMB)
53/* Specific definitions for PowerPC embedded */
54/* BookE have 36 bits physical address space */
3cd7d1dd
JM		 55#if defined(CONFIG_USER_ONLY)
56/* It looks like a lot of Linux programs assume page size
57 * is 4kB long. This is evil, but we have to deal with it...
58 */
35cdaad6 59#define TARGET_PAGE_BITS 12
3cd7d1dd
JM		 60#else /* defined(CONFIG_USER_ONLY) */
61/* Pages can be 1 kB small */
62#define TARGET_PAGE_BITS 10
63#endif /* defined(CONFIG_USER_ONLY) */
64#else /* defined(TARGET_PPCEMB) */
65/* "standard" PowerPC 32 definitions */
66#define TARGET_PAGE_BITS 12
67#endif /* defined(TARGET_PPCEMB) */
68
8b242eba 69#define TARGET_PHYS_ADDR_SPACE_BITS 36
52705890
RH		 70#define TARGET_VIRT_ADDR_SPACE_BITS 32
71
3cd7d1dd 72#endif /* defined (TARGET_PPC64) */
3cf1e035 73
9349b4f9 74#define CPUArchState struct CPUPPCState
c2764719 75
022c62cb 76#include "exec/cpu-defs.h"
79aceca5 77
6b4c305c 78#include "fpu/softfloat.h"
4ecc3190 79
1fddef4b
FB		 80#define TARGET_HAS_ICE 1
81
7f70c937 82#if defined (TARGET_PPC64)
76a66253
JM		 83#define ELF_MACHINE EM_PPC64
84#else
85#define ELF_MACHINE EM_PPC
86#endif
9042c0e2 87
3fc6c082 88/*****************************************************************************/
a750fc0b 89/* MMU model */
c227f099
AL		 90typedef enum powerpc_mmu_t powerpc_mmu_t;
91enum powerpc_mmu_t {
add78955 92 POWERPC_MMU_UNKNOWN = 0x00000000,
a750fc0b 93 /* Standard 32 bits PowerPC MMU */
add78955 94 POWERPC_MMU_32B = 0x00000001,
a750fc0b 95 /* PowerPC 6xx MMU with software TLB */
add78955 96 POWERPC_MMU_SOFT_6xx = 0x00000002,
a750fc0b 97 /* PowerPC 74xx MMU with software TLB */
add78955 98 POWERPC_MMU_SOFT_74xx = 0x00000003,
a750fc0b 99 /* PowerPC 4xx MMU with software TLB */
add78955 100 POWERPC_MMU_SOFT_4xx = 0x00000004,
a750fc0b 101 /* PowerPC 4xx MMU with software TLB and zones protections */
add78955 102 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
b4095fed 103 /* PowerPC MMU in real mode only */
add78955 104 POWERPC_MMU_REAL = 0x00000006,
b4095fed 105 /* Freescale MPC8xx MMU model */
add78955 106 POWERPC_MMU_MPC8xx = 0x00000007,
a750fc0b 107 /* BookE MMU model */
add78955 108 POWERPC_MMU_BOOKE = 0x00000008,
01662f3e
AG		 109 /* BookE 2.06 MMU model */
110 POWERPC_MMU_BOOKE206 = 0x00000009,
faadf50e 111 /* PowerPC 601 MMU model (specific BATs format) */
add78955 112 POWERPC_MMU_601 = 0x0000000A,
00af685f 113#if defined(TARGET_PPC64)
add78955 114#define POWERPC_MMU_64 0x00010000
cdaee006 115#define POWERPC_MMU_1TSEG 0x00020000
12de9a39 116 /* 64 bits PowerPC MMU */
add78955 117 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
9d52e907
DG		 118 /* Architecture 2.06 variant */
119 POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | 0x00000003,
4656e1f0
BH		 120 /* Architecture 2.06 "degraded" (no 1T segments) */
121 POWERPC_MMU_2_06d = POWERPC_MMU_64 | 0x00000003,
00af685f 122#endif /* defined(TARGET_PPC64) */
3fc6c082
FB		 123};
124
125/*****************************************************************************/
a750fc0b 126/* Exception model */
c227f099
AL		 127typedef enum powerpc_excp_t powerpc_excp_t;
128enum powerpc_excp_t {
a750fc0b 129 POWERPC_EXCP_UNKNOWN = 0,
3fc6c082 130 /* Standard PowerPC exception model */
a750fc0b 131 POWERPC_EXCP_STD,
2662a059 132 /* PowerPC 40x exception model */
a750fc0b 133 POWERPC_EXCP_40x,
2662a059 134 /* PowerPC 601 exception model */
a750fc0b 135 POWERPC_EXCP_601,
2662a059 136 /* PowerPC 602 exception model */
a750fc0b 137 POWERPC_EXCP_602,
2662a059 138 /* PowerPC 603 exception model */
a750fc0b
JM		 139 POWERPC_EXCP_603,
140 /* PowerPC 603e exception model */
141 POWERPC_EXCP_603E,
142 /* PowerPC G2 exception model */
143 POWERPC_EXCP_G2,
2662a059 144 /* PowerPC 604 exception model */
a750fc0b 145 POWERPC_EXCP_604,
2662a059 146 /* PowerPC 7x0 exception model */
a750fc0b 147 POWERPC_EXCP_7x0,
2662a059 148 /* PowerPC 7x5 exception model */
a750fc0b 149 POWERPC_EXCP_7x5,
2662a059 150 /* PowerPC 74xx exception model */
a750fc0b 151 POWERPC_EXCP_74xx,
2662a059 152 /* BookE exception model */
a750fc0b 153 POWERPC_EXCP_BOOKE,
00af685f
JM		 154#if defined(TARGET_PPC64)
155 /* PowerPC 970 exception model */
156 POWERPC_EXCP_970,
9d52e907
DG		 157 /* POWER7 exception model */
158 POWERPC_EXCP_POWER7,
00af685f 159#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 160};
161
e1833e1f
JM		 162/*****************************************************************************/
163/* Exception vectors definitions */
164enum {
165 POWERPC_EXCP_NONE = -1,
166 /* The 64 first entries are used by the PowerPC embedded specification */
167 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
168 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
169 POWERPC_EXCP_DSI = 2, /* Data storage exception */
170 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
171 POWERPC_EXCP_EXTERNAL = 4, /* External input */
172 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
173 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
174 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
175 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
176 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
177 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
178 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
179 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
b4095fed
JM		 180 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
181 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
e1833e1f
JM		 182 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
183 /* Vectors 16 to 31 are reserved */
e1833e1f
JM		 184 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
185 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
186 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
187 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
188 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
189 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
0ef654e3
AG		 190 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
191 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
192 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
193 /* Vectors 42 to 63 are reserved */
e1833e1f
JM		 194 /* Exceptions defined in the PowerPC server specification */
195 POWERPC_EXCP_RESET = 64, /* System reset exception */
e1833e1f
JM		 196 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
197 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
e1833e1f 198 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
e1833e1f 199 POWERPC_EXCP_TRACE = 68, /* Trace exception */
e1833e1f
JM		 200 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
201 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
202 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
203 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
e1833e1f
JM		 204 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
205 /* 40x specific exceptions */
206 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
207 /* 601 specific exceptions */
208 POWERPC_EXCP_IO = 75, /* IO error exception */
209 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
210 /* 602 specific exceptions */
211 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
212 /* 602/603 specific exceptions */
b4095fed 213 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
e1833e1f
JM		 214 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
215 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
216 /* Exceptions available on most PowerPC */
217 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
b4095fed
JM		 218 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
219 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
220 POWERPC_EXCP_SMI = 84, /* System management interrupt */
221 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
e1833e1f 222 /* 7xx/74xx specific exceptions */
b4095fed 223 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
e1833e1f 224 /* 74xx specific exceptions */
b4095fed 225 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
e1833e1f 226 /* 970FX specific exceptions */
b4095fed
JM		 227 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
228 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
5b46d07d 229 /* Freescale embedded cores specific exceptions */
b4095fed
JM		 230 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
231 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
232 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
233 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
e1833e1f
JM		 234 /* EOL */
235 POWERPC_EXCP_NB = 96,
5cbdb3a3 236 /* QEMU exceptions: used internally during code translation */
e1833e1f
JM		 237 POWERPC_EXCP_STOP = 0x200, /* stop translation */
238 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
5cbdb3a3 239 /* QEMU exceptions: special cases we want to stop translation */
e1833e1f
JM		 240 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
241 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
4425265b 242 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
e1833e1f
JM		 243};
244
e1833e1f
JM		 245/* Exceptions error codes */
246enum {
247 /* Exception subtypes for POWERPC_EXCP_ALIGN */
248 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
249 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
250 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
251 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
252 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
253 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
254 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
255 /* FP exceptions */
256 POWERPC_EXCP_FP = 0x10,
257 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
258 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
259 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
260 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
7c58044c 261 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
e1833e1f
JM		 262 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
263 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
264 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
265 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
266 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
267 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
268 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
269 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
270 /* Invalid instruction */
271 POWERPC_EXCP_INVAL = 0x20,
272 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
273 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
274 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
275 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
276 /* Privileged instruction */
277 POWERPC_EXCP_PRIV = 0x30,
278 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
279 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
280 /* Trap */
281 POWERPC_EXCP_TRAP = 0x40,
282};
283
a750fc0b
JM		 284/*****************************************************************************/
285/* Input pins model */
c227f099
AL		 286typedef enum powerpc_input_t powerpc_input_t;
287enum powerpc_input_t {
a750fc0b 288 PPC_FLAGS_INPUT_UNKNOWN = 0,
2662a059 289 /* PowerPC 6xx bus */
a750fc0b 290 PPC_FLAGS_INPUT_6xx,
2662a059 291 /* BookE bus */
a750fc0b
JM		 292 PPC_FLAGS_INPUT_BookE,
293 /* PowerPC 405 bus */
294 PPC_FLAGS_INPUT_405,
2662a059 295 /* PowerPC 970 bus */
a750fc0b 296 PPC_FLAGS_INPUT_970,
9d52e907
DG		 297 /* PowerPC POWER7 bus */
298 PPC_FLAGS_INPUT_POWER7,
a750fc0b
JM		 299 /* PowerPC 401 bus */
300 PPC_FLAGS_INPUT_401,
b4095fed
JM		 301 /* Freescale RCPU bus */
302 PPC_FLAGS_INPUT_RCPU,
3fc6c082
FB		 303};
304
a750fc0b 305#define PPC_INPUT(env) (env->bus_model)
3fc6c082 306
be147d08 307/*****************************************************************************/
c227f099 308typedef struct opc_handler_t opc_handler_t;
79aceca5 309
3fc6c082
FB		 310/*****************************************************************************/
311/* Types used to describe some PowerPC registers */
312typedef struct CPUPPCState CPUPPCState;
c227f099
AL		 313typedef struct ppc_tb_t ppc_tb_t;
314typedef struct ppc_spr_t ppc_spr_t;
315typedef struct ppc_dcr_t ppc_dcr_t;
316typedef union ppc_avr_t ppc_avr_t;
317typedef union ppc_tlb_t ppc_tlb_t;
76a66253 318
3fc6c082 319/* SPR access micro-ops generations callbacks */
c227f099 320struct ppc_spr_t {
45d827d2
AJ		 321 void (*uea_read)(void *opaque, int gpr_num, int spr_num);
322 void (*uea_write)(void *opaque, int spr_num, int gpr_num);
76a66253 323#if !defined(CONFIG_USER_ONLY)
45d827d2
AJ		 324 void (*oea_read)(void *opaque, int gpr_num, int spr_num);
325 void (*oea_write)(void *opaque, int spr_num, int gpr_num);
326 void (*hea_read)(void *opaque, int gpr_num, int spr_num);
327 void (*hea_write)(void *opaque, int spr_num, int gpr_num);
76a66253 328#endif
b55266b5 329 const char *name;
d67d40ea
DG		 330#ifdef CONFIG_KVM
331 /* We (ab)use the fact that all the SPRs will have ids for the
332 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
333 * don't sync this */
334 uint64_t one_reg_id;
335#endif
3fc6c082
FB		 336};
337
338/* Altivec registers (128 bits) */
c227f099 339union ppc_avr_t {
0f6fbcbc 340 float32 f[4];
a9d9eb8f
JM		 341 uint8_t u8[16];
342 uint16_t u16[8];
343 uint32_t u32[4];
ab5f265d
AJ		 344 int8_t s8[16];
345 int16_t s16[8];
346 int32_t s32[4];
a9d9eb8f 347 uint64_t u64[2];
3fc6c082 348};
9fddaa0c 349
3c7b48b7 350#if !defined(CONFIG_USER_ONLY)
3fc6c082 351/* Software TLB cache */
c227f099
AL		 352typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
353struct ppc6xx_tlb_t {
76a66253
JM		 354 target_ulong pte0;
355 target_ulong pte1;
356 target_ulong EPN;
1d0a48fb
JM		 357};
358
c227f099
AL		 359typedef struct ppcemb_tlb_t ppcemb_tlb_t;
360struct ppcemb_tlb_t {
b162d02e 361 uint64_t RPN;
1d0a48fb 362 target_ulong EPN;
76a66253 363 target_ulong PID;
c55e9aef
JM		 364 target_ulong size;
365 uint32_t prot;
366 uint32_t attr; /* Storage attributes */
1d0a48fb
JM		 367};
368
d1e256fe
AG		 369typedef struct ppcmas_tlb_t {
370 uint32_t mas8;
371 uint32_t mas1;
372 uint64_t mas2;
373 uint64_t mas7_3;
374} ppcmas_tlb_t;
375
c227f099 376union ppc_tlb_t {
1c53accc
AG		 377 ppc6xx_tlb_t *tlb6;
378 ppcemb_tlb_t *tlbe;
379 ppcmas_tlb_t *tlbm;
3fc6c082 380};
1c53accc
AG		 381
382/* possible TLB variants */
383#define TLB_NONE 0
384#define TLB_6XX 1
385#define TLB_EMB 2
386#define TLB_MAS 3
3c7b48b7 387#endif
3fc6c082 388
bb593904
DG		 389#define SDR_32_HTABORG 0xFFFF0000UL
390#define SDR_32_HTABMASK 0x000001FFUL
391
392#if defined(TARGET_PPC64)
393#define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
394#define SDR_64_HTABSIZE 0x000000000000001FULL
395#endif /* defined(TARGET_PPC64 */
396
c227f099
AL		 397typedef struct ppc_slb_t ppc_slb_t;
398struct ppc_slb_t {
81762d6d
DG		 399 uint64_t esid;
400 uint64_t vsid;
8eee0af9
BS		 401};
402
81762d6d
DG		 403#define SEGMENT_SHIFT_256M 28
404#define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
405
cdaee006
DG		 406#define SEGMENT_SHIFT_1T 40
407#define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
408
409
3fc6c082
FB		 410/*****************************************************************************/
411/* Machine state register bits definition */
76a66253 412#define MSR_SF 63 /* Sixty-four-bit mode hflags */
bd928eba 413#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
3fc6c082 414#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
a4f30719 415#define MSR_SHV 60 /* hypervisor state hflags */
363be49c
JM		 416#define MSR_CM 31 /* Computation mode for BookE hflags */
417#define MSR_ICM 30 /* Interrupt computation mode for BookE */
a4f30719 418#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
71afeb61 419#define MSR_GS 28 /* guest state for BookE */
363be49c 420#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
d26bfc9a
JM		 421#define MSR_VR 25 /* altivec available x hflags */
422#define MSR_SPE 25 /* SPE enable for BookE x hflags */
76a66253
JM		 423#define MSR_AP 23 /* Access privilege state on 602 hflags */
424#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
3fc6c082 425#define MSR_KEY 19 /* key bit on 603e */
25ba3a68 426#define MSR_POW 18 /* Power management */
d26bfc9a
JM		 427#define MSR_TGPR 17 /* TGPR usage on 602/603 x */
428#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
3fc6c082
FB		 429#define MSR_ILE 16 /* Interrupt little-endian mode */
430#define MSR_EE 15 /* External interrupt enable */
76a66253
JM		 431#define MSR_PR 14 /* Problem state hflags */
432#define MSR_FP 13 /* Floating point available hflags */
3fc6c082 433#define MSR_ME 12 /* Machine check interrupt enable */
76a66253 434#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
d26bfc9a
JM		 435#define MSR_SE 10 /* Single-step trace enable x hflags */
436#define MSR_DWE 10 /* Debug wait enable on 405 x */
437#define MSR_UBLE 10 /* User BTB lock enable on e500 x */
438#define MSR_BE 9 /* Branch trace enable x hflags */
439#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
76a66253 440#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
3fc6c082 441#define MSR_AL 7 /* AL bit on POWER */
0411a972 442#define MSR_EP 6 /* Exception prefix on 601 */
3fc6c082 443#define MSR_IR 5 /* Instruction relocate */
3fc6c082 444#define MSR_DR 4 /* Data relocate */
25ba3a68 445#define MSR_PE 3 /* Protection enable on 403 */
d26bfc9a
JM		 446#define MSR_PX 2 /* Protection exclusive on 403 x */
447#define MSR_PMM 2 /* Performance monitor mark on POWER x */
448#define MSR_RI 1 /* Recoverable interrupt 1 */
449#define MSR_LE 0 /* Little-endian mode 1 hflags */
0411a972
JM		 450
451#define msr_sf ((env->msr >> MSR_SF) & 1)
452#define msr_isf ((env->msr >> MSR_ISF) & 1)
a4f30719 453#define msr_shv ((env->msr >> MSR_SHV) & 1)
0411a972
JM		 454#define msr_cm ((env->msr >> MSR_CM) & 1)
455#define msr_icm ((env->msr >> MSR_ICM) & 1)
a4f30719 456#define msr_thv ((env->msr >> MSR_THV) & 1)
71afeb61 457#define msr_gs ((env->msr >> MSR_GS) & 1)
0411a972
JM		 458#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
459#define msr_vr ((env->msr >> MSR_VR) & 1)
f9320410 460#define msr_spe ((env->msr >> MSR_SPE) & 1)
0411a972
JM		 461#define msr_ap ((env->msr >> MSR_AP) & 1)
462#define msr_sa ((env->msr >> MSR_SA) & 1)
463#define msr_key ((env->msr >> MSR_KEY) & 1)
464#define msr_pow ((env->msr >> MSR_POW) & 1)
465#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
466#define msr_ce ((env->msr >> MSR_CE) & 1)
467#define msr_ile ((env->msr >> MSR_ILE) & 1)
468#define msr_ee ((env->msr >> MSR_EE) & 1)
469#define msr_pr ((env->msr >> MSR_PR) & 1)
470#define msr_fp ((env->msr >> MSR_FP) & 1)
471#define msr_me ((env->msr >> MSR_ME) & 1)
472#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
473#define msr_se ((env->msr >> MSR_SE) & 1)
474#define msr_dwe ((env->msr >> MSR_DWE) & 1)
475#define msr_uble ((env->msr >> MSR_UBLE) & 1)
476#define msr_be ((env->msr >> MSR_BE) & 1)
477#define msr_de ((env->msr >> MSR_DE) & 1)
478#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
479#define msr_al ((env->msr >> MSR_AL) & 1)
480#define msr_ep ((env->msr >> MSR_EP) & 1)
481#define msr_ir ((env->msr >> MSR_IR) & 1)
482#define msr_dr ((env->msr >> MSR_DR) & 1)
483#define msr_pe ((env->msr >> MSR_PE) & 1)
484#define msr_px ((env->msr >> MSR_PX) & 1)
485#define msr_pmm ((env->msr >> MSR_PMM) & 1)
486#define msr_ri ((env->msr >> MSR_RI) & 1)
487#define msr_le ((env->msr >> MSR_LE) & 1)
a4f30719
JM		 488/* Hypervisor bit is more specific */
489#if defined(TARGET_PPC64)
490#define MSR_HVB (1ULL << MSR_SHV)
491#define msr_hv msr_shv
492#else
493#if defined(PPC_EMULATE_32BITS_HYPV)
494#define MSR_HVB (1ULL << MSR_THV)
495#define msr_hv msr_thv
a4f30719
JM		 496#else
497#define MSR_HVB (0ULL)
498#define msr_hv (0)
499#endif
500#endif
79aceca5 501
a586e548 502/* Exception state register bits definition */
542df9bf
AG		 503#define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
504#define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
505#define ESR_PTR (1 << (63 - 38)) /* Trap */
506#define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
507#define ESR_ST (1 << (63 - 40)) /* Store Operation */
508#define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
509#define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
510#define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
511#define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
512#define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
513#define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
514#define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
515#define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
516#define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
517#define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
518#define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
a586e548 519
d26bfc9a 520enum {
4018bae9 521 POWERPC_FLAG_NONE = 0x00000000,
d26bfc9a 522 /* Flag for MSR bit 25 signification (VRE/SPE) */
4018bae9
JM		 523 POWERPC_FLAG_SPE = 0x00000001,
524 POWERPC_FLAG_VRE = 0x00000002,
d26bfc9a 525 /* Flag for MSR bit 17 signification (TGPR/CE) */
4018bae9
JM		 526 POWERPC_FLAG_TGPR = 0x00000004,
527 POWERPC_FLAG_CE = 0x00000008,
d26bfc9a 528 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
4018bae9
JM		 529 POWERPC_FLAG_SE = 0x00000010,
530 POWERPC_FLAG_DWE = 0x00000020,
531 POWERPC_FLAG_UBLE = 0x00000040,
d26bfc9a 532 /* Flag for MSR bit 9 signification (BE/DE) */
4018bae9
JM		 533 POWERPC_FLAG_BE = 0x00000080,
534 POWERPC_FLAG_DE = 0x00000100,
a4f30719 535 /* Flag for MSR bit 2 signification (PX/PMM) */
4018bae9
JM		 536 POWERPC_FLAG_PX = 0x00000200,
537 POWERPC_FLAG_PMM = 0x00000400,
538 /* Flag for special features */
539 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
540 POWERPC_FLAG_RTC_CLK = 0x00010000,
541 POWERPC_FLAG_BUS_CLK = 0x00020000,
697ab892
DG		 542 /* Has CFAR */
543 POWERPC_FLAG_CFAR = 0x00040000,
d26bfc9a
JM		 544};
545
7c58044c
JM		 546/*****************************************************************************/
547/* Floating point status and control register */
548#define FPSCR_FX 31 /* Floating-point exception summary */
549#define FPSCR_FEX 30 /* Floating-point enabled exception summary */
550#define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
551#define FPSCR_OX 28 /* Floating-point overflow exception */
552#define FPSCR_UX 27 /* Floating-point underflow exception */
553#define FPSCR_ZX 26 /* Floating-point zero divide exception */
554#define FPSCR_XX 25 /* Floating-point inexact exception */
555#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
556#define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
557#define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
558#define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
559#define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
560#define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
561#define FPSCR_FR 18 /* Floating-point fraction rounded */
562#define FPSCR_FI 17 /* Floating-point fraction inexact */
563#define FPSCR_C 16 /* Floating-point result class descriptor */
564#define FPSCR_FL 15 /* Floating-point less than or negative */
565#define FPSCR_FG 14 /* Floating-point greater than or negative */
566#define FPSCR_FE 13 /* Floating-point equal or zero */
567#define FPSCR_FU 12 /* Floating-point unordered or NaN */
568#define FPSCR_FPCC 12 /* Floating-point condition code */
569#define FPSCR_FPRF 12 /* Floating-point result flags */
570#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
571#define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
572#define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
573#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
574#define FPSCR_OE 6 /* Floating-point overflow exception enable */
575#define FPSCR_UE 5 /* Floating-point undeflow exception enable */
576#define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
577#define FPSCR_XE 3 /* Floating-point inexact exception enable */
578#define FPSCR_NI 2 /* Floating-point non-IEEE mode */
579#define FPSCR_RN1 1
580#define FPSCR_RN 0 /* Floating-point rounding control */
581#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
582#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
583#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
584#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
585#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
586#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
587#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
588#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
589#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
590#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
591#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
592#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
593#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
594#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
595#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
596#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
597#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
598#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
599#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
600#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
601#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
602#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
603#define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
604/* Invalid operation exception summary */
605#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
606 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
607 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
608 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
609 (1 << FPSCR_VXCVI)))
610/* exception summary */
611#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
612/* enabled exception summary */
613#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
614 0x1F)
615
616/*****************************************************************************/
6fa724a3
AJ		 617/* Vector status and control register */
618#define VSCR_NJ 16 /* Vector non-java */
619#define VSCR_SAT 0 /* Vector saturation */
620#define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
621#define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
622
01662f3e
AG		 623/*****************************************************************************/
624/* BookE e500 MMU registers */
625
626#define MAS0_NV_SHIFT 0
627#define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
628
629#define MAS0_WQ_SHIFT 12
630#define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
631/* Write TLB entry regardless of reservation */
632#define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
633/* Write TLB entry only already in use */
634#define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
635/* Clear TLB entry */
636#define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
637
638#define MAS0_HES_SHIFT 14
639#define MAS0_HES (1 << MAS0_HES_SHIFT)
640
641#define MAS0_ESEL_SHIFT 16
642#define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
643
644#define MAS0_TLBSEL_SHIFT 28
645#define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
646#define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
647#define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
648#define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
649#define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
650
651#define MAS0_ATSEL_SHIFT 31
652#define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
653#define MAS0_ATSEL_TLB 0
654#define MAS0_ATSEL_LRAT MAS0_ATSEL
655
2bd9543c
SW		 656#define MAS1_TSIZE_SHIFT 7
657#define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
01662f3e
AG		 658
659#define MAS1_TS_SHIFT 12
660#define MAS1_TS (1 << MAS1_TS_SHIFT)
661
662#define MAS1_IND_SHIFT 13
663#define MAS1_IND (1 << MAS1_IND_SHIFT)
664
665#define MAS1_TID_SHIFT 16
666#define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
667
668#define MAS1_IPROT_SHIFT 30
669#define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
670
671#define MAS1_VALID_SHIFT 31
672#define MAS1_VALID 0x80000000
673
674#define MAS2_EPN_SHIFT 12
96091698 675#define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
01662f3e
AG		 676
677#define MAS2_ACM_SHIFT 6
678#define MAS2_ACM (1 << MAS2_ACM_SHIFT)
679
680#define MAS2_VLE_SHIFT 5
681#define MAS2_VLE (1 << MAS2_VLE_SHIFT)
682
683#define MAS2_W_SHIFT 4
684#define MAS2_W (1 << MAS2_W_SHIFT)
685
686#define MAS2_I_SHIFT 3
687#define MAS2_I (1 << MAS2_I_SHIFT)
688
689#define MAS2_M_SHIFT 2
690#define MAS2_M (1 << MAS2_M_SHIFT)
691
692#define MAS2_G_SHIFT 1
693#define MAS2_G (1 << MAS2_G_SHIFT)
694
695#define MAS2_E_SHIFT 0
696#define MAS2_E (1 << MAS2_E_SHIFT)
697
698#define MAS3_RPN_SHIFT 12
699#define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
700
701#define MAS3_U0 0x00000200
702#define MAS3_U1 0x00000100
703#define MAS3_U2 0x00000080
704#define MAS3_U3 0x00000040
705#define MAS3_UX 0x00000020
706#define MAS3_SX 0x00000010
707#define MAS3_UW 0x00000008
708#define MAS3_SW 0x00000004
709#define MAS3_UR 0x00000002
710#define MAS3_SR 0x00000001
711#define MAS3_SPSIZE_SHIFT 1
712#define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
713
714#define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
715#define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
716#define MAS4_TIDSELD_MASK 0x00030000
717#define MAS4_TIDSELD_PID0 0x00000000
718#define MAS4_TIDSELD_PID1 0x00010000
719#define MAS4_TIDSELD_PID2 0x00020000
720#define MAS4_TIDSELD_PIDZ 0x00030000
721#define MAS4_INDD 0x00008000 /* Default IND */
722#define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
723#define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
724#define MAS4_ACMD 0x00000040
725#define MAS4_VLED 0x00000020
726#define MAS4_WD 0x00000010
727#define MAS4_ID 0x00000008
728#define MAS4_MD 0x00000004
729#define MAS4_GD 0x00000002
730#define MAS4_ED 0x00000001
731#define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
732#define MAS4_WIMGED_SHIFT 0
733
734#define MAS5_SGS 0x80000000
735#define MAS5_SLPID_MASK 0x00000fff
736
737#define MAS6_SPID0 0x3fff0000
738#define MAS6_SPID1 0x00007ffe
739#define MAS6_ISIZE(x) MAS1_TSIZE(x)
740#define MAS6_SAS 0x00000001
741#define MAS6_SPID MAS6_SPID0
742#define MAS6_SIND 0x00000002 /* Indirect page */
743#define MAS6_SIND_SHIFT 1
744#define MAS6_SPID_MASK 0x3fff0000
745#define MAS6_SPID_SHIFT 16
746#define MAS6_ISIZE_MASK 0x00000f80
747#define MAS6_ISIZE_SHIFT 7
748
749#define MAS7_RPN 0xffffffff
750
751#define MAS8_TGS 0x80000000
752#define MAS8_VF 0x40000000
753#define MAS8_TLBPID 0x00000fff
754
755/* Bit definitions for MMUCFG */
756#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
757#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
758#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
759#define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
760#define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
761#define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
762#define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
763#define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
764#define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
765
766/* Bit definitions for MMUCSR0 */
767#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
768#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
769#define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
770#define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
771#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
772 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
773#define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
774#define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
775#define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
776#define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
777
778/* TLBnCFG encoding */
779#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
780#define TLBnCFG_HES 0x00002000 /* HW select supported */
781#define TLBnCFG_AVAIL 0x00004000 /* variable page size */
782#define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
783#define TLBnCFG_GTWE 0x00010000 /* Guest can write */
784#define TLBnCFG_IND 0x00020000 /* IND entries supported */
785#define TLBnCFG_PT 0x00040000 /* Can load from page table */
786#define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
787#define TLBnCFG_MINSIZE_SHIFT 20
788#define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
789#define TLBnCFG_MAXSIZE_SHIFT 16
790#define TLBnCFG_ASSOC 0xff000000 /* Associativity */
791#define TLBnCFG_ASSOC_SHIFT 24
792
793/* TLBnPS encoding */
794#define TLBnPS_4K 0x00000004
795#define TLBnPS_8K 0x00000008
796#define TLBnPS_16K 0x00000010
797#define TLBnPS_32K 0x00000020
798#define TLBnPS_64K 0x00000040
799#define TLBnPS_128K 0x00000080
800#define TLBnPS_256K 0x00000100
801#define TLBnPS_512K 0x00000200
802#define TLBnPS_1M 0x00000400
803#define TLBnPS_2M 0x00000800
804#define TLBnPS_4M 0x00001000
805#define TLBnPS_8M 0x00002000
806#define TLBnPS_16M 0x00004000
807#define TLBnPS_32M 0x00008000
808#define TLBnPS_64M 0x00010000
809#define TLBnPS_128M 0x00020000
810#define TLBnPS_256M 0x00040000
811#define TLBnPS_512M 0x00080000
812#define TLBnPS_1G 0x00100000
813#define TLBnPS_2G 0x00200000
814#define TLBnPS_4G 0x00400000
815#define TLBnPS_8G 0x00800000
816#define TLBnPS_16G 0x01000000
817#define TLBnPS_32G 0x02000000
818#define TLBnPS_64G 0x04000000
819#define TLBnPS_128G 0x08000000
820#define TLBnPS_256G 0x10000000
821
822/* tlbilx action encoding */
823#define TLBILX_T_ALL 0
824#define TLBILX_T_TID 1
825#define TLBILX_T_FULLMATCH 3
826#define TLBILX_T_CLASS0 4
827#define TLBILX_T_CLASS1 5
828#define TLBILX_T_CLASS2 6
829#define TLBILX_T_CLASS3 7
830
831/* BookE 2.06 helper defines */
832
833#define BOOKE206_FLUSH_TLB0 (1 << 0)
834#define BOOKE206_FLUSH_TLB1 (1 << 1)
835#define BOOKE206_FLUSH_TLB2 (1 << 2)
836#define BOOKE206_FLUSH_TLB3 (1 << 3)
837
838/* number of possible TLBs */
839#define BOOKE206_MAX_TLBN 4
840
58e00a24
AG		 841/*****************************************************************************/
842/* Embedded.Processor Control */
843
844#define DBELL_TYPE_SHIFT 27
845#define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
846#define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
847#define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
848#define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
849#define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
850#define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
851
852#define DBELL_BRDCAST (1 << 26)
853#define DBELL_LPIDTAG_SHIFT 14
854#define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
855#define DBELL_PIRTAG_MASK 0x3fff
856
4656e1f0
BH		 857/*****************************************************************************/
858/* Segment page size information, used by recent hash MMUs
859 * The format of this structure mirrors kvm_ppc_smmu_info
860 */
861
862#define PPC_PAGE_SIZES_MAX_SZ 8
863
864struct ppc_one_page_size {
865 uint32_t page_shift; /* Page shift (or 0) */
866 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
867};
868
869struct ppc_one_seg_page_size {
870 uint32_t page_shift; /* Base page shift of segment (or 0) */
871 uint32_t slb_enc; /* SLB encoding for BookS */
872 struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
873};
874
875struct ppc_segment_page_sizes {
876 struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
877};
878
879
6fa724a3 880/*****************************************************************************/
7c58044c 881/* The whole PowerPC CPU context */
6ebbf390 882#define NB_MMU_MODES 3
6ebbf390 883
3fc6c082
FB		 884struct CPUPPCState {
885 /* First are the most commonly used resources
886 * during translated code execution
887 */
79aceca5 888 /* general purpose registers */
bd7d9a6d 889 target_ulong gpr[32];
65d6c0f3 890#if !defined(TARGET_PPC64)
3cd7d1dd 891 /* Storage for GPR MSB, used by the SPE extension */
bd7d9a6d 892 target_ulong gprh[32];
3cd7d1dd 893#endif
3fc6c082
FB		 894 /* LR */
895 target_ulong lr;
896 /* CTR */
897 target_ulong ctr;
898 /* condition register */
47e4661c 899 uint32_t crf[8];
697ab892
DG		 900#if defined(TARGET_PPC64)
901 /* CFAR */
902 target_ulong cfar;
903#endif
da91a00f 904 /* XER (with SO, OV, CA split out) */
3d7b417e 905 target_ulong xer;
da91a00f
RH		 906 target_ulong so;
907 target_ulong ov;
908 target_ulong ca;
79aceca5 909 /* Reservation address */
18b21a2f
NF		 910 target_ulong reserve_addr;
911 /* Reservation value */
912 target_ulong reserve_val;
4425265b
NF		 913 /* Reservation store address */
914 target_ulong reserve_ea;
915 /* Reserved store source register and size */
916 target_ulong reserve_info;
3fc6c082
FB		 917
918 /* Those ones are used in supervisor mode only */
79aceca5 919 /* machine state register */
0411a972 920 target_ulong msr;
3fc6c082 921 /* temporary general purpose registers */
bd7d9a6d 922 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
3fc6c082
FB		 923
924 /* Floating point execution context */
4ecc3190 925 float_status fp_status;
3fc6c082
FB		 926 /* floating point registers */
927 float64 fpr[32];
928 /* floating point status and control register */
30304420 929 target_ulong fpscr;
4ecc3190 930
cb2dbfc3
AJ		 931 /* Next instruction pointer */
932 target_ulong nip;
a316d335 933
ac9eb073
FB		 934 int access_type; /* when a memory exception occurs, the access
935 type is stored here */
a541f297 936
cb2dbfc3
AJ		 937 CPU_COMMON
938
f2e63a42
JM		 939 /* MMU context - only relevant for full system emulation */
940#if !defined(CONFIG_USER_ONLY)
941#if defined(TARGET_PPC64)
f2e63a42 942 /* PowerPC 64 SLB area */
c227f099 943 ppc_slb_t slb[64];
f2e63a42
JM		 944 int slb_nr;
945#endif
3fc6c082 946 /* segment registers */
a8170e5e
AK		 947 hwaddr htab_base;
948 hwaddr htab_mask;
74d37793 949 target_ulong sr[32];
f43e3525
DG		 950 /* externally stored hash table */
951 uint8_t *external_htab;
3fc6c082
FB		 952 /* BATs */
953 int nb_BATs;
954 target_ulong DBAT[2][8];
955 target_ulong IBAT[2][8];
01662f3e 956 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
f2e63a42
JM		 957 int nb_tlb; /* Total number of TLB */
958 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
959 int nb_ways; /* Number of ways in the TLB set */
960 int last_way; /* Last used way used to allocate TLB in a LRU way */
961 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
962 int nb_pids; /* Number of available PID registers */
1c53accc
AG		 963 int tlb_type; /* Type of TLB we're dealing with */
964 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
f2e63a42
JM		 965 /* 403 dedicated access protection registers */
966 target_ulong pb[4];
93dd5e85
SW		 967 bool tlb_dirty; /* Set to non-zero when modifying TLB */
968 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
f2e63a42 969#endif
9fddaa0c 970
3fc6c082
FB		 971 /* Other registers */
972 /* Special purpose registers */
973 target_ulong spr[1024];
c227f099 974 ppc_spr_t spr_cb[1024];
3fc6c082 975 /* Altivec registers */
c227f099 976 ppc_avr_t avr[32];
3fc6c082 977 uint32_t vscr;
30304420
DG		 978 /* VSX registers */
979 uint64_t vsr[32];
d9bce9d9 980 /* SPE registers */
2231ef10 981 uint64_t spe_acc;
d9bce9d9 982 uint32_t spe_fscr;
fbd265b6
AJ		 983 /* SPE and Altivec can share a status since they will never be used
984 * simultaneously */
985 float_status vec_status;
3fc6c082
FB		 986
987 /* Internal devices resources */
9fddaa0c 988 /* Time base and decrementer */
c227f099 989 ppc_tb_t *tb_env;
3fc6c082 990 /* Device control registers */
c227f099 991 ppc_dcr_t *dcr_env;
3fc6c082 992
d63001d1
JM		 993 int dcache_line_size;
994 int icache_line_size;
995
3fc6c082
FB		 996 /* Those resources are used during exception processing */
997 /* CPU model definition */
a750fc0b 998 target_ulong msr_mask;
c227f099
AL		 999 powerpc_mmu_t mmu_model;
1000 powerpc_excp_t excp_model;
1001 powerpc_input_t bus_model;
237c0af0 1002 int bfd_mach;
3fc6c082 1003 uint32_t flags;
c29b735c 1004 uint64_t insns_flags;
a5858d7a 1005 uint64_t insns_flags2;
4656e1f0
BH		 1006#if defined(TARGET_PPC64)
1007 struct ppc_segment_page_sizes sps;
1008#endif
3fc6c082 1009
ed120055 1010#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
ac7d12ba
DG		 1011 uint64_t vpa_addr;
1012 uint64_t slb_shadow_addr, slb_shadow_size;
1013 uint64_t dtl_addr, dtl_size;
ed120055
DG		 1014#endif /* TARGET_PPC64 */
1015
3fc6c082 1016 int error_code;
47103572 1017 uint32_t pending_interrupts;
e9df014c 1018#if !defined(CONFIG_USER_ONLY)
4abf79a4 1019 /* This is the IRQ controller, which is implementation dependent
e9df014c
JM		 1020 * and only relevant when emulating a complete machine.
1021 */
1022 uint32_t irq_input_state;
1023 void **irq_inputs;
e1833e1f
JM		 1024 /* Exception vectors */
1025 target_ulong excp_vectors[POWERPC_EXCP_NB];
1026 target_ulong excp_prefix;
fc1c67bc 1027 target_ulong hreset_excp_prefix;
e1833e1f
JM		 1028 target_ulong ivor_mask;
1029 target_ulong ivpr_mask;
d63001d1 1030 target_ulong hreset_vector;
68c2dd70
AG		 1031 hwaddr mpic_iack;
1032 /* true when the external proxy facility mode is enabled */
1033 bool mpic_proxy;
e9df014c 1034#endif
3fc6c082
FB		 1035
1036 /* Those resources are used only during code translation */
3fc6c082 1037 /* opcode handlers */
c227f099 1038 opc_handler_t *opcodes[0x40];
3fc6c082 1039
5cbdb3a3 1040 /* Those resources are used only in QEMU core */
056401ea 1041 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
4abf79a4 1042 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
6ebbf390 1043 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
3fc6c082 1044
9fddaa0c 1045 /* Power management */
cd346349 1046 int (*check_pow)(CPUPPCState *env);
a541f297 1047
2c50e26e
EI		 1048#if !defined(CONFIG_USER_ONLY)
1049 void *load_info; /* Holds boot loading state. */
1050#endif
ddd1055b
FC		 1051
1052 /* booke timers */
1053
1054 /* Specifies bit locations of the Time Base used to signal a fixed timer
1055 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1056 *
1057 * 0 selects the least significant bit.
1058 * 63 selects the most significant bit.
1059 */
1060 uint8_t fit_period[4];
1061 uint8_t wdt_period[4];
3fc6c082 1062};
79aceca5 1063
ddd1055b
FC		 1064#define SET_FIT_PERIOD(a_, b_, c_, d_) \
1065do { \
1066 env->fit_period[0] = (a_); \
1067 env->fit_period[1] = (b_); \
1068 env->fit_period[2] = (c_); \
1069 env->fit_period[3] = (d_); \
1070 } while (0)
1071
1072#define SET_WDT_PERIOD(a_, b_, c_, d_) \
1073do { \
1074 env->wdt_period[0] = (a_); \
1075 env->wdt_period[1] = (b_); \
1076 env->wdt_period[2] = (c_); \
1077 env->wdt_period[3] = (d_); \
1078 } while (0)
1079
1d0cb67d
AF		 1080#include "cpu-qom.h"
1081
3fc6c082 1082/*****************************************************************************/
397b457d 1083PowerPCCPU *cpu_ppc_init(const char *cpu_model);
2e70f6ef 1084void ppc_translate_init(void);
36081602 1085int cpu_ppc_exec (CPUPPCState *s);
79aceca5
FB		 1086/* you can call this signal handler from your SIGBUS and SIGSEGV
1087 signal handlers to inform the virtual CPU of exceptions. non zero
1088 is returned if the signal was handled by the virtual CPU. */
36081602
JM		 1089int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1090 void *puc);
93220573 1091int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
97b348e7 1092 int mmu_idx);
0b5c1ce8 1093#define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
e9df014c 1094void ppc_hw_interrupt (CPUPPCState *env);
a541f297 1095
76a66253 1096#if !defined(CONFIG_USER_ONLY)
45d827d2 1097void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
12de9a39 1098#endif /* !defined(CONFIG_USER_ONLY) */
0411a972 1099void ppc_store_msr (CPUPPCState *env, target_ulong value);
3fc6c082 1100
9a78eead 1101void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
aaed909a 1102
9fddaa0c
FB		 1103/* Time-base and decrementer management */
1104#ifndef NO_CPU_IO_DEFS
e3ea6529 1105uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
9fddaa0c
FB		 1106uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1107void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1108void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
b711de95 1109uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
a062e36c
JM		 1110uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1111void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1112void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
9fddaa0c
FB		 1113uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1114void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
58a7d328
JM		 1115uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1116void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1117uint64_t cpu_ppc_load_purr (CPUPPCState *env);
d9bce9d9
JM		 1118uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1119uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1120#if !defined(CONFIG_USER_ONLY)
1121void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1122void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1123target_ulong load_40x_pit (CPUPPCState *env);
1124void store_40x_pit (CPUPPCState *env, target_ulong val);
8ecc7913 1125void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
c294fc58 1126void store_40x_sler (CPUPPCState *env, uint32_t val);
d9bce9d9
JM		 1127void store_booke_tcr (CPUPPCState *env, target_ulong val);
1128void store_booke_tsr (CPUPPCState *env, target_ulong val);
0a032cbe 1129void ppc_tlb_invalidate_all (CPUPPCState *env);
daf4f96e 1130void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
d9bce9d9 1131#endif
9fddaa0c 1132#endif
79aceca5 1133
d6478bc7
FC		 1134void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1135
636aa200 1136static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
6b542af7
JM		 1137{
1138 uint64_t gprv;
1139
1140 gprv = env->gpr[gprn];
1141#if !defined(TARGET_PPC64)
1142 if (env->flags & POWERPC_FLAG_SPE) {
1143 /* If the CPU implements the SPE extension, we have to get the
1144 * high bits of the GPR from the gprh storage area
1145 */
1146 gprv &= 0xFFFFFFFFULL;
1147 gprv |= (uint64_t)env->gprh[gprn] << 32;
1148 }
1149#endif
1150
1151 return gprv;
1152}
1153
2e719ba3 1154/* Device control registers */
73b01960
AG		 1155int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1156int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
2e719ba3 1157
397b457d
AF		 1158static inline CPUPPCState *cpu_init(const char *cpu_model)
1159{
1160 PowerPCCPU *cpu = cpu_ppc_init(cpu_model);
1161 if (cpu == NULL) {
1162 return NULL;
1163 }
1164 return &cpu->env;
1165}
1166
9467d44c
TS		 1167#define cpu_exec cpu_ppc_exec
1168#define cpu_gen_code cpu_ppc_gen_code
1169#define cpu_signal_handler cpu_ppc_signal_handler
c732abe2 1170#define cpu_list ppc_cpu_list
9467d44c 1171
fc1c67bc 1172#define CPU_SAVE_VERSION 4
b3c7724c 1173
6ebbf390
JM		 1174/* MMU modes definitions */
1175#define MMU_MODE0_SUFFIX _user
1176#define MMU_MODE1_SUFFIX _kernel
6ebbf390 1177#define MMU_MODE2_SUFFIX _hypv
6ebbf390 1178#define MMU_USER_IDX 0
1328c2bf 1179static inline int cpu_mmu_index (CPUPPCState *env)
6ebbf390
JM		 1180{
1181 return env->mmu_idx;
1182}
1183
6e68e076 1184#if defined(CONFIG_USER_ONLY)
1328c2bf 1185static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp)
6e68e076 1186{
f8ed7070 1187 if (newsp)
6e68e076 1188 env->gpr[1] = newsp;
d11f69b2 1189 env->gpr[3] = 0;
6e68e076
PB		 1190}
1191#endif
1192
022c62cb 1193#include "exec/cpu-all.h"
79aceca5 1194
3fc6c082 1195/*****************************************************************************/
e1571908 1196/* CRF definitions */
57951c27
AJ		 1197#define CRF_LT 3
1198#define CRF_GT 2
1199#define CRF_EQ 1
1200#define CRF_SO 0
e6bba2ef
NF		 1201#define CRF_CH (1 << CRF_LT)
1202#define CRF_CL (1 << CRF_GT)
1203#define CRF_CH_OR_CL (1 << CRF_EQ)
1204#define CRF_CH_AND_CL (1 << CRF_SO)
e1571908
AJ		 1205
1206/* XER definitions */
3d7b417e
AJ		 1207#define XER_SO 31
1208#define XER_OV 30
1209#define XER_CA 29
1210#define XER_CMP 8
1211#define XER_BC 0
da91a00f
RH		 1212#define xer_so (env->so)
1213#define xer_ov (env->ov)
1214#define xer_ca (env->ca)
3d7b417e
AJ		 1215#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1216#define xer_bc ((env->xer >> XER_BC) & 0x7F)
79aceca5 1217
3fc6c082 1218/* SPR definitions */
80d11f44
JM		 1219#define SPR_MQ (0x000)
1220#define SPR_XER (0x001)
1221#define SPR_601_VRTCU (0x004)
1222#define SPR_601_VRTCL (0x005)
1223#define SPR_601_UDECR (0x006)
1224#define SPR_LR (0x008)
1225#define SPR_CTR (0x009)
697ab892 1226#define SPR_DSCR (0x011)
80d11f44
JM		 1227#define SPR_DSISR (0x012)
1228#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1229#define SPR_601_RTCU (0x014)
1230#define SPR_601_RTCL (0x015)
1231#define SPR_DECR (0x016)
1232#define SPR_SDR1 (0x019)
1233#define SPR_SRR0 (0x01A)
1234#define SPR_SRR1 (0x01B)
697ab892 1235#define SPR_CFAR (0x01C)
80d11f44
JM		 1236#define SPR_AMR (0x01D)
1237#define SPR_BOOKE_PID (0x030)
1238#define SPR_BOOKE_DECAR (0x036)
1239#define SPR_BOOKE_CSRR0 (0x03A)
1240#define SPR_BOOKE_CSRR1 (0x03B)
1241#define SPR_BOOKE_DEAR (0x03D)
1242#define SPR_BOOKE_ESR (0x03E)
1243#define SPR_BOOKE_IVPR (0x03F)
1244#define SPR_MPC_EIE (0x050)
1245#define SPR_MPC_EID (0x051)
1246#define SPR_MPC_NRI (0x052)
1247#define SPR_CTRL (0x088)
1248#define SPR_MPC_CMPA (0x090)
1249#define SPR_MPC_CMPB (0x091)
1250#define SPR_MPC_CMPC (0x092)
1251#define SPR_MPC_CMPD (0x093)
1252#define SPR_MPC_ECR (0x094)
1253#define SPR_MPC_DER (0x095)
1254#define SPR_MPC_COUNTA (0x096)
1255#define SPR_MPC_COUNTB (0x097)
1256#define SPR_UCTRL (0x098)
1257#define SPR_MPC_CMPE (0x098)
1258#define SPR_MPC_CMPF (0x099)
1259#define SPR_MPC_CMPG (0x09A)
1260#define SPR_MPC_CMPH (0x09B)
1261#define SPR_MPC_LCTRL1 (0x09C)
1262#define SPR_MPC_LCTRL2 (0x09D)
1263#define SPR_MPC_ICTRL (0x09E)
1264#define SPR_MPC_BAR (0x09F)
1265#define SPR_VRSAVE (0x100)
1266#define SPR_USPRG0 (0x100)
1267#define SPR_USPRG1 (0x101)
1268#define SPR_USPRG2 (0x102)
1269#define SPR_USPRG3 (0x103)
1270#define SPR_USPRG4 (0x104)
1271#define SPR_USPRG5 (0x105)
1272#define SPR_USPRG6 (0x106)
1273#define SPR_USPRG7 (0x107)
1274#define SPR_VTBL (0x10C)
1275#define SPR_VTBU (0x10D)
1276#define SPR_SPRG0 (0x110)
1277#define SPR_SPRG1 (0x111)
1278#define SPR_SPRG2 (0x112)
1279#define SPR_SPRG3 (0x113)
1280#define SPR_SPRG4 (0x114)
1281#define SPR_SCOMC (0x114)
1282#define SPR_SPRG5 (0x115)
1283#define SPR_SCOMD (0x115)
1284#define SPR_SPRG6 (0x116)
1285#define SPR_SPRG7 (0x117)
1286#define SPR_ASR (0x118)
1287#define SPR_EAR (0x11A)
1288#define SPR_TBL (0x11C)
1289#define SPR_TBU (0x11D)
1290#define SPR_TBU40 (0x11E)
1291#define SPR_SVR (0x11E)
1292#define SPR_BOOKE_PIR (0x11E)
1293#define SPR_PVR (0x11F)
1294#define SPR_HSPRG0 (0x130)
1295#define SPR_BOOKE_DBSR (0x130)
1296#define SPR_HSPRG1 (0x131)
1297#define SPR_HDSISR (0x132)
1298#define SPR_HDAR (0x133)
90dc8812 1299#define SPR_BOOKE_EPCR (0x133)
9d52e907 1300#define SPR_SPURR (0x134)
80d11f44
JM		 1301#define SPR_BOOKE_DBCR0 (0x134)
1302#define SPR_IBCR (0x135)
1303#define SPR_PURR (0x135)
1304#define SPR_BOOKE_DBCR1 (0x135)
1305#define SPR_DBCR (0x136)
1306#define SPR_HDEC (0x136)
1307#define SPR_BOOKE_DBCR2 (0x136)
1308#define SPR_HIOR (0x137)
1309#define SPR_MBAR (0x137)
1310#define SPR_RMOR (0x138)
1311#define SPR_BOOKE_IAC1 (0x138)
1312#define SPR_HRMOR (0x139)
1313#define SPR_BOOKE_IAC2 (0x139)
1314#define SPR_HSRR0 (0x13A)
1315#define SPR_BOOKE_IAC3 (0x13A)
1316#define SPR_HSRR1 (0x13B)
1317#define SPR_BOOKE_IAC4 (0x13B)
1318#define SPR_LPCR (0x13C)
1319#define SPR_BOOKE_DAC1 (0x13C)
1320#define SPR_LPIDR (0x13D)
1321#define SPR_DABR2 (0x13D)
1322#define SPR_BOOKE_DAC2 (0x13D)
1323#define SPR_BOOKE_DVC1 (0x13E)
1324#define SPR_BOOKE_DVC2 (0x13F)
1325#define SPR_BOOKE_TSR (0x150)
1326#define SPR_BOOKE_TCR (0x154)
a1ef618a
AG		 1327#define SPR_BOOKE_TLB0PS (0x158)
1328#define SPR_BOOKE_TLB1PS (0x159)
1329#define SPR_BOOKE_TLB2PS (0x15A)
1330#define SPR_BOOKE_TLB3PS (0x15B)
84755ed5 1331#define SPR_BOOKE_MAS7_MAS3 (0x174)
80d11f44
JM		 1332#define SPR_BOOKE_IVOR0 (0x190)
1333#define SPR_BOOKE_IVOR1 (0x191)
1334#define SPR_BOOKE_IVOR2 (0x192)
1335#define SPR_BOOKE_IVOR3 (0x193)
1336#define SPR_BOOKE_IVOR4 (0x194)
1337#define SPR_BOOKE_IVOR5 (0x195)
1338#define SPR_BOOKE_IVOR6 (0x196)
1339#define SPR_BOOKE_IVOR7 (0x197)
1340#define SPR_BOOKE_IVOR8 (0x198)
1341#define SPR_BOOKE_IVOR9 (0x199)
1342#define SPR_BOOKE_IVOR10 (0x19A)
1343#define SPR_BOOKE_IVOR11 (0x19B)
1344#define SPR_BOOKE_IVOR12 (0x19C)
1345#define SPR_BOOKE_IVOR13 (0x19D)
1346#define SPR_BOOKE_IVOR14 (0x19E)
1347#define SPR_BOOKE_IVOR15 (0x19F)
e9205258
AG		 1348#define SPR_BOOKE_IVOR38 (0x1B0)
1349#define SPR_BOOKE_IVOR39 (0x1B1)
1350#define SPR_BOOKE_IVOR40 (0x1B2)
1351#define SPR_BOOKE_IVOR41 (0x1B3)
1352#define SPR_BOOKE_IVOR42 (0x1B4)
80d11f44
JM		 1353#define SPR_BOOKE_SPEFSCR (0x200)
1354#define SPR_Exxx_BBEAR (0x201)
1355#define SPR_Exxx_BBTAR (0x202)
1356#define SPR_Exxx_L1CFG0 (0x203)
1357#define SPR_Exxx_NPIDR (0x205)
1358#define SPR_ATBL (0x20E)
1359#define SPR_ATBU (0x20F)
1360#define SPR_IBAT0U (0x210)
1361#define SPR_BOOKE_IVOR32 (0x210)
1362#define SPR_RCPU_MI_GRA (0x210)
1363#define SPR_IBAT0L (0x211)
1364#define SPR_BOOKE_IVOR33 (0x211)
1365#define SPR_IBAT1U (0x212)
1366#define SPR_BOOKE_IVOR34 (0x212)
1367#define SPR_IBAT1L (0x213)
1368#define SPR_BOOKE_IVOR35 (0x213)
1369#define SPR_IBAT2U (0x214)
1370#define SPR_BOOKE_IVOR36 (0x214)
1371#define SPR_IBAT2L (0x215)
1372#define SPR_BOOKE_IVOR37 (0x215)
1373#define SPR_IBAT3U (0x216)
1374#define SPR_IBAT3L (0x217)
1375#define SPR_DBAT0U (0x218)
1376#define SPR_RCPU_L2U_GRA (0x218)
1377#define SPR_DBAT0L (0x219)
1378#define SPR_DBAT1U (0x21A)
1379#define SPR_DBAT1L (0x21B)
1380#define SPR_DBAT2U (0x21C)
1381#define SPR_DBAT2L (0x21D)
1382#define SPR_DBAT3U (0x21E)
1383#define SPR_DBAT3L (0x21F)
1384#define SPR_IBAT4U (0x230)
1385#define SPR_RPCU_BBCMCR (0x230)
1386#define SPR_MPC_IC_CST (0x230)
1387#define SPR_Exxx_CTXCR (0x230)
1388#define SPR_IBAT4L (0x231)
1389#define SPR_MPC_IC_ADR (0x231)
1390#define SPR_Exxx_DBCR3 (0x231)
1391#define SPR_IBAT5U (0x232)
1392#define SPR_MPC_IC_DAT (0x232)
1393#define SPR_Exxx_DBCNT (0x232)
1394#define SPR_IBAT5L (0x233)
1395#define SPR_IBAT6U (0x234)
1396#define SPR_IBAT6L (0x235)
1397#define SPR_IBAT7U (0x236)
1398#define SPR_IBAT7L (0x237)
1399#define SPR_DBAT4U (0x238)
1400#define SPR_RCPU_L2U_MCR (0x238)
1401#define SPR_MPC_DC_CST (0x238)
1402#define SPR_Exxx_ALTCTXCR (0x238)
1403#define SPR_DBAT4L (0x239)
1404#define SPR_MPC_DC_ADR (0x239)
1405#define SPR_DBAT5U (0x23A)
1406#define SPR_BOOKE_MCSRR0 (0x23A)
1407#define SPR_MPC_DC_DAT (0x23A)
1408#define SPR_DBAT5L (0x23B)
1409#define SPR_BOOKE_MCSRR1 (0x23B)
1410#define SPR_DBAT6U (0x23C)
1411#define SPR_BOOKE_MCSR (0x23C)
1412#define SPR_DBAT6L (0x23D)
1413#define SPR_Exxx_MCAR (0x23D)
1414#define SPR_DBAT7U (0x23E)
1415#define SPR_BOOKE_DSRR0 (0x23E)
1416#define SPR_DBAT7L (0x23F)
1417#define SPR_BOOKE_DSRR1 (0x23F)
1418#define SPR_BOOKE_SPRG8 (0x25C)
1419#define SPR_BOOKE_SPRG9 (0x25D)
1420#define SPR_BOOKE_MAS0 (0x270)
1421#define SPR_BOOKE_MAS1 (0x271)
1422#define SPR_BOOKE_MAS2 (0x272)
1423#define SPR_BOOKE_MAS3 (0x273)
1424#define SPR_BOOKE_MAS4 (0x274)
1425#define SPR_BOOKE_MAS5 (0x275)
1426#define SPR_BOOKE_MAS6 (0x276)
1427#define SPR_BOOKE_PID1 (0x279)
1428#define SPR_BOOKE_PID2 (0x27A)
1429#define SPR_MPC_DPDR (0x280)
1430#define SPR_MPC_IMMR (0x288)
1431#define SPR_BOOKE_TLB0CFG (0x2B0)
1432#define SPR_BOOKE_TLB1CFG (0x2B1)
1433#define SPR_BOOKE_TLB2CFG (0x2B2)
1434#define SPR_BOOKE_TLB3CFG (0x2B3)
1435#define SPR_BOOKE_EPR (0x2BE)
1436#define SPR_PERF0 (0x300)
1437#define SPR_RCPU_MI_RBA0 (0x300)
1438#define SPR_MPC_MI_CTR (0x300)
1439#define SPR_PERF1 (0x301)
1440#define SPR_RCPU_MI_RBA1 (0x301)
1441#define SPR_PERF2 (0x302)
1442#define SPR_RCPU_MI_RBA2 (0x302)
1443#define SPR_MPC_MI_AP (0x302)
1444#define SPR_PERF3 (0x303)
1445#define SPR_RCPU_MI_RBA3 (0x303)
1446#define SPR_MPC_MI_EPN (0x303)
1447#define SPR_PERF4 (0x304)
1448#define SPR_PERF5 (0x305)
1449#define SPR_MPC_MI_TWC (0x305)
1450#define SPR_PERF6 (0x306)
1451#define SPR_MPC_MI_RPN (0x306)
1452#define SPR_PERF7 (0x307)
1453#define SPR_PERF8 (0x308)
1454#define SPR_RCPU_L2U_RBA0 (0x308)
1455#define SPR_MPC_MD_CTR (0x308)
1456#define SPR_PERF9 (0x309)
1457#define SPR_RCPU_L2U_RBA1 (0x309)
1458#define SPR_MPC_MD_CASID (0x309)
1459#define SPR_PERFA (0x30A)
1460#define SPR_RCPU_L2U_RBA2 (0x30A)
1461#define SPR_MPC_MD_AP (0x30A)
1462#define SPR_PERFB (0x30B)
1463#define SPR_RCPU_L2U_RBA3 (0x30B)
1464#define SPR_MPC_MD_EPN (0x30B)
1465#define SPR_PERFC (0x30C)
1466#define SPR_MPC_MD_TWB (0x30C)
1467#define SPR_PERFD (0x30D)
1468#define SPR_MPC_MD_TWC (0x30D)
1469#define SPR_PERFE (0x30E)
1470#define SPR_MPC_MD_RPN (0x30E)
1471#define SPR_PERFF (0x30F)
1472#define SPR_MPC_MD_TW (0x30F)
1473#define SPR_UPERF0 (0x310)
1474#define SPR_UPERF1 (0x311)
1475#define SPR_UPERF2 (0x312)
1476#define SPR_UPERF3 (0x313)
1477#define SPR_UPERF4 (0x314)
1478#define SPR_UPERF5 (0x315)
1479#define SPR_UPERF6 (0x316)
1480#define SPR_UPERF7 (0x317)
1481#define SPR_UPERF8 (0x318)
1482#define SPR_UPERF9 (0x319)
1483#define SPR_UPERFA (0x31A)
1484#define SPR_UPERFB (0x31B)
1485#define SPR_UPERFC (0x31C)
1486#define SPR_UPERFD (0x31D)
1487#define SPR_UPERFE (0x31E)
1488#define SPR_UPERFF (0x31F)
1489#define SPR_RCPU_MI_RA0 (0x320)
1490#define SPR_MPC_MI_DBCAM (0x320)
1491#define SPR_RCPU_MI_RA1 (0x321)
1492#define SPR_MPC_MI_DBRAM0 (0x321)
1493#define SPR_RCPU_MI_RA2 (0x322)
1494#define SPR_MPC_MI_DBRAM1 (0x322)
1495#define SPR_RCPU_MI_RA3 (0x323)
1496#define SPR_RCPU_L2U_RA0 (0x328)
1497#define SPR_MPC_MD_DBCAM (0x328)
1498#define SPR_RCPU_L2U_RA1 (0x329)
1499#define SPR_MPC_MD_DBRAM0 (0x329)
1500#define SPR_RCPU_L2U_RA2 (0x32A)
1501#define SPR_MPC_MD_DBRAM1 (0x32A)
1502#define SPR_RCPU_L2U_RA3 (0x32B)
1503#define SPR_440_INV0 (0x370)
1504#define SPR_440_INV1 (0x371)
1505#define SPR_440_INV2 (0x372)
1506#define SPR_440_INV3 (0x373)
1507#define SPR_440_ITV0 (0x374)
1508#define SPR_440_ITV1 (0x375)
1509#define SPR_440_ITV2 (0x376)
1510#define SPR_440_ITV3 (0x377)
1511#define SPR_440_CCR1 (0x378)
1512#define SPR_DCRIPR (0x37B)
1513#define SPR_PPR (0x380)
bd928eba 1514#define SPR_750_GQR0 (0x390)
80d11f44 1515#define SPR_440_DNV0 (0x390)
bd928eba 1516#define SPR_750_GQR1 (0x391)
80d11f44 1517#define SPR_440_DNV1 (0x391)
bd928eba 1518#define SPR_750_GQR2 (0x392)
80d11f44 1519#define SPR_440_DNV2 (0x392)
bd928eba 1520#define SPR_750_GQR3 (0x393)
80d11f44 1521#define SPR_440_DNV3 (0x393)
bd928eba 1522#define SPR_750_GQR4 (0x394)
80d11f44 1523#define SPR_440_DTV0 (0x394)
bd928eba 1524#define SPR_750_GQR5 (0x395)
80d11f44 1525#define SPR_440_DTV1 (0x395)
bd928eba 1526#define SPR_750_GQR6 (0x396)
80d11f44 1527#define SPR_440_DTV2 (0x396)
bd928eba 1528#define SPR_750_GQR7 (0x397)
80d11f44 1529#define SPR_440_DTV3 (0x397)
bd928eba
JM		 1530#define SPR_750_THRM4 (0x398)
1531#define SPR_750CL_HID2 (0x398)
80d11f44 1532#define SPR_440_DVLIM (0x398)
bd928eba 1533#define SPR_750_WPAR (0x399)
80d11f44 1534#define SPR_440_IVLIM (0x399)
bd928eba
JM		 1535#define SPR_750_DMAU (0x39A)
1536#define SPR_750_DMAL (0x39B)
80d11f44
JM		 1537#define SPR_440_RSTCFG (0x39B)
1538#define SPR_BOOKE_DCDBTRL (0x39C)
1539#define SPR_BOOKE_DCDBTRH (0x39D)
1540#define SPR_BOOKE_ICDBTRL (0x39E)
1541#define SPR_BOOKE_ICDBTRH (0x39F)
1542#define SPR_UMMCR2 (0x3A0)
1543#define SPR_UPMC5 (0x3A1)
1544#define SPR_UPMC6 (0x3A2)
1545#define SPR_UBAMR (0x3A7)
1546#define SPR_UMMCR0 (0x3A8)
1547#define SPR_UPMC1 (0x3A9)
1548#define SPR_UPMC2 (0x3AA)
1549#define SPR_USIAR (0x3AB)
1550#define SPR_UMMCR1 (0x3AC)
1551#define SPR_UPMC3 (0x3AD)
1552#define SPR_UPMC4 (0x3AE)
1553#define SPR_USDA (0x3AF)
1554#define SPR_40x_ZPR (0x3B0)
1555#define SPR_BOOKE_MAS7 (0x3B0)
80d11f44
JM		 1556#define SPR_MMCR2 (0x3B0)
1557#define SPR_PMC5 (0x3B1)
1558#define SPR_40x_PID (0x3B1)
80d11f44
JM		 1559#define SPR_PMC6 (0x3B2)
1560#define SPR_440_MMUCR (0x3B2)
80d11f44
JM		 1561#define SPR_4xx_CCR0 (0x3B3)
1562#define SPR_BOOKE_EPLC (0x3B3)
80d11f44
JM		 1563#define SPR_405_IAC3 (0x3B4)
1564#define SPR_BOOKE_EPSC (0x3B4)
80d11f44 1565#define SPR_405_IAC4 (0x3B5)
80d11f44 1566#define SPR_405_DVC1 (0x3B6)
80d11f44 1567#define SPR_405_DVC2 (0x3B7)
80d11f44
JM		 1568#define SPR_BAMR (0x3B7)
1569#define SPR_MMCR0 (0x3B8)
80d11f44
JM		 1570#define SPR_PMC1 (0x3B9)
1571#define SPR_40x_SGR (0x3B9)
80d11f44
JM		 1572#define SPR_PMC2 (0x3BA)
1573#define SPR_40x_DCWR (0x3BA)
80d11f44
JM		 1574#define SPR_SIAR (0x3BB)
1575#define SPR_405_SLER (0x3BB)
80d11f44
JM		 1576#define SPR_MMCR1 (0x3BC)
1577#define SPR_405_SU0R (0x3BC)
80d11f44
JM		 1578#define SPR_401_SKR (0x3BC)
1579#define SPR_PMC3 (0x3BD)
1580#define SPR_405_DBCR1 (0x3BD)
80d11f44 1581#define SPR_PMC4 (0x3BE)
80d11f44 1582#define SPR_SDA (0x3BF)
80d11f44
JM		 1583#define SPR_403_VTBL (0x3CC)
1584#define SPR_403_VTBU (0x3CD)
1585#define SPR_DMISS (0x3D0)
1586#define SPR_DCMP (0x3D1)
1587#define SPR_HASH1 (0x3D2)
1588#define SPR_HASH2 (0x3D3)
1589#define SPR_BOOKE_ICDBDR (0x3D3)
1590#define SPR_TLBMISS (0x3D4)
1591#define SPR_IMISS (0x3D4)
1592#define SPR_40x_ESR (0x3D4)
1593#define SPR_PTEHI (0x3D5)
1594#define SPR_ICMP (0x3D5)
1595#define SPR_40x_DEAR (0x3D5)
1596#define SPR_PTELO (0x3D6)
1597#define SPR_RPA (0x3D6)
1598#define SPR_40x_EVPR (0x3D6)
1599#define SPR_L3PM (0x3D7)
1600#define SPR_403_CDBCR (0x3D7)
4e777442 1601#define SPR_L3ITCR0 (0x3D8)
80d11f44
JM		 1602#define SPR_TCR (0x3D8)
1603#define SPR_40x_TSR (0x3D8)
1604#define SPR_IBR (0x3DA)
1605#define SPR_40x_TCR (0x3DA)
1606#define SPR_ESASRR (0x3DB)
1607#define SPR_40x_PIT (0x3DB)
1608#define SPR_403_TBL (0x3DC)
1609#define SPR_403_TBU (0x3DD)
1610#define SPR_SEBR (0x3DE)
1611#define SPR_40x_SRR2 (0x3DE)
1612#define SPR_SER (0x3DF)
1613#define SPR_40x_SRR3 (0x3DF)
4e777442 1614#define SPR_L3OHCR (0x3E8)
80d11f44
JM		 1615#define SPR_L3ITCR1 (0x3E9)
1616#define SPR_L3ITCR2 (0x3EA)
1617#define SPR_L3ITCR3 (0x3EB)
1618#define SPR_HID0 (0x3F0)
1619#define SPR_40x_DBSR (0x3F0)
1620#define SPR_HID1 (0x3F1)
1621#define SPR_IABR (0x3F2)
1622#define SPR_40x_DBCR0 (0x3F2)
1623#define SPR_601_HID2 (0x3F2)
1624#define SPR_Exxx_L1CSR0 (0x3F2)
1625#define SPR_ICTRL (0x3F3)
1626#define SPR_HID2 (0x3F3)
bd928eba 1627#define SPR_750CL_HID4 (0x3F3)
80d11f44
JM		 1628#define SPR_Exxx_L1CSR1 (0x3F3)
1629#define SPR_440_DBDR (0x3F3)
1630#define SPR_LDSTDB (0x3F4)
bd928eba 1631#define SPR_750_TDCL (0x3F4)
80d11f44
JM		 1632#define SPR_40x_IAC1 (0x3F4)
1633#define SPR_MMUCSR0 (0x3F4)
1634#define SPR_DABR (0x3F5)
3fc6c082 1635#define DABR_MASK (~(target_ulong)0x7)
80d11f44
JM		 1636#define SPR_Exxx_BUCSR (0x3F5)
1637#define SPR_40x_IAC2 (0x3F5)
1638#define SPR_601_HID5 (0x3F5)
1639#define SPR_40x_DAC1 (0x3F6)
1640#define SPR_MSSCR0 (0x3F6)
1641#define SPR_970_HID5 (0x3F6)
1642#define SPR_MSSSR0 (0x3F7)
4e777442 1643#define SPR_MSSCR1 (0x3F7)
80d11f44
JM		 1644#define SPR_DABRX (0x3F7)
1645#define SPR_40x_DAC2 (0x3F7)
1646#define SPR_MMUCFG (0x3F7)
1647#define SPR_LDSTCR (0x3F8)
1648#define SPR_L2PMCR (0x3F8)
bd928eba 1649#define SPR_750FX_HID2 (0x3F8)
80d11f44
JM		 1650#define SPR_Exxx_L1FINV0 (0x3F8)
1651#define SPR_L2CR (0x3F9)
80d11f44 1652#define SPR_L3CR (0x3FA)
bd928eba 1653#define SPR_750_TDCH (0x3FA)
80d11f44
JM		 1654#define SPR_IABR2 (0x3FA)
1655#define SPR_40x_DCCR (0x3FA)
1656#define SPR_ICTC (0x3FB)
1657#define SPR_40x_ICCR (0x3FB)
1658#define SPR_THRM1 (0x3FC)
1659#define SPR_403_PBL1 (0x3FC)
1660#define SPR_SP (0x3FD)
1661#define SPR_THRM2 (0x3FD)
1662#define SPR_403_PBU1 (0x3FD)
1663#define SPR_604_HID13 (0x3FD)
1664#define SPR_LT (0x3FE)
1665#define SPR_THRM3 (0x3FE)
1666#define SPR_RCPU_FPECR (0x3FE)
1667#define SPR_403_PBL2 (0x3FE)
1668#define SPR_PIR (0x3FF)
1669#define SPR_403_PBU2 (0x3FF)
1670#define SPR_601_HID15 (0x3FF)
1671#define SPR_604_HID15 (0x3FF)
1672#define SPR_E500_SVR (0x3FF)
79aceca5 1673
84755ed5
AG		 1674/* Disable MAS Interrupt Updates for Hypervisor */
1675#define EPCR_DMIUH (1 << 22)
1676/* Disable Guest TLB Management Instructions */
1677#define EPCR_DGTMI (1 << 23)
1678/* Guest Interrupt Computation Mode */
1679#define EPCR_GICM (1 << 24)
1680/* Interrupt Computation Mode */
1681#define EPCR_ICM (1 << 25)
1682/* Disable Embedded Hypervisor Debug */
1683#define EPCR_DUVD (1 << 26)
1684/* Instruction Storage Interrupt Directed to Guest State */
1685#define EPCR_ISIGS (1 << 27)
1686/* Data Storage Interrupt Directed to Guest State */
1687#define EPCR_DSIGS (1 << 28)
1688/* Instruction TLB Error Interrupt Directed to Guest State */
1689#define EPCR_ITLBGS (1 << 29)
1690/* Data TLB Error Interrupt Directed to Guest State */
1691#define EPCR_DTLBGS (1 << 30)
1692/* External Input Interrupt Directed to Guest State */
1693#define EPCR_EXTGS (1 << 31)
1694
c29b735c
NF		 1695/*****************************************************************************/
1696/* PowerPC Instructions types definitions */
1697enum {
1698 PPC_NONE = 0x0000000000000000ULL,
1699 /* PowerPC base instructions set */
1700 PPC_INSNS_BASE = 0x0000000000000001ULL,
1701 /* integer operations instructions */
1702#define PPC_INTEGER PPC_INSNS_BASE
1703 /* flow control instructions */
1704#define PPC_FLOW PPC_INSNS_BASE
1705 /* virtual memory instructions */
1706#define PPC_MEM PPC_INSNS_BASE
1707 /* ld/st with reservation instructions */
1708#define PPC_RES PPC_INSNS_BASE
1709 /* spr/msr access instructions */
1710#define PPC_MISC PPC_INSNS_BASE
1711 /* Deprecated instruction sets */
1712 /* Original POWER instruction set */
1713 PPC_POWER = 0x0000000000000002ULL,
1714 /* POWER2 instruction set extension */
1715 PPC_POWER2 = 0x0000000000000004ULL,
1716 /* Power RTC support */
1717 PPC_POWER_RTC = 0x0000000000000008ULL,
1718 /* Power-to-PowerPC bridge (601) */
1719 PPC_POWER_BR = 0x0000000000000010ULL,
1720 /* 64 bits PowerPC instruction set */
1721 PPC_64B = 0x0000000000000020ULL,
1722 /* New 64 bits extensions (PowerPC 2.0x) */
1723 PPC_64BX = 0x0000000000000040ULL,
1724 /* 64 bits hypervisor extensions */
1725 PPC_64H = 0x0000000000000080ULL,
1726 /* New wait instruction (PowerPC 2.0x) */
1727 PPC_WAIT = 0x0000000000000100ULL,
1728 /* Time base mftb instruction */
1729 PPC_MFTB = 0x0000000000000200ULL,
1730
1731 /* Fixed-point unit extensions */
1732 /* PowerPC 602 specific */
1733 PPC_602_SPEC = 0x0000000000000400ULL,
1734 /* isel instruction */
1735 PPC_ISEL = 0x0000000000000800ULL,
1736 /* popcntb instruction */
1737 PPC_POPCNTB = 0x0000000000001000ULL,
1738 /* string load / store */
1739 PPC_STRING = 0x0000000000002000ULL,
1740
1741 /* Floating-point unit extensions */
1742 /* Optional floating point instructions */
1743 PPC_FLOAT = 0x0000000000010000ULL,
1744 /* New floating-point extensions (PowerPC 2.0x) */
1745 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1746 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1747 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1748 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1749 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1750 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1751 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1752
1753 /* Vector/SIMD extensions */
1754 /* Altivec support */
1755 PPC_ALTIVEC = 0x0000000001000000ULL,
1756 /* PowerPC 2.03 SPE extension */
1757 PPC_SPE = 0x0000000002000000ULL,
1758 /* PowerPC 2.03 SPE single-precision floating-point extension */
1759 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1760 /* PowerPC 2.03 SPE double-precision floating-point extension */
1761 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1762
1763 /* Optional memory control instructions */
1764 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1765 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1766 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1767 /* sync instruction */
1768 PPC_MEM_SYNC = 0x0000000080000000ULL,
1769 /* eieio instruction */
1770 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1771
1772 /* Cache control instructions */
1773 PPC_CACHE = 0x0000000200000000ULL,
1774 /* icbi instruction */
1775 PPC_CACHE_ICBI = 0x0000000400000000ULL,
8e33944f 1776 /* dcbz instruction */
c29b735c 1777 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
c29b735c
NF		 1778 /* dcba instruction */
1779 PPC_CACHE_DCBA = 0x0000002000000000ULL,
1780 /* Freescale cache locking instructions */
1781 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1782
1783 /* MMU related extensions */
1784 /* external control instructions */
1785 PPC_EXTERN = 0x0000010000000000ULL,
1786 /* segment register access instructions */
1787 PPC_SEGMENT = 0x0000020000000000ULL,
1788 /* PowerPC 6xx TLB management instructions */
1789 PPC_6xx_TLB = 0x0000040000000000ULL,
1790 /* PowerPC 74xx TLB management instructions */
1791 PPC_74xx_TLB = 0x0000080000000000ULL,
1792 /* PowerPC 40x TLB management instructions */
1793 PPC_40x_TLB = 0x0000100000000000ULL,
1794 /* segment register access instructions for PowerPC 64 "bridge" */
1795 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1796 /* SLB management */
1797 PPC_SLBI = 0x0000400000000000ULL,
1798
1799 /* Embedded PowerPC dedicated instructions */
1800 PPC_WRTEE = 0x0001000000000000ULL,
1801 /* PowerPC 40x exception model */
1802 PPC_40x_EXCP = 0x0002000000000000ULL,
1803 /* PowerPC 405 Mac instructions */
1804 PPC_405_MAC = 0x0004000000000000ULL,
1805 /* PowerPC 440 specific instructions */
1806 PPC_440_SPEC = 0x0008000000000000ULL,
1807 /* BookE (embedded) PowerPC specification */
1808 PPC_BOOKE = 0x0010000000000000ULL,
1809 /* mfapidi instruction */
1810 PPC_MFAPIDI = 0x0020000000000000ULL,
1811 /* tlbiva instruction */
1812 PPC_TLBIVA = 0x0040000000000000ULL,
1813 /* tlbivax instruction */
1814 PPC_TLBIVAX = 0x0080000000000000ULL,
1815 /* PowerPC 4xx dedicated instructions */
1816 PPC_4xx_COMMON = 0x0100000000000000ULL,
1817 /* PowerPC 40x ibct instructions */
1818 PPC_40x_ICBT = 0x0200000000000000ULL,
1819 /* rfmci is not implemented in all BookE PowerPC */
1820 PPC_RFMCI = 0x0400000000000000ULL,
1821 /* rfdi instruction */
1822 PPC_RFDI = 0x0800000000000000ULL,
1823 /* DCR accesses */
1824 PPC_DCR = 0x1000000000000000ULL,
1825 /* DCR extended accesse */
1826 PPC_DCRX = 0x2000000000000000ULL,
1827 /* user-mode DCR access, implemented in PowerPC 460 */
1828 PPC_DCRUX = 0x4000000000000000ULL,
eaabeef2
DG		 1829 /* popcntw and popcntd instructions */
1830 PPC_POPCNTWD = 0x8000000000000000ULL,
01662f3e 1831
02d4eae4
DG		 1832#define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
1833 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
1834 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
1835 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
1836 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
1837 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
1838 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
1839 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
1840 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
1841 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
1842 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
1843 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
1844 | PPC_CACHE | PPC_CACHE_ICBI \
8e33944f 1845 | PPC_CACHE_DCBZ \
02d4eae4
DG		 1846 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
1847 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
1848 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
1849 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
1850 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
1851 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
1852 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
1853 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
1854 | PPC_POPCNTWD)
1855
01662f3e
AG		 1856 /* extended type values */
1857
1858 /* BookE 2.06 PowerPC specification */
1859 PPC2_BOOKE206 = 0x0000000000000001ULL,
a7342588
DG		 1860 /* VSX (extensions to Altivec / VMX) */
1861 PPC2_VSX = 0x0000000000000002ULL,
1862 /* Decimal Floating Point (DFP) */
1863 PPC2_DFP = 0x0000000000000004ULL,
3f9f6a50
AG		 1864 /* Embedded.Processor Control */
1865 PPC2_PRCNTL = 0x0000000000000008ULL,
cd6e9320
TH		 1866 /* Byte-reversed, indexed, double-word load and store */
1867 PPC2_DBRX = 0x0000000000000010ULL,
02d4eae4 1868
cd6e9320 1869#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX)
c29b735c
NF		 1870};
1871
76a66253 1872/*****************************************************************************/
9a64fbe4
FB		 1873/* Memory access type :
1874 * may be needed for precise access rights control and precise exceptions.
1875 */
79aceca5 1876enum {
9a64fbe4
FB		 1877 /* 1 bit to define user level / supervisor access */
1878 ACCESS_USER = 0x00,
1879 ACCESS_SUPER = 0x01,
1880 /* Type of instruction that generated the access */
1881 ACCESS_CODE = 0x10, /* Code fetch access */
1882 ACCESS_INT = 0x20, /* Integer load/store access */
1883 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1884 ACCESS_RES = 0x40, /* load/store with reservation */
1885 ACCESS_EXT = 0x50, /* external access */
1886 ACCESS_CACHE = 0x60, /* Cache manipulation */
1887};
1888
47103572
JM		 1889/* Hardware interruption sources:
1890 * all those exception can be raised simulteaneously
1891 */
e9df014c
JM		 1892/* Input pins definitions */
1893enum {
1894 /* 6xx bus input pins */
24be5ae3
JM		 1895 PPC6xx_INPUT_HRESET = 0,
1896 PPC6xx_INPUT_SRESET = 1,
1897 PPC6xx_INPUT_CKSTP_IN = 2,
1898 PPC6xx_INPUT_MCP = 3,
1899 PPC6xx_INPUT_SMI = 4,
1900 PPC6xx_INPUT_INT = 5,
d68f1306
JM		 1901 PPC6xx_INPUT_TBEN = 6,
1902 PPC6xx_INPUT_WAKEUP = 7,
1903 PPC6xx_INPUT_NB,
24be5ae3
JM		 1904};
1905
1906enum {
e9df014c 1907 /* Embedded PowerPC input pins */
24be5ae3
JM		 1908 PPCBookE_INPUT_HRESET = 0,
1909 PPCBookE_INPUT_SRESET = 1,
1910 PPCBookE_INPUT_CKSTP_IN = 2,
1911 PPCBookE_INPUT_MCP = 3,
1912 PPCBookE_INPUT_SMI = 4,
1913 PPCBookE_INPUT_INT = 5,
1914 PPCBookE_INPUT_CINT = 6,
d68f1306 1915 PPCBookE_INPUT_NB,
24be5ae3
JM		 1916};
1917
9fdc60bf
AJ		 1918enum {
1919 /* PowerPC E500 input pins */
1920 PPCE500_INPUT_RESET_CORE = 0,
1921 PPCE500_INPUT_MCK = 1,
1922 PPCE500_INPUT_CINT = 3,
1923 PPCE500_INPUT_INT = 4,
1924 PPCE500_INPUT_DEBUG = 6,
1925 PPCE500_INPUT_NB,
1926};
1927
a750fc0b 1928enum {
4e290a0b
JM		 1929 /* PowerPC 40x input pins */
1930 PPC40x_INPUT_RESET_CORE = 0,
1931 PPC40x_INPUT_RESET_CHIP = 1,
1932 PPC40x_INPUT_RESET_SYS = 2,
1933 PPC40x_INPUT_CINT = 3,
1934 PPC40x_INPUT_INT = 4,
1935 PPC40x_INPUT_HALT = 5,
1936 PPC40x_INPUT_DEBUG = 6,
1937 PPC40x_INPUT_NB,
e9df014c
JM		 1938};
1939
b4095fed
JM		 1940enum {
1941 /* RCPU input pins */
1942 PPCRCPU_INPUT_PORESET = 0,
1943 PPCRCPU_INPUT_HRESET = 1,
1944 PPCRCPU_INPUT_SRESET = 2,
1945 PPCRCPU_INPUT_IRQ0 = 3,
1946 PPCRCPU_INPUT_IRQ1 = 4,
1947 PPCRCPU_INPUT_IRQ2 = 5,
1948 PPCRCPU_INPUT_IRQ3 = 6,
1949 PPCRCPU_INPUT_IRQ4 = 7,
1950 PPCRCPU_INPUT_IRQ5 = 8,
1951 PPCRCPU_INPUT_IRQ6 = 9,
1952 PPCRCPU_INPUT_IRQ7 = 10,
1953 PPCRCPU_INPUT_NB,
1954};
1955
00af685f 1956#if defined(TARGET_PPC64)
d0dfae6e
JM		 1957enum {
1958 /* PowerPC 970 input pins */
1959 PPC970_INPUT_HRESET = 0,
1960 PPC970_INPUT_SRESET = 1,
1961 PPC970_INPUT_CKSTP = 2,
1962 PPC970_INPUT_TBEN = 3,
1963 PPC970_INPUT_MCP = 4,
1964 PPC970_INPUT_INT = 5,
1965 PPC970_INPUT_THINT = 6,
7b62a955 1966 PPC970_INPUT_NB,
9d52e907
DG		 1967};
1968
1969enum {
1970 /* POWER7 input pins */
1971 POWER7_INPUT_INT = 0,
1972 /* POWER7 probably has other inputs, but we don't care about them
1973 * for any existing machine. We can wire these up when we need
1974 * them */
1975 POWER7_INPUT_NB,
d0dfae6e 1976};
00af685f 1977#endif
d0dfae6e 1978
e9df014c 1979/* Hardware exceptions definitions */
47103572 1980enum {
e9df014c 1981 /* External hardware exception sources */
e1833e1f 1982 PPC_INTERRUPT_RESET = 0, /* Reset exception */
d68f1306
JM		 1983 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
1984 PPC_INTERRUPT_MCK, /* Machine check exception */
1985 PPC_INTERRUPT_EXT, /* External interrupt */
1986 PPC_INTERRUPT_SMI, /* System management interrupt */
1987 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
1988 PPC_INTERRUPT_DEBUG, /* External debug exception */
1989 PPC_INTERRUPT_THERM, /* Thermal exception */
e9df014c 1990 /* Internal hardware exception sources */
d68f1306
JM		 1991 PPC_INTERRUPT_DECR, /* Decrementer exception */
1992 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
1993 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
1994 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
1995 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
1996 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
1997 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
1998 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
47103572
JM		 1999};
2000
fc0b2c0f
AG		 2001/* CPU should be reset next, restart from scratch afterwards */
2002#define CPU_INTERRUPT_RESET CPU_INTERRUPT_TGT_INT_0
2003
9a64fbe4
FB		 2004/*****************************************************************************/
2005
da91a00f
RH		 2006static inline target_ulong cpu_read_xer(CPUPPCState *env)
2007{
2008 return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA);
2009}
2010
2011static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
2012{
2013 env->so = (xer >> XER_SO) & 1;
2014 env->ov = (xer >> XER_OV) & 1;
2015 env->ca = (xer >> XER_CA) & 1;
2016 env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
2017}
2018
1328c2bf 2019static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
6b917547
AL		 2020 target_ulong *cs_base, int *flags)
2021{
2022 *pc = env->nip;
2023 *cs_base = 0;
2024 *flags = env->hflags;
2025}
2026
1328c2bf 2027static inline void cpu_set_tls(CPUPPCState *env, target_ulong newtls)
174c80d5
NF		 2028{
2029#if defined(TARGET_PPC64)
2030 /* The kernel checks TIF_32BIT here; we don't support loading 32-bit
2031 binaries on PPC64 yet. */
2032 env->gpr[13] = newtls;
2033#else
2034 env->gpr[2] = newtls;
2035#endif
2036}
2037
01662f3e 2038#if !defined(CONFIG_USER_ONLY)
1328c2bf 2039static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
01662f3e 2040{
d1e256fe 2041 uintptr_t tlbml = (uintptr_t)tlbm;
1c53accc 2042 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
01662f3e 2043
1c53accc 2044 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
01662f3e
AG		 2045}
2046
1328c2bf 2047static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
01662f3e
AG		 2048{
2049 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2050 int r = tlbncfg & TLBnCFG_N_ENTRY;
2051 return r;
2052}
2053
1328c2bf 2054static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
01662f3e
AG		 2055{
2056 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2057 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2058 return r;
2059}
2060
1328c2bf 2061static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
01662f3e 2062{
d1e256fe 2063 int id = booke206_tlbm_id(env, tlbm);
01662f3e
AG		 2064 int end = 0;
2065 int i;
2066
2067 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2068 end += booke206_tlb_size(env, i);
2069 if (id < end) {
2070 return i;
2071 }
2072 }
2073
2074 cpu_abort(env, "Unknown TLBe: %d\n", id);
2075 return 0;
2076}
2077
1328c2bf 2078static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
01662f3e 2079{
d1e256fe
AG		 2080 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2081 int tlbid = booke206_tlbm_id(env, tlb);
01662f3e
AG		 2082 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2083}
2084
1328c2bf 2085static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
01662f3e
AG		 2086 target_ulong ea, int way)
2087{
2088 int r;
2089 uint32_t ways = booke206_tlb_ways(env, tlbn);
2090 int ways_bits = ffs(ways) - 1;
2091 int tlb_bits = ffs(booke206_tlb_size(env, tlbn)) - 1;
2092 int i;
2093
2094 way &= ways - 1;
2095 ea >>= MAS2_EPN_SHIFT;
2096 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2097 r = (ea << ways_bits) | way;
2098
3f162d11
AG		 2099 if (r >= booke206_tlb_size(env, tlbn)) {
2100 return NULL;
2101 }
2102
01662f3e
AG		 2103 /* bump up to tlbn index */
2104 for (i = 0; i < tlbn; i++) {
2105 r += booke206_tlb_size(env, i);
2106 }
2107
1c53accc 2108 return &env->tlb.tlbm[r];
01662f3e
AG		 2109}
2110
a1ef618a 2111/* returns bitmap of supported page sizes for a given TLB */
1328c2bf 2112static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
a1ef618a
AG		 2113{
2114 bool mav2 = false;
2115 uint32_t ret = 0;
2116
2117 if (mav2) {
2118 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2119 } else {
2120 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2121 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2122 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2123 int i;
2124 for (i = min; i <= max; i++) {
2125 ret |= (1 << (i << 1));
2126 }
2127 }
2128
2129 return ret;
2130}
2131
01662f3e
AG		 2132#endif
2133
e42a61f1
AG		 2134static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2135{
2136 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2137 return msr & (1ULL << MSR_CM);
2138 }
2139
2140 return msr & (1ULL << MSR_SF);
2141}
2142
1b14670a 2143extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
d569956e 2144
3993c6bd 2145static inline bool cpu_has_work(CPUState *cpu)
f081c76c 2146{
259186a7
AF		 2147 PowerPCCPU *ppc_cpu = POWERPC_CPU(cpu);
2148 CPUPPCState *env = &ppc_cpu->env;
3993c6bd 2149
259186a7 2150 return msr_ee && (cpu->interrupt_request & CPU_INTERRUPT_HARD);
f081c76c
BS		 2151}
2152
022c62cb 2153#include "exec/exec-all.h"
f081c76c 2154
1328c2bf 2155static inline void cpu_pc_from_tb(CPUPPCState *env, TranslationBlock *tb)
f081c76c
BS		 2156{
2157 env->nip = tb->pc;
2158}
2159
1328c2bf 2160void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
bebabbc7 2161
79aceca5 2162#endif /* !defined (__CPU_PPC_H__) */
Qemu copy for testing