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79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation cpu definitions for qemu. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
79aceca5 FB |
5 | * |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | #if !defined (__CPU_PPC_H__) | |
21 | #define __CPU_PPC_H__ | |
22 | ||
3fc6c082 | 23 | #include "config.h" |
de270b3c | 24 | #include <inttypes.h> |
3fc6c082 | 25 | |
35cdaad6 | 26 | #if !defined(TARGET_PPCEMB) |
51789c41 JM |
27 | #if defined(TARGET_PPC64) || (HOST_LONG_BITS >= 64) |
28 | /* When using 64 bits temporary registers, | |
29 | * we can use 64 bits GPR with no extra cost | |
30 | */ | |
35cdaad6 JM |
31 | #define TARGET_PPCEMB |
32 | #endif | |
51789c41 JM |
33 | #endif |
34 | ||
76a66253 JM |
35 | #if defined (TARGET_PPC64) |
36 | typedef uint64_t ppc_gpr_t; | |
37 | #define TARGET_LONG_BITS 64 | |
0487d6a8 | 38 | #define TARGET_GPR_BITS 64 |
76a66253 | 39 | #define REGX "%016" PRIx64 |
35cdaad6 JM |
40 | #define TARGET_PAGE_BITS 12 |
41 | #elif defined(TARGET_PPCEMB) | |
e96efcfc JM |
42 | /* e500v2 have 36 bits physical address space */ |
43 | #define TARGET_PHYS_ADDR_BITS 64 | |
76a66253 JM |
44 | /* GPR are 64 bits: used by vector extension */ |
45 | typedef uint64_t ppc_gpr_t; | |
3cf1e035 | 46 | #define TARGET_LONG_BITS 32 |
0487d6a8 | 47 | #define TARGET_GPR_BITS 64 |
1b9eb036 | 48 | #define REGX "%016" PRIx64 |
35cdaad6 JM |
49 | /* Pages can be 1 kB small */ |
50 | #define TARGET_PAGE_BITS 10 | |
76a66253 JM |
51 | #else |
52 | typedef uint32_t ppc_gpr_t; | |
53 | #define TARGET_LONG_BITS 32 | |
0487d6a8 | 54 | #define TARGET_GPR_BITS 32 |
76a66253 | 55 | #define REGX "%08" PRIx32 |
35cdaad6 | 56 | #define TARGET_PAGE_BITS 12 |
76a66253 | 57 | #endif |
3cf1e035 | 58 | |
79aceca5 FB |
59 | #include "cpu-defs.h" |
60 | ||
e96efcfc JM |
61 | #define ADDRX TARGET_FMT_lx |
62 | #define PADDRX TARGET_FMT_plx | |
63 | ||
79aceca5 FB |
64 | #include <setjmp.h> |
65 | ||
4ecc3190 FB |
66 | #include "softfloat.h" |
67 | ||
1fddef4b FB |
68 | #define TARGET_HAS_ICE 1 |
69 | ||
76a66253 JM |
70 | #if defined (TARGET_PPC64) |
71 | #define ELF_MACHINE EM_PPC64 | |
72 | #else | |
73 | #define ELF_MACHINE EM_PPC | |
74 | #endif | |
9042c0e2 | 75 | |
fdabc366 FB |
76 | /* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC |
77 | * have different cache line sizes | |
78 | */ | |
79 | #define ICACHE_LINE_SIZE 32 | |
80 | #define DCACHE_LINE_SIZE 32 | |
81 | ||
82 | /* XXX: put this in a common place */ | |
83 | #define likely(x) __builtin_expect(!!(x), 1) | |
76a66253 | 84 | #define unlikely(x) __builtin_expect(!!(x), 0) |
fdabc366 | 85 | |
3fc6c082 FB |
86 | /*****************************************************************************/ |
87 | /* PVR definitions for most known PowerPC */ | |
88 | enum { | |
89 | /* PowerPC 401 cores */ | |
90 | CPU_PPC_401A1 = 0x00210000, | |
91 | CPU_PPC_401B2 = 0x00220000, | |
92 | CPU_PPC_401C2 = 0x00230000, | |
93 | CPU_PPC_401D2 = 0x00240000, | |
94 | CPU_PPC_401E2 = 0x00250000, | |
95 | CPU_PPC_401F2 = 0x00260000, | |
96 | CPU_PPC_401G2 = 0x00270000, | |
76a66253 JM |
97 | #define CPU_PPC_401 CPU_PPC_401G2 |
98 | CPU_PPC_IOP480 = 0x40100000, /* 401B2 ? */ | |
99 | CPU_PPC_COBRA = 0x10100000, /* IBM Processor for Network Resources */ | |
3fc6c082 | 100 | /* PowerPC 403 cores */ |
76a66253 | 101 | CPU_PPC_403GA = 0x00200011, |
3fc6c082 FB |
102 | CPU_PPC_403GB = 0x00200100, |
103 | CPU_PPC_403GC = 0x00200200, | |
104 | CPU_PPC_403GCX = 0x00201400, | |
76a66253 | 105 | #define CPU_PPC_403 CPU_PPC_403GCX |
3fc6c082 | 106 | /* PowerPC 405 cores */ |
76a66253 JM |
107 | CPU_PPC_405CR = 0x40110145, |
108 | #define CPU_PPC_405GP CPU_PPC_405CR | |
109 | CPU_PPC_405EP = 0x51210950, | |
110 | CPU_PPC_405GPR = 0x50910951, | |
3fc6c082 FB |
111 | CPU_PPC_405D2 = 0x20010000, |
112 | CPU_PPC_405D4 = 0x41810000, | |
76a66253 JM |
113 | #define CPU_PPC_405 CPU_PPC_405D4 |
114 | CPU_PPC_NPE405H = 0x414100C0, | |
115 | CPU_PPC_NPE405H2 = 0x41410140, | |
116 | CPU_PPC_NPE405L = 0x416100C0, | |
117 | /* XXX: missing 405LP, LC77700 */ | |
118 | /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */ | |
119 | #if 0 | |
120 | CPU_PPC_STB01000 = xxx, | |
121 | #endif | |
3fc6c082 | 122 | #if 0 |
76a66253 JM |
123 | CPU_PPC_STB01010 = xxx, |
124 | #endif | |
125 | #if 0 | |
126 | CPU_PPC_STB0210 = xxx, | |
3fc6c082 FB |
127 | #endif |
128 | CPU_PPC_STB03 = 0x40310000, | |
129 | #if 0 | |
76a66253 | 130 | CPU_PPC_STB043 = xxx, |
3fc6c082 | 131 | #endif |
76a66253 JM |
132 | #if 0 |
133 | CPU_PPC_STB045 = xxx, | |
134 | #endif | |
135 | CPU_PPC_STB25 = 0x51510950, | |
3fc6c082 FB |
136 | #if 0 |
137 | CPU_PPC_STB130 = xxx, | |
138 | #endif | |
76a66253 JM |
139 | /* Xilinx cores */ |
140 | CPU_PPC_X2VP4 = 0x20010820, | |
141 | #define CPU_PPC_X2VP7 CPU_PPC_X2VP4 | |
142 | CPU_PPC_X2VP20 = 0x20010860, | |
143 | #define CPU_PPC_X2VP50 CPU_PPC_X2VP20 | |
3fc6c082 | 144 | /* PowerPC 440 cores */ |
76a66253 JM |
145 | CPU_PPC_440EP = 0x422218D3, |
146 | #define CPU_PPC_440GR CPU_PPC_440EP | |
147 | CPU_PPC_440GP = 0x40120481, | |
148 | CPU_PPC_440GX = 0x51B21850, | |
149 | CPU_PPC_440GXc = 0x51B21892, | |
150 | CPU_PPC_440GXf = 0x51B21894, | |
151 | CPU_PPC_440SP = 0x53221850, | |
152 | CPU_PPC_440SP2 = 0x53221891, | |
153 | CPU_PPC_440SPE = 0x53421890, | |
154 | /* XXX: missing 440GRX */ | |
155 | /* PowerPC 460 cores - TODO */ | |
156 | /* PowerPC MPC 5xx cores */ | |
157 | CPU_PPC_5xx = 0x00020020, | |
158 | /* PowerPC MPC 8xx cores (aka PowerQUICC) */ | |
3fc6c082 | 159 | CPU_PPC_8xx = 0x00500000, |
76a66253 JM |
160 | /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */ |
161 | CPU_PPC_82xx_HIP3 = 0x00810101, | |
162 | CPU_PPC_82xx_HIP4 = 0x80811014, | |
163 | CPU_PPC_827x = 0x80822013, | |
164 | /* eCores */ | |
165 | CPU_PPC_e200 = 0x81120000, | |
166 | CPU_PPC_e500v110 = 0x80200010, | |
167 | CPU_PPC_e500v120 = 0x80200020, | |
168 | CPU_PPC_e500v210 = 0x80210010, | |
169 | CPU_PPC_e500v220 = 0x80210020, | |
170 | #define CPU_PPC_e500 CPU_PPC_e500v220 | |
171 | CPU_PPC_e600 = 0x80040010, | |
3fc6c082 | 172 | /* PowerPC 6xx cores */ |
76a66253 JM |
173 | CPU_PPC_601 = 0x00010001, |
174 | CPU_PPC_602 = 0x00050100, | |
175 | CPU_PPC_603 = 0x00030100, | |
176 | CPU_PPC_603E = 0x00060101, | |
177 | CPU_PPC_603P = 0x00070000, | |
178 | CPU_PPC_603E7v = 0x00070100, | |
179 | CPU_PPC_603E7v2 = 0x00070201, | |
180 | CPU_PPC_603E7 = 0x00070200, | |
181 | CPU_PPC_603R = 0x00071201, | |
182 | CPU_PPC_G2 = 0x00810011, | |
183 | CPU_PPC_G2H4 = 0x80811010, | |
184 | CPU_PPC_G2gp = 0x80821010, | |
185 | CPU_PPC_G2ls = 0x90810010, | |
186 | CPU_PPC_G2LE = 0x80820010, | |
187 | CPU_PPC_G2LEgp = 0x80822010, | |
188 | CPU_PPC_G2LEls = 0xA0822010, | |
3fc6c082 | 189 | CPU_PPC_604 = 0x00040000, |
76a66253 JM |
190 | CPU_PPC_604E = 0x00090100, /* Also 2110 & 2120 */ |
191 | CPU_PPC_604R = 0x000a0101, | |
3fc6c082 FB |
192 | /* PowerPC 74x/75x cores (aka G3) */ |
193 | CPU_PPC_74x = 0x00080000, | |
76a66253 JM |
194 | CPU_PPC_740E = 0x00080100, |
195 | CPU_PPC_750E = 0x00080200, | |
196 | CPU_PPC_755_10 = 0x00083100, | |
197 | CPU_PPC_755_11 = 0x00083101, | |
198 | CPU_PPC_755_20 = 0x00083200, | |
199 | CPU_PPC_755D = 0x00083202, | |
200 | CPU_PPC_755E = 0x00083203, | |
201 | #define CPU_PPC_755 CPU_PPC_755E | |
3fc6c082 | 202 | CPU_PPC_74xP = 0x10080000, |
76a66253 JM |
203 | CPU_PPC_750CXE21 = 0x00082201, |
204 | CPU_PPC_750CXE22 = 0x00082212, | |
205 | CPU_PPC_750CXE23 = 0x00082203, | |
3fc6c082 FB |
206 | CPU_PPC_750CXE24 = 0x00082214, |
207 | CPU_PPC_750CXE24b = 0x00083214, | |
208 | CPU_PPC_750CXE31 = 0x00083211, | |
209 | CPU_PPC_750CXE31b = 0x00083311, | |
210 | #define CPU_PPC_750CXE CPU_PPC_750CXE31b | |
76a66253 JM |
211 | CPU_PPC_750CXR = 0x00083410, |
212 | CPU_PPC_750FX10 = 0x70000100, | |
213 | CPU_PPC_750FX20 = 0x70000200, | |
214 | CPU_PPC_750FX21 = 0x70000201, | |
215 | CPU_PPC_750FX22 = 0x70000202, | |
216 | CPU_PPC_750FX23 = 0x70000203, | |
217 | #define CPU_PPC_750FX CPU_PPC_750FX23 | |
218 | CPU_PPC_750FL = 0x700A0203, | |
219 | CPU_PPC_750GX10 = 0x70020100, | |
220 | CPU_PPC_750GX11 = 0x70020101, | |
221 | CPU_PPC_750GX12 = 0x70020102, | |
222 | #define CPU_PPC_750GX CPU_PPC_750GX12 | |
223 | CPU_PPC_750GL = 0x70020102, | |
224 | CPU_PPC_750L30 = 0x00088300, | |
225 | CPU_PPC_750L32 = 0x00088302, | |
226 | CPU_PPC_750CL = 0x00087200, | |
3fc6c082 | 227 | /* PowerPC 74xx cores (aka G4) */ |
76a66253 JM |
228 | CPU_PPC_7400 = 0x000C0100, |
229 | CPU_PPC_7410C = 0x800C1102, | |
230 | CPU_PPC_7410D = 0x800C1103, | |
231 | CPU_PPC_7410E = 0x800C1104, | |
232 | CPU_PPC_7441 = 0x80000210, | |
233 | CPU_PPC_7445 = 0x80010100, | |
234 | CPU_PPC_7447 = 0x80020100, | |
235 | CPU_PPC_7447A = 0x80030101, | |
236 | CPU_PPC_7448 = 0x80040100, | |
237 | CPU_PPC_7450 = 0x80000200, | |
238 | CPU_PPC_7450b = 0x80000201, | |
3fc6c082 | 239 | CPU_PPC_7451 = 0x80000203, |
76a66253 JM |
240 | CPU_PPC_7451G = 0x80000210, |
241 | CPU_PPC_7455 = 0x80010201, | |
242 | CPU_PPC_7455F = 0x80010303, | |
243 | CPU_PPC_7455G = 0x80010304, | |
244 | CPU_PPC_7457 = 0x80020101, | |
245 | CPU_PPC_7457C = 0x80020102, | |
3fc6c082 FB |
246 | CPU_PPC_7457A = 0x80030000, |
247 | /* 64 bits PowerPC */ | |
248 | CPU_PPC_620 = 0x00140000, | |
249 | CPU_PPC_630 = 0x00400000, | |
250 | CPU_PPC_631 = 0x00410000, | |
251 | CPU_PPC_POWER4 = 0x00350000, | |
252 | CPU_PPC_POWER4P = 0x00380000, | |
253 | CPU_PPC_POWER5 = 0x003A0000, | |
254 | CPU_PPC_POWER5P = 0x003B0000, | |
255 | CPU_PPC_970 = 0x00390000, | |
76a66253 JM |
256 | CPU_PPC_970FX10 = 0x00391100, |
257 | CPU_PPC_970FX20 = 0x003C0200, | |
258 | CPU_PPC_970FX21 = 0x003C0201, | |
259 | CPU_PPC_970FX30 = 0x003C0300, | |
260 | CPU_PPC_970FX31 = 0x003C0301, | |
261 | #define CPU_PPC_970FX CPU_PPC_970FX31 | |
262 | CPU_PPC_970MP10 = 0x00440100, | |
263 | CPU_PPC_970MP11 = 0x00440101, | |
264 | #define CPU_PPC_970MP CPU_PPC_970MP11 | |
265 | CPU_PPC_CELL10 = 0x00700100, | |
266 | CPU_PPC_CELL20 = 0x00700400, | |
267 | CPU_PPC_CELL30 = 0x00700500, | |
268 | CPU_PPC_CELL31 = 0x00700501, | |
269 | #define CPU_PPC_CELL32 CPU_PPC_CELL31 | |
270 | #define CPU_PPC_CELL CPU_PPC_CELL32 | |
3fc6c082 FB |
271 | CPU_PPC_RS64 = 0x00330000, |
272 | CPU_PPC_RS64II = 0x00340000, | |
273 | CPU_PPC_RS64III = 0x00360000, | |
274 | CPU_PPC_RS64IV = 0x00370000, | |
275 | /* Original POWER */ | |
276 | /* XXX: should be POWER (RIOS), RSC3308, RSC4608, | |
277 | * POWER2 (RIOS2) & RSC2 (P2SC) here | |
278 | */ | |
279 | #if 0 | |
280 | CPU_POWER = xxx, | |
281 | #endif | |
282 | #if 0 | |
283 | CPU_POWER2 = xxx, | |
284 | #endif | |
285 | }; | |
286 | ||
76a66253 | 287 | /* System version register (used on MPC 8xxx) */ |
3fc6c082 FB |
288 | enum { |
289 | PPC_SVR_8540 = 0x80300000, | |
76a66253 JM |
290 | PPC_SVR_8541E = 0x807A0010, |
291 | PPC_SVR_8543v10 = 0x80320010, | |
292 | PPC_SVR_8543v11 = 0x80320011, | |
293 | PPC_SVR_8543v20 = 0x80320020, | |
294 | PPC_SVR_8543Ev10 = 0x803A0010, | |
295 | PPC_SVR_8543Ev11 = 0x803A0011, | |
296 | PPC_SVR_8543Ev20 = 0x803A0020, | |
297 | PPC_SVR_8545 = 0x80310220, | |
298 | PPC_SVR_8545E = 0x80390220, | |
299 | PPC_SVR_8547E = 0x80390120, | |
300 | PPC_SCR_8548v10 = 0x80310010, | |
301 | PPC_SCR_8548v11 = 0x80310011, | |
302 | PPC_SCR_8548v20 = 0x80310020, | |
303 | PPC_SVR_8548Ev10 = 0x80390010, | |
304 | PPC_SVR_8548Ev11 = 0x80390011, | |
305 | PPC_SVR_8548Ev20 = 0x80390020, | |
306 | PPC_SVR_8555E = 0x80790010, | |
307 | PPC_SVR_8560v10 = 0x80700010, | |
308 | PPC_SVR_8560v20 = 0x80700020, | |
3fc6c082 FB |
309 | }; |
310 | ||
311 | /*****************************************************************************/ | |
9a64fbe4 FB |
312 | /* Instruction types */ |
313 | enum { | |
3fc6c082 FB |
314 | PPC_NONE = 0x00000000, |
315 | /* integer operations instructions */ | |
316 | /* flow control instructions */ | |
317 | /* virtual memory instructions */ | |
318 | /* ld/st with reservation instructions */ | |
319 | /* cache control instructions */ | |
320 | /* spr/msr access instructions */ | |
0487d6a8 | 321 | PPC_INSNS_BASE = 0x0000000000000001ULL, |
3fc6c082 FB |
322 | #define PPC_INTEGER PPC_INSNS_BASE |
323 | #define PPC_FLOW PPC_INSNS_BASE | |
324 | #define PPC_MEM PPC_INSNS_BASE | |
325 | #define PPC_RES PPC_INSNS_BASE | |
326 | #define PPC_CACHE PPC_INSNS_BASE | |
327 | #define PPC_MISC PPC_INSNS_BASE | |
328 | /* floating point operations instructions */ | |
0487d6a8 | 329 | PPC_FLOAT = 0x0000000000000002ULL, |
3fc6c082 | 330 | /* more floating point operations instructions */ |
0487d6a8 | 331 | PPC_FLOAT_EXT = 0x0000000000000004ULL, |
3fc6c082 | 332 | /* external control instructions */ |
0487d6a8 | 333 | PPC_EXTERN = 0x0000000000000008ULL, |
3fc6c082 | 334 | /* segment register access instructions */ |
0487d6a8 | 335 | PPC_SEGMENT = 0x0000000000000010ULL, |
3fc6c082 | 336 | /* Optional cache control instructions */ |
0487d6a8 | 337 | PPC_CACHE_OPT = 0x0000000000000020ULL, |
3fc6c082 | 338 | /* Optional floating point op instructions */ |
0487d6a8 | 339 | PPC_FLOAT_OPT = 0x0000000000000040ULL, |
3fc6c082 | 340 | /* Optional memory control instructions */ |
0487d6a8 JM |
341 | PPC_MEM_TLBIA = 0x0000000000000080ULL, |
342 | PPC_MEM_TLBIE = 0x0000000000000100ULL, | |
343 | PPC_MEM_TLBSYNC = 0x0000000000000200ULL, | |
3fc6c082 | 344 | /* eieio & sync */ |
0487d6a8 | 345 | PPC_MEM_SYNC = 0x0000000000000400ULL, |
3fc6c082 | 346 | /* PowerPC 6xx TLB management instructions */ |
0487d6a8 | 347 | PPC_6xx_TLB = 0x0000000000000800ULL, |
3fc6c082 | 348 | /* Altivec support */ |
0487d6a8 | 349 | PPC_ALTIVEC = 0x0000000000001000ULL, |
3fc6c082 | 350 | /* Time base support */ |
0487d6a8 | 351 | PPC_TB = 0x0000000000002000ULL, |
3fc6c082 | 352 | /* Embedded PowerPC dedicated instructions */ |
0487d6a8 | 353 | PPC_EMB_COMMON = 0x0000000000004000ULL, |
3fc6c082 | 354 | /* PowerPC 40x exception model */ |
0487d6a8 | 355 | PPC_40x_EXCP = 0x0000000000008000ULL, |
3fc6c082 | 356 | /* PowerPC 40x specific instructions */ |
0487d6a8 | 357 | PPC_40x_SPEC = 0x0000000000010000ULL, |
3fc6c082 | 358 | /* PowerPC 405 Mac instructions */ |
0487d6a8 | 359 | PPC_405_MAC = 0x0000000000020000ULL, |
3fc6c082 | 360 | /* PowerPC 440 specific instructions */ |
0487d6a8 | 361 | PPC_440_SPEC = 0x0000000000040000ULL, |
3fc6c082 FB |
362 | /* Specific extensions */ |
363 | /* Power-to-PowerPC bridge (601) */ | |
0487d6a8 | 364 | PPC_POWER_BR = 0x0000000000080000ULL, |
3fc6c082 | 365 | /* PowerPC 602 specific */ |
0487d6a8 | 366 | PPC_602_SPEC = 0x0000000000100000ULL, |
3fc6c082 FB |
367 | /* Deprecated instructions */ |
368 | /* Original POWER instruction set */ | |
0487d6a8 | 369 | PPC_POWER = 0x0000000000200000ULL, |
3fc6c082 | 370 | /* POWER2 instruction set extension */ |
0487d6a8 | 371 | PPC_POWER2 = 0x0000000000400000ULL, |
3fc6c082 | 372 | /* Power RTC support */ |
0487d6a8 | 373 | PPC_POWER_RTC = 0x0000000000800000ULL, |
3fc6c082 FB |
374 | /* 64 bits PowerPC instructions */ |
375 | /* 64 bits PowerPC instruction set */ | |
0487d6a8 | 376 | PPC_64B = 0x0000000001000000ULL, |
3fc6c082 | 377 | /* 64 bits hypervisor extensions */ |
0487d6a8 | 378 | PPC_64H = 0x0000000002000000ULL, |
3fc6c082 | 379 | /* 64 bits PowerPC "bridge" features */ |
0487d6a8 | 380 | PPC_64_BRIDGE = 0x0000000004000000ULL, |
76a66253 | 381 | /* BookE (embedded) PowerPC specification */ |
0487d6a8 | 382 | PPC_BOOKE = 0x0000000008000000ULL, |
76a66253 | 383 | /* eieio */ |
0487d6a8 | 384 | PPC_MEM_EIEIO = 0x0000000010000000ULL, |
76a66253 | 385 | /* e500 vector instructions */ |
0487d6a8 | 386 | PPC_E500_VECTOR = 0x0000000020000000ULL, |
76a66253 | 387 | /* PowerPC 4xx dedicated instructions */ |
0487d6a8 | 388 | PPC_4xx_COMMON = 0x0000000040000000ULL, |
d9bce9d9 | 389 | /* PowerPC 2.03 specification extensions */ |
0487d6a8 JM |
390 | PPC_203 = 0x0000000080000000ULL, |
391 | /* PowerPC 2.03 SPE extension */ | |
392 | PPC_SPE = 0x0000000100000000ULL, | |
393 | /* PowerPC 2.03 SPE floating-point extension */ | |
394 | PPC_SPEFPU = 0x0000000200000000ULL, | |
426613db JM |
395 | /* SLB management */ |
396 | PPC_SLBI = 0x0000000400000000ULL, | |
9a64fbe4 | 397 | }; |
79aceca5 | 398 | |
3fc6c082 FB |
399 | /* CPU run-time flags (MMU and exception model) */ |
400 | enum { | |
401 | /* MMU model */ | |
d0dfae6e | 402 | PPC_FLAGS_MMU_MASK = 0x000000FF, |
3fc6c082 | 403 | /* Standard 32 bits PowerPC MMU */ |
d0dfae6e | 404 | PPC_FLAGS_MMU_32B = 0x00000000, |
3fc6c082 | 405 | /* Standard 64 bits PowerPC MMU */ |
d0dfae6e | 406 | PPC_FLAGS_MMU_64B = 0x00000001, |
3fc6c082 | 407 | /* PowerPC 601 MMU */ |
d0dfae6e | 408 | PPC_FLAGS_MMU_601 = 0x00000002, |
3fc6c082 | 409 | /* PowerPC 6xx MMU with software TLB */ |
d0dfae6e | 410 | PPC_FLAGS_MMU_SOFT_6xx = 0x00000003, |
3fc6c082 | 411 | /* PowerPC 4xx MMU with software TLB */ |
d0dfae6e | 412 | PPC_FLAGS_MMU_SOFT_4xx = 0x00000004, |
3fc6c082 | 413 | /* PowerPC 403 MMU */ |
d0dfae6e JM |
414 | PPC_FLAGS_MMU_403 = 0x00000005, |
415 | /* BookE FSL MMU model */ | |
416 | PPC_FLAGS_MMU_BOOKE_FSL = 0x00000006, | |
d9bce9d9 | 417 | /* BookE MMU model */ |
d0dfae6e JM |
418 | PPC_FLAGS_MMU_BOOKE = 0x00000007, |
419 | /* 64 bits "bridge" PowerPC MMU */ | |
420 | PPC_FLAGS_MMU_64BRIDGE = 0x00000008, | |
3fc6c082 | 421 | /* Exception model */ |
d0dfae6e | 422 | PPC_FLAGS_EXCP_MASK = 0x0000FF00, |
3fc6c082 | 423 | /* Standard PowerPC exception model */ |
d0dfae6e | 424 | PPC_FLAGS_EXCP_STD = 0x00000000, |
3fc6c082 | 425 | /* PowerPC 40x exception model */ |
d0dfae6e | 426 | PPC_FLAGS_EXCP_40x = 0x00000100, |
3fc6c082 | 427 | /* PowerPC 601 exception model */ |
d0dfae6e | 428 | PPC_FLAGS_EXCP_601 = 0x00000200, |
3fc6c082 | 429 | /* PowerPC 602 exception model */ |
d0dfae6e | 430 | PPC_FLAGS_EXCP_602 = 0x00000300, |
3fc6c082 | 431 | /* PowerPC 603 exception model */ |
d0dfae6e | 432 | PPC_FLAGS_EXCP_603 = 0x00000400, |
3fc6c082 | 433 | /* PowerPC 604 exception model */ |
d0dfae6e | 434 | PPC_FLAGS_EXCP_604 = 0x00000500, |
3fc6c082 | 435 | /* PowerPC 7x0 exception model */ |
d0dfae6e | 436 | PPC_FLAGS_EXCP_7x0 = 0x00000600, |
3fc6c082 | 437 | /* PowerPC 7x5 exception model */ |
d0dfae6e | 438 | PPC_FLAGS_EXCP_7x5 = 0x00000700, |
3fc6c082 | 439 | /* PowerPC 74xx exception model */ |
d0dfae6e | 440 | PPC_FLAGS_EXCP_74xx = 0x00000800, |
3fc6c082 | 441 | /* PowerPC 970 exception model */ |
d0dfae6e | 442 | PPC_FLAGS_EXCP_970 = 0x00000900, |
d9bce9d9 | 443 | /* BookE exception model */ |
d0dfae6e JM |
444 | PPC_FLAGS_EXCP_BOOKE = 0x00000A00, |
445 | /* Input pins model */ | |
446 | PPC_FLAGS_INPUT_MASK = 0x000F0000, | |
447 | PPC_FLAGS_INPUT_6xx = 0x00000000, | |
448 | PPC_FLAGS_INPUT_BookE = 0x00010000, | |
449 | PPC_FLAGS_INPUT_40x = 0x00020000, | |
450 | PPC_FLAGS_INPUT_970 = 0x00030000, | |
3fc6c082 FB |
451 | }; |
452 | ||
453 | #define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK) | |
454 | #define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK) | |
d0dfae6e | 455 | #define PPC_INPUT(env) (env->flags & PPC_FLAGS_INPUT_MASK) |
3fc6c082 FB |
456 | |
457 | /*****************************************************************************/ | |
458 | /* Supported instruction set definitions */ | |
459 | /* This generates an empty opcode table... */ | |
460 | #define PPC_INSNS_TODO (PPC_NONE) | |
461 | #define PPC_FLAGS_TODO (0x00000000) | |
462 | ||
463 | /* PowerPC 40x instruction set */ | |
76a66253 | 464 | #define PPC_INSNS_EMB (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_EMB_COMMON) |
3fc6c082 FB |
465 | /* PowerPC 401 */ |
466 | #define PPC_INSNS_401 (PPC_INSNS_TODO) | |
467 | #define PPC_FLAGS_401 (PPC_FLAGS_TODO) | |
468 | /* PowerPC 403 */ | |
76a66253 JM |
469 | #define PPC_INSNS_403 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
470 | PPC_MEM_TLBIA | PPC_4xx_COMMON | PPC_40x_EXCP | \ | |
471 | PPC_40x_SPEC) | |
d0dfae6e JM |
472 | #define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x | \ |
473 | PPC_FLAGS_INPUT_40x) | |
3fc6c082 | 474 | /* PowerPC 405 */ |
76a66253 JM |
475 | #define PPC_INSNS_405 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ |
476 | PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_TB | \ | |
477 | PPC_4xx_COMMON | PPC_40x_SPEC | PPC_40x_EXCP | \ | |
3fc6c082 | 478 | PPC_405_MAC) |
d0dfae6e JM |
479 | #define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \ |
480 | PPC_FLAGS_INPUT_40x) | |
3fc6c082 | 481 | /* PowerPC 440 */ |
76a66253 JM |
482 | #define PPC_INSNS_440 (PPC_INSNS_EMB | PPC_CACHE_OPT | PPC_BOOKE | \ |
483 | PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC) | |
d0dfae6e JM |
484 | #define PPC_FLAGS_440 (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \ |
485 | PPC_FLAGS_INPUT_BookE) | |
76a66253 JM |
486 | /* Generic BookE PowerPC */ |
487 | #define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \ | |
488 | PPC_FLOAT | PPC_FLOAT_OPT | PPC_CACHE_OPT) | |
d0dfae6e JM |
489 | #define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \ |
490 | PPC_FLAGS_INPUT_BookE) | |
76a66253 JM |
491 | /* e500 core */ |
492 | #define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \ | |
493 | PPC_CACHE_OPT | PPC_E500_VECTOR) | |
d0dfae6e JM |
494 | #define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \ |
495 | PPC_FLAGS_INPUT_BookE) | |
3fc6c082 FB |
496 | /* Non-embedded PowerPC */ |
497 | #define PPC_INSNS_COMMON (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \ | |
d0dfae6e | 498 | PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE) |
3fc6c082 FB |
499 | /* PowerPC 601 */ |
500 | #define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR) | |
d0dfae6e JM |
501 | #define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601 | \ |
502 | PPC_FLAGS_INPUT_6xx) | |
3fc6c082 FB |
503 | /* PowerPC 602 */ |
504 | #define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \ | |
76a66253 | 505 | PPC_MEM_TLBSYNC | PPC_TB | PPC_602_SPEC) |
d0dfae6e JM |
506 | #define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602 | \ |
507 | PPC_FLAGS_INPUT_6xx) | |
3fc6c082 FB |
508 | /* PowerPC 603 */ |
509 | #define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \ | |
510 | PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB) | |
d0dfae6e JM |
511 | #define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603 | \ |
512 | PPC_FLAGS_INPUT_6xx) | |
3fc6c082 FB |
513 | /* PowerPC G2 */ |
514 | #define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \ | |
515 | PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB) | |
d0dfae6e JM |
516 | #define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603 | \ |
517 | PPC_FLAGS_INPUT_6xx) | |
3fc6c082 FB |
518 | /* PowerPC 604 */ |
519 | #define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \ | |
520 | PPC_MEM_TLBSYNC | PPC_TB) | |
d0dfae6e JM |
521 | #define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604 | \ |
522 | PPC_FLAGS_INPUT_6xx) | |
3fc6c082 FB |
523 | /* PowerPC 740/750 (aka G3) */ |
524 | #define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \ | |
525 | PPC_MEM_TLBSYNC | PPC_TB) | |
d0dfae6e JM |
526 | #define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0 | \ |
527 | PPC_FLAGS_INPUT_6xx) | |
3fc6c082 FB |
528 | /* PowerPC 745/755 */ |
529 | #define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \ | |
530 | PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB) | |
d0dfae6e JM |
531 | #define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5 | \ |
532 | PPC_FLAGS_INPUT_6xx) | |
3fc6c082 FB |
533 | /* PowerPC 74xx (aka G4) */ |
534 | #define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC | \ | |
535 | PPC_MEM_TLBSYNC | PPC_TB) | |
d0dfae6e JM |
536 | #define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx | \ |
537 | PPC_FLAGS_INPUT_6xx) | |
426613db JM |
538 | /* PowerPC 970 (aka G5) */ |
539 | #define PPC_INSNS_970 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_FLOAT_OPT | \ | |
540 | PPC_ALTIVEC | PPC_MEM_TLBSYNC | PPC_TB | \ | |
541 | PPC_64B | PPC_64_BRIDGE | PPC_SLBI) | |
d0dfae6e JM |
542 | #define PPC_FLAGS_970 (PPC_FLAGS_MMU_64BRIDGE | PPC_FLAGS_EXCP_970 | \ |
543 | PPC_FLAGS_INPUT_970) | |
3fc6c082 FB |
544 | |
545 | /* Default PowerPC will be 604/970 */ | |
546 | #define PPC_INSNS_PPC32 PPC_INSNS_604 | |
547 | #define PPC_FLAGS_PPC32 PPC_FLAGS_604 | |
3fc6c082 FB |
548 | #define PPC_INSNS_PPC64 PPC_INSNS_970 |
549 | #define PPC_FLAGS_PPC64 PPC_FLAGS_970 | |
3fc6c082 FB |
550 | #define PPC_INSNS_DEFAULT PPC_INSNS_604 |
551 | #define PPC_FLAGS_DEFAULT PPC_FLAGS_604 | |
552 | typedef struct ppc_def_t ppc_def_t; | |
79aceca5 | 553 | |
3fc6c082 FB |
554 | /*****************************************************************************/ |
555 | /* Types used to describe some PowerPC registers */ | |
556 | typedef struct CPUPPCState CPUPPCState; | |
557 | typedef struct opc_handler_t opc_handler_t; | |
9fddaa0c | 558 | typedef struct ppc_tb_t ppc_tb_t; |
3fc6c082 FB |
559 | typedef struct ppc_spr_t ppc_spr_t; |
560 | typedef struct ppc_dcr_t ppc_dcr_t; | |
561 | typedef struct ppc_avr_t ppc_avr_t; | |
1d0a48fb | 562 | typedef union ppc_tlb_t ppc_tlb_t; |
76a66253 | 563 | |
3fc6c082 FB |
564 | /* SPR access micro-ops generations callbacks */ |
565 | struct ppc_spr_t { | |
566 | void (*uea_read)(void *opaque, int spr_num); | |
567 | void (*uea_write)(void *opaque, int spr_num); | |
76a66253 | 568 | #if !defined(CONFIG_USER_ONLY) |
3fc6c082 FB |
569 | void (*oea_read)(void *opaque, int spr_num); |
570 | void (*oea_write)(void *opaque, int spr_num); | |
76a66253 | 571 | #endif |
3fc6c082 FB |
572 | const unsigned char *name; |
573 | }; | |
574 | ||
575 | /* Altivec registers (128 bits) */ | |
576 | struct ppc_avr_t { | |
577 | uint32_t u[4]; | |
578 | }; | |
9fddaa0c | 579 | |
3fc6c082 | 580 | /* Software TLB cache */ |
1d0a48fb JM |
581 | typedef struct ppc6xx_tlb_t ppc6xx_tlb_t; |
582 | struct ppc6xx_tlb_t { | |
76a66253 JM |
583 | target_ulong pte0; |
584 | target_ulong pte1; | |
585 | target_ulong EPN; | |
1d0a48fb JM |
586 | }; |
587 | ||
588 | typedef struct ppcemb_tlb_t ppcemb_tlb_t; | |
589 | struct ppcemb_tlb_t { | |
c55e9aef | 590 | target_phys_addr_t RPN; |
1d0a48fb | 591 | target_ulong EPN; |
76a66253 | 592 | target_ulong PID; |
c55e9aef JM |
593 | target_ulong size; |
594 | uint32_t prot; | |
595 | uint32_t attr; /* Storage attributes */ | |
1d0a48fb JM |
596 | }; |
597 | ||
598 | union ppc_tlb_t { | |
599 | ppc6xx_tlb_t tlb6; | |
600 | ppcemb_tlb_t tlbe; | |
3fc6c082 FB |
601 | }; |
602 | ||
603 | /*****************************************************************************/ | |
604 | /* Machine state register bits definition */ | |
76a66253 | 605 | #define MSR_SF 63 /* Sixty-four-bit mode hflags */ |
3fc6c082 | 606 | #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ |
76a66253 | 607 | #define MSR_HV 60 /* hypervisor state hflags */ |
363be49c JM |
608 | #define MSR_CM 31 /* Computation mode for BookE hflags */ |
609 | #define MSR_ICM 30 /* Interrupt computation mode for BookE */ | |
610 | #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */ | |
76a66253 | 611 | #define MSR_VR 25 /* altivec available hflags */ |
363be49c | 612 | #define MSR_SPE 25 /* SPE enable for BookE hflags */ |
76a66253 JM |
613 | #define MSR_AP 23 /* Access privilege state on 602 hflags */ |
614 | #define MSR_SA 22 /* Supervisor access mode on 602 hflags */ | |
3fc6c082 FB |
615 | #define MSR_KEY 19 /* key bit on 603e */ |
616 | #define MSR_POW 18 /* Power management */ | |
617 | #define MSR_WE 18 /* Wait state enable on embedded PowerPC */ | |
618 | #define MSR_TGPR 17 /* TGPR usage on 602/603 */ | |
76a66253 | 619 | #define MSR_TLB 17 /* TLB update on ? */ |
3fc6c082 FB |
620 | #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC */ |
621 | #define MSR_ILE 16 /* Interrupt little-endian mode */ | |
622 | #define MSR_EE 15 /* External interrupt enable */ | |
76a66253 JM |
623 | #define MSR_PR 14 /* Problem state hflags */ |
624 | #define MSR_FP 13 /* Floating point available hflags */ | |
3fc6c082 | 625 | #define MSR_ME 12 /* Machine check interrupt enable */ |
76a66253 JM |
626 | #define MSR_FE0 11 /* Floating point exception mode 0 hflags */ |
627 | #define MSR_SE 10 /* Single-step trace enable hflags */ | |
3fc6c082 | 628 | #define MSR_DWE 10 /* Debug wait enable on 405 */ |
76a66253 JM |
629 | #define MSR_UBLE 10 /* User BTB lock enable on e500 */ |
630 | #define MSR_BE 9 /* Branch trace enable hflags */ | |
3fc6c082 | 631 | #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC */ |
76a66253 | 632 | #define MSR_FE1 8 /* Floating point exception mode 1 hflags */ |
3fc6c082 FB |
633 | #define MSR_AL 7 /* AL bit on POWER */ |
634 | #define MSR_IP 6 /* Interrupt prefix */ | |
635 | #define MSR_IR 5 /* Instruction relocate */ | |
636 | #define MSR_IS 5 /* Instruction address space on embedded PowerPC */ | |
637 | #define MSR_DR 4 /* Data relocate */ | |
638 | #define MSR_DS 4 /* Data address space on embedded PowerPC */ | |
639 | #define MSR_PE 3 /* Protection enable on 403 */ | |
640 | #define MSR_EP 3 /* Exception prefix on 601 */ | |
641 | #define MSR_PX 2 /* Protection exclusive on 403 */ | |
642 | #define MSR_PMM 2 /* Performance monitor mark on POWER */ | |
643 | #define MSR_RI 1 /* Recoverable interrupt */ | |
76a66253 | 644 | #define MSR_LE 0 /* Little-endian mode hflags */ |
3fc6c082 FB |
645 | #define msr_sf env->msr[MSR_SF] |
646 | #define msr_isf env->msr[MSR_ISF] | |
647 | #define msr_hv env->msr[MSR_HV] | |
363be49c JM |
648 | #define msr_cm env->msr[MSR_CM] |
649 | #define msr_icm env->msr[MSR_ICM] | |
76a66253 | 650 | #define msr_ucle env->msr[MSR_UCLE] |
3fc6c082 | 651 | #define msr_vr env->msr[MSR_VR] |
76a66253 | 652 | #define msr_spe env->msr[MSR_SPE] |
3fc6c082 FB |
653 | #define msr_ap env->msr[MSR_AP] |
654 | #define msr_sa env->msr[MSR_SA] | |
655 | #define msr_key env->msr[MSR_KEY] | |
76a66253 | 656 | #define msr_pow env->msr[MSR_POW] |
3fc6c082 FB |
657 | #define msr_we env->msr[MSR_WE] |
658 | #define msr_tgpr env->msr[MSR_TGPR] | |
659 | #define msr_tlb env->msr[MSR_TLB] | |
660 | #define msr_ce env->msr[MSR_CE] | |
76a66253 JM |
661 | #define msr_ile env->msr[MSR_ILE] |
662 | #define msr_ee env->msr[MSR_EE] | |
663 | #define msr_pr env->msr[MSR_PR] | |
664 | #define msr_fp env->msr[MSR_FP] | |
665 | #define msr_me env->msr[MSR_ME] | |
666 | #define msr_fe0 env->msr[MSR_FE0] | |
667 | #define msr_se env->msr[MSR_SE] | |
3fc6c082 | 668 | #define msr_dwe env->msr[MSR_DWE] |
76a66253 JM |
669 | #define msr_uble env->msr[MSR_UBLE] |
670 | #define msr_be env->msr[MSR_BE] | |
3fc6c082 | 671 | #define msr_de env->msr[MSR_DE] |
76a66253 | 672 | #define msr_fe1 env->msr[MSR_FE1] |
3fc6c082 | 673 | #define msr_al env->msr[MSR_AL] |
76a66253 JM |
674 | #define msr_ip env->msr[MSR_IP] |
675 | #define msr_ir env->msr[MSR_IR] | |
3fc6c082 | 676 | #define msr_is env->msr[MSR_IS] |
76a66253 | 677 | #define msr_dr env->msr[MSR_DR] |
3fc6c082 FB |
678 | #define msr_ds env->msr[MSR_DS] |
679 | #define msr_pe env->msr[MSR_PE] | |
680 | #define msr_ep env->msr[MSR_EP] | |
681 | #define msr_px env->msr[MSR_PX] | |
682 | #define msr_pmm env->msr[MSR_PMM] | |
76a66253 JM |
683 | #define msr_ri env->msr[MSR_RI] |
684 | #define msr_le env->msr[MSR_LE] | |
79aceca5 | 685 | |
3fc6c082 FB |
686 | /*****************************************************************************/ |
687 | /* The whole PowerPC CPU context */ | |
688 | struct CPUPPCState { | |
689 | /* First are the most commonly used resources | |
690 | * during translated code execution | |
691 | */ | |
0487d6a8 | 692 | #if TARGET_GPR_BITS > HOST_LONG_BITS |
3fc6c082 FB |
693 | /* temporary fixed-point registers |
694 | * used to emulate 64 bits target on 32 bits hosts | |
5fafdf24 | 695 | */ |
3c4c9f9f | 696 | ppc_gpr_t t0, t1, t2; |
3fc6c082 | 697 | #endif |
d9bce9d9 JM |
698 | ppc_avr_t t0_avr, t1_avr, t2_avr; |
699 | ||
79aceca5 | 700 | /* general purpose registers */ |
76a66253 | 701 | ppc_gpr_t gpr[32]; |
3fc6c082 FB |
702 | /* LR */ |
703 | target_ulong lr; | |
704 | /* CTR */ | |
705 | target_ulong ctr; | |
706 | /* condition register */ | |
707 | uint8_t crf[8]; | |
79aceca5 | 708 | /* XER */ |
3fc6c082 FB |
709 | /* XXX: We use only 5 fields, but we want to keep the structure aligned */ |
710 | uint8_t xer[8]; | |
79aceca5 | 711 | /* Reservation address */ |
3fc6c082 FB |
712 | target_ulong reserve; |
713 | ||
714 | /* Those ones are used in supervisor mode only */ | |
79aceca5 | 715 | /* machine state register */ |
3fc6c082 FB |
716 | uint8_t msr[64]; |
717 | /* temporary general purpose registers */ | |
76a66253 | 718 | ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */ |
3fc6c082 FB |
719 | |
720 | /* Floating point execution context */ | |
76a66253 | 721 | /* temporary float registers */ |
4ecc3190 FB |
722 | float64 ft0; |
723 | float64 ft1; | |
724 | float64 ft2; | |
725 | float_status fp_status; | |
3fc6c082 FB |
726 | /* floating point registers */ |
727 | float64 fpr[32]; | |
728 | /* floating point status and control register */ | |
729 | uint8_t fpscr[8]; | |
4ecc3190 | 730 | |
a316d335 FB |
731 | CPU_COMMON |
732 | ||
50443c98 FB |
733 | int halted; /* TRUE if the CPU is in suspend state */ |
734 | ||
ac9eb073 FB |
735 | int access_type; /* when a memory exception occurs, the access |
736 | type is stored here */ | |
a541f297 | 737 | |
3fc6c082 FB |
738 | /* MMU context */ |
739 | /* Address space register */ | |
740 | target_ulong asr; | |
741 | /* segment registers */ | |
742 | target_ulong sdr1; | |
743 | target_ulong sr[16]; | |
744 | /* BATs */ | |
745 | int nb_BATs; | |
746 | target_ulong DBAT[2][8]; | |
747 | target_ulong IBAT[2][8]; | |
9fddaa0c | 748 | |
3fc6c082 FB |
749 | /* Other registers */ |
750 | /* Special purpose registers */ | |
751 | target_ulong spr[1024]; | |
752 | /* Altivec registers */ | |
753 | ppc_avr_t avr[32]; | |
754 | uint32_t vscr; | |
d9bce9d9 JM |
755 | /* SPE registers */ |
756 | ppc_gpr_t spe_acc; | |
0487d6a8 | 757 | float_status spe_status; |
d9bce9d9 | 758 | uint32_t spe_fscr; |
3fc6c082 FB |
759 | |
760 | /* Internal devices resources */ | |
9fddaa0c FB |
761 | /* Time base and decrementer */ |
762 | ppc_tb_t *tb_env; | |
3fc6c082 | 763 | /* Device control registers */ |
3fc6c082 FB |
764 | ppc_dcr_t *dcr_env; |
765 | ||
766 | /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */ | |
76a66253 JM |
767 | int nb_tlb; /* Total number of TLB */ |
768 | int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */ | |
769 | int nb_ways; /* Number of ways in the TLB set */ | |
770 | int last_way; /* Last used way used to allocate TLB in a LRU way */ | |
771 | int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */ | |
363be49c | 772 | int nb_pids; /* Number of available PID registers */ |
76a66253 | 773 | ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */ |
3fc6c082 FB |
774 | /* 403 dedicated access protection registers */ |
775 | target_ulong pb[4]; | |
776 | ||
777 | /* Those resources are used during exception processing */ | |
778 | /* CPU model definition */ | |
779 | uint64_t msr_mask; | |
780 | uint32_t flags; | |
781 | ||
782 | int exception_index; | |
783 | int error_code; | |
784 | int interrupt_request; | |
47103572 | 785 | uint32_t pending_interrupts; |
e9df014c JM |
786 | #if !defined(CONFIG_USER_ONLY) |
787 | /* This is the IRQ controller, which is implementation dependant | |
788 | * and only relevant when emulating a complete machine. | |
789 | */ | |
790 | uint32_t irq_input_state; | |
791 | void **irq_inputs; | |
792 | #endif | |
3fc6c082 FB |
793 | |
794 | /* Those resources are used only during code translation */ | |
795 | /* Next instruction pointer */ | |
796 | target_ulong nip; | |
797 | /* SPR translation callbacks */ | |
798 | ppc_spr_t spr_cb[1024]; | |
799 | /* opcode handlers */ | |
800 | opc_handler_t *opcodes[0x40]; | |
801 | ||
802 | /* Those resources are used only in Qemu core */ | |
803 | jmp_buf jmp_env; | |
804 | int user_mode_only; /* user mode only simulation */ | |
3fc6c082 FB |
805 | uint32_t hflags; |
806 | ||
9fddaa0c FB |
807 | /* Power management */ |
808 | int power_mode; | |
a541f297 | 809 | |
6d506e6d FB |
810 | /* temporary hack to handle OSI calls (only used if non NULL) */ |
811 | int (*osi_call)(struct CPUPPCState *env); | |
3fc6c082 | 812 | }; |
79aceca5 | 813 | |
76a66253 JM |
814 | /* Context used internally during MMU translations */ |
815 | typedef struct mmu_ctx_t mmu_ctx_t; | |
816 | struct mmu_ctx_t { | |
817 | target_phys_addr_t raddr; /* Real address */ | |
818 | int prot; /* Protection bits */ | |
819 | target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */ | |
820 | target_ulong ptem; /* Virtual segment ID | API */ | |
821 | int key; /* Access key */ | |
822 | }; | |
823 | ||
3fc6c082 | 824 | /*****************************************************************************/ |
36081602 JM |
825 | CPUPPCState *cpu_ppc_init (void); |
826 | int cpu_ppc_exec (CPUPPCState *s); | |
827 | void cpu_ppc_close (CPUPPCState *s); | |
79aceca5 FB |
828 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
829 | signal handlers to inform the virtual CPU of exceptions. non zero | |
830 | is returned if the signal was handled by the virtual CPU. */ | |
36081602 JM |
831 | int cpu_ppc_signal_handler (int host_signum, void *pinfo, |
832 | void *puc); | |
79aceca5 | 833 | |
a541f297 | 834 | void do_interrupt (CPUPPCState *env); |
e9df014c | 835 | void ppc_hw_interrupt (CPUPPCState *env); |
36081602 | 836 | void cpu_loop_exit (void); |
a541f297 | 837 | |
9a64fbe4 | 838 | void dump_stack (CPUPPCState *env); |
a541f297 | 839 | |
76a66253 | 840 | #if !defined(CONFIG_USER_ONLY) |
3fc6c082 FB |
841 | target_ulong do_load_ibatu (CPUPPCState *env, int nr); |
842 | target_ulong do_load_ibatl (CPUPPCState *env, int nr); | |
843 | void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value); | |
844 | void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value); | |
845 | target_ulong do_load_dbatu (CPUPPCState *env, int nr); | |
846 | target_ulong do_load_dbatl (CPUPPCState *env, int nr); | |
847 | void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value); | |
848 | void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value); | |
3fc6c082 FB |
849 | target_ulong do_load_sdr1 (CPUPPCState *env); |
850 | void do_store_sdr1 (CPUPPCState *env, target_ulong value); | |
d9bce9d9 JM |
851 | #if defined(TARGET_PPC64) |
852 | target_ulong ppc_load_asr (CPUPPCState *env); | |
853 | void ppc_store_asr (CPUPPCState *env, target_ulong value); | |
854 | #endif | |
3fc6c082 FB |
855 | target_ulong do_load_sr (CPUPPCState *env, int srnum); |
856 | void do_store_sr (CPUPPCState *env, int srnum, target_ulong value); | |
76a66253 JM |
857 | #endif |
858 | uint32_t ppc_load_xer (CPUPPCState *env); | |
859 | void ppc_store_xer (CPUPPCState *env, uint32_t value); | |
3fc6c082 FB |
860 | target_ulong do_load_msr (CPUPPCState *env); |
861 | void do_store_msr (CPUPPCState *env, target_ulong value); | |
426613db | 862 | void ppc_store_msr_32 (CPUPPCState *env, uint32_t value); |
3fc6c082 FB |
863 | |
864 | void do_compute_hflags (CPUPPCState *env); | |
0a032cbe JM |
865 | void cpu_ppc_reset (void *opaque); |
866 | CPUPPCState *cpu_ppc_init (void); | |
867 | void cpu_ppc_close(CPUPPCState *env); | |
a541f297 | 868 | |
3fc6c082 FB |
869 | int ppc_find_by_name (const unsigned char *name, ppc_def_t **def); |
870 | int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def); | |
871 | void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); | |
872 | int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def); | |
85c4adf6 | 873 | |
9fddaa0c FB |
874 | /* Time-base and decrementer management */ |
875 | #ifndef NO_CPU_IO_DEFS | |
876 | uint32_t cpu_ppc_load_tbl (CPUPPCState *env); | |
877 | uint32_t cpu_ppc_load_tbu (CPUPPCState *env); | |
878 | void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value); | |
879 | void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value); | |
880 | uint32_t cpu_ppc_load_decr (CPUPPCState *env); | |
881 | void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value); | |
d9bce9d9 JM |
882 | uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env); |
883 | uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env); | |
884 | #if !defined(CONFIG_USER_ONLY) | |
885 | void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value); | |
886 | void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value); | |
887 | target_ulong load_40x_pit (CPUPPCState *env); | |
888 | void store_40x_pit (CPUPPCState *env, target_ulong val); | |
8ecc7913 | 889 | void store_40x_dbcr0 (CPUPPCState *env, uint32_t val); |
c294fc58 | 890 | void store_40x_sler (CPUPPCState *env, uint32_t val); |
d9bce9d9 JM |
891 | void store_booke_tcr (CPUPPCState *env, target_ulong val); |
892 | void store_booke_tsr (CPUPPCState *env, target_ulong val); | |
0a032cbe | 893 | void ppc_tlb_invalidate_all (CPUPPCState *env); |
36081602 | 894 | int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid); |
d9bce9d9 | 895 | #endif |
9fddaa0c | 896 | #endif |
79aceca5 | 897 | |
2e719ba3 JM |
898 | /* Device control registers */ |
899 | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp); | |
900 | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); | |
901 | ||
9467d44c TS |
902 | #define CPUState CPUPPCState |
903 | #define cpu_init cpu_ppc_init | |
904 | #define cpu_exec cpu_ppc_exec | |
905 | #define cpu_gen_code cpu_ppc_gen_code | |
906 | #define cpu_signal_handler cpu_ppc_signal_handler | |
907 | ||
79aceca5 FB |
908 | #include "cpu-all.h" |
909 | ||
3fc6c082 FB |
910 | /*****************************************************************************/ |
911 | /* Registers definitions */ | |
79aceca5 | 912 | #define ugpr(n) (env->gpr[n]) |
79aceca5 | 913 | |
79aceca5 FB |
914 | #define XER_SO 31 |
915 | #define XER_OV 30 | |
916 | #define XER_CA 29 | |
3fc6c082 | 917 | #define XER_CMP 8 |
36081602 | 918 | #define XER_BC 0 |
3fc6c082 FB |
919 | #define xer_so env->xer[4] |
920 | #define xer_ov env->xer[6] | |
921 | #define xer_ca env->xer[2] | |
922 | #define xer_cmp env->xer[1] | |
36081602 | 923 | #define xer_bc env->xer[0] |
79aceca5 | 924 | |
3fc6c082 | 925 | /* SPR definitions */ |
76a66253 JM |
926 | #define SPR_MQ (0x000) |
927 | #define SPR_XER (0x001) | |
928 | #define SPR_601_VRTCU (0x004) | |
929 | #define SPR_601_VRTCL (0x005) | |
930 | #define SPR_601_UDECR (0x006) | |
931 | #define SPR_LR (0x008) | |
932 | #define SPR_CTR (0x009) | |
933 | #define SPR_DSISR (0x012) | |
934 | #define SPR_DAR (0x013) | |
935 | #define SPR_601_RTCU (0x014) | |
936 | #define SPR_601_RTCL (0x015) | |
937 | #define SPR_DECR (0x016) | |
938 | #define SPR_SDR1 (0x019) | |
939 | #define SPR_SRR0 (0x01A) | |
940 | #define SPR_SRR1 (0x01B) | |
941 | #define SPR_BOOKE_PID (0x030) | |
942 | #define SPR_BOOKE_DECAR (0x036) | |
363be49c JM |
943 | #define SPR_BOOKE_CSRR0 (0x03A) |
944 | #define SPR_BOOKE_CSRR1 (0x03B) | |
76a66253 JM |
945 | #define SPR_BOOKE_DEAR (0x03D) |
946 | #define SPR_BOOKE_ESR (0x03E) | |
363be49c | 947 | #define SPR_BOOKE_IVPR (0x03F) |
76a66253 JM |
948 | #define SPR_8xx_EIE (0x050) |
949 | #define SPR_8xx_EID (0x051) | |
950 | #define SPR_8xx_NRE (0x052) | |
951 | #define SPR_58x_CMPA (0x090) | |
952 | #define SPR_58x_CMPB (0x091) | |
953 | #define SPR_58x_CMPC (0x092) | |
954 | #define SPR_58x_CMPD (0x093) | |
955 | #define SPR_58x_ICR (0x094) | |
956 | #define SPR_58x_DER (0x094) | |
957 | #define SPR_58x_COUNTA (0x096) | |
958 | #define SPR_58x_COUNTB (0x097) | |
959 | #define SPR_58x_CMPE (0x098) | |
960 | #define SPR_58x_CMPF (0x099) | |
961 | #define SPR_58x_CMPG (0x09A) | |
962 | #define SPR_58x_CMPH (0x09B) | |
963 | #define SPR_58x_LCTRL1 (0x09C) | |
964 | #define SPR_58x_LCTRL2 (0x09D) | |
965 | #define SPR_58x_ICTRL (0x09E) | |
966 | #define SPR_58x_BAR (0x09F) | |
967 | #define SPR_VRSAVE (0x100) | |
968 | #define SPR_USPRG0 (0x100) | |
363be49c JM |
969 | #define SPR_USPRG1 (0x101) |
970 | #define SPR_USPRG2 (0x102) | |
971 | #define SPR_USPRG3 (0x103) | |
76a66253 JM |
972 | #define SPR_USPRG4 (0x104) |
973 | #define SPR_USPRG5 (0x105) | |
974 | #define SPR_USPRG6 (0x106) | |
975 | #define SPR_USPRG7 (0x107) | |
976 | #define SPR_VTBL (0x10C) | |
977 | #define SPR_VTBU (0x10D) | |
978 | #define SPR_SPRG0 (0x110) | |
979 | #define SPR_SPRG1 (0x111) | |
980 | #define SPR_SPRG2 (0x112) | |
981 | #define SPR_SPRG3 (0x113) | |
982 | #define SPR_SPRG4 (0x114) | |
983 | #define SPR_SCOMC (0x114) | |
984 | #define SPR_SPRG5 (0x115) | |
985 | #define SPR_SCOMD (0x115) | |
986 | #define SPR_SPRG6 (0x116) | |
987 | #define SPR_SPRG7 (0x117) | |
988 | #define SPR_ASR (0x118) | |
989 | #define SPR_EAR (0x11A) | |
990 | #define SPR_TBL (0x11C) | |
991 | #define SPR_TBU (0x11D) | |
992 | #define SPR_SVR (0x11E) | |
993 | #define SPR_BOOKE_PIR (0x11E) | |
994 | #define SPR_PVR (0x11F) | |
995 | #define SPR_HSPRG0 (0x130) | |
996 | #define SPR_BOOKE_DBSR (0x130) | |
997 | #define SPR_HSPRG1 (0x131) | |
998 | #define SPR_BOOKE_DBCR0 (0x134) | |
999 | #define SPR_IBCR (0x135) | |
1000 | #define SPR_BOOKE_DBCR1 (0x135) | |
1001 | #define SPR_DBCR (0x136) | |
1002 | #define SPR_HDEC (0x136) | |
1003 | #define SPR_BOOKE_DBCR2 (0x136) | |
1004 | #define SPR_HIOR (0x137) | |
1005 | #define SPR_MBAR (0x137) | |
1006 | #define SPR_RMOR (0x138) | |
1007 | #define SPR_BOOKE_IAC1 (0x138) | |
1008 | #define SPR_HRMOR (0x139) | |
1009 | #define SPR_BOOKE_IAC2 (0x139) | |
1010 | #define SPR_HSSR0 (0x13A) | |
1011 | #define SPR_BOOKE_IAC3 (0x13A) | |
1012 | #define SPR_HSSR1 (0x13B) | |
1013 | #define SPR_BOOKE_IAC4 (0x13B) | |
1014 | #define SPR_LPCR (0x13C) | |
1015 | #define SPR_BOOKE_DAC1 (0x13C) | |
1016 | #define SPR_LPIDR (0x13D) | |
1017 | #define SPR_DABR2 (0x13D) | |
1018 | #define SPR_BOOKE_DAC2 (0x13D) | |
1019 | #define SPR_BOOKE_DVC1 (0x13E) | |
1020 | #define SPR_BOOKE_DVC2 (0x13F) | |
1021 | #define SPR_BOOKE_TSR (0x150) | |
1022 | #define SPR_BOOKE_TCR (0x154) | |
1023 | #define SPR_BOOKE_IVOR0 (0x190) | |
1024 | #define SPR_BOOKE_IVOR1 (0x191) | |
1025 | #define SPR_BOOKE_IVOR2 (0x192) | |
1026 | #define SPR_BOOKE_IVOR3 (0x193) | |
1027 | #define SPR_BOOKE_IVOR4 (0x194) | |
1028 | #define SPR_BOOKE_IVOR5 (0x195) | |
1029 | #define SPR_BOOKE_IVOR6 (0x196) | |
1030 | #define SPR_BOOKE_IVOR7 (0x197) | |
1031 | #define SPR_BOOKE_IVOR8 (0x198) | |
1032 | #define SPR_BOOKE_IVOR9 (0x199) | |
1033 | #define SPR_BOOKE_IVOR10 (0x19A) | |
1034 | #define SPR_BOOKE_IVOR11 (0x19B) | |
1035 | #define SPR_BOOKE_IVOR12 (0x19C) | |
1036 | #define SPR_BOOKE_IVOR13 (0x19D) | |
1037 | #define SPR_BOOKE_IVOR14 (0x19E) | |
1038 | #define SPR_BOOKE_IVOR15 (0x19F) | |
1039 | #define SPR_E500_SPEFSCR (0x200) | |
1040 | #define SPR_E500_BBEAR (0x201) | |
1041 | #define SPR_E500_BBTAR (0x202) | |
1042 | #define SPR_BOOKE_ATBL (0x20E) | |
1043 | #define SPR_BOOKE_ATBU (0x20F) | |
1044 | #define SPR_IBAT0U (0x210) | |
363be49c | 1045 | #define SPR_BOOKE_IVOR32 (0x210) |
76a66253 | 1046 | #define SPR_IBAT0L (0x211) |
363be49c | 1047 | #define SPR_BOOKE_IVOR33 (0x211) |
76a66253 | 1048 | #define SPR_IBAT1U (0x212) |
363be49c | 1049 | #define SPR_BOOKE_IVOR34 (0x212) |
76a66253 | 1050 | #define SPR_IBAT1L (0x213) |
363be49c | 1051 | #define SPR_BOOKE_IVOR35 (0x213) |
76a66253 | 1052 | #define SPR_IBAT2U (0x214) |
363be49c | 1053 | #define SPR_BOOKE_IVOR36 (0x214) |
76a66253 JM |
1054 | #define SPR_IBAT2L (0x215) |
1055 | #define SPR_E500_L1CFG0 (0x215) | |
363be49c | 1056 | #define SPR_BOOKE_IVOR37 (0x215) |
76a66253 JM |
1057 | #define SPR_IBAT3U (0x216) |
1058 | #define SPR_E500_L1CFG1 (0x216) | |
1059 | #define SPR_IBAT3L (0x217) | |
1060 | #define SPR_DBAT0U (0x218) | |
1061 | #define SPR_DBAT0L (0x219) | |
1062 | #define SPR_DBAT1U (0x21A) | |
1063 | #define SPR_DBAT1L (0x21B) | |
1064 | #define SPR_DBAT2U (0x21C) | |
1065 | #define SPR_DBAT2L (0x21D) | |
1066 | #define SPR_DBAT3U (0x21E) | |
1067 | #define SPR_DBAT3L (0x21F) | |
1068 | #define SPR_IBAT4U (0x230) | |
1069 | #define SPR_IBAT4L (0x231) | |
1070 | #define SPR_IBAT5U (0x232) | |
1071 | #define SPR_IBAT5L (0x233) | |
1072 | #define SPR_IBAT6U (0x234) | |
1073 | #define SPR_IBAT6L (0x235) | |
1074 | #define SPR_IBAT7U (0x236) | |
1075 | #define SPR_IBAT7L (0x237) | |
1076 | #define SPR_DBAT4U (0x238) | |
1077 | #define SPR_DBAT4L (0x239) | |
1078 | #define SPR_DBAT5U (0x23A) | |
363be49c | 1079 | #define SPR_BOOKE_MCSRR0 (0x23A) |
76a66253 | 1080 | #define SPR_DBAT5L (0x23B) |
363be49c | 1081 | #define SPR_BOOKE_MCSRR1 (0x23B) |
76a66253 | 1082 | #define SPR_DBAT6U (0x23C) |
363be49c | 1083 | #define SPR_BOOKE_MCSR (0x23C) |
76a66253 JM |
1084 | #define SPR_DBAT6L (0x23D) |
1085 | #define SPR_E500_MCAR (0x23D) | |
1086 | #define SPR_DBAT7U (0x23E) | |
363be49c | 1087 | #define SPR_BOOKE_DSRR0 (0x23E) |
76a66253 | 1088 | #define SPR_DBAT7L (0x23F) |
363be49c JM |
1089 | #define SPR_BOOKE_DSRR1 (0x23F) |
1090 | #define SPR_BOOKE_SPRG8 (0x25C) | |
1091 | #define SPR_BOOKE_SPRG9 (0x25D) | |
1092 | #define SPR_BOOKE_MAS0 (0x270) | |
1093 | #define SPR_BOOKE_MAS1 (0x271) | |
1094 | #define SPR_BOOKE_MAS2 (0x272) | |
1095 | #define SPR_BOOKE_MAS3 (0x273) | |
1096 | #define SPR_BOOKE_MAS4 (0x274) | |
1097 | #define SPR_BOOKE_MAS6 (0x276) | |
1098 | #define SPR_BOOKE_PID1 (0x279) | |
1099 | #define SPR_BOOKE_PID2 (0x27A) | |
1100 | #define SPR_BOOKE_TLB0CFG (0x2B0) | |
1101 | #define SPR_BOOKE_TLB1CFG (0x2B1) | |
1102 | #define SPR_BOOKE_TLB2CFG (0x2B2) | |
1103 | #define SPR_BOOKE_TLB3CFG (0x2B3) | |
1104 | #define SPR_BOOKE_EPR (0x2BE) | |
76a66253 JM |
1105 | #define SPR_440_INV0 (0x370) |
1106 | #define SPR_440_INV1 (0x371) | |
1107 | #define SPR_440_INV2 (0x372) | |
1108 | #define SPR_440_INV3 (0x373) | |
1109 | #define SPR_440_IVT0 (0x374) | |
1110 | #define SPR_440_IVT1 (0x375) | |
1111 | #define SPR_440_IVT2 (0x376) | |
1112 | #define SPR_440_IVT3 (0x377) | |
1113 | #define SPR_440_DNV0 (0x390) | |
1114 | #define SPR_440_DNV1 (0x391) | |
1115 | #define SPR_440_DNV2 (0x392) | |
1116 | #define SPR_440_DNV3 (0x393) | |
1117 | #define SPR_440_DVT0 (0x394) | |
1118 | #define SPR_440_DVT1 (0x395) | |
1119 | #define SPR_440_DVT2 (0x396) | |
1120 | #define SPR_440_DVT3 (0x397) | |
1121 | #define SPR_440_DVLIM (0x398) | |
1122 | #define SPR_440_IVLIM (0x399) | |
1123 | #define SPR_440_RSTCFG (0x39B) | |
363be49c JM |
1124 | #define SPR_BOOKE_DCBTRL (0x39C) |
1125 | #define SPR_BOOKE_DCBTRH (0x39D) | |
1126 | #define SPR_BOOKE_ICBTRL (0x39E) | |
1127 | #define SPR_BOOKE_ICBTRH (0x39F) | |
76a66253 JM |
1128 | #define SPR_UMMCR0 (0x3A8) |
1129 | #define SPR_UPMC1 (0x3A9) | |
1130 | #define SPR_UPMC2 (0x3AA) | |
1131 | #define SPR_USIA (0x3AB) | |
1132 | #define SPR_UMMCR1 (0x3AC) | |
1133 | #define SPR_UPMC3 (0x3AD) | |
1134 | #define SPR_UPMC4 (0x3AE) | |
1135 | #define SPR_USDA (0x3AF) | |
1136 | #define SPR_40x_ZPR (0x3B0) | |
363be49c | 1137 | #define SPR_BOOKE_MAS7 (0x3B0) |
76a66253 JM |
1138 | #define SPR_40x_PID (0x3B1) |
1139 | #define SPR_440_MMUCR (0x3B2) | |
1140 | #define SPR_4xx_CCR0 (0x3B3) | |
363be49c | 1141 | #define SPR_BOOKE_EPLC (0x3B3) |
76a66253 | 1142 | #define SPR_405_IAC3 (0x3B4) |
363be49c | 1143 | #define SPR_BOOKE_EPSC (0x3B4) |
76a66253 JM |
1144 | #define SPR_405_IAC4 (0x3B5) |
1145 | #define SPR_405_DVC1 (0x3B6) | |
1146 | #define SPR_405_DVC2 (0x3B7) | |
1147 | #define SPR_MMCR0 (0x3B8) | |
1148 | #define SPR_PMC1 (0x3B9) | |
1149 | #define SPR_40x_SGR (0x3B9) | |
1150 | #define SPR_PMC2 (0x3BA) | |
1151 | #define SPR_40x_DCWR (0x3BA) | |
1152 | #define SPR_SIA (0x3BB) | |
1153 | #define SPR_405_SLER (0x3BB) | |
1154 | #define SPR_MMCR1 (0x3BC) | |
1155 | #define SPR_405_SU0R (0x3BC) | |
1156 | #define SPR_PMC3 (0x3BD) | |
1157 | #define SPR_405_DBCR1 (0x3BD) | |
1158 | #define SPR_PMC4 (0x3BE) | |
1159 | #define SPR_SDA (0x3BF) | |
1160 | #define SPR_403_VTBL (0x3CC) | |
1161 | #define SPR_403_VTBU (0x3CD) | |
1162 | #define SPR_DMISS (0x3D0) | |
1163 | #define SPR_DCMP (0x3D1) | |
1164 | #define SPR_HASH1 (0x3D2) | |
1165 | #define SPR_HASH2 (0x3D3) | |
363be49c | 1166 | #define SPR_BOOKE_ICBDR (0x3D3) |
76a66253 JM |
1167 | #define SPR_IMISS (0x3D4) |
1168 | #define SPR_40x_ESR (0x3D4) | |
1169 | #define SPR_ICMP (0x3D5) | |
1170 | #define SPR_40x_DEAR (0x3D5) | |
1171 | #define SPR_RPA (0x3D6) | |
1172 | #define SPR_40x_EVPR (0x3D6) | |
1173 | #define SPR_403_CDBCR (0x3D7) | |
1174 | #define SPR_TCR (0x3D8) | |
1175 | #define SPR_40x_TSR (0x3D8) | |
1176 | #define SPR_IBR (0x3DA) | |
1177 | #define SPR_40x_TCR (0x3DA) | |
1178 | #define SPR_ESASR (0x3DB) | |
1179 | #define SPR_40x_PIT (0x3DB) | |
1180 | #define SPR_403_TBL (0x3DC) | |
1181 | #define SPR_403_TBU (0x3DD) | |
1182 | #define SPR_SEBR (0x3DE) | |
1183 | #define SPR_40x_SRR2 (0x3DE) | |
1184 | #define SPR_SER (0x3DF) | |
1185 | #define SPR_40x_SRR3 (0x3DF) | |
1186 | #define SPR_HID0 (0x3F0) | |
1187 | #define SPR_40x_DBSR (0x3F0) | |
1188 | #define SPR_HID1 (0x3F1) | |
1189 | #define SPR_IABR (0x3F2) | |
1190 | #define SPR_40x_DBCR0 (0x3F2) | |
1191 | #define SPR_601_HID2 (0x3F2) | |
1192 | #define SPR_E500_L1CSR0 (0x3F2) | |
1193 | #define SPR_HID2 (0x3F3) | |
1194 | #define SPR_E500_L1CSR1 (0x3F3) | |
1195 | #define SPR_440_DBDR (0x3F3) | |
1196 | #define SPR_40x_IAC1 (0x3F4) | |
363be49c | 1197 | #define SPR_BOOKE_MMUCSR0 (0x3F4) |
76a66253 | 1198 | #define SPR_DABR (0x3F5) |
3fc6c082 | 1199 | #define DABR_MASK (~(target_ulong)0x7) |
76a66253 JM |
1200 | #define SPR_E500_BUCSR (0x3F5) |
1201 | #define SPR_40x_IAC2 (0x3F5) | |
1202 | #define SPR_601_HID5 (0x3F5) | |
1203 | #define SPR_40x_DAC1 (0x3F6) | |
1204 | #define SPR_40x_DAC2 (0x3F7) | |
363be49c | 1205 | #define SPR_BOOKE_MMUCFG (0x3F7) |
76a66253 JM |
1206 | #define SPR_L2PM (0x3F8) |
1207 | #define SPR_750_HID2 (0x3F8) | |
1208 | #define SPR_L2CR (0x3F9) | |
1209 | #define SPR_IABR2 (0x3FA) | |
1210 | #define SPR_40x_DCCR (0x3FA) | |
1211 | #define SPR_ICTC (0x3FB) | |
1212 | #define SPR_40x_ICCR (0x3FB) | |
1213 | #define SPR_THRM1 (0x3FC) | |
1214 | #define SPR_403_PBL1 (0x3FC) | |
1215 | #define SPR_SP (0x3FD) | |
1216 | #define SPR_THRM2 (0x3FD) | |
1217 | #define SPR_403_PBU1 (0x3FD) | |
1218 | #define SPR_LT (0x3FE) | |
1219 | #define SPR_THRM3 (0x3FE) | |
1220 | #define SPR_FPECR (0x3FE) | |
1221 | #define SPR_403_PBL2 (0x3FE) | |
1222 | #define SPR_PIR (0x3FF) | |
1223 | #define SPR_403_PBU2 (0x3FF) | |
1224 | #define SPR_601_HID15 (0x3FF) | |
1225 | #define SPR_E500_SVR (0x3FF) | |
79aceca5 | 1226 | |
76a66253 | 1227 | /*****************************************************************************/ |
9a64fbe4 FB |
1228 | /* Memory access type : |
1229 | * may be needed for precise access rights control and precise exceptions. | |
1230 | */ | |
79aceca5 | 1231 | enum { |
9a64fbe4 FB |
1232 | /* 1 bit to define user level / supervisor access */ |
1233 | ACCESS_USER = 0x00, | |
1234 | ACCESS_SUPER = 0x01, | |
1235 | /* Type of instruction that generated the access */ | |
1236 | ACCESS_CODE = 0x10, /* Code fetch access */ | |
1237 | ACCESS_INT = 0x20, /* Integer load/store access */ | |
1238 | ACCESS_FLOAT = 0x30, /* floating point load/store access */ | |
1239 | ACCESS_RES = 0x40, /* load/store with reservation */ | |
1240 | ACCESS_EXT = 0x50, /* external access */ | |
1241 | ACCESS_CACHE = 0x60, /* Cache manipulation */ | |
1242 | }; | |
1243 | ||
1244 | /*****************************************************************************/ | |
1245 | /* Exceptions */ | |
2be0071f FB |
1246 | #define EXCP_NONE -1 |
1247 | /* PowerPC hardware exceptions : exception vectors defined in PowerPC book 3 */ | |
1248 | #define EXCP_RESET 0x0100 /* System reset */ | |
1249 | #define EXCP_MACHINE_CHECK 0x0200 /* Machine check exception */ | |
1250 | #define EXCP_DSI 0x0300 /* Data storage exception */ | |
1251 | #define EXCP_DSEG 0x0380 /* Data segment exception */ | |
1252 | #define EXCP_ISI 0x0400 /* Instruction storage exception */ | |
1253 | #define EXCP_ISEG 0x0480 /* Instruction segment exception */ | |
1254 | #define EXCP_EXTERNAL 0x0500 /* External interruption */ | |
1255 | #define EXCP_ALIGN 0x0600 /* Alignment exception */ | |
1256 | #define EXCP_PROGRAM 0x0700 /* Program exception */ | |
1257 | #define EXCP_NO_FP 0x0800 /* Floating point unavailable exception */ | |
1258 | #define EXCP_DECR 0x0900 /* Decrementer exception */ | |
1259 | #define EXCP_HDECR 0x0980 /* Hypervisor decrementer exception */ | |
1260 | #define EXCP_SYSCALL 0x0C00 /* System call */ | |
1261 | #define EXCP_TRACE 0x0D00 /* Trace exception */ | |
1262 | #define EXCP_PERF 0x0F00 /* Performance monitor exception */ | |
1263 | /* Exceptions defined in PowerPC 32 bits programming environment manual */ | |
1264 | #define EXCP_FP_ASSIST 0x0E00 /* Floating-point assist */ | |
1265 | /* Implementation specific exceptions */ | |
1266 | /* 40x exceptions */ | |
1267 | #define EXCP_40x_PIT 0x1000 /* Programmable interval timer interrupt */ | |
1268 | #define EXCP_40x_FIT 0x1010 /* Fixed interval timer interrupt */ | |
1269 | #define EXCP_40x_WATCHDOG 0x1020 /* Watchdog timer exception */ | |
1270 | #define EXCP_40x_DTLBMISS 0x1100 /* Data TLB miss exception */ | |
1271 | #define EXCP_40x_ITLBMISS 0x1200 /* Instruction TLB miss exception */ | |
1272 | #define EXCP_40x_DEBUG 0x2000 /* Debug exception */ | |
1273 | /* 405 specific exceptions */ | |
1274 | #define EXCP_405_APU 0x0F20 /* APU unavailable exception */ | |
1275 | /* TLB assist exceptions (602/603) */ | |
1276 | #define EXCP_I_TLBMISS 0x1000 /* Instruction TLB miss */ | |
1277 | #define EXCP_DL_TLBMISS 0x1100 /* Data load TLB miss */ | |
1278 | #define EXCP_DS_TLBMISS 0x1200 /* Data store TLB miss */ | |
1279 | /* Breakpoint exceptions (602/603/604/620/740/745/750/755...) */ | |
1280 | #define EXCP_IABR 0x1300 /* Instruction address breakpoint */ | |
1281 | #define EXCP_SMI 0x1400 /* System management interrupt */ | |
1282 | /* Altivec related exceptions */ | |
1283 | #define EXCP_VPU 0x0F20 /* VPU unavailable exception */ | |
1284 | /* 601 specific exceptions */ | |
1285 | #define EXCP_601_IO 0x0600 /* IO error exception */ | |
1286 | #define EXCP_601_RUNM 0x2000 /* Run mode exception */ | |
1287 | /* 602 specific exceptions */ | |
1288 | #define EXCP_602_WATCHDOG 0x1500 /* Watchdog exception */ | |
1289 | #define EXCP_602_EMUL 0x1600 /* Emulation trap exception */ | |
1290 | /* G2 specific exceptions */ | |
1291 | #define EXCP_G2_CRIT 0x0A00 /* Critical interrupt */ | |
1292 | /* MPC740/745/750 & IBM 750 specific exceptions */ | |
1293 | #define EXCP_THRM 0x1700 /* Thermal management interrupt */ | |
1294 | /* 74xx specific exceptions */ | |
1295 | #define EXCP_74xx_VPUA 0x1600 /* VPU assist exception */ | |
1296 | /* 970FX specific exceptions */ | |
1297 | #define EXCP_970_SOFTP 0x1500 /* Soft patch exception */ | |
1298 | #define EXCP_970_MAINT 0x1600 /* Maintenance exception */ | |
1299 | #define EXCP_970_THRM 0x1800 /* Thermal exception */ | |
1300 | #define EXCP_970_VPUA 0x1700 /* VPU assist exception */ | |
0487d6a8 JM |
1301 | /* SPE related exceptions */ |
1302 | #define EXCP_NO_SPE 0x0F20 /* SPE unavailable exception */ | |
2be0071f FB |
1303 | /* End of exception vectors area */ |
1304 | #define EXCP_PPC_MAX 0x4000 | |
1305 | /* Qemu exceptions: special cases we want to stop translation */ | |
1306 | #define EXCP_MTMSR 0x11000 /* mtmsr instruction: */ | |
76a66253 | 1307 | /* may change privilege level */ |
2be0071f FB |
1308 | #define EXCP_BRANCH 0x11001 /* branch instruction */ |
1309 | #define EXCP_SYSCALL_USER 0x12000 /* System call in user mode only */ | |
1310 | #define EXCP_INTERRUPT_CRITICAL 0x13000 /* critical IRQ */ | |
1311 | ||
9a64fbe4 FB |
1312 | /* Error codes */ |
1313 | enum { | |
9a64fbe4 FB |
1314 | /* Exception subtypes for EXCP_ALIGN */ |
1315 | EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ | |
1316 | EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ | |
1317 | EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ | |
1318 | EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ | |
1319 | EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ | |
1320 | EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ | |
1321 | /* Exception subtypes for EXCP_PROGRAM */ | |
79aceca5 | 1322 | /* FP exceptions */ |
9a64fbe4 FB |
1323 | EXCP_FP = 0x10, |
1324 | EXCP_FP_OX = 0x01, /* FP overflow */ | |
1325 | EXCP_FP_UX = 0x02, /* FP underflow */ | |
1326 | EXCP_FP_ZX = 0x03, /* FP divide by zero */ | |
1327 | EXCP_FP_XX = 0x04, /* FP inexact */ | |
1328 | EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */ | |
0cfec834 | 1329 | EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */ |
9a64fbe4 FB |
1330 | EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ |
1331 | EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ | |
1332 | EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ | |
1333 | EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ | |
1334 | EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ | |
1335 | EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ | |
1336 | EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ | |
79aceca5 | 1337 | /* Invalid instruction */ |
9a64fbe4 FB |
1338 | EXCP_INVAL = 0x20, |
1339 | EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ | |
1340 | EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ | |
1341 | EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ | |
1342 | EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ | |
79aceca5 | 1343 | /* Privileged instruction */ |
9a64fbe4 FB |
1344 | EXCP_PRIV = 0x30, |
1345 | EXCP_PRIV_OPC = 0x01, | |
1346 | EXCP_PRIV_REG = 0x02, | |
79aceca5 | 1347 | /* Trap */ |
9a64fbe4 | 1348 | EXCP_TRAP = 0x40, |
79aceca5 FB |
1349 | }; |
1350 | ||
47103572 JM |
1351 | /* Hardware interruption sources: |
1352 | * all those exception can be raised simulteaneously | |
1353 | */ | |
e9df014c JM |
1354 | /* Input pins definitions */ |
1355 | enum { | |
1356 | /* 6xx bus input pins */ | |
24be5ae3 JM |
1357 | PPC6xx_INPUT_HRESET = 0, |
1358 | PPC6xx_INPUT_SRESET = 1, | |
1359 | PPC6xx_INPUT_CKSTP_IN = 2, | |
1360 | PPC6xx_INPUT_MCP = 3, | |
1361 | PPC6xx_INPUT_SMI = 4, | |
1362 | PPC6xx_INPUT_INT = 5, | |
1363 | }; | |
1364 | ||
1365 | enum { | |
e9df014c | 1366 | /* Embedded PowerPC input pins */ |
24be5ae3 JM |
1367 | PPCBookE_INPUT_HRESET = 0, |
1368 | PPCBookE_INPUT_SRESET = 1, | |
1369 | PPCBookE_INPUT_CKSTP_IN = 2, | |
1370 | PPCBookE_INPUT_MCP = 3, | |
1371 | PPCBookE_INPUT_SMI = 4, | |
1372 | PPCBookE_INPUT_INT = 5, | |
1373 | PPCBookE_INPUT_CINT = 6, | |
1374 | }; | |
1375 | ||
1376 | enum { | |
1377 | /* PowerPC 405 input pins */ | |
1378 | PPC405_INPUT_RESET_CORE = 0, | |
1379 | PPC405_INPUT_RESET_CHIP = 1, | |
1380 | PPC405_INPUT_RESET_SYS = 2, | |
1381 | PPC405_INPUT_CINT = 3, | |
1382 | PPC405_INPUT_INT = 4, | |
1383 | PPC405_INPUT_HALT = 5, | |
1384 | PPC405_INPUT_DEBUG = 6, | |
e9df014c JM |
1385 | }; |
1386 | ||
d0dfae6e JM |
1387 | enum { |
1388 | /* PowerPC 970 input pins */ | |
1389 | PPC970_INPUT_HRESET = 0, | |
1390 | PPC970_INPUT_SRESET = 1, | |
1391 | PPC970_INPUT_CKSTP = 2, | |
1392 | PPC970_INPUT_TBEN = 3, | |
1393 | PPC970_INPUT_MCP = 4, | |
1394 | PPC970_INPUT_INT = 5, | |
1395 | PPC970_INPUT_THINT = 6, | |
1396 | }; | |
1397 | ||
e9df014c | 1398 | /* Hardware exceptions definitions */ |
47103572 | 1399 | enum { |
e9df014c JM |
1400 | /* External hardware exception sources */ |
1401 | PPC_INTERRUPT_RESET = 0, /* Reset exception */ | |
1402 | PPC_INTERRUPT_MCK = 1, /* Machine check exception */ | |
1403 | PPC_INTERRUPT_EXT = 2, /* External interrupt */ | |
1404 | PPC_INTERRUPT_SMI = 3, /* System management interrupt */ | |
1405 | PPC_INTERRUPT_CEXT = 4, /* Critical external interrupt */ | |
1406 | PPC_INTERRUPT_DEBUG = 5, /* External debug exception */ | |
d0dfae6e | 1407 | PPC_INTERRUPT_THERM = 6, /* Thermal exception */ |
e9df014c | 1408 | /* Internal hardware exception sources */ |
d0dfae6e JM |
1409 | PPC_INTERRUPT_DECR = 7, /* Decrementer exception */ |
1410 | PPC_INTERRUPT_HDECR = 8, /* Hypervisor decrementer exception */ | |
1411 | PPC_INTERRUPT_PIT = 9, /* Programmable inteval timer interrupt */ | |
1412 | PPC_INTERRUPT_FIT = 10, /* Fixed interval timer interrupt */ | |
1413 | PPC_INTERRUPT_WDT = 11, /* Watchdog timer interrupt */ | |
47103572 JM |
1414 | }; |
1415 | ||
9a64fbe4 FB |
1416 | /*****************************************************************************/ |
1417 | ||
79aceca5 | 1418 | #endif /* !defined (__CPU_PPC_H__) */ |