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ppc: Convert GPR moves to TCG
[qemu.git] / target-ppc / cpu.h
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation cpu definitions for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#if !defined (__CPU_PPC_H__)
21#define __CPU_PPC_H__
22
3fc6c082 23#include "config.h"
de270b3c 24#include <inttypes.h>
3fc6c082 25
a4f30719
JM		 26//#define PPC_EMULATE_32BITS_HYPV
27
76a66253 28#if defined (TARGET_PPC64)
3cd7d1dd 29/* PowerPC 64 definitions */
76a66253 30typedef uint64_t ppc_gpr_t;
d9d7210c 31#define TARGET_LONG_BITS 64
35cdaad6 32#define TARGET_PAGE_BITS 12
3cd7d1dd
JM		 33
34#else /* defined (TARGET_PPC64) */
35/* PowerPC 32 definitions */
76a66253 36typedef uint32_t ppc_gpr_t;
d9d7210c 37#define TARGET_LONG_BITS 32
3cd7d1dd
JM		 38
39#if defined(TARGET_PPCEMB)
40/* Specific definitions for PowerPC embedded */
41/* BookE have 36 bits physical address space */
42#define TARGET_PHYS_ADDR_BITS 64
43#if defined(CONFIG_USER_ONLY)
44/* It looks like a lot of Linux programs assume page size
45 * is 4kB long. This is evil, but we have to deal with it...
46 */
35cdaad6 47#define TARGET_PAGE_BITS 12
3cd7d1dd
JM		 48#else /* defined(CONFIG_USER_ONLY) */
49/* Pages can be 1 kB small */
50#define TARGET_PAGE_BITS 10
51#endif /* defined(CONFIG_USER_ONLY) */
52#else /* defined(TARGET_PPCEMB) */
53/* "standard" PowerPC 32 definitions */
54#define TARGET_PAGE_BITS 12
55#endif /* defined(TARGET_PPCEMB) */
56
57#endif /* defined (TARGET_PPC64) */
3cf1e035 58
79aceca5
FB		 59#include "cpu-defs.h"
60
6b542af7 61#define REGX "%016" PRIx64
e96efcfc
JM		 62#define ADDRX TARGET_FMT_lx
63#define PADDRX TARGET_FMT_plx
64
79aceca5
FB		 65#include <setjmp.h>
66
4ecc3190
FB		 67#include "softfloat.h"
68
1fddef4b
FB		 69#define TARGET_HAS_ICE 1
70
76a66253
JM		 71#if defined (TARGET_PPC64)
72#define ELF_MACHINE EM_PPC64
73#else
74#define ELF_MACHINE EM_PPC
75#endif
9042c0e2 76
3fc6c082 77/*****************************************************************************/
a750fc0b 78/* MMU model */
7820dbf3
JM		 79typedef enum powerpc_mmu_t powerpc_mmu_t;
80enum powerpc_mmu_t {
add78955 81 POWERPC_MMU_UNKNOWN = 0x00000000,
a750fc0b 82 /* Standard 32 bits PowerPC MMU */
add78955 83 POWERPC_MMU_32B = 0x00000001,
a750fc0b 84 /* PowerPC 6xx MMU with software TLB */
add78955 85 POWERPC_MMU_SOFT_6xx = 0x00000002,
a750fc0b 86 /* PowerPC 74xx MMU with software TLB */
add78955 87 POWERPC_MMU_SOFT_74xx = 0x00000003,
a750fc0b 88 /* PowerPC 4xx MMU with software TLB */
add78955 89 POWERPC_MMU_SOFT_4xx = 0x00000004,
a750fc0b 90 /* PowerPC 4xx MMU with software TLB and zones protections */
add78955 91 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
b4095fed 92 /* PowerPC MMU in real mode only */
add78955 93 POWERPC_MMU_REAL = 0x00000006,
b4095fed 94 /* Freescale MPC8xx MMU model */
add78955 95 POWERPC_MMU_MPC8xx = 0x00000007,
a750fc0b 96 /* BookE MMU model */
add78955 97 POWERPC_MMU_BOOKE = 0x00000008,
a750fc0b 98 /* BookE FSL MMU model */
add78955 99 POWERPC_MMU_BOOKE_FSL = 0x00000009,
faadf50e 100 /* PowerPC 601 MMU model (specific BATs format) */
add78955 101 POWERPC_MMU_601 = 0x0000000A,
00af685f 102#if defined(TARGET_PPC64)
add78955 103#define POWERPC_MMU_64 0x00010000
12de9a39 104 /* 64 bits PowerPC MMU */
add78955
JM		 105 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
106 /* 620 variant (no segment exceptions) */
107 POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002,
00af685f 108#endif /* defined(TARGET_PPC64) */
3fc6c082
FB		 109};
110
111/*****************************************************************************/
a750fc0b 112/* Exception model */
7820dbf3
JM		 113typedef enum powerpc_excp_t powerpc_excp_t;
114enum powerpc_excp_t {
a750fc0b 115 POWERPC_EXCP_UNKNOWN = 0,
3fc6c082 116 /* Standard PowerPC exception model */
a750fc0b 117 POWERPC_EXCP_STD,
2662a059 118 /* PowerPC 40x exception model */
a750fc0b 119 POWERPC_EXCP_40x,
2662a059 120 /* PowerPC 601 exception model */
a750fc0b 121 POWERPC_EXCP_601,
2662a059 122 /* PowerPC 602 exception model */
a750fc0b 123 POWERPC_EXCP_602,
2662a059 124 /* PowerPC 603 exception model */
a750fc0b
JM		 125 POWERPC_EXCP_603,
126 /* PowerPC 603e exception model */
127 POWERPC_EXCP_603E,
128 /* PowerPC G2 exception model */
129 POWERPC_EXCP_G2,
2662a059 130 /* PowerPC 604 exception model */
a750fc0b 131 POWERPC_EXCP_604,
2662a059 132 /* PowerPC 7x0 exception model */
a750fc0b 133 POWERPC_EXCP_7x0,
2662a059 134 /* PowerPC 7x5 exception model */
a750fc0b 135 POWERPC_EXCP_7x5,
2662a059 136 /* PowerPC 74xx exception model */
a750fc0b 137 POWERPC_EXCP_74xx,
2662a059 138 /* BookE exception model */
a750fc0b 139 POWERPC_EXCP_BOOKE,
00af685f
JM		 140#if defined(TARGET_PPC64)
141 /* PowerPC 970 exception model */
142 POWERPC_EXCP_970,
143#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 144};
145
e1833e1f
JM		 146/*****************************************************************************/
147/* Exception vectors definitions */
148enum {
149 POWERPC_EXCP_NONE = -1,
150 /* The 64 first entries are used by the PowerPC embedded specification */
151 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
152 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
153 POWERPC_EXCP_DSI = 2, /* Data storage exception */
154 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
155 POWERPC_EXCP_EXTERNAL = 4, /* External input */
156 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
157 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
158 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
159 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
160 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
161 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
162 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
163 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
b4095fed
JM		 164 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
165 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
e1833e1f
JM		 166 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
167 /* Vectors 16 to 31 are reserved */
e1833e1f
JM		 168 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
169 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
170 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
171 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
172 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
173 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
e1833e1f
JM		 174 /* Vectors 38 to 63 are reserved */
175 /* Exceptions defined in the PowerPC server specification */
176 POWERPC_EXCP_RESET = 64, /* System reset exception */
e1833e1f
JM		 177 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
178 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
e1833e1f 179 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
e1833e1f 180 POWERPC_EXCP_TRACE = 68, /* Trace exception */
e1833e1f
JM		 181 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
182 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
183 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
184 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
e1833e1f
JM		 185 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
186 /* 40x specific exceptions */
187 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
188 /* 601 specific exceptions */
189 POWERPC_EXCP_IO = 75, /* IO error exception */
190 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
191 /* 602 specific exceptions */
192 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
193 /* 602/603 specific exceptions */
b4095fed 194 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
e1833e1f
JM		 195 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
196 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
197 /* Exceptions available on most PowerPC */
198 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
b4095fed
JM		 199 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
200 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
201 POWERPC_EXCP_SMI = 84, /* System management interrupt */
202 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
e1833e1f 203 /* 7xx/74xx specific exceptions */
b4095fed 204 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
e1833e1f 205 /* 74xx specific exceptions */
b4095fed 206 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
e1833e1f 207 /* 970FX specific exceptions */
b4095fed
JM		 208 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
209 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
210 /* Freescale embeded cores specific exceptions */
211 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
212 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
213 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
214 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
e1833e1f
JM		 215 /* EOL */
216 POWERPC_EXCP_NB = 96,
217 /* Qemu exceptions: used internally during code translation */
218 POWERPC_EXCP_STOP = 0x200, /* stop translation */
219 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
220 /* Qemu exceptions: special cases we want to stop translation */
221 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
222 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
223};
224
e1833e1f
JM		 225/* Exceptions error codes */
226enum {
227 /* Exception subtypes for POWERPC_EXCP_ALIGN */
228 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
229 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
230 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
231 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
232 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
233 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
234 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
235 /* FP exceptions */
236 POWERPC_EXCP_FP = 0x10,
237 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
238 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
239 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
240 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
7c58044c 241 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
e1833e1f
JM		 242 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
243 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
244 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
245 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
246 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
247 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
248 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
249 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
250 /* Invalid instruction */
251 POWERPC_EXCP_INVAL = 0x20,
252 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
253 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
254 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
255 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
256 /* Privileged instruction */
257 POWERPC_EXCP_PRIV = 0x30,
258 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
259 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
260 /* Trap */
261 POWERPC_EXCP_TRAP = 0x40,
262};
263
a750fc0b
JM		 264/*****************************************************************************/
265/* Input pins model */
7820dbf3
JM		 266typedef enum powerpc_input_t powerpc_input_t;
267enum powerpc_input_t {
a750fc0b 268 PPC_FLAGS_INPUT_UNKNOWN = 0,
2662a059 269 /* PowerPC 6xx bus */
a750fc0b 270 PPC_FLAGS_INPUT_6xx,
2662a059 271 /* BookE bus */
a750fc0b
JM		 272 PPC_FLAGS_INPUT_BookE,
273 /* PowerPC 405 bus */
274 PPC_FLAGS_INPUT_405,
2662a059 275 /* PowerPC 970 bus */
a750fc0b
JM		 276 PPC_FLAGS_INPUT_970,
277 /* PowerPC 401 bus */
278 PPC_FLAGS_INPUT_401,
b4095fed
JM		 279 /* Freescale RCPU bus */
280 PPC_FLAGS_INPUT_RCPU,
3fc6c082
FB		 281};
282
a750fc0b 283#define PPC_INPUT(env) (env->bus_model)
3fc6c082 284
be147d08 285/*****************************************************************************/
3fc6c082 286typedef struct ppc_def_t ppc_def_t;
a750fc0b 287typedef struct opc_handler_t opc_handler_t;
79aceca5 288
3fc6c082
FB		 289/*****************************************************************************/
290/* Types used to describe some PowerPC registers */
291typedef struct CPUPPCState CPUPPCState;
9fddaa0c 292typedef struct ppc_tb_t ppc_tb_t;
3fc6c082
FB		 293typedef struct ppc_spr_t ppc_spr_t;
294typedef struct ppc_dcr_t ppc_dcr_t;
a9d9eb8f 295typedef union ppc_avr_t ppc_avr_t;
1d0a48fb 296typedef union ppc_tlb_t ppc_tlb_t;
76a66253 297
3fc6c082
FB		 298/* SPR access micro-ops generations callbacks */
299struct ppc_spr_t {
300 void (*uea_read)(void *opaque, int spr_num);
301 void (*uea_write)(void *opaque, int spr_num);
76a66253 302#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 303 void (*oea_read)(void *opaque, int spr_num);
304 void (*oea_write)(void *opaque, int spr_num);
be147d08
JM		 305 void (*hea_read)(void *opaque, int spr_num);
306 void (*hea_write)(void *opaque, int spr_num);
76a66253 307#endif
3fc6c082
FB		 308 const unsigned char *name;
309};
310
311/* Altivec registers (128 bits) */
a9d9eb8f
JM		 312union ppc_avr_t {
313 uint8_t u8[16];
314 uint16_t u16[8];
315 uint32_t u32[4];
316 uint64_t u64[2];
3fc6c082 317};
9fddaa0c 318
3fc6c082 319/* Software TLB cache */
1d0a48fb
JM		 320typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
321struct ppc6xx_tlb_t {
76a66253
JM		 322 target_ulong pte0;
323 target_ulong pte1;
324 target_ulong EPN;
1d0a48fb
JM		 325};
326
327typedef struct ppcemb_tlb_t ppcemb_tlb_t;
328struct ppcemb_tlb_t {
c55e9aef 329 target_phys_addr_t RPN;
1d0a48fb 330 target_ulong EPN;
76a66253 331 target_ulong PID;
c55e9aef
JM		 332 target_ulong size;
333 uint32_t prot;
334 uint32_t attr; /* Storage attributes */
1d0a48fb
JM		 335};
336
337union ppc_tlb_t {
338 ppc6xx_tlb_t tlb6;
339 ppcemb_tlb_t tlbe;
3fc6c082
FB		 340};
341
342/*****************************************************************************/
343/* Machine state register bits definition */
76a66253 344#define MSR_SF 63 /* Sixty-four-bit mode hflags */
bd928eba 345#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
3fc6c082 346#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
a4f30719 347#define MSR_SHV 60 /* hypervisor state hflags */
363be49c
JM		 348#define MSR_CM 31 /* Computation mode for BookE hflags */
349#define MSR_ICM 30 /* Interrupt computation mode for BookE */
a4f30719 350#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
363be49c 351#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
d26bfc9a
JM		 352#define MSR_VR 25 /* altivec available x hflags */
353#define MSR_SPE 25 /* SPE enable for BookE x hflags */
76a66253
JM		 354#define MSR_AP 23 /* Access privilege state on 602 hflags */
355#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
3fc6c082 356#define MSR_KEY 19 /* key bit on 603e */
25ba3a68 357#define MSR_POW 18 /* Power management */
d26bfc9a
JM		 358#define MSR_TGPR 17 /* TGPR usage on 602/603 x */
359#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
3fc6c082
FB		 360#define MSR_ILE 16 /* Interrupt little-endian mode */
361#define MSR_EE 15 /* External interrupt enable */
76a66253
JM		 362#define MSR_PR 14 /* Problem state hflags */
363#define MSR_FP 13 /* Floating point available hflags */
3fc6c082 364#define MSR_ME 12 /* Machine check interrupt enable */
76a66253 365#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
d26bfc9a
JM		 366#define MSR_SE 10 /* Single-step trace enable x hflags */
367#define MSR_DWE 10 /* Debug wait enable on 405 x */
368#define MSR_UBLE 10 /* User BTB lock enable on e500 x */
369#define MSR_BE 9 /* Branch trace enable x hflags */
370#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
76a66253 371#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
3fc6c082 372#define MSR_AL 7 /* AL bit on POWER */
0411a972 373#define MSR_EP 6 /* Exception prefix on 601 */
3fc6c082 374#define MSR_IR 5 /* Instruction relocate */
3fc6c082 375#define MSR_DR 4 /* Data relocate */
25ba3a68 376#define MSR_PE 3 /* Protection enable on 403 */
d26bfc9a
JM		 377#define MSR_PX 2 /* Protection exclusive on 403 x */
378#define MSR_PMM 2 /* Performance monitor mark on POWER x */
379#define MSR_RI 1 /* Recoverable interrupt 1 */
380#define MSR_LE 0 /* Little-endian mode 1 hflags */
0411a972
JM		 381
382#define msr_sf ((env->msr >> MSR_SF) & 1)
383#define msr_isf ((env->msr >> MSR_ISF) & 1)
a4f30719 384#define msr_shv ((env->msr >> MSR_SHV) & 1)
0411a972
JM		 385#define msr_cm ((env->msr >> MSR_CM) & 1)
386#define msr_icm ((env->msr >> MSR_ICM) & 1)
a4f30719 387#define msr_thv ((env->msr >> MSR_THV) & 1)
0411a972
JM		 388#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
389#define msr_vr ((env->msr >> MSR_VR) & 1)
f9320410 390#define msr_spe ((env->msr >> MSR_SPE) & 1)
0411a972
JM		 391#define msr_ap ((env->msr >> MSR_AP) & 1)
392#define msr_sa ((env->msr >> MSR_SA) & 1)
393#define msr_key ((env->msr >> MSR_KEY) & 1)
394#define msr_pow ((env->msr >> MSR_POW) & 1)
395#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
396#define msr_ce ((env->msr >> MSR_CE) & 1)
397#define msr_ile ((env->msr >> MSR_ILE) & 1)
398#define msr_ee ((env->msr >> MSR_EE) & 1)
399#define msr_pr ((env->msr >> MSR_PR) & 1)
400#define msr_fp ((env->msr >> MSR_FP) & 1)
401#define msr_me ((env->msr >> MSR_ME) & 1)
402#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
403#define msr_se ((env->msr >> MSR_SE) & 1)
404#define msr_dwe ((env->msr >> MSR_DWE) & 1)
405#define msr_uble ((env->msr >> MSR_UBLE) & 1)
406#define msr_be ((env->msr >> MSR_BE) & 1)
407#define msr_de ((env->msr >> MSR_DE) & 1)
408#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
409#define msr_al ((env->msr >> MSR_AL) & 1)
410#define msr_ep ((env->msr >> MSR_EP) & 1)
411#define msr_ir ((env->msr >> MSR_IR) & 1)
412#define msr_dr ((env->msr >> MSR_DR) & 1)
413#define msr_pe ((env->msr >> MSR_PE) & 1)
414#define msr_px ((env->msr >> MSR_PX) & 1)
415#define msr_pmm ((env->msr >> MSR_PMM) & 1)
416#define msr_ri ((env->msr >> MSR_RI) & 1)
417#define msr_le ((env->msr >> MSR_LE) & 1)
a4f30719
JM		 418/* Hypervisor bit is more specific */
419#if defined(TARGET_PPC64)
420#define MSR_HVB (1ULL << MSR_SHV)
421#define msr_hv msr_shv
422#else
423#if defined(PPC_EMULATE_32BITS_HYPV)
424#define MSR_HVB (1ULL << MSR_THV)
425#define msr_hv msr_thv
a4f30719
JM		 426#else
427#define MSR_HVB (0ULL)
428#define msr_hv (0)
429#endif
430#endif
79aceca5 431
d26bfc9a 432enum {
4018bae9 433 POWERPC_FLAG_NONE = 0x00000000,
d26bfc9a 434 /* Flag for MSR bit 25 signification (VRE/SPE) */
4018bae9
JM		 435 POWERPC_FLAG_SPE = 0x00000001,
436 POWERPC_FLAG_VRE = 0x00000002,
d26bfc9a 437 /* Flag for MSR bit 17 signification (TGPR/CE) */
4018bae9
JM		 438 POWERPC_FLAG_TGPR = 0x00000004,
439 POWERPC_FLAG_CE = 0x00000008,
d26bfc9a 440 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
4018bae9
JM		 441 POWERPC_FLAG_SE = 0x00000010,
442 POWERPC_FLAG_DWE = 0x00000020,
443 POWERPC_FLAG_UBLE = 0x00000040,
d26bfc9a 444 /* Flag for MSR bit 9 signification (BE/DE) */
4018bae9
JM		 445 POWERPC_FLAG_BE = 0x00000080,
446 POWERPC_FLAG_DE = 0x00000100,
a4f30719 447 /* Flag for MSR bit 2 signification (PX/PMM) */
4018bae9
JM		 448 POWERPC_FLAG_PX = 0x00000200,
449 POWERPC_FLAG_PMM = 0x00000400,
450 /* Flag for special features */
451 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
452 POWERPC_FLAG_RTC_CLK = 0x00010000,
453 POWERPC_FLAG_BUS_CLK = 0x00020000,
d26bfc9a
JM		 454};
455
7c58044c
JM		 456/*****************************************************************************/
457/* Floating point status and control register */
458#define FPSCR_FX 31 /* Floating-point exception summary */
459#define FPSCR_FEX 30 /* Floating-point enabled exception summary */
460#define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
461#define FPSCR_OX 28 /* Floating-point overflow exception */
462#define FPSCR_UX 27 /* Floating-point underflow exception */
463#define FPSCR_ZX 26 /* Floating-point zero divide exception */
464#define FPSCR_XX 25 /* Floating-point inexact exception */
465#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
466#define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
467#define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
468#define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
469#define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
470#define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
471#define FPSCR_FR 18 /* Floating-point fraction rounded */
472#define FPSCR_FI 17 /* Floating-point fraction inexact */
473#define FPSCR_C 16 /* Floating-point result class descriptor */
474#define FPSCR_FL 15 /* Floating-point less than or negative */
475#define FPSCR_FG 14 /* Floating-point greater than or negative */
476#define FPSCR_FE 13 /* Floating-point equal or zero */
477#define FPSCR_FU 12 /* Floating-point unordered or NaN */
478#define FPSCR_FPCC 12 /* Floating-point condition code */
479#define FPSCR_FPRF 12 /* Floating-point result flags */
480#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
481#define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
482#define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
483#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
484#define FPSCR_OE 6 /* Floating-point overflow exception enable */
485#define FPSCR_UE 5 /* Floating-point undeflow exception enable */
486#define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
487#define FPSCR_XE 3 /* Floating-point inexact exception enable */
488#define FPSCR_NI 2 /* Floating-point non-IEEE mode */
489#define FPSCR_RN1 1
490#define FPSCR_RN 0 /* Floating-point rounding control */
491#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
492#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
493#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
494#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
495#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
496#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
497#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
498#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
499#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
500#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
501#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
502#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
503#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
504#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
505#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
506#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
507#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
508#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
509#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
510#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
511#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
512#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
513#define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
514/* Invalid operation exception summary */
515#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
516 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
517 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
518 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
519 (1 << FPSCR_VXCVI)))
520/* exception summary */
521#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
522/* enabled exception summary */
523#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
524 0x1F)
525
526/*****************************************************************************/
527/* The whole PowerPC CPU context */
6ebbf390 528#define NB_MMU_MODES 3
6ebbf390 529
3fc6c082
FB		 530struct CPUPPCState {
531 /* First are the most commonly used resources
532 * during translated code execution
533 */
f78fb44e 534#if (TARGET_LONG_BITS > HOST_LONG_BITS) || !defined(TARGET_PPC64)
3fc6c082 535 /* temporary fixed-point registers
57c26279 536 * used to emulate 64 bits registers on 32 bits hosts
5fafdf24 537 */
57c26279 538 uint64_t t0, t1, t2;
3fc6c082 539#endif
a9d9eb8f 540 ppc_avr_t avr0, avr1, avr2;
d9bce9d9 541
79aceca5 542 /* general purpose registers */
76a66253 543 ppc_gpr_t gpr[32];
65d6c0f3 544#if !defined(TARGET_PPC64)
3cd7d1dd
JM		 545 /* Storage for GPR MSB, used by the SPE extension */
546 ppc_gpr_t gprh[32];
547#endif
3fc6c082
FB		 548 /* LR */
549 target_ulong lr;
550 /* CTR */
551 target_ulong ctr;
552 /* condition register */
553 uint8_t crf[8];
79aceca5 554 /* XER */
3fc6c082
FB		 555 /* XXX: We use only 5 fields, but we want to keep the structure aligned */
556 uint8_t xer[8];
79aceca5 557 /* Reservation address */
3fc6c082
FB		 558 target_ulong reserve;
559
560 /* Those ones are used in supervisor mode only */
79aceca5 561 /* machine state register */
0411a972 562 target_ulong msr;
3fc6c082 563 /* temporary general purpose registers */
76a66253 564 ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
3fc6c082
FB		 565
566 /* Floating point execution context */
76a66253 567 /* temporary float registers */
4ecc3190
FB		 568 float64 ft0;
569 float64 ft1;
570 float64 ft2;
571 float_status fp_status;
3fc6c082
FB		 572 /* floating point registers */
573 float64 fpr[32];
574 /* floating point status and control register */
7c58044c 575 uint32_t fpscr;
4ecc3190 576
a316d335
FB		 577 CPU_COMMON
578
ac9eb073
FB		 579 int access_type; /* when a memory exception occurs, the access
580 type is stored here */
a541f297 581
f2e63a42
JM		 582 /* MMU context - only relevant for full system emulation */
583#if !defined(CONFIG_USER_ONLY)
584#if defined(TARGET_PPC64)
3fc6c082
FB		 585 /* Address space register */
586 target_ulong asr;
f2e63a42
JM		 587 /* PowerPC 64 SLB area */
588 int slb_nr;
589#endif
3fc6c082
FB		 590 /* segment registers */
591 target_ulong sdr1;
592 target_ulong sr[16];
593 /* BATs */
594 int nb_BATs;
595 target_ulong DBAT[2][8];
596 target_ulong IBAT[2][8];
f2e63a42
JM		 597 /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
598 int nb_tlb; /* Total number of TLB */
599 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
600 int nb_ways; /* Number of ways in the TLB set */
601 int last_way; /* Last used way used to allocate TLB in a LRU way */
602 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
603 int nb_pids; /* Number of available PID registers */
604 ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
605 /* 403 dedicated access protection registers */
606 target_ulong pb[4];
607#endif
9fddaa0c 608
3fc6c082
FB		 609 /* Other registers */
610 /* Special purpose registers */
611 target_ulong spr[1024];
f2e63a42 612 ppc_spr_t spr_cb[1024];
3fc6c082
FB		 613 /* Altivec registers */
614 ppc_avr_t avr[32];
615 uint32_t vscr;
d9bce9d9
JM		 616 /* SPE registers */
617 ppc_gpr_t spe_acc;
0487d6a8 618 float_status spe_status;
d9bce9d9 619 uint32_t spe_fscr;
3fc6c082
FB		 620
621 /* Internal devices resources */
9fddaa0c
FB		 622 /* Time base and decrementer */
623 ppc_tb_t *tb_env;
3fc6c082 624 /* Device control registers */
3fc6c082
FB		 625 ppc_dcr_t *dcr_env;
626
d63001d1
JM		 627 int dcache_line_size;
628 int icache_line_size;
629
3fc6c082
FB		 630 /* Those resources are used during exception processing */
631 /* CPU model definition */
a750fc0b 632 target_ulong msr_mask;
7820dbf3
JM		 633 powerpc_mmu_t mmu_model;
634 powerpc_excp_t excp_model;
635 powerpc_input_t bus_model;
237c0af0 636 int bfd_mach;
3fc6c082
FB		 637 uint32_t flags;
638
3fc6c082 639 int error_code;
47103572 640 uint32_t pending_interrupts;
e9df014c
JM		 641#if !defined(CONFIG_USER_ONLY)
642 /* This is the IRQ controller, which is implementation dependant
643 * and only relevant when emulating a complete machine.
644 */
645 uint32_t irq_input_state;
646 void **irq_inputs;
e1833e1f
JM		 647 /* Exception vectors */
648 target_ulong excp_vectors[POWERPC_EXCP_NB];
649 target_ulong excp_prefix;
650 target_ulong ivor_mask;
651 target_ulong ivpr_mask;
d63001d1 652 target_ulong hreset_vector;
e9df014c 653#endif
3fc6c082
FB		 654
655 /* Those resources are used only during code translation */
656 /* Next instruction pointer */
657 target_ulong nip;
f2e63a42 658
3fc6c082
FB		 659 /* opcode handlers */
660 opc_handler_t *opcodes[0x40];
661
662 /* Those resources are used only in Qemu core */
056401ea
JM		 663 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
664 target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
6ebbf390 665 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
3fc6c082 666
9fddaa0c
FB		 667 /* Power management */
668 int power_mode;
cd346349 669 int (*check_pow)(CPUPPCState *env);
a541f297 670
6d506e6d
FB		 671 /* temporary hack to handle OSI calls (only used if non NULL) */
672 int (*osi_call)(struct CPUPPCState *env);
3fc6c082 673};
79aceca5 674
76a66253
JM		 675/* Context used internally during MMU translations */
676typedef struct mmu_ctx_t mmu_ctx_t;
677struct mmu_ctx_t {
678 target_phys_addr_t raddr; /* Real address */
679 int prot; /* Protection bits */
680 target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
681 target_ulong ptem; /* Virtual segment ID | API */
682 int key; /* Access key */
b227a8e9 683 int nx; /* Non-execute area */
76a66253
JM		 684};
685
3fc6c082 686/*****************************************************************************/
aaed909a 687CPUPPCState *cpu_ppc_init (const char *cpu_model);
2e70f6ef 688void ppc_translate_init(void);
36081602
JM		 689int cpu_ppc_exec (CPUPPCState *s);
690void cpu_ppc_close (CPUPPCState *s);
79aceca5
FB		 691/* you can call this signal handler from your SIGBUS and SIGSEGV
692 signal handlers to inform the virtual CPU of exceptions. non zero
693 is returned if the signal was handled by the virtual CPU. */
36081602
JM		 694int cpu_ppc_signal_handler (int host_signum, void *pinfo,
695 void *puc);
79aceca5 696
a541f297 697void do_interrupt (CPUPPCState *env);
e9df014c 698void ppc_hw_interrupt (CPUPPCState *env);
36081602 699void cpu_loop_exit (void);
a541f297 700
9a64fbe4 701void dump_stack (CPUPPCState *env);
a541f297 702
76a66253 703#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 704target_ulong do_load_ibatu (CPUPPCState *env, int nr);
705target_ulong do_load_ibatl (CPUPPCState *env, int nr);
706void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
707void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
708target_ulong do_load_dbatu (CPUPPCState *env, int nr);
709target_ulong do_load_dbatl (CPUPPCState *env, int nr);
710void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
711void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
056401ea
JM		 712void do_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);
713void do_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);
3fc6c082
FB		 714target_ulong do_load_sdr1 (CPUPPCState *env);
715void do_store_sdr1 (CPUPPCState *env, target_ulong value);
d9bce9d9
JM		 716#if defined(TARGET_PPC64)
717target_ulong ppc_load_asr (CPUPPCState *env);
718void ppc_store_asr (CPUPPCState *env, target_ulong value);
12de9a39
JM		 719target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
720void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs);
721#endif /* defined(TARGET_PPC64) */
722#if 0 // Unused
3fc6c082 723target_ulong do_load_sr (CPUPPCState *env, int srnum);
76a66253 724#endif
12de9a39
JM		 725void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
726#endif /* !defined(CONFIG_USER_ONLY) */
bfa1e5cf
JM		 727target_ulong ppc_load_xer (CPUPPCState *env);
728void ppc_store_xer (CPUPPCState *env, target_ulong value);
0411a972 729void ppc_store_msr (CPUPPCState *env, target_ulong value);
3fc6c082 730
0a032cbe 731void cpu_ppc_reset (void *opaque);
a541f297 732
3fc6c082 733void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
aaed909a
FB		 734
735const ppc_def_t *cpu_ppc_find_by_name (const unsigned char *name);
aaed909a 736int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
85c4adf6 737
9fddaa0c
FB		 738/* Time-base and decrementer management */
739#ifndef NO_CPU_IO_DEFS
740uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
741uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
742void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
743void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
a062e36c
JM		 744uint32_t cpu_ppc_load_atbl (CPUPPCState *env);
745uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
746void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
747void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
9fddaa0c
FB		 748uint32_t cpu_ppc_load_decr (CPUPPCState *env);
749void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
58a7d328
JM		 750uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
751void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
752uint64_t cpu_ppc_load_purr (CPUPPCState *env);
753void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
d9bce9d9
JM		 754uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
755uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
756#if !defined(CONFIG_USER_ONLY)
757void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
758void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
759target_ulong load_40x_pit (CPUPPCState *env);
760void store_40x_pit (CPUPPCState *env, target_ulong val);
8ecc7913 761void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
c294fc58 762void store_40x_sler (CPUPPCState *env, uint32_t val);
d9bce9d9
JM		 763void store_booke_tcr (CPUPPCState *env, target_ulong val);
764void store_booke_tsr (CPUPPCState *env, target_ulong val);
0a032cbe 765void ppc_tlb_invalidate_all (CPUPPCState *env);
daf4f96e
JM		 766void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
767#if defined(TARGET_PPC64)
768void ppc_slb_invalidate_all (CPUPPCState *env);
769void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
770#endif
36081602 771int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
d9bce9d9 772#endif
9fddaa0c 773#endif
79aceca5 774
6b542af7
JM		 775static always_inline uint64_t ppc_dump_gpr (CPUPPCState *env, int gprn)
776{
777 uint64_t gprv;
778
779 gprv = env->gpr[gprn];
780#if !defined(TARGET_PPC64)
781 if (env->flags & POWERPC_FLAG_SPE) {
782 /* If the CPU implements the SPE extension, we have to get the
783 * high bits of the GPR from the gprh storage area
784 */
785 gprv &= 0xFFFFFFFFULL;
786 gprv |= (uint64_t)env->gprh[gprn] << 32;
787 }
788#endif
789
790 return gprv;
791}
792
2e719ba3
JM		 793/* Device control registers */
794int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
795int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
796
9467d44c
TS		 797#define CPUState CPUPPCState
798#define cpu_init cpu_ppc_init
799#define cpu_exec cpu_ppc_exec
800#define cpu_gen_code cpu_ppc_gen_code
801#define cpu_signal_handler cpu_ppc_signal_handler
c732abe2 802#define cpu_list ppc_cpu_list
9467d44c 803
b3c7724c
PB		 804#define CPU_SAVE_VERSION 3
805
6ebbf390
JM		 806/* MMU modes definitions */
807#define MMU_MODE0_SUFFIX _user
808#define MMU_MODE1_SUFFIX _kernel
6ebbf390 809#define MMU_MODE2_SUFFIX _hypv
6ebbf390
JM		 810#define MMU_USER_IDX 0
811static inline int cpu_mmu_index (CPUState *env)
812{
813 return env->mmu_idx;
814}
815
6e68e076
PB		 816#if defined(CONFIG_USER_ONLY)
817static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
818{
819 int i;
f8ed7070 820 if (newsp)
6e68e076
PB		 821 env->gpr[1] = newsp;
822 for (i = 7; i < 32; i++)
823 env->gpr[i] = 0;
824}
825#endif
826
2e70f6ef
PB		 827#define CPU_PC_FROM_TB(env, tb) env->nip = tb->pc
828
79aceca5
FB		 829#include "cpu-all.h"
830
3fc6c082
FB		 831/*****************************************************************************/
832/* Registers definitions */
79aceca5
FB		 833#define XER_SO 31
834#define XER_OV 30
835#define XER_CA 29
3fc6c082 836#define XER_CMP 8
36081602 837#define XER_BC 0
3fc6c082
FB		 838#define xer_so env->xer[4]
839#define xer_ov env->xer[6]
840#define xer_ca env->xer[2]
841#define xer_cmp env->xer[1]
36081602 842#define xer_bc env->xer[0]
79aceca5 843
3fc6c082 844/* SPR definitions */
80d11f44
JM		 845#define SPR_MQ (0x000)
846#define SPR_XER (0x001)
847#define SPR_601_VRTCU (0x004)
848#define SPR_601_VRTCL (0x005)
849#define SPR_601_UDECR (0x006)
850#define SPR_LR (0x008)
851#define SPR_CTR (0x009)
852#define SPR_DSISR (0x012)
853#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
854#define SPR_601_RTCU (0x014)
855#define SPR_601_RTCL (0x015)
856#define SPR_DECR (0x016)
857#define SPR_SDR1 (0x019)
858#define SPR_SRR0 (0x01A)
859#define SPR_SRR1 (0x01B)
860#define SPR_AMR (0x01D)
861#define SPR_BOOKE_PID (0x030)
862#define SPR_BOOKE_DECAR (0x036)
863#define SPR_BOOKE_CSRR0 (0x03A)
864#define SPR_BOOKE_CSRR1 (0x03B)
865#define SPR_BOOKE_DEAR (0x03D)
866#define SPR_BOOKE_ESR (0x03E)
867#define SPR_BOOKE_IVPR (0x03F)
868#define SPR_MPC_EIE (0x050)
869#define SPR_MPC_EID (0x051)
870#define SPR_MPC_NRI (0x052)
871#define SPR_CTRL (0x088)
872#define SPR_MPC_CMPA (0x090)
873#define SPR_MPC_CMPB (0x091)
874#define SPR_MPC_CMPC (0x092)
875#define SPR_MPC_CMPD (0x093)
876#define SPR_MPC_ECR (0x094)
877#define SPR_MPC_DER (0x095)
878#define SPR_MPC_COUNTA (0x096)
879#define SPR_MPC_COUNTB (0x097)
880#define SPR_UCTRL (0x098)
881#define SPR_MPC_CMPE (0x098)
882#define SPR_MPC_CMPF (0x099)
883#define SPR_MPC_CMPG (0x09A)
884#define SPR_MPC_CMPH (0x09B)
885#define SPR_MPC_LCTRL1 (0x09C)
886#define SPR_MPC_LCTRL2 (0x09D)
887#define SPR_MPC_ICTRL (0x09E)
888#define SPR_MPC_BAR (0x09F)
889#define SPR_VRSAVE (0x100)
890#define SPR_USPRG0 (0x100)
891#define SPR_USPRG1 (0x101)
892#define SPR_USPRG2 (0x102)
893#define SPR_USPRG3 (0x103)
894#define SPR_USPRG4 (0x104)
895#define SPR_USPRG5 (0x105)
896#define SPR_USPRG6 (0x106)
897#define SPR_USPRG7 (0x107)
898#define SPR_VTBL (0x10C)
899#define SPR_VTBU (0x10D)
900#define SPR_SPRG0 (0x110)
901#define SPR_SPRG1 (0x111)
902#define SPR_SPRG2 (0x112)
903#define SPR_SPRG3 (0x113)
904#define SPR_SPRG4 (0x114)
905#define SPR_SCOMC (0x114)
906#define SPR_SPRG5 (0x115)
907#define SPR_SCOMD (0x115)
908#define SPR_SPRG6 (0x116)
909#define SPR_SPRG7 (0x117)
910#define SPR_ASR (0x118)
911#define SPR_EAR (0x11A)
912#define SPR_TBL (0x11C)
913#define SPR_TBU (0x11D)
914#define SPR_TBU40 (0x11E)
915#define SPR_SVR (0x11E)
916#define SPR_BOOKE_PIR (0x11E)
917#define SPR_PVR (0x11F)
918#define SPR_HSPRG0 (0x130)
919#define SPR_BOOKE_DBSR (0x130)
920#define SPR_HSPRG1 (0x131)
921#define SPR_HDSISR (0x132)
922#define SPR_HDAR (0x133)
923#define SPR_BOOKE_DBCR0 (0x134)
924#define SPR_IBCR (0x135)
925#define SPR_PURR (0x135)
926#define SPR_BOOKE_DBCR1 (0x135)
927#define SPR_DBCR (0x136)
928#define SPR_HDEC (0x136)
929#define SPR_BOOKE_DBCR2 (0x136)
930#define SPR_HIOR (0x137)
931#define SPR_MBAR (0x137)
932#define SPR_RMOR (0x138)
933#define SPR_BOOKE_IAC1 (0x138)
934#define SPR_HRMOR (0x139)
935#define SPR_BOOKE_IAC2 (0x139)
936#define SPR_HSRR0 (0x13A)
937#define SPR_BOOKE_IAC3 (0x13A)
938#define SPR_HSRR1 (0x13B)
939#define SPR_BOOKE_IAC4 (0x13B)
940#define SPR_LPCR (0x13C)
941#define SPR_BOOKE_DAC1 (0x13C)
942#define SPR_LPIDR (0x13D)
943#define SPR_DABR2 (0x13D)
944#define SPR_BOOKE_DAC2 (0x13D)
945#define SPR_BOOKE_DVC1 (0x13E)
946#define SPR_BOOKE_DVC2 (0x13F)
947#define SPR_BOOKE_TSR (0x150)
948#define SPR_BOOKE_TCR (0x154)
949#define SPR_BOOKE_IVOR0 (0x190)
950#define SPR_BOOKE_IVOR1 (0x191)
951#define SPR_BOOKE_IVOR2 (0x192)
952#define SPR_BOOKE_IVOR3 (0x193)
953#define SPR_BOOKE_IVOR4 (0x194)
954#define SPR_BOOKE_IVOR5 (0x195)
955#define SPR_BOOKE_IVOR6 (0x196)
956#define SPR_BOOKE_IVOR7 (0x197)
957#define SPR_BOOKE_IVOR8 (0x198)
958#define SPR_BOOKE_IVOR9 (0x199)
959#define SPR_BOOKE_IVOR10 (0x19A)
960#define SPR_BOOKE_IVOR11 (0x19B)
961#define SPR_BOOKE_IVOR12 (0x19C)
962#define SPR_BOOKE_IVOR13 (0x19D)
963#define SPR_BOOKE_IVOR14 (0x19E)
964#define SPR_BOOKE_IVOR15 (0x19F)
965#define SPR_BOOKE_SPEFSCR (0x200)
966#define SPR_Exxx_BBEAR (0x201)
967#define SPR_Exxx_BBTAR (0x202)
968#define SPR_Exxx_L1CFG0 (0x203)
969#define SPR_Exxx_NPIDR (0x205)
970#define SPR_ATBL (0x20E)
971#define SPR_ATBU (0x20F)
972#define SPR_IBAT0U (0x210)
973#define SPR_BOOKE_IVOR32 (0x210)
974#define SPR_RCPU_MI_GRA (0x210)
975#define SPR_IBAT0L (0x211)
976#define SPR_BOOKE_IVOR33 (0x211)
977#define SPR_IBAT1U (0x212)
978#define SPR_BOOKE_IVOR34 (0x212)
979#define SPR_IBAT1L (0x213)
980#define SPR_BOOKE_IVOR35 (0x213)
981#define SPR_IBAT2U (0x214)
982#define SPR_BOOKE_IVOR36 (0x214)
983#define SPR_IBAT2L (0x215)
984#define SPR_BOOKE_IVOR37 (0x215)
985#define SPR_IBAT3U (0x216)
986#define SPR_IBAT3L (0x217)
987#define SPR_DBAT0U (0x218)
988#define SPR_RCPU_L2U_GRA (0x218)
989#define SPR_DBAT0L (0x219)
990#define SPR_DBAT1U (0x21A)
991#define SPR_DBAT1L (0x21B)
992#define SPR_DBAT2U (0x21C)
993#define SPR_DBAT2L (0x21D)
994#define SPR_DBAT3U (0x21E)
995#define SPR_DBAT3L (0x21F)
996#define SPR_IBAT4U (0x230)
997#define SPR_RPCU_BBCMCR (0x230)
998#define SPR_MPC_IC_CST (0x230)
999#define SPR_Exxx_CTXCR (0x230)
1000#define SPR_IBAT4L (0x231)
1001#define SPR_MPC_IC_ADR (0x231)
1002#define SPR_Exxx_DBCR3 (0x231)
1003#define SPR_IBAT5U (0x232)
1004#define SPR_MPC_IC_DAT (0x232)
1005#define SPR_Exxx_DBCNT (0x232)
1006#define SPR_IBAT5L (0x233)
1007#define SPR_IBAT6U (0x234)
1008#define SPR_IBAT6L (0x235)
1009#define SPR_IBAT7U (0x236)
1010#define SPR_IBAT7L (0x237)
1011#define SPR_DBAT4U (0x238)
1012#define SPR_RCPU_L2U_MCR (0x238)
1013#define SPR_MPC_DC_CST (0x238)
1014#define SPR_Exxx_ALTCTXCR (0x238)
1015#define SPR_DBAT4L (0x239)
1016#define SPR_MPC_DC_ADR (0x239)
1017#define SPR_DBAT5U (0x23A)
1018#define SPR_BOOKE_MCSRR0 (0x23A)
1019#define SPR_MPC_DC_DAT (0x23A)
1020#define SPR_DBAT5L (0x23B)
1021#define SPR_BOOKE_MCSRR1 (0x23B)
1022#define SPR_DBAT6U (0x23C)
1023#define SPR_BOOKE_MCSR (0x23C)
1024#define SPR_DBAT6L (0x23D)
1025#define SPR_Exxx_MCAR (0x23D)
1026#define SPR_DBAT7U (0x23E)
1027#define SPR_BOOKE_DSRR0 (0x23E)
1028#define SPR_DBAT7L (0x23F)
1029#define SPR_BOOKE_DSRR1 (0x23F)
1030#define SPR_BOOKE_SPRG8 (0x25C)
1031#define SPR_BOOKE_SPRG9 (0x25D)
1032#define SPR_BOOKE_MAS0 (0x270)
1033#define SPR_BOOKE_MAS1 (0x271)
1034#define SPR_BOOKE_MAS2 (0x272)
1035#define SPR_BOOKE_MAS3 (0x273)
1036#define SPR_BOOKE_MAS4 (0x274)
1037#define SPR_BOOKE_MAS5 (0x275)
1038#define SPR_BOOKE_MAS6 (0x276)
1039#define SPR_BOOKE_PID1 (0x279)
1040#define SPR_BOOKE_PID2 (0x27A)
1041#define SPR_MPC_DPDR (0x280)
1042#define SPR_MPC_IMMR (0x288)
1043#define SPR_BOOKE_TLB0CFG (0x2B0)
1044#define SPR_BOOKE_TLB1CFG (0x2B1)
1045#define SPR_BOOKE_TLB2CFG (0x2B2)
1046#define SPR_BOOKE_TLB3CFG (0x2B3)
1047#define SPR_BOOKE_EPR (0x2BE)
1048#define SPR_PERF0 (0x300)
1049#define SPR_RCPU_MI_RBA0 (0x300)
1050#define SPR_MPC_MI_CTR (0x300)
1051#define SPR_PERF1 (0x301)
1052#define SPR_RCPU_MI_RBA1 (0x301)
1053#define SPR_PERF2 (0x302)
1054#define SPR_RCPU_MI_RBA2 (0x302)
1055#define SPR_MPC_MI_AP (0x302)
1056#define SPR_PERF3 (0x303)
082c6681 1057#define SPR_620_PMC1R (0x303)
80d11f44
JM		 1058#define SPR_RCPU_MI_RBA3 (0x303)
1059#define SPR_MPC_MI_EPN (0x303)
1060#define SPR_PERF4 (0x304)
082c6681 1061#define SPR_620_PMC2R (0x304)
80d11f44
JM		 1062#define SPR_PERF5 (0x305)
1063#define SPR_MPC_MI_TWC (0x305)
1064#define SPR_PERF6 (0x306)
1065#define SPR_MPC_MI_RPN (0x306)
1066#define SPR_PERF7 (0x307)
1067#define SPR_PERF8 (0x308)
1068#define SPR_RCPU_L2U_RBA0 (0x308)
1069#define SPR_MPC_MD_CTR (0x308)
1070#define SPR_PERF9 (0x309)
1071#define SPR_RCPU_L2U_RBA1 (0x309)
1072#define SPR_MPC_MD_CASID (0x309)
1073#define SPR_PERFA (0x30A)
1074#define SPR_RCPU_L2U_RBA2 (0x30A)
1075#define SPR_MPC_MD_AP (0x30A)
1076#define SPR_PERFB (0x30B)
082c6681 1077#define SPR_620_MMCR0R (0x30B)
80d11f44
JM		 1078#define SPR_RCPU_L2U_RBA3 (0x30B)
1079#define SPR_MPC_MD_EPN (0x30B)
1080#define SPR_PERFC (0x30C)
1081#define SPR_MPC_MD_TWB (0x30C)
1082#define SPR_PERFD (0x30D)
1083#define SPR_MPC_MD_TWC (0x30D)
1084#define SPR_PERFE (0x30E)
1085#define SPR_MPC_MD_RPN (0x30E)
1086#define SPR_PERFF (0x30F)
1087#define SPR_MPC_MD_TW (0x30F)
1088#define SPR_UPERF0 (0x310)
1089#define SPR_UPERF1 (0x311)
1090#define SPR_UPERF2 (0x312)
1091#define SPR_UPERF3 (0x313)
082c6681 1092#define SPR_620_PMC1W (0x313)
80d11f44 1093#define SPR_UPERF4 (0x314)
082c6681 1094#define SPR_620_PMC2W (0x314)
80d11f44
JM		 1095#define SPR_UPERF5 (0x315)
1096#define SPR_UPERF6 (0x316)
1097#define SPR_UPERF7 (0x317)
1098#define SPR_UPERF8 (0x318)
1099#define SPR_UPERF9 (0x319)
1100#define SPR_UPERFA (0x31A)
1101#define SPR_UPERFB (0x31B)
082c6681 1102#define SPR_620_MMCR0W (0x31B)
80d11f44
JM		 1103#define SPR_UPERFC (0x31C)
1104#define SPR_UPERFD (0x31D)
1105#define SPR_UPERFE (0x31E)
1106#define SPR_UPERFF (0x31F)
1107#define SPR_RCPU_MI_RA0 (0x320)
1108#define SPR_MPC_MI_DBCAM (0x320)
1109#define SPR_RCPU_MI_RA1 (0x321)
1110#define SPR_MPC_MI_DBRAM0 (0x321)
1111#define SPR_RCPU_MI_RA2 (0x322)
1112#define SPR_MPC_MI_DBRAM1 (0x322)
1113#define SPR_RCPU_MI_RA3 (0x323)
1114#define SPR_RCPU_L2U_RA0 (0x328)
1115#define SPR_MPC_MD_DBCAM (0x328)
1116#define SPR_RCPU_L2U_RA1 (0x329)
1117#define SPR_MPC_MD_DBRAM0 (0x329)
1118#define SPR_RCPU_L2U_RA2 (0x32A)
1119#define SPR_MPC_MD_DBRAM1 (0x32A)
1120#define SPR_RCPU_L2U_RA3 (0x32B)
1121#define SPR_440_INV0 (0x370)
1122#define SPR_440_INV1 (0x371)
1123#define SPR_440_INV2 (0x372)
1124#define SPR_440_INV3 (0x373)
1125#define SPR_440_ITV0 (0x374)
1126#define SPR_440_ITV1 (0x375)
1127#define SPR_440_ITV2 (0x376)
1128#define SPR_440_ITV3 (0x377)
1129#define SPR_440_CCR1 (0x378)
1130#define SPR_DCRIPR (0x37B)
1131#define SPR_PPR (0x380)
bd928eba 1132#define SPR_750_GQR0 (0x390)
80d11f44 1133#define SPR_440_DNV0 (0x390)
bd928eba 1134#define SPR_750_GQR1 (0x391)
80d11f44 1135#define SPR_440_DNV1 (0x391)
bd928eba 1136#define SPR_750_GQR2 (0x392)
80d11f44 1137#define SPR_440_DNV2 (0x392)
bd928eba 1138#define SPR_750_GQR3 (0x393)
80d11f44 1139#define SPR_440_DNV3 (0x393)
bd928eba 1140#define SPR_750_GQR4 (0x394)
80d11f44 1141#define SPR_440_DTV0 (0x394)
bd928eba 1142#define SPR_750_GQR5 (0x395)
80d11f44 1143#define SPR_440_DTV1 (0x395)
bd928eba 1144#define SPR_750_GQR6 (0x396)
80d11f44 1145#define SPR_440_DTV2 (0x396)
bd928eba 1146#define SPR_750_GQR7 (0x397)
80d11f44 1147#define SPR_440_DTV3 (0x397)
bd928eba
JM		 1148#define SPR_750_THRM4 (0x398)
1149#define SPR_750CL_HID2 (0x398)
80d11f44 1150#define SPR_440_DVLIM (0x398)
bd928eba 1151#define SPR_750_WPAR (0x399)
80d11f44 1152#define SPR_440_IVLIM (0x399)
bd928eba
JM		 1153#define SPR_750_DMAU (0x39A)
1154#define SPR_750_DMAL (0x39B)
80d11f44
JM		 1155#define SPR_440_RSTCFG (0x39B)
1156#define SPR_BOOKE_DCDBTRL (0x39C)
1157#define SPR_BOOKE_DCDBTRH (0x39D)
1158#define SPR_BOOKE_ICDBTRL (0x39E)
1159#define SPR_BOOKE_ICDBTRH (0x39F)
1160#define SPR_UMMCR2 (0x3A0)
1161#define SPR_UPMC5 (0x3A1)
1162#define SPR_UPMC6 (0x3A2)
1163#define SPR_UBAMR (0x3A7)
1164#define SPR_UMMCR0 (0x3A8)
1165#define SPR_UPMC1 (0x3A9)
1166#define SPR_UPMC2 (0x3AA)
1167#define SPR_USIAR (0x3AB)
1168#define SPR_UMMCR1 (0x3AC)
1169#define SPR_UPMC3 (0x3AD)
1170#define SPR_UPMC4 (0x3AE)
1171#define SPR_USDA (0x3AF)
1172#define SPR_40x_ZPR (0x3B0)
1173#define SPR_BOOKE_MAS7 (0x3B0)
1174#define SPR_620_PMR0 (0x3B0)
1175#define SPR_MMCR2 (0x3B0)
1176#define SPR_PMC5 (0x3B1)
1177#define SPR_40x_PID (0x3B1)
1178#define SPR_620_PMR1 (0x3B1)
1179#define SPR_PMC6 (0x3B2)
1180#define SPR_440_MMUCR (0x3B2)
1181#define SPR_620_PMR2 (0x3B2)
1182#define SPR_4xx_CCR0 (0x3B3)
1183#define SPR_BOOKE_EPLC (0x3B3)
1184#define SPR_620_PMR3 (0x3B3)
1185#define SPR_405_IAC3 (0x3B4)
1186#define SPR_BOOKE_EPSC (0x3B4)
1187#define SPR_620_PMR4 (0x3B4)
1188#define SPR_405_IAC4 (0x3B5)
1189#define SPR_620_PMR5 (0x3B5)
1190#define SPR_405_DVC1 (0x3B6)
1191#define SPR_620_PMR6 (0x3B6)
1192#define SPR_405_DVC2 (0x3B7)
1193#define SPR_620_PMR7 (0x3B7)
1194#define SPR_BAMR (0x3B7)
1195#define SPR_MMCR0 (0x3B8)
1196#define SPR_620_PMR8 (0x3B8)
1197#define SPR_PMC1 (0x3B9)
1198#define SPR_40x_SGR (0x3B9)
1199#define SPR_620_PMR9 (0x3B9)
1200#define SPR_PMC2 (0x3BA)
1201#define SPR_40x_DCWR (0x3BA)
1202#define SPR_620_PMRA (0x3BA)
1203#define SPR_SIAR (0x3BB)
1204#define SPR_405_SLER (0x3BB)
1205#define SPR_620_PMRB (0x3BB)
1206#define SPR_MMCR1 (0x3BC)
1207#define SPR_405_SU0R (0x3BC)
1208#define SPR_620_PMRC (0x3BC)
1209#define SPR_401_SKR (0x3BC)
1210#define SPR_PMC3 (0x3BD)
1211#define SPR_405_DBCR1 (0x3BD)
1212#define SPR_620_PMRD (0x3BD)
1213#define SPR_PMC4 (0x3BE)
1214#define SPR_620_PMRE (0x3BE)
1215#define SPR_SDA (0x3BF)
1216#define SPR_620_PMRF (0x3BF)
1217#define SPR_403_VTBL (0x3CC)
1218#define SPR_403_VTBU (0x3CD)
1219#define SPR_DMISS (0x3D0)
1220#define SPR_DCMP (0x3D1)
1221#define SPR_HASH1 (0x3D2)
1222#define SPR_HASH2 (0x3D3)
1223#define SPR_BOOKE_ICDBDR (0x3D3)
1224#define SPR_TLBMISS (0x3D4)
1225#define SPR_IMISS (0x3D4)
1226#define SPR_40x_ESR (0x3D4)
1227#define SPR_PTEHI (0x3D5)
1228#define SPR_ICMP (0x3D5)
1229#define SPR_40x_DEAR (0x3D5)
1230#define SPR_PTELO (0x3D6)
1231#define SPR_RPA (0x3D6)
1232#define SPR_40x_EVPR (0x3D6)
1233#define SPR_L3PM (0x3D7)
1234#define SPR_403_CDBCR (0x3D7)
4e777442 1235#define SPR_L3ITCR0 (0x3D8)
80d11f44
JM		 1236#define SPR_TCR (0x3D8)
1237#define SPR_40x_TSR (0x3D8)
1238#define SPR_IBR (0x3DA)
1239#define SPR_40x_TCR (0x3DA)
1240#define SPR_ESASRR (0x3DB)
1241#define SPR_40x_PIT (0x3DB)
1242#define SPR_403_TBL (0x3DC)
1243#define SPR_403_TBU (0x3DD)
1244#define SPR_SEBR (0x3DE)
1245#define SPR_40x_SRR2 (0x3DE)
1246#define SPR_SER (0x3DF)
1247#define SPR_40x_SRR3 (0x3DF)
4e777442 1248#define SPR_L3OHCR (0x3E8)
80d11f44
JM		 1249#define SPR_L3ITCR1 (0x3E9)
1250#define SPR_L3ITCR2 (0x3EA)
1251#define SPR_L3ITCR3 (0x3EB)
1252#define SPR_HID0 (0x3F0)
1253#define SPR_40x_DBSR (0x3F0)
1254#define SPR_HID1 (0x3F1)
1255#define SPR_IABR (0x3F2)
1256#define SPR_40x_DBCR0 (0x3F2)
1257#define SPR_601_HID2 (0x3F2)
1258#define SPR_Exxx_L1CSR0 (0x3F2)
1259#define SPR_ICTRL (0x3F3)
1260#define SPR_HID2 (0x3F3)
bd928eba 1261#define SPR_750CL_HID4 (0x3F3)
80d11f44
JM		 1262#define SPR_Exxx_L1CSR1 (0x3F3)
1263#define SPR_440_DBDR (0x3F3)
1264#define SPR_LDSTDB (0x3F4)
bd928eba 1265#define SPR_750_TDCL (0x3F4)
80d11f44
JM		 1266#define SPR_40x_IAC1 (0x3F4)
1267#define SPR_MMUCSR0 (0x3F4)
1268#define SPR_DABR (0x3F5)
3fc6c082 1269#define DABR_MASK (~(target_ulong)0x7)
80d11f44
JM		 1270#define SPR_Exxx_BUCSR (0x3F5)
1271#define SPR_40x_IAC2 (0x3F5)
1272#define SPR_601_HID5 (0x3F5)
1273#define SPR_40x_DAC1 (0x3F6)
1274#define SPR_MSSCR0 (0x3F6)
1275#define SPR_970_HID5 (0x3F6)
1276#define SPR_MSSSR0 (0x3F7)
4e777442 1277#define SPR_MSSCR1 (0x3F7)
80d11f44
JM		 1278#define SPR_DABRX (0x3F7)
1279#define SPR_40x_DAC2 (0x3F7)
1280#define SPR_MMUCFG (0x3F7)
1281#define SPR_LDSTCR (0x3F8)
1282#define SPR_L2PMCR (0x3F8)
bd928eba 1283#define SPR_750FX_HID2 (0x3F8)
082c6681 1284#define SPR_620_BUSCSR (0x3F8)
80d11f44
JM		 1285#define SPR_Exxx_L1FINV0 (0x3F8)
1286#define SPR_L2CR (0x3F9)
082c6681 1287#define SPR_620_L2CR (0x3F9)
80d11f44 1288#define SPR_L3CR (0x3FA)
bd928eba 1289#define SPR_750_TDCH (0x3FA)
80d11f44
JM		 1290#define SPR_IABR2 (0x3FA)
1291#define SPR_40x_DCCR (0x3FA)
082c6681 1292#define SPR_620_L2SR (0x3FA)
80d11f44
JM		 1293#define SPR_ICTC (0x3FB)
1294#define SPR_40x_ICCR (0x3FB)
1295#define SPR_THRM1 (0x3FC)
1296#define SPR_403_PBL1 (0x3FC)
1297#define SPR_SP (0x3FD)
1298#define SPR_THRM2 (0x3FD)
1299#define SPR_403_PBU1 (0x3FD)
1300#define SPR_604_HID13 (0x3FD)
1301#define SPR_LT (0x3FE)
1302#define SPR_THRM3 (0x3FE)
1303#define SPR_RCPU_FPECR (0x3FE)
1304#define SPR_403_PBL2 (0x3FE)
1305#define SPR_PIR (0x3FF)
1306#define SPR_403_PBU2 (0x3FF)
1307#define SPR_601_HID15 (0x3FF)
1308#define SPR_604_HID15 (0x3FF)
1309#define SPR_E500_SVR (0x3FF)
79aceca5 1310
76a66253 1311/*****************************************************************************/
9a64fbe4
FB		 1312/* Memory access type :
1313 * may be needed for precise access rights control and precise exceptions.
1314 */
79aceca5 1315enum {
9a64fbe4
FB		 1316 /* 1 bit to define user level / supervisor access */
1317 ACCESS_USER = 0x00,
1318 ACCESS_SUPER = 0x01,
1319 /* Type of instruction that generated the access */
1320 ACCESS_CODE = 0x10, /* Code fetch access */
1321 ACCESS_INT = 0x20, /* Integer load/store access */
1322 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1323 ACCESS_RES = 0x40, /* load/store with reservation */
1324 ACCESS_EXT = 0x50, /* external access */
1325 ACCESS_CACHE = 0x60, /* Cache manipulation */
1326};
1327
47103572
JM		 1328/* Hardware interruption sources:
1329 * all those exception can be raised simulteaneously
1330 */
e9df014c
JM		 1331/* Input pins definitions */
1332enum {
1333 /* 6xx bus input pins */
24be5ae3
JM		 1334 PPC6xx_INPUT_HRESET = 0,
1335 PPC6xx_INPUT_SRESET = 1,
1336 PPC6xx_INPUT_CKSTP_IN = 2,
1337 PPC6xx_INPUT_MCP = 3,
1338 PPC6xx_INPUT_SMI = 4,
1339 PPC6xx_INPUT_INT = 5,
d68f1306
JM		 1340 PPC6xx_INPUT_TBEN = 6,
1341 PPC6xx_INPUT_WAKEUP = 7,
1342 PPC6xx_INPUT_NB,
24be5ae3
JM		 1343};
1344
1345enum {
e9df014c 1346 /* Embedded PowerPC input pins */
24be5ae3
JM		 1347 PPCBookE_INPUT_HRESET = 0,
1348 PPCBookE_INPUT_SRESET = 1,
1349 PPCBookE_INPUT_CKSTP_IN = 2,
1350 PPCBookE_INPUT_MCP = 3,
1351 PPCBookE_INPUT_SMI = 4,
1352 PPCBookE_INPUT_INT = 5,
1353 PPCBookE_INPUT_CINT = 6,
d68f1306 1354 PPCBookE_INPUT_NB,
24be5ae3
JM		 1355};
1356
a750fc0b 1357enum {
4e290a0b
JM		 1358 /* PowerPC 40x input pins */
1359 PPC40x_INPUT_RESET_CORE = 0,
1360 PPC40x_INPUT_RESET_CHIP = 1,
1361 PPC40x_INPUT_RESET_SYS = 2,
1362 PPC40x_INPUT_CINT = 3,
1363 PPC40x_INPUT_INT = 4,
1364 PPC40x_INPUT_HALT = 5,
1365 PPC40x_INPUT_DEBUG = 6,
1366 PPC40x_INPUT_NB,
e9df014c
JM		 1367};
1368
b4095fed
JM		 1369enum {
1370 /* RCPU input pins */
1371 PPCRCPU_INPUT_PORESET = 0,
1372 PPCRCPU_INPUT_HRESET = 1,
1373 PPCRCPU_INPUT_SRESET = 2,
1374 PPCRCPU_INPUT_IRQ0 = 3,
1375 PPCRCPU_INPUT_IRQ1 = 4,
1376 PPCRCPU_INPUT_IRQ2 = 5,
1377 PPCRCPU_INPUT_IRQ3 = 6,
1378 PPCRCPU_INPUT_IRQ4 = 7,
1379 PPCRCPU_INPUT_IRQ5 = 8,
1380 PPCRCPU_INPUT_IRQ6 = 9,
1381 PPCRCPU_INPUT_IRQ7 = 10,
1382 PPCRCPU_INPUT_NB,
1383};
1384
00af685f 1385#if defined(TARGET_PPC64)
d0dfae6e
JM		 1386enum {
1387 /* PowerPC 970 input pins */
1388 PPC970_INPUT_HRESET = 0,
1389 PPC970_INPUT_SRESET = 1,
1390 PPC970_INPUT_CKSTP = 2,
1391 PPC970_INPUT_TBEN = 3,
1392 PPC970_INPUT_MCP = 4,
1393 PPC970_INPUT_INT = 5,
1394 PPC970_INPUT_THINT = 6,
7b62a955 1395 PPC970_INPUT_NB,
d0dfae6e 1396};
00af685f 1397#endif
d0dfae6e 1398
e9df014c 1399/* Hardware exceptions definitions */
47103572 1400enum {
e9df014c 1401 /* External hardware exception sources */
e1833e1f 1402 PPC_INTERRUPT_RESET = 0, /* Reset exception */
d68f1306
JM		 1403 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
1404 PPC_INTERRUPT_MCK, /* Machine check exception */
1405 PPC_INTERRUPT_EXT, /* External interrupt */
1406 PPC_INTERRUPT_SMI, /* System management interrupt */
1407 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
1408 PPC_INTERRUPT_DEBUG, /* External debug exception */
1409 PPC_INTERRUPT_THERM, /* Thermal exception */
e9df014c 1410 /* Internal hardware exception sources */
d68f1306
JM		 1411 PPC_INTERRUPT_DECR, /* Decrementer exception */
1412 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
1413 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
1414 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
1415 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
1416 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
1417 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
1418 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
47103572
JM		 1419};
1420
9a64fbe4
FB		 1421/*****************************************************************************/
1422
79aceca5 1423#endif /* !defined (__CPU_PPC_H__) */
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