]> git.proxmox.com Git - qemu.git/blame - target-ppc/exec.h
target-ppc: convert POWER2 load/store instructions to TCG
[qemu.git] / target-ppc / exec.h
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation definitions for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#if !defined (__PPC_H__)
21#define __PPC_H__
22
fdabc366
FB
23#include "config.h"
24
79aceca5
FB
25#include "dyngen-exec.h"
26
76a66253
JM
27#include "cpu.h"
28#include "exec-all.h"
fdabc366 29
1cdb9c3d
AJ
30/* For normal operations, precise emulation should not be needed */
31//#define USE_PRECISE_EMULATION 1
32#define USE_PRECISE_EMULATION 0
33
79aceca5 34register struct CPUPPCState *env asm(AREG0);
76a66253
JM
35#if TARGET_LONG_BITS > HOST_LONG_BITS
36/* no registers can be used */
37#define T0 (env->t0)
38#define T1 (env->t1)
39#define T2 (env->t2)
6b542af7 40#define TDX "%016" PRIx64
76a66253 41#else
bd7d9a6d
AJ
42register target_ulong T0 asm(AREG1);
43register target_ulong T1 asm(AREG2);
44register target_ulong T2 asm(AREG3);
6b542af7 45#define TDX "%016lx"
76a66253 46#endif
79aceca5 47
a541f297 48#if defined (DEBUG_OP)
70ead434 49# define RETURN() __asm__ __volatile__("nop" : : : "memory");
a541f297 50#else
70ead434 51# define RETURN() __asm__ __volatile__("" : : : "memory");
a541f297 52#endif
79aceca5 53
b068d6a7 54static always_inline target_ulong rotl8 (target_ulong i, int n)
76a66253
JM
55{
56 return (((uint8_t)i << n) | ((uint8_t)i >> (8 - n)));
57}
58
b068d6a7 59static always_inline target_ulong rotl16 (target_ulong i, int n)
76a66253
JM
60{
61 return (((uint16_t)i << n) | ((uint16_t)i >> (16 - n)));
62}
79aceca5 63
b068d6a7 64static always_inline target_ulong rotl32 (target_ulong i, int n)
79aceca5 65{
76a66253 66 return (((uint32_t)i << n) | ((uint32_t)i >> (32 - n)));
79aceca5
FB
67}
68
76a66253 69#if defined(TARGET_PPC64)
b068d6a7 70static always_inline target_ulong rotl64 (target_ulong i, int n)
76a66253
JM
71{
72 return (((uint64_t)i << n) | ((uint64_t)i >> (64 - n)));
73}
74#endif
75
9a64fbe4 76#if !defined(CONFIG_USER_ONLY)
a9049a07 77#include "softmmu_exec.h"
9a64fbe4 78#endif /* !defined(CONFIG_USER_ONLY) */
79aceca5 79
64adab3f
AJ
80void raise_exception_err (CPUState *env, int exception, int error_code);
81void raise_exception (CPUState *env, int exception);
79aceca5 82
76a66253 83int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong vaddr,
faadf50e 84 int rw, int access_type);
79aceca5 85
76a66253
JM
86void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
87 target_ulong pte0, target_ulong pte1);
9a64fbe4 88
b068d6a7 89static always_inline void env_to_regs (void)
0d1a29f9
FB
90{
91}
92
b068d6a7 93static always_inline void regs_to_env (void)
0d1a29f9
FB
94{
95}
96
76a66253 97int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390 98 int mmu_idx, int is_softmmu);
0fa85d43 99
b068d6a7 100static always_inline int cpu_halted (CPUState *env)
36081602 101{
bfed01fc
TS
102 if (!env->halted)
103 return 0;
0411a972 104 if (msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD)) {
bfed01fc
TS
105 env->halted = 0;
106 return 0;
107 }
108 return EXCP_HALTED;
109}
110
79aceca5 111#endif /* !defined (__PPC_H__) */