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ppc: Move load and store helpers, switch to AREG0 free mode
[qemu.git] / target-ppc / fpu_helper.c
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bd23cd45
BS		 1/*
2 * PowerPC floating point and SPE emulation helpers for QEMU.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include "cpu.h"
bd23cd45
BS		 20#include "helper.h"
21
22/*****************************************************************************/
23/* Floating point operations helpers */
8e703949 24uint64_t helper_float32_to_float64(CPUPPCState *env, uint32_t arg)
bd23cd45
BS		 25{
26 CPU_FloatU f;
27 CPU_DoubleU d;
28
29 f.l = arg;
30 d.d = float32_to_float64(f.f, &env->fp_status);
31 return d.ll;
32}
33
8e703949 34uint32_t helper_float64_to_float32(CPUPPCState *env, uint64_t arg)
bd23cd45
BS		 35{
36 CPU_FloatU f;
37 CPU_DoubleU d;
38
39 d.ll = arg;
40 f.f = float64_to_float32(d.d, &env->fp_status);
41 return f.l;
42}
43
44static inline int isden(float64 d)
45{
46 CPU_DoubleU u;
47
48 u.d = d;
49
50 return ((u.ll >> 52) & 0x7FF) == 0;
51}
52
8e703949 53uint32_t helper_compute_fprf(CPUPPCState *env, uint64_t arg, uint32_t set_fprf)
bd23cd45
BS		 54{
55 CPU_DoubleU farg;
56 int isneg;
57 int ret;
58
59 farg.ll = arg;
60 isneg = float64_is_neg(farg.d);
61 if (unlikely(float64_is_any_nan(farg.d))) {
62 if (float64_is_signaling_nan(farg.d)) {
63 /* Signaling NaN: flags are undefined */
64 ret = 0x00;
65 } else {
66 /* Quiet NaN */
67 ret = 0x11;
68 }
69 } else if (unlikely(float64_is_infinity(farg.d))) {
70 /* +/- infinity */
71 if (isneg) {
72 ret = 0x09;
73 } else {
74 ret = 0x05;
75 }
76 } else {
77 if (float64_is_zero(farg.d)) {
78 /* +/- zero */
79 if (isneg) {
80 ret = 0x12;
81 } else {
82 ret = 0x02;
83 }
84 } else {
85 if (isden(farg.d)) {
86 /* Denormalized numbers */
87 ret = 0x10;
88 } else {
89 /* Normalized numbers */
90 ret = 0x00;
91 }
92 if (isneg) {
93 ret |= 0x08;
94 } else {
95 ret |= 0x04;
96 }
97 }
98 }
99 if (set_fprf) {
100 /* We update FPSCR_FPRF */
101 env->fpscr &= ~(0x1F << FPSCR_FPRF);
102 env->fpscr |= ret << FPSCR_FPRF;
103 }
104 /* We just need fpcc to update Rc1 */
105 return ret & 0xF;
106}
107
108/* Floating-point invalid operations exception */
8e703949 109static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op)
bd23cd45
BS		 110{
111 uint64_t ret = 0;
112 int ve;
113
114 ve = fpscr_ve;
115 switch (op) {
116 case POWERPC_EXCP_FP_VXSNAN:
117 env->fpscr |= 1 << FPSCR_VXSNAN;
118 break;
119 case POWERPC_EXCP_FP_VXSOFT:
120 env->fpscr |= 1 << FPSCR_VXSOFT;
121 break;
122 case POWERPC_EXCP_FP_VXISI:
123 /* Magnitude subtraction of infinities */
124 env->fpscr |= 1 << FPSCR_VXISI;
125 goto update_arith;
126 case POWERPC_EXCP_FP_VXIDI:
127 /* Division of infinity by infinity */
128 env->fpscr |= 1 << FPSCR_VXIDI;
129 goto update_arith;
130 case POWERPC_EXCP_FP_VXZDZ:
131 /* Division of zero by zero */
132 env->fpscr |= 1 << FPSCR_VXZDZ;
133 goto update_arith;
134 case POWERPC_EXCP_FP_VXIMZ:
135 /* Multiplication of zero by infinity */
136 env->fpscr |= 1 << FPSCR_VXIMZ;
137 goto update_arith;
138 case POWERPC_EXCP_FP_VXVC:
139 /* Ordered comparison of NaN */
140 env->fpscr |= 1 << FPSCR_VXVC;
141 env->fpscr &= ~(0xF << FPSCR_FPCC);
142 env->fpscr |= 0x11 << FPSCR_FPCC;
143 /* We must update the target FPR before raising the exception */
144 if (ve != 0) {
145 env->exception_index = POWERPC_EXCP_PROGRAM;
146 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
147 /* Update the floating-point enabled exception summary */
148 env->fpscr |= 1 << FPSCR_FEX;
149 /* Exception is differed */
150 ve = 0;
151 }
152 break;
153 case POWERPC_EXCP_FP_VXSQRT:
154 /* Square root of a negative number */
155 env->fpscr |= 1 << FPSCR_VXSQRT;
156 update_arith:
157 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
158 if (ve == 0) {
159 /* Set the result to quiet NaN */
160 ret = 0x7FF8000000000000ULL;
161 env->fpscr &= ~(0xF << FPSCR_FPCC);
162 env->fpscr |= 0x11 << FPSCR_FPCC;
163 }
164 break;
165 case POWERPC_EXCP_FP_VXCVI:
166 /* Invalid conversion */
167 env->fpscr |= 1 << FPSCR_VXCVI;
168 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
169 if (ve == 0) {
170 /* Set the result to quiet NaN */
171 ret = 0x7FF8000000000000ULL;
172 env->fpscr &= ~(0xF << FPSCR_FPCC);
173 env->fpscr |= 0x11 << FPSCR_FPCC;
174 }
175 break;
176 }
177 /* Update the floating-point invalid operation summary */
178 env->fpscr |= 1 << FPSCR_VX;
179 /* Update the floating-point exception summary */
180 env->fpscr |= 1 << FPSCR_FX;
181 if (ve != 0) {
182 /* Update the floating-point enabled exception summary */
183 env->fpscr |= 1 << FPSCR_FEX;
184 if (msr_fe0 != 0 || msr_fe1 != 0) {
185 helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
186 POWERPC_EXCP_FP | op);
187 }
188 }
189 return ret;
190}
191
8e703949 192static inline void float_zero_divide_excp(CPUPPCState *env)
bd23cd45
BS		 193{
194 env->fpscr |= 1 << FPSCR_ZX;
195 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
196 /* Update the floating-point exception summary */
197 env->fpscr |= 1 << FPSCR_FX;
198 if (fpscr_ze != 0) {
199 /* Update the floating-point enabled exception summary */
200 env->fpscr |= 1 << FPSCR_FEX;
201 if (msr_fe0 != 0 || msr_fe1 != 0) {
202 helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
203 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
204 }
205 }
206}
207
8e703949 208static inline void float_overflow_excp(CPUPPCState *env)
bd23cd45
BS		 209{
210 env->fpscr |= 1 << FPSCR_OX;
211 /* Update the floating-point exception summary */
212 env->fpscr |= 1 << FPSCR_FX;
213 if (fpscr_oe != 0) {
214 /* XXX: should adjust the result */
215 /* Update the floating-point enabled exception summary */
216 env->fpscr |= 1 << FPSCR_FEX;
217 /* We must update the target FPR before raising the exception */
218 env->exception_index = POWERPC_EXCP_PROGRAM;
219 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
220 } else {
221 env->fpscr |= 1 << FPSCR_XX;
222 env->fpscr |= 1 << FPSCR_FI;
223 }
224}
225
8e703949 226static inline void float_underflow_excp(CPUPPCState *env)
bd23cd45
BS		 227{
228 env->fpscr |= 1 << FPSCR_UX;
229 /* Update the floating-point exception summary */
230 env->fpscr |= 1 << FPSCR_FX;
231 if (fpscr_ue != 0) {
232 /* XXX: should adjust the result */
233 /* Update the floating-point enabled exception summary */
234 env->fpscr |= 1 << FPSCR_FEX;
235 /* We must update the target FPR before raising the exception */
236 env->exception_index = POWERPC_EXCP_PROGRAM;
237 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
238 }
239}
240
8e703949 241static inline void float_inexact_excp(CPUPPCState *env)
bd23cd45
BS		 242{
243 env->fpscr |= 1 << FPSCR_XX;
244 /* Update the floating-point exception summary */
245 env->fpscr |= 1 << FPSCR_FX;
246 if (fpscr_xe != 0) {
247 /* Update the floating-point enabled exception summary */
248 env->fpscr |= 1 << FPSCR_FEX;
249 /* We must update the target FPR before raising the exception */
250 env->exception_index = POWERPC_EXCP_PROGRAM;
251 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
252 }
253}
254
8e703949 255static inline void fpscr_set_rounding_mode(CPUPPCState *env)
bd23cd45
BS		 256{
257 int rnd_type;
258
259 /* Set rounding mode */
260 switch (fpscr_rn) {
261 case 0:
262 /* Best approximation (round to nearest) */
263 rnd_type = float_round_nearest_even;
264 break;
265 case 1:
266 /* Smaller magnitude (round toward zero) */
267 rnd_type = float_round_to_zero;
268 break;
269 case 2:
270 /* Round toward +infinite */
271 rnd_type = float_round_up;
272 break;
273 default:
274 case 3:
275 /* Round toward -infinite */
276 rnd_type = float_round_down;
277 break;
278 }
279 set_float_rounding_mode(rnd_type, &env->fp_status);
280}
281
8e703949 282void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)
bd23cd45
BS		 283{
284 int prev;
285
286 prev = (env->fpscr >> bit) & 1;
287 env->fpscr &= ~(1 << bit);
288 if (prev == 1) {
289 switch (bit) {
290 case FPSCR_RN1:
291 case FPSCR_RN:
8e703949 292 fpscr_set_rounding_mode(env);
bd23cd45
BS		 293 break;
294 default:
295 break;
296 }
297 }
298}
299
8e703949 300void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
bd23cd45
BS		 301{
302 int prev;
303
304 prev = (env->fpscr >> bit) & 1;
305 env->fpscr |= 1 << bit;
306 if (prev == 0) {
307 switch (bit) {
308 case FPSCR_VX:
309 env->fpscr |= 1 << FPSCR_FX;
310 if (fpscr_ve) {
311 goto raise_ve;
312 }
313 case FPSCR_OX:
314 env->fpscr |= 1 << FPSCR_FX;
315 if (fpscr_oe) {
316 goto raise_oe;
317 }
318 break;
319 case FPSCR_UX:
320 env->fpscr |= 1 << FPSCR_FX;
321 if (fpscr_ue) {
322 goto raise_ue;
323 }
324 break;
325 case FPSCR_ZX:
326 env->fpscr |= 1 << FPSCR_FX;
327 if (fpscr_ze) {
328 goto raise_ze;
329 }
330 break;
331 case FPSCR_XX:
332 env->fpscr |= 1 << FPSCR_FX;
333 if (fpscr_xe) {
334 goto raise_xe;
335 }
336 break;
337 case FPSCR_VXSNAN:
338 case FPSCR_VXISI:
339 case FPSCR_VXIDI:
340 case FPSCR_VXZDZ:
341 case FPSCR_VXIMZ:
342 case FPSCR_VXVC:
343 case FPSCR_VXSOFT:
344 case FPSCR_VXSQRT:
345 case FPSCR_VXCVI:
346 env->fpscr |= 1 << FPSCR_VX;
347 env->fpscr |= 1 << FPSCR_FX;
348 if (fpscr_ve != 0) {
349 goto raise_ve;
350 }
351 break;
352 case FPSCR_VE:
353 if (fpscr_vx != 0) {
354 raise_ve:
355 env->error_code = POWERPC_EXCP_FP;
356 if (fpscr_vxsnan) {
357 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
358 }
359 if (fpscr_vxisi) {
360 env->error_code |= POWERPC_EXCP_FP_VXISI;
361 }
362 if (fpscr_vxidi) {
363 env->error_code |= POWERPC_EXCP_FP_VXIDI;
364 }
365 if (fpscr_vxzdz) {
366 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
367 }
368 if (fpscr_vximz) {
369 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
370 }
371 if (fpscr_vxvc) {
372 env->error_code |= POWERPC_EXCP_FP_VXVC;
373 }
374 if (fpscr_vxsoft) {
375 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
376 }
377 if (fpscr_vxsqrt) {
378 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
379 }
380 if (fpscr_vxcvi) {
381 env->error_code |= POWERPC_EXCP_FP_VXCVI;
382 }
383 goto raise_excp;
384 }
385 break;
386 case FPSCR_OE:
387 if (fpscr_ox != 0) {
388 raise_oe:
389 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
390 goto raise_excp;
391 }
392 break;
393 case FPSCR_UE:
394 if (fpscr_ux != 0) {
395 raise_ue:
396 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
397 goto raise_excp;
398 }
399 break;
400 case FPSCR_ZE:
401 if (fpscr_zx != 0) {
402 raise_ze:
403 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
404 goto raise_excp;
405 }
406 break;
407 case FPSCR_XE:
408 if (fpscr_xx != 0) {
409 raise_xe:
410 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
411 goto raise_excp;
412 }
413 break;
414 case FPSCR_RN1:
415 case FPSCR_RN:
8e703949 416 fpscr_set_rounding_mode(env);
bd23cd45
BS		 417 break;
418 default:
419 break;
420 raise_excp:
421 /* Update the floating-point enabled exception summary */
422 env->fpscr |= 1 << FPSCR_FEX;
423 /* We have to update Rc1 before raising the exception */
424 env->exception_index = POWERPC_EXCP_PROGRAM;
425 break;
426 }
427 }
428}
429
8e703949 430void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
bd23cd45
BS		 431{
432 /*
433 * We use only the 32 LSB of the incoming fpr
434 */
435 uint32_t prev, new;
436 int i;
437
438 prev = env->fpscr;
439 new = (uint32_t)arg;
440 new &= ~0x60000000;
441 new |= prev & 0x60000000;
442 for (i = 0; i < 8; i++) {
443 if (mask & (1 << i)) {
444 env->fpscr &= ~(0xF << (4 * i));
445 env->fpscr |= new & (0xF << (4 * i));
446 }
447 }
448 /* Update VX and FEX */
449 if (fpscr_ix != 0) {
450 env->fpscr |= 1 << FPSCR_VX;
451 } else {
452 env->fpscr &= ~(1 << FPSCR_VX);
453 }
454 if ((fpscr_ex & fpscr_eex) != 0) {
455 env->fpscr |= 1 << FPSCR_FEX;
456 env->exception_index = POWERPC_EXCP_PROGRAM;
457 /* XXX: we should compute it properly */
458 env->error_code = POWERPC_EXCP_FP;
459 } else {
460 env->fpscr &= ~(1 << FPSCR_FEX);
461 }
8e703949 462 fpscr_set_rounding_mode(env);
bd23cd45
BS		 463}
464
8e703949 465void helper_float_check_status(CPUPPCState *env)
bd23cd45
BS		 466{
467 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
468 (env->error_code & POWERPC_EXCP_FP)) {
469 /* Differred floating-point exception after target FPR update */
470 if (msr_fe0 != 0 || msr_fe1 != 0) {
471 helper_raise_exception_err(env, env->exception_index,
472 env->error_code);
473 }
474 } else {
475 int status = get_float_exception_flags(&env->fp_status);
476 if (status & float_flag_divbyzero) {
8e703949 477 float_zero_divide_excp(env);
bd23cd45 478 } else if (status & float_flag_overflow) {
8e703949 479 float_overflow_excp(env);
bd23cd45 480 } else if (status & float_flag_underflow) {
8e703949 481 float_underflow_excp(env);
bd23cd45 482 } else if (status & float_flag_inexact) {
8e703949 483 float_inexact_excp(env);
bd23cd45
BS		 484 }
485 }
486}
487
8e703949 488void helper_reset_fpstatus(CPUPPCState *env)
bd23cd45
BS		 489{
490 set_float_exception_flags(0, &env->fp_status);
491}
492
493/* fadd - fadd. */
8e703949 494uint64_t helper_fadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
bd23cd45
BS		 495{
496 CPU_DoubleU farg1, farg2;
497
498 farg1.ll = arg1;
499 farg2.ll = arg2;
500
501 if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
502 float64_is_neg(farg1.d) != float64_is_neg(farg2.d))) {
503 /* Magnitude subtraction of infinities */
8e703949 504 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI);
bd23cd45
BS		 505 } else {
506 if (unlikely(float64_is_signaling_nan(farg1.d) ||
507 float64_is_signaling_nan(farg2.d))) {
508 /* sNaN addition */
8e703949 509 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
bd23cd45
BS		 510 }
511 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
512 }
513
514 return farg1.ll;
515}
516
517/* fsub - fsub. */
8e703949 518uint64_t helper_fsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
bd23cd45
BS		 519{
520 CPU_DoubleU farg1, farg2;
521
522 farg1.ll = arg1;
523 farg2.ll = arg2;
524
525 if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
526 float64_is_neg(farg1.d) == float64_is_neg(farg2.d))) {
527 /* Magnitude subtraction of infinities */
8e703949 528 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI);
bd23cd45
BS		 529 } else {
530 if (unlikely(float64_is_signaling_nan(farg1.d) ||
531 float64_is_signaling_nan(farg2.d))) {
532 /* sNaN subtraction */
8e703949 533 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
bd23cd45
BS		 534 }
535 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
536 }
537
538 return farg1.ll;
539}
540
541/* fmul - fmul. */
8e703949 542uint64_t helper_fmul(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
bd23cd45
BS		 543{
544 CPU_DoubleU farg1, farg2;
545
546 farg1.ll = arg1;
547 farg2.ll = arg2;
548
549 if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
550 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
551 /* Multiplication of zero by infinity */
8e703949 552 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ);
bd23cd45
BS		 553 } else {
554 if (unlikely(float64_is_signaling_nan(farg1.d) ||
555 float64_is_signaling_nan(farg2.d))) {
556 /* sNaN multiplication */
8e703949 557 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
bd23cd45
BS		 558 }
559 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
560 }
561
562 return farg1.ll;
563}
564
565/* fdiv - fdiv. */
8e703949 566uint64_t helper_fdiv(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
bd23cd45
BS		 567{
568 CPU_DoubleU farg1, farg2;
569
570 farg1.ll = arg1;
571 farg2.ll = arg2;
572
573 if (unlikely(float64_is_infinity(farg1.d) &&
574 float64_is_infinity(farg2.d))) {
575 /* Division of infinity by infinity */
8e703949 576 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI);
bd23cd45
BS		 577 } else if (unlikely(float64_is_zero(farg1.d) && float64_is_zero(farg2.d))) {
578 /* Division of zero by zero */
8e703949 579 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ);
bd23cd45
BS		 580 } else {
581 if (unlikely(float64_is_signaling_nan(farg1.d) ||
582 float64_is_signaling_nan(farg2.d))) {
583 /* sNaN division */
8e703949 584 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
bd23cd45
BS		 585 }
586 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
587 }
588
589 return farg1.ll;
590}
591
592/* fabs */
8e703949 593uint64_t helper_fabs(CPUPPCState *env, uint64_t arg)
bd23cd45
BS		 594{
595 CPU_DoubleU farg;
596
597 farg.ll = arg;
598 farg.d = float64_abs(farg.d);
599 return farg.ll;
600}
601
602/* fnabs */
8e703949 603uint64_t helper_fnabs(CPUPPCState *env, uint64_t arg)
bd23cd45
BS		 604{
605 CPU_DoubleU farg;
606
607 farg.ll = arg;
608 farg.d = float64_abs(farg.d);
609 farg.d = float64_chs(farg.d);
610 return farg.ll;
611}
612
613/* fneg */
8e703949 614uint64_t helper_fneg(CPUPPCState *env, uint64_t arg)
bd23cd45
BS		 615{
616 CPU_DoubleU farg;
617
618 farg.ll = arg;
619 farg.d = float64_chs(farg.d);
620 return farg.ll;
621}
622
623/* fctiw - fctiw. */
8e703949 624uint64_t helper_fctiw(CPUPPCState *env, uint64_t arg)
bd23cd45
BS		 625{
626 CPU_DoubleU farg;
627
628 farg.ll = arg;
629
630 if (unlikely(float64_is_signaling_nan(farg.d))) {
631 /* sNaN conversion */
8e703949 632 farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
bd23cd45
BS		 633 POWERPC_EXCP_FP_VXCVI);
634 } else if (unlikely(float64_is_quiet_nan(farg.d) ||
635 float64_is_infinity(farg.d))) {
636 /* qNan / infinity conversion */
8e703949 637 farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI);
bd23cd45
BS		 638 } else {
639 farg.ll = float64_to_int32(farg.d, &env->fp_status);
640 /* XXX: higher bits are not supposed to be significant.
641 * to make tests easier, return the same as a real PowerPC 750
642 */
643 farg.ll |= 0xFFF80000ULL << 32;
644 }
645 return farg.ll;
646}
647
648/* fctiwz - fctiwz. */
8e703949 649uint64_t helper_fctiwz(CPUPPCState *env, uint64_t arg)
bd23cd45
BS		 650{
651 CPU_DoubleU farg;
652
653 farg.ll = arg;
654
655 if (unlikely(float64_is_signaling_nan(farg.d))) {
656 /* sNaN conversion */
8e703949 657 farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
bd23cd45
BS		 658 POWERPC_EXCP_FP_VXCVI);
659 } else if (unlikely(float64_is_quiet_nan(farg.d) ||
660 float64_is_infinity(farg.d))) {
661 /* qNan / infinity conversion */
8e703949 662 farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI);
bd23cd45
BS		 663 } else {
664 farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
665 /* XXX: higher bits are not supposed to be significant.
666 * to make tests easier, return the same as a real PowerPC 750
667 */
668 farg.ll |= 0xFFF80000ULL << 32;
669 }
670 return farg.ll;
671}
672
673#if defined(TARGET_PPC64)
674/* fcfid - fcfid. */
8e703949 675uint64_t helper_fcfid(CPUPPCState *env, uint64_t arg)
bd23cd45
BS		 676{
677 CPU_DoubleU farg;
678
679 farg.d = int64_to_float64(arg, &env->fp_status);
680 return farg.ll;
681}
682
683/* fctid - fctid. */
8e703949 684uint64_t helper_fctid(CPUPPCState *env, uint64_t arg)
bd23cd45
BS		 685{
686 CPU_DoubleU farg;
687
688 farg.ll = arg;
689
690 if (unlikely(float64_is_signaling_nan(farg.d))) {
691 /* sNaN conversion */
8e703949 692 farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
bd23cd45
BS		 693 POWERPC_EXCP_FP_VXCVI);
694 } else if (unlikely(float64_is_quiet_nan(farg.d) ||
695 float64_is_infinity(farg.d))) {
696 /* qNan / infinity conversion */
8e703949 697 farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI);
bd23cd45
BS		 698 } else {
699 farg.ll = float64_to_int64(farg.d, &env->fp_status);
700 }
701 return farg.ll;
702}
703
704/* fctidz - fctidz. */
8e703949 705uint64_t helper_fctidz(CPUPPCState *env, uint64_t arg)
bd23cd45
BS		 706{
707 CPU_DoubleU farg;
708
709 farg.ll = arg;
710
711 if (unlikely(float64_is_signaling_nan(farg.d))) {
712 /* sNaN conversion */
8e703949 713 farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
bd23cd45
BS		 714 POWERPC_EXCP_FP_VXCVI);
715 } else if (unlikely(float64_is_quiet_nan(farg.d) ||
716 float64_is_infinity(farg.d))) {
717 /* qNan / infinity conversion */
8e703949 718 farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI);
bd23cd45
BS		 719 } else {
720 farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
721 }
722 return farg.ll;
723}
724
725#endif
726
8e703949
BS		 727static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg,
728 int rounding_mode)
bd23cd45
BS		 729{
730 CPU_DoubleU farg;
731
732 farg.ll = arg;
733
734 if (unlikely(float64_is_signaling_nan(farg.d))) {
735 /* sNaN round */
8e703949 736 farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
bd23cd45
BS		 737 POWERPC_EXCP_FP_VXCVI);
738 } else if (unlikely(float64_is_quiet_nan(farg.d) ||
739 float64_is_infinity(farg.d))) {
740 /* qNan / infinity round */
8e703949 741 farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI);
bd23cd45
BS		 742 } else {
743 set_float_rounding_mode(rounding_mode, &env->fp_status);
744 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
745 /* Restore rounding mode from FPSCR */
8e703949 746 fpscr_set_rounding_mode(env);
bd23cd45
BS		 747 }
748 return farg.ll;
749}
750
8e703949 751uint64_t helper_frin(CPUPPCState *env, uint64_t arg)
bd23cd45 752{
8e703949 753 return do_fri(env, arg, float_round_nearest_even);
bd23cd45
BS		 754}
755
8e703949 756uint64_t helper_friz(CPUPPCState *env, uint64_t arg)
bd23cd45 757{
8e703949 758 return do_fri(env, arg, float_round_to_zero);
bd23cd45
BS		 759}
760
8e703949 761uint64_t helper_frip(CPUPPCState *env, uint64_t arg)
bd23cd45 762{
8e703949 763 return do_fri(env, arg, float_round_up);
bd23cd45
BS		 764}
765
8e703949 766uint64_t helper_frim(CPUPPCState *env, uint64_t arg)
bd23cd45 767{
8e703949 768 return do_fri(env, arg, float_round_down);
bd23cd45
BS		 769}
770
771/* fmadd - fmadd. */
8e703949
BS		 772uint64_t helper_fmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
773 uint64_t arg3)
bd23cd45
BS		 774{
775 CPU_DoubleU farg1, farg2, farg3;
776
777 farg1.ll = arg1;
778 farg2.ll = arg2;
779 farg3.ll = arg3;
780
781 if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
782 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
783 /* Multiplication of zero by infinity */
8e703949 784 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ);
bd23cd45
BS		 785 } else {
786 if (unlikely(float64_is_signaling_nan(farg1.d) ||
787 float64_is_signaling_nan(farg2.d) ||
788 float64_is_signaling_nan(farg3.d))) {
789 /* sNaN operation */
8e703949 790 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
bd23cd45
BS		 791 }
792 /* This is the way the PowerPC specification defines it */
793 float128 ft0_128, ft1_128;
794
795 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
796 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
797 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
798 if (unlikely(float128_is_infinity(ft0_128) &&
799 float64_is_infinity(farg3.d) &&
800 float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
801 /* Magnitude subtraction of infinities */
8e703949 802 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI);
bd23cd45
BS		 803 } else {
804 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
805 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
806 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
807 }
808 }
809
810 return farg1.ll;
811}
812
813/* fmsub - fmsub. */
8e703949
BS		 814uint64_t helper_fmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
815 uint64_t arg3)
bd23cd45
BS		 816{
817 CPU_DoubleU farg1, farg2, farg3;
818
819 farg1.ll = arg1;
820 farg2.ll = arg2;
821 farg3.ll = arg3;
822
823 if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
824 (float64_is_zero(farg1.d) &&
825 float64_is_infinity(farg2.d)))) {
826 /* Multiplication of zero by infinity */
8e703949 827 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ);
bd23cd45
BS		 828 } else {
829 if (unlikely(float64_is_signaling_nan(farg1.d) ||
830 float64_is_signaling_nan(farg2.d) ||
831 float64_is_signaling_nan(farg3.d))) {
832 /* sNaN operation */
8e703949 833 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
bd23cd45
BS		 834 }
835 /* This is the way the PowerPC specification defines it */
836 float128 ft0_128, ft1_128;
837
838 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
839 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
840 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
841 if (unlikely(float128_is_infinity(ft0_128) &&
842 float64_is_infinity(farg3.d) &&
843 float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
844 /* Magnitude subtraction of infinities */
8e703949 845 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI);
bd23cd45
BS		 846 } else {
847 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
848 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
849 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
850 }
851 }
852 return farg1.ll;
853}
854
855/* fnmadd - fnmadd. */
8e703949
BS		 856uint64_t helper_fnmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
857 uint64_t arg3)
bd23cd45
BS		 858{
859 CPU_DoubleU farg1, farg2, farg3;
860
861 farg1.ll = arg1;
862 farg2.ll = arg2;
863 farg3.ll = arg3;
864
865 if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
866 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
867 /* Multiplication of zero by infinity */
8e703949 868 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ);
bd23cd45
BS		 869 } else {
870 if (unlikely(float64_is_signaling_nan(farg1.d) ||
871 float64_is_signaling_nan(farg2.d) ||
872 float64_is_signaling_nan(farg3.d))) {
873 /* sNaN operation */
8e703949 874 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
bd23cd45
BS		 875 }
876 /* This is the way the PowerPC specification defines it */
877 float128 ft0_128, ft1_128;
878
879 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
880 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
881 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
882 if (unlikely(float128_is_infinity(ft0_128) &&
883 float64_is_infinity(farg3.d) &&
884 float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
885 /* Magnitude subtraction of infinities */
8e703949 886 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI);
bd23cd45
BS		 887 } else {
888 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
889 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
890 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
891 }
892 if (likely(!float64_is_any_nan(farg1.d))) {
893 farg1.d = float64_chs(farg1.d);
894 }
895 }
896 return farg1.ll;
897}
898
899/* fnmsub - fnmsub. */
8e703949
BS		 900uint64_t helper_fnmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
901 uint64_t arg3)
bd23cd45
BS		 902{
903 CPU_DoubleU farg1, farg2, farg3;
904
905 farg1.ll = arg1;
906 farg2.ll = arg2;
907 farg3.ll = arg3;
908
909 if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
910 (float64_is_zero(farg1.d) &&
911 float64_is_infinity(farg2.d)))) {
912 /* Multiplication of zero by infinity */
8e703949 913 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ);
bd23cd45
BS		 914 } else {
915 if (unlikely(float64_is_signaling_nan(farg1.d) ||
916 float64_is_signaling_nan(farg2.d) ||
917 float64_is_signaling_nan(farg3.d))) {
918 /* sNaN operation */
8e703949 919 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
bd23cd45
BS		 920 }
921 /* This is the way the PowerPC specification defines it */
922 float128 ft0_128, ft1_128;
923
924 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
925 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
926 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
927 if (unlikely(float128_is_infinity(ft0_128) &&
928 float64_is_infinity(farg3.d) &&
929 float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
930 /* Magnitude subtraction of infinities */
8e703949 931 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI);
bd23cd45
BS		 932 } else {
933 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
934 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
935 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
936 }
937 if (likely(!float64_is_any_nan(farg1.d))) {
938 farg1.d = float64_chs(farg1.d);
939 }
940 }
941 return farg1.ll;
942}
943
944/* frsp - frsp. */
8e703949 945uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
bd23cd45
BS		 946{
947 CPU_DoubleU farg;
948 float32 f32;
949
950 farg.ll = arg;
951
952 if (unlikely(float64_is_signaling_nan(farg.d))) {
953 /* sNaN square root */
8e703949 954 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
bd23cd45
BS		 955 }
956 f32 = float64_to_float32(farg.d, &env->fp_status);
957 farg.d = float32_to_float64(f32, &env->fp_status);
958
959 return farg.ll;
960}
961
962/* fsqrt - fsqrt. */
8e703949 963uint64_t helper_fsqrt(CPUPPCState *env, uint64_t arg)
bd23cd45
BS		 964{
965 CPU_DoubleU farg;
966
967 farg.ll = arg;
968
969 if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
970 /* Square root of a negative nonzero number */
8e703949 971 farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT);
bd23cd45
BS		 972 } else {
973 if (unlikely(float64_is_signaling_nan(farg.d))) {
974 /* sNaN square root */
8e703949 975 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
bd23cd45
BS		 976 }
977 farg.d = float64_sqrt(farg.d, &env->fp_status);
978 }
979 return farg.ll;
980}
981
982/* fre - fre. */
8e703949 983uint64_t helper_fre(CPUPPCState *env, uint64_t arg)
bd23cd45
BS		 984{
985 CPU_DoubleU farg;
986
987 farg.ll = arg;
988
989 if (unlikely(float64_is_signaling_nan(farg.d))) {
990 /* sNaN reciprocal */
8e703949 991 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
bd23cd45
BS		 992 }
993 farg.d = float64_div(float64_one, farg.d, &env->fp_status);
994 return farg.d;
995}
996
997/* fres - fres. */
8e703949 998uint64_t helper_fres(CPUPPCState *env, uint64_t arg)
bd23cd45
BS		 999{
1000 CPU_DoubleU farg;
1001 float32 f32;
1002
1003 farg.ll = arg;
1004
1005 if (unlikely(float64_is_signaling_nan(farg.d))) {
1006 /* sNaN reciprocal */
8e703949 1007 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
bd23cd45
BS		 1008 }
1009 farg.d = float64_div(float64_one, farg.d, &env->fp_status);
1010 f32 = float64_to_float32(farg.d, &env->fp_status);
1011 farg.d = float32_to_float64(f32, &env->fp_status);
1012
1013 return farg.ll;
1014}
1015
1016/* frsqrte - frsqrte. */
8e703949 1017uint64_t helper_frsqrte(CPUPPCState *env, uint64_t arg)
bd23cd45
BS		 1018{
1019 CPU_DoubleU farg;
1020 float32 f32;
1021
1022 farg.ll = arg;
1023
1024 if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
1025 /* Reciprocal square root of a negative nonzero number */
8e703949 1026 farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT);
bd23cd45
BS		 1027 } else {
1028 if (unlikely(float64_is_signaling_nan(farg.d))) {
1029 /* sNaN reciprocal square root */
8e703949 1030 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
bd23cd45
BS		 1031 }
1032 farg.d = float64_sqrt(farg.d, &env->fp_status);
1033 farg.d = float64_div(float64_one, farg.d, &env->fp_status);
1034 f32 = float64_to_float32(farg.d, &env->fp_status);
1035 farg.d = float32_to_float64(f32, &env->fp_status);
1036 }
1037 return farg.ll;
1038}
1039
1040/* fsel - fsel. */
8e703949
BS		 1041uint64_t helper_fsel(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1042 uint64_t arg3)
bd23cd45
BS		 1043{
1044 CPU_DoubleU farg1;
1045
1046 farg1.ll = arg1;
1047
1048 if ((!float64_is_neg(farg1.d) || float64_is_zero(farg1.d)) &&
1049 !float64_is_any_nan(farg1.d)) {
1050 return arg2;
1051 } else {
1052 return arg3;
1053 }
1054}
1055
8e703949
BS		 1056void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1057 uint32_t crfD)
bd23cd45
BS		 1058{
1059 CPU_DoubleU farg1, farg2;
1060 uint32_t ret = 0;
1061
1062 farg1.ll = arg1;
1063 farg2.ll = arg2;
1064
1065 if (unlikely(float64_is_any_nan(farg1.d) ||
1066 float64_is_any_nan(farg2.d))) {
1067 ret = 0x01UL;
1068 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1069 ret = 0x08UL;
1070 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1071 ret = 0x04UL;
1072 } else {
1073 ret = 0x02UL;
1074 }
1075
1076 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1077 env->fpscr |= ret << FPSCR_FPRF;
1078 env->crf[crfD] = ret;
1079 if (unlikely(ret == 0x01UL
1080 && (float64_is_signaling_nan(farg1.d) ||
1081 float64_is_signaling_nan(farg2.d)))) {
1082 /* sNaN comparison */
8e703949 1083 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN);
bd23cd45
BS		 1084 }
1085}
1086
8e703949
BS		 1087void helper_fcmpo(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1088 uint32_t crfD)
bd23cd45
BS		 1089{
1090 CPU_DoubleU farg1, farg2;
1091 uint32_t ret = 0;
1092
1093 farg1.ll = arg1;
1094 farg2.ll = arg2;
1095
1096 if (unlikely(float64_is_any_nan(farg1.d) ||
1097 float64_is_any_nan(farg2.d))) {
1098 ret = 0x01UL;
1099 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1100 ret = 0x08UL;
1101 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1102 ret = 0x04UL;
1103 } else {
1104 ret = 0x02UL;
1105 }
1106
1107 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1108 env->fpscr |= ret << FPSCR_FPRF;
1109 env->crf[crfD] = ret;
1110 if (unlikely(ret == 0x01UL)) {
1111 if (float64_is_signaling_nan(farg1.d) ||
1112 float64_is_signaling_nan(farg2.d)) {
1113 /* sNaN comparison */
8e703949 1114 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
bd23cd45
BS		 1115 POWERPC_EXCP_FP_VXVC);
1116 } else {
1117 /* qNaN comparison */
8e703949 1118 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC);
bd23cd45
BS		 1119 }
1120 }
1121}
1122
1123/* Single-precision floating-point conversions */
8e703949 1124static inline uint32_t efscfsi(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1125{
1126 CPU_FloatU u;
1127
1128 u.f = int32_to_float32(val, &env->vec_status);
1129
1130 return u.l;
1131}
1132
8e703949 1133static inline uint32_t efscfui(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1134{
1135 CPU_FloatU u;
1136
1137 u.f = uint32_to_float32(val, &env->vec_status);
1138
1139 return u.l;
1140}
1141
8e703949 1142static inline int32_t efsctsi(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1143{
1144 CPU_FloatU u;
1145
1146 u.l = val;
1147 /* NaN are not treated the same way IEEE 754 does */
1148 if (unlikely(float32_is_quiet_nan(u.f))) {
1149 return 0;
1150 }
1151
1152 return float32_to_int32(u.f, &env->vec_status);
1153}
1154
8e703949 1155static inline uint32_t efsctui(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1156{
1157 CPU_FloatU u;
1158
1159 u.l = val;
1160 /* NaN are not treated the same way IEEE 754 does */
1161 if (unlikely(float32_is_quiet_nan(u.f))) {
1162 return 0;
1163 }
1164
1165 return float32_to_uint32(u.f, &env->vec_status);
1166}
1167
8e703949 1168static inline uint32_t efsctsiz(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1169{
1170 CPU_FloatU u;
1171
1172 u.l = val;
1173 /* NaN are not treated the same way IEEE 754 does */
1174 if (unlikely(float32_is_quiet_nan(u.f))) {
1175 return 0;
1176 }
1177
1178 return float32_to_int32_round_to_zero(u.f, &env->vec_status);
1179}
1180
8e703949 1181static inline uint32_t efsctuiz(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1182{
1183 CPU_FloatU u;
1184
1185 u.l = val;
1186 /* NaN are not treated the same way IEEE 754 does */
1187 if (unlikely(float32_is_quiet_nan(u.f))) {
1188 return 0;
1189 }
1190
1191 return float32_to_uint32_round_to_zero(u.f, &env->vec_status);
1192}
1193
8e703949 1194static inline uint32_t efscfsf(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1195{
1196 CPU_FloatU u;
1197 float32 tmp;
1198
1199 u.f = int32_to_float32(val, &env->vec_status);
1200 tmp = int64_to_float32(1ULL << 32, &env->vec_status);
1201 u.f = float32_div(u.f, tmp, &env->vec_status);
1202
1203 return u.l;
1204}
1205
8e703949 1206static inline uint32_t efscfuf(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1207{
1208 CPU_FloatU u;
1209 float32 tmp;
1210
1211 u.f = uint32_to_float32(val, &env->vec_status);
1212 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1213 u.f = float32_div(u.f, tmp, &env->vec_status);
1214
1215 return u.l;
1216}
1217
8e703949 1218static inline uint32_t efsctsf(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1219{
1220 CPU_FloatU u;
1221 float32 tmp;
1222
1223 u.l = val;
1224 /* NaN are not treated the same way IEEE 754 does */
1225 if (unlikely(float32_is_quiet_nan(u.f))) {
1226 return 0;
1227 }
1228 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1229 u.f = float32_mul(u.f, tmp, &env->vec_status);
1230
1231 return float32_to_int32(u.f, &env->vec_status);
1232}
1233
8e703949 1234static inline uint32_t efsctuf(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1235{
1236 CPU_FloatU u;
1237 float32 tmp;
1238
1239 u.l = val;
1240 /* NaN are not treated the same way IEEE 754 does */
1241 if (unlikely(float32_is_quiet_nan(u.f))) {
1242 return 0;
1243 }
1244 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1245 u.f = float32_mul(u.f, tmp, &env->vec_status);
1246
1247 return float32_to_uint32(u.f, &env->vec_status);
1248}
1249
8e703949
BS		 1250#define HELPER_SPE_SINGLE_CONV(name) \
1251 uint32_t helper_e##name(CPUPPCState *env, uint32_t val) \
1252 { \
1253 return e##name(env, val); \
bd23cd45
BS		 1254 }
1255/* efscfsi */
1256HELPER_SPE_SINGLE_CONV(fscfsi);
1257/* efscfui */
1258HELPER_SPE_SINGLE_CONV(fscfui);
1259/* efscfuf */
1260HELPER_SPE_SINGLE_CONV(fscfuf);
1261/* efscfsf */
1262HELPER_SPE_SINGLE_CONV(fscfsf);
1263/* efsctsi */
1264HELPER_SPE_SINGLE_CONV(fsctsi);
1265/* efsctui */
1266HELPER_SPE_SINGLE_CONV(fsctui);
1267/* efsctsiz */
1268HELPER_SPE_SINGLE_CONV(fsctsiz);
1269/* efsctuiz */
1270HELPER_SPE_SINGLE_CONV(fsctuiz);
1271/* efsctsf */
1272HELPER_SPE_SINGLE_CONV(fsctsf);
1273/* efsctuf */
1274HELPER_SPE_SINGLE_CONV(fsctuf);
1275
8e703949
BS		 1276#define HELPER_SPE_VECTOR_CONV(name) \
1277 uint64_t helper_ev##name(CPUPPCState *env, uint64_t val) \
1278 { \
1279 return ((uint64_t)e##name(env, val >> 32) << 32) | \
1280 (uint64_t)e##name(env, val); \
bd23cd45
BS		 1281 }
1282/* evfscfsi */
1283HELPER_SPE_VECTOR_CONV(fscfsi);
1284/* evfscfui */
1285HELPER_SPE_VECTOR_CONV(fscfui);
1286/* evfscfuf */
1287HELPER_SPE_VECTOR_CONV(fscfuf);
1288/* evfscfsf */
1289HELPER_SPE_VECTOR_CONV(fscfsf);
1290/* evfsctsi */
1291HELPER_SPE_VECTOR_CONV(fsctsi);
1292/* evfsctui */
1293HELPER_SPE_VECTOR_CONV(fsctui);
1294/* evfsctsiz */
1295HELPER_SPE_VECTOR_CONV(fsctsiz);
1296/* evfsctuiz */
1297HELPER_SPE_VECTOR_CONV(fsctuiz);
1298/* evfsctsf */
1299HELPER_SPE_VECTOR_CONV(fsctsf);
1300/* evfsctuf */
1301HELPER_SPE_VECTOR_CONV(fsctuf);
1302
1303/* Single-precision floating-point arithmetic */
8e703949 1304static inline uint32_t efsadd(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1305{
1306 CPU_FloatU u1, u2;
1307
1308 u1.l = op1;
1309 u2.l = op2;
1310 u1.f = float32_add(u1.f, u2.f, &env->vec_status);
1311 return u1.l;
1312}
1313
8e703949 1314static inline uint32_t efssub(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1315{
1316 CPU_FloatU u1, u2;
1317
1318 u1.l = op1;
1319 u2.l = op2;
1320 u1.f = float32_sub(u1.f, u2.f, &env->vec_status);
1321 return u1.l;
1322}
1323
8e703949 1324static inline uint32_t efsmul(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1325{
1326 CPU_FloatU u1, u2;
1327
1328 u1.l = op1;
1329 u2.l = op2;
1330 u1.f = float32_mul(u1.f, u2.f, &env->vec_status);
1331 return u1.l;
1332}
1333
8e703949 1334static inline uint32_t efsdiv(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1335{
1336 CPU_FloatU u1, u2;
1337
1338 u1.l = op1;
1339 u2.l = op2;
1340 u1.f = float32_div(u1.f, u2.f, &env->vec_status);
1341 return u1.l;
1342}
1343
8e703949
BS		 1344#define HELPER_SPE_SINGLE_ARITH(name) \
1345 uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1346 { \
1347 return e##name(env, op1, op2); \
bd23cd45
BS		 1348 }
1349/* efsadd */
1350HELPER_SPE_SINGLE_ARITH(fsadd);
1351/* efssub */
1352HELPER_SPE_SINGLE_ARITH(fssub);
1353/* efsmul */
1354HELPER_SPE_SINGLE_ARITH(fsmul);
1355/* efsdiv */
1356HELPER_SPE_SINGLE_ARITH(fsdiv);
1357
1358#define HELPER_SPE_VECTOR_ARITH(name) \
8e703949 1359 uint64_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
bd23cd45 1360 { \
8e703949
BS		 1361 return ((uint64_t)e##name(env, op1 >> 32, op2 >> 32) << 32) | \
1362 (uint64_t)e##name(env, op1, op2); \
bd23cd45
BS		 1363 }
1364/* evfsadd */
1365HELPER_SPE_VECTOR_ARITH(fsadd);
1366/* evfssub */
1367HELPER_SPE_VECTOR_ARITH(fssub);
1368/* evfsmul */
1369HELPER_SPE_VECTOR_ARITH(fsmul);
1370/* evfsdiv */
1371HELPER_SPE_VECTOR_ARITH(fsdiv);
1372
1373/* Single-precision floating-point comparisons */
8e703949 1374static inline uint32_t efscmplt(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1375{
1376 CPU_FloatU u1, u2;
1377
1378 u1.l = op1;
1379 u2.l = op2;
1380 return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1381}
1382
8e703949 1383static inline uint32_t efscmpgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1384{
1385 CPU_FloatU u1, u2;
1386
1387 u1.l = op1;
1388 u2.l = op2;
1389 return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4;
1390}
1391
8e703949 1392static inline uint32_t efscmpeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1393{
1394 CPU_FloatU u1, u2;
1395
1396 u1.l = op1;
1397 u2.l = op2;
1398 return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1399}
1400
8e703949 1401static inline uint32_t efststlt(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1402{
1403 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
8e703949 1404 return efscmplt(env, op1, op2);
bd23cd45
BS		 1405}
1406
8e703949 1407static inline uint32_t efststgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1408{
1409 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
8e703949 1410 return efscmpgt(env, op1, op2);
bd23cd45
BS		 1411}
1412
8e703949 1413static inline uint32_t efststeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1414{
1415 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
8e703949 1416 return efscmpeq(env, op1, op2);
bd23cd45
BS		 1417}
1418
8e703949
BS		 1419#define HELPER_SINGLE_SPE_CMP(name) \
1420 uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1421 { \
1422 return e##name(env, op1, op2) << 2; \
bd23cd45
BS		 1423 }
1424/* efststlt */
1425HELPER_SINGLE_SPE_CMP(fststlt);
1426/* efststgt */
1427HELPER_SINGLE_SPE_CMP(fststgt);
1428/* efststeq */
1429HELPER_SINGLE_SPE_CMP(fststeq);
1430/* efscmplt */
1431HELPER_SINGLE_SPE_CMP(fscmplt);
1432/* efscmpgt */
1433HELPER_SINGLE_SPE_CMP(fscmpgt);
1434/* efscmpeq */
1435HELPER_SINGLE_SPE_CMP(fscmpeq);
1436
1437static inline uint32_t evcmp_merge(int t0, int t1)
1438{
1439 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1440}
1441
1442#define HELPER_VECTOR_SPE_CMP(name) \
8e703949 1443 uint32_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
bd23cd45 1444 { \
8e703949
BS		 1445 return evcmp_merge(e##name(env, op1 >> 32, op2 >> 32), \
1446 e##name(env, op1, op2)); \
bd23cd45
BS		 1447 }
1448/* evfststlt */
1449HELPER_VECTOR_SPE_CMP(fststlt);
1450/* evfststgt */
1451HELPER_VECTOR_SPE_CMP(fststgt);
1452/* evfststeq */
1453HELPER_VECTOR_SPE_CMP(fststeq);
1454/* evfscmplt */
1455HELPER_VECTOR_SPE_CMP(fscmplt);
1456/* evfscmpgt */
1457HELPER_VECTOR_SPE_CMP(fscmpgt);
1458/* evfscmpeq */
1459HELPER_VECTOR_SPE_CMP(fscmpeq);
1460
1461/* Double-precision floating-point conversion */
8e703949 1462uint64_t helper_efdcfsi(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1463{
1464 CPU_DoubleU u;
1465
1466 u.d = int32_to_float64(val, &env->vec_status);
1467
1468 return u.ll;
1469}
1470
8e703949 1471uint64_t helper_efdcfsid(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1472{
1473 CPU_DoubleU u;
1474
1475 u.d = int64_to_float64(val, &env->vec_status);
1476
1477 return u.ll;
1478}
1479
8e703949 1480uint64_t helper_efdcfui(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1481{
1482 CPU_DoubleU u;
1483
1484 u.d = uint32_to_float64(val, &env->vec_status);
1485
1486 return u.ll;
1487}
1488
8e703949 1489uint64_t helper_efdcfuid(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1490{
1491 CPU_DoubleU u;
1492
1493 u.d = uint64_to_float64(val, &env->vec_status);
1494
1495 return u.ll;
1496}
1497
8e703949 1498uint32_t helper_efdctsi(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1499{
1500 CPU_DoubleU u;
1501
1502 u.ll = val;
1503 /* NaN are not treated the same way IEEE 754 does */
1504 if (unlikely(float64_is_any_nan(u.d))) {
1505 return 0;
1506 }
1507
1508 return float64_to_int32(u.d, &env->vec_status);
1509}
1510
8e703949 1511uint32_t helper_efdctui(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1512{
1513 CPU_DoubleU u;
1514
1515 u.ll = val;
1516 /* NaN are not treated the same way IEEE 754 does */
1517 if (unlikely(float64_is_any_nan(u.d))) {
1518 return 0;
1519 }
1520
1521 return float64_to_uint32(u.d, &env->vec_status);
1522}
1523
8e703949 1524uint32_t helper_efdctsiz(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1525{
1526 CPU_DoubleU u;
1527
1528 u.ll = val;
1529 /* NaN are not treated the same way IEEE 754 does */
1530 if (unlikely(float64_is_any_nan(u.d))) {
1531 return 0;
1532 }
1533
1534 return float64_to_int32_round_to_zero(u.d, &env->vec_status);
1535}
1536
8e703949 1537uint64_t helper_efdctsidz(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1538{
1539 CPU_DoubleU u;
1540
1541 u.ll = val;
1542 /* NaN are not treated the same way IEEE 754 does */
1543 if (unlikely(float64_is_any_nan(u.d))) {
1544 return 0;
1545 }
1546
1547 return float64_to_int64_round_to_zero(u.d, &env->vec_status);
1548}
1549
8e703949 1550uint32_t helper_efdctuiz(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1551{
1552 CPU_DoubleU u;
1553
1554 u.ll = val;
1555 /* NaN are not treated the same way IEEE 754 does */
1556 if (unlikely(float64_is_any_nan(u.d))) {
1557 return 0;
1558 }
1559
1560 return float64_to_uint32_round_to_zero(u.d, &env->vec_status);
1561}
1562
8e703949 1563uint64_t helper_efdctuidz(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1564{
1565 CPU_DoubleU u;
1566
1567 u.ll = val;
1568 /* NaN are not treated the same way IEEE 754 does */
1569 if (unlikely(float64_is_any_nan(u.d))) {
1570 return 0;
1571 }
1572
1573 return float64_to_uint64_round_to_zero(u.d, &env->vec_status);
1574}
1575
8e703949 1576uint64_t helper_efdcfsf(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1577{
1578 CPU_DoubleU u;
1579 float64 tmp;
1580
1581 u.d = int32_to_float64(val, &env->vec_status);
1582 tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1583 u.d = float64_div(u.d, tmp, &env->vec_status);
1584
1585 return u.ll;
1586}
1587
8e703949 1588uint64_t helper_efdcfuf(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1589{
1590 CPU_DoubleU u;
1591 float64 tmp;
1592
1593 u.d = uint32_to_float64(val, &env->vec_status);
1594 tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1595 u.d = float64_div(u.d, tmp, &env->vec_status);
1596
1597 return u.ll;
1598}
1599
8e703949 1600uint32_t helper_efdctsf(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1601{
1602 CPU_DoubleU u;
1603 float64 tmp;
1604
1605 u.ll = val;
1606 /* NaN are not treated the same way IEEE 754 does */
1607 if (unlikely(float64_is_any_nan(u.d))) {
1608 return 0;
1609 }
1610 tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1611 u.d = float64_mul(u.d, tmp, &env->vec_status);
1612
1613 return float64_to_int32(u.d, &env->vec_status);
1614}
1615
8e703949 1616uint32_t helper_efdctuf(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1617{
1618 CPU_DoubleU u;
1619 float64 tmp;
1620
1621 u.ll = val;
1622 /* NaN are not treated the same way IEEE 754 does */
1623 if (unlikely(float64_is_any_nan(u.d))) {
1624 return 0;
1625 }
1626 tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1627 u.d = float64_mul(u.d, tmp, &env->vec_status);
1628
1629 return float64_to_uint32(u.d, &env->vec_status);
1630}
1631
8e703949 1632uint32_t helper_efscfd(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1633{
1634 CPU_DoubleU u1;
1635 CPU_FloatU u2;
1636
1637 u1.ll = val;
1638 u2.f = float64_to_float32(u1.d, &env->vec_status);
1639
1640 return u2.l;
1641}
1642
8e703949 1643uint64_t helper_efdcfs(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1644{
1645 CPU_DoubleU u2;
1646 CPU_FloatU u1;
1647
1648 u1.l = val;
1649 u2.d = float32_to_float64(u1.f, &env->vec_status);
1650
1651 return u2.ll;
1652}
1653
1654/* Double precision fixed-point arithmetic */
8e703949 1655uint64_t helper_efdadd(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1656{
1657 CPU_DoubleU u1, u2;
1658
1659 u1.ll = op1;
1660 u2.ll = op2;
1661 u1.d = float64_add(u1.d, u2.d, &env->vec_status);
1662 return u1.ll;
1663}
1664
8e703949 1665uint64_t helper_efdsub(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1666{
1667 CPU_DoubleU u1, u2;
1668
1669 u1.ll = op1;
1670 u2.ll = op2;
1671 u1.d = float64_sub(u1.d, u2.d, &env->vec_status);
1672 return u1.ll;
1673}
1674
8e703949 1675uint64_t helper_efdmul(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1676{
1677 CPU_DoubleU u1, u2;
1678
1679 u1.ll = op1;
1680 u2.ll = op2;
1681 u1.d = float64_mul(u1.d, u2.d, &env->vec_status);
1682 return u1.ll;
1683}
1684
8e703949 1685uint64_t helper_efddiv(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1686{
1687 CPU_DoubleU u1, u2;
1688
1689 u1.ll = op1;
1690 u2.ll = op2;
1691 u1.d = float64_div(u1.d, u2.d, &env->vec_status);
1692 return u1.ll;
1693}
1694
1695/* Double precision floating point helpers */
8e703949 1696uint32_t helper_efdtstlt(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1697{
1698 CPU_DoubleU u1, u2;
1699
1700 u1.ll = op1;
1701 u2.ll = op2;
1702 return float64_lt(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1703}
1704
8e703949 1705uint32_t helper_efdtstgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1706{
1707 CPU_DoubleU u1, u2;
1708
1709 u1.ll = op1;
1710 u2.ll = op2;
1711 return float64_le(u1.d, u2.d, &env->vec_status) ? 0 : 4;
1712}
1713
8e703949 1714uint32_t helper_efdtsteq(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1715{
1716 CPU_DoubleU u1, u2;
1717
1718 u1.ll = op1;
1719 u2.ll = op2;
1720 return float64_eq_quiet(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1721}
1722
8e703949 1723uint32_t helper_efdcmplt(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1724{
1725 /* XXX: TODO: test special values (NaN, infinites, ...) */
8e703949 1726 return helper_efdtstlt(env, op1, op2);
bd23cd45
BS		 1727}
1728
8e703949 1729uint32_t helper_efdcmpgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1730{
1731 /* XXX: TODO: test special values (NaN, infinites, ...) */
8e703949 1732 return helper_efdtstgt(env, op1, op2);
bd23cd45
BS		 1733}
1734
8e703949 1735uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1736{
1737 /* XXX: TODO: test special values (NaN, infinites, ...) */
8e703949 1738 return helper_efdtsteq(env, op1, op2);
bd23cd45 1739}
Qemu copy for testing