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79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation helpers for qemu. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
79aceca5 FB |
5 | * |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
fad6cb1a | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA |
79aceca5 | 19 | */ |
fdabc366 FB |
20 | #include <stdarg.h> |
21 | #include <stdlib.h> | |
22 | #include <stdio.h> | |
23 | #include <string.h> | |
24 | #include <inttypes.h> | |
25 | #include <signal.h> | |
fdabc366 FB |
26 | |
27 | #include "cpu.h" | |
28 | #include "exec-all.h" | |
0411a972 | 29 | #include "helper_regs.h" |
ca10f867 | 30 | #include "qemu-common.h" |
d76d1650 | 31 | #include "kvm.h" |
9a64fbe4 FB |
32 | |
33 | //#define DEBUG_MMU | |
34 | //#define DEBUG_BATS | |
6b542af7 | 35 | //#define DEBUG_SLB |
76a66253 | 36 | //#define DEBUG_SOFTWARE_TLB |
0411a972 | 37 | //#define DUMP_PAGE_TABLES |
9a64fbe4 | 38 | //#define DEBUG_EXCEPTIONS |
fdabc366 | 39 | //#define FLUSH_ALL_TLBS |
9a64fbe4 | 40 | |
d12d51d5 | 41 | #ifdef DEBUG_MMU |
93fcfe39 AL |
42 | # define LOG_MMU(...) qemu_log(__VA_ARGS__) |
43 | # define LOG_MMU_STATE(env) log_cpu_state((env), 0) | |
d12d51d5 AL |
44 | #else |
45 | # define LOG_MMU(...) do { } while (0) | |
46 | # define LOG_MMU_STATE(...) do { } while (0) | |
47 | #endif | |
48 | ||
49 | ||
50 | #ifdef DEBUG_SOFTWARE_TLB | |
93fcfe39 | 51 | # define LOG_SWTLB(...) qemu_log(__VA_ARGS__) |
d12d51d5 AL |
52 | #else |
53 | # define LOG_SWTLB(...) do { } while (0) | |
54 | #endif | |
55 | ||
56 | #ifdef DEBUG_BATS | |
93fcfe39 | 57 | # define LOG_BATS(...) qemu_log(__VA_ARGS__) |
d12d51d5 AL |
58 | #else |
59 | # define LOG_BATS(...) do { } while (0) | |
60 | #endif | |
61 | ||
62 | #ifdef DEBUG_SLB | |
93fcfe39 | 63 | # define LOG_SLB(...) qemu_log(__VA_ARGS__) |
d12d51d5 AL |
64 | #else |
65 | # define LOG_SLB(...) do { } while (0) | |
66 | #endif | |
67 | ||
68 | #ifdef DEBUG_EXCEPTIONS | |
93fcfe39 | 69 | # define LOG_EXCP(...) qemu_log(__VA_ARGS__) |
d12d51d5 AL |
70 | #else |
71 | # define LOG_EXCP(...) do { } while (0) | |
72 | #endif | |
73 | ||
74 | ||
64adab3f | 75 | /*****************************************************************************/ |
3fc6c082 | 76 | /* PowerPC MMU emulation */ |
a541f297 | 77 | |
d9bce9d9 | 78 | #if defined(CONFIG_USER_ONLY) |
e96efcfc | 79 | int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
6ebbf390 | 80 | int mmu_idx, int is_softmmu) |
24741ef3 FB |
81 | { |
82 | int exception, error_code; | |
d9bce9d9 | 83 | |
24741ef3 | 84 | if (rw == 2) { |
e1833e1f | 85 | exception = POWERPC_EXCP_ISI; |
8f793433 | 86 | error_code = 0x40000000; |
24741ef3 | 87 | } else { |
e1833e1f | 88 | exception = POWERPC_EXCP_DSI; |
8f793433 | 89 | error_code = 0x40000000; |
24741ef3 FB |
90 | if (rw) |
91 | error_code |= 0x02000000; | |
92 | env->spr[SPR_DAR] = address; | |
93 | env->spr[SPR_DSISR] = error_code; | |
94 | } | |
95 | env->exception_index = exception; | |
96 | env->error_code = error_code; | |
76a66253 | 97 | |
24741ef3 FB |
98 | return 1; |
99 | } | |
76a66253 | 100 | |
9b3c35e0 | 101 | target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
24741ef3 FB |
102 | { |
103 | return addr; | |
104 | } | |
36081602 | 105 | |
24741ef3 | 106 | #else |
76a66253 | 107 | /* Common routines used by software and hardware TLBs emulation */ |
b068d6a7 | 108 | static always_inline int pte_is_valid (target_ulong pte0) |
76a66253 JM |
109 | { |
110 | return pte0 & 0x80000000 ? 1 : 0; | |
111 | } | |
112 | ||
b068d6a7 | 113 | static always_inline void pte_invalidate (target_ulong *pte0) |
76a66253 JM |
114 | { |
115 | *pte0 &= ~0x80000000; | |
116 | } | |
117 | ||
caa4039c | 118 | #if defined(TARGET_PPC64) |
b068d6a7 | 119 | static always_inline int pte64_is_valid (target_ulong pte0) |
caa4039c JM |
120 | { |
121 | return pte0 & 0x0000000000000001ULL ? 1 : 0; | |
122 | } | |
123 | ||
b068d6a7 | 124 | static always_inline void pte64_invalidate (target_ulong *pte0) |
caa4039c JM |
125 | { |
126 | *pte0 &= ~0x0000000000000001ULL; | |
127 | } | |
128 | #endif | |
129 | ||
76a66253 JM |
130 | #define PTE_PTEM_MASK 0x7FFFFFBF |
131 | #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) | |
caa4039c JM |
132 | #if defined(TARGET_PPC64) |
133 | #define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL | |
134 | #define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F) | |
135 | #endif | |
76a66253 | 136 | |
b227a8e9 JM |
137 | static always_inline int pp_check (int key, int pp, int nx) |
138 | { | |
139 | int access; | |
140 | ||
141 | /* Compute access rights */ | |
142 | /* When pp is 3/7, the result is undefined. Set it to noaccess */ | |
143 | access = 0; | |
144 | if (key == 0) { | |
145 | switch (pp) { | |
146 | case 0x0: | |
147 | case 0x1: | |
148 | case 0x2: | |
149 | access |= PAGE_WRITE; | |
150 | /* No break here */ | |
151 | case 0x3: | |
152 | case 0x6: | |
153 | access |= PAGE_READ; | |
154 | break; | |
155 | } | |
156 | } else { | |
157 | switch (pp) { | |
158 | case 0x0: | |
159 | case 0x6: | |
160 | access = 0; | |
161 | break; | |
162 | case 0x1: | |
163 | case 0x3: | |
164 | access = PAGE_READ; | |
165 | break; | |
166 | case 0x2: | |
167 | access = PAGE_READ | PAGE_WRITE; | |
168 | break; | |
169 | } | |
170 | } | |
171 | if (nx == 0) | |
172 | access |= PAGE_EXEC; | |
173 | ||
174 | return access; | |
175 | } | |
176 | ||
177 | static always_inline int check_prot (int prot, int rw, int access_type) | |
178 | { | |
179 | int ret; | |
180 | ||
181 | if (access_type == ACCESS_CODE) { | |
182 | if (prot & PAGE_EXEC) | |
183 | ret = 0; | |
184 | else | |
185 | ret = -2; | |
186 | } else if (rw) { | |
187 | if (prot & PAGE_WRITE) | |
188 | ret = 0; | |
189 | else | |
190 | ret = -2; | |
191 | } else { | |
192 | if (prot & PAGE_READ) | |
193 | ret = 0; | |
194 | else | |
195 | ret = -2; | |
196 | } | |
197 | ||
198 | return ret; | |
199 | } | |
200 | ||
b068d6a7 JM |
201 | static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b, |
202 | target_ulong pte0, target_ulong pte1, | |
b227a8e9 | 203 | int h, int rw, int type) |
76a66253 | 204 | { |
caa4039c | 205 | target_ulong ptem, mmask; |
b227a8e9 | 206 | int access, ret, pteh, ptev, pp; |
76a66253 JM |
207 | |
208 | access = 0; | |
209 | ret = -1; | |
210 | /* Check validity and table match */ | |
caa4039c JM |
211 | #if defined(TARGET_PPC64) |
212 | if (is_64b) { | |
213 | ptev = pte64_is_valid(pte0); | |
214 | pteh = (pte0 >> 1) & 1; | |
215 | } else | |
216 | #endif | |
217 | { | |
218 | ptev = pte_is_valid(pte0); | |
219 | pteh = (pte0 >> 6) & 1; | |
220 | } | |
221 | if (ptev && h == pteh) { | |
76a66253 | 222 | /* Check vsid & api */ |
caa4039c JM |
223 | #if defined(TARGET_PPC64) |
224 | if (is_64b) { | |
225 | ptem = pte0 & PTE64_PTEM_MASK; | |
226 | mmask = PTE64_CHECK_MASK; | |
b227a8e9 | 227 | pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004); |
29c8ca6f | 228 | ctx->nx = (pte1 >> 2) & 1; /* No execute bit */ |
b227a8e9 | 229 | ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */ |
caa4039c JM |
230 | } else |
231 | #endif | |
232 | { | |
233 | ptem = pte0 & PTE_PTEM_MASK; | |
234 | mmask = PTE_CHECK_MASK; | |
b227a8e9 | 235 | pp = pte1 & 0x00000003; |
caa4039c JM |
236 | } |
237 | if (ptem == ctx->ptem) { | |
6f2d8978 | 238 | if (ctx->raddr != (target_phys_addr_t)-1ULL) { |
76a66253 | 239 | /* all matches should have equal RPN, WIMG & PP */ |
caa4039c | 240 | if ((ctx->raddr & mmask) != (pte1 & mmask)) { |
93fcfe39 | 241 | qemu_log("Bad RPN/WIMG/PP\n"); |
76a66253 JM |
242 | return -3; |
243 | } | |
244 | } | |
245 | /* Compute access rights */ | |
b227a8e9 | 246 | access = pp_check(ctx->key, pp, ctx->nx); |
76a66253 JM |
247 | /* Keep the matching PTE informations */ |
248 | ctx->raddr = pte1; | |
249 | ctx->prot = access; | |
b227a8e9 JM |
250 | ret = check_prot(ctx->prot, rw, type); |
251 | if (ret == 0) { | |
76a66253 | 252 | /* Access granted */ |
d12d51d5 | 253 | LOG_MMU("PTE access granted !\n"); |
76a66253 JM |
254 | } else { |
255 | /* Access right violation */ | |
d12d51d5 | 256 | LOG_MMU("PTE access rejected\n"); |
76a66253 JM |
257 | } |
258 | } | |
259 | } | |
260 | ||
261 | return ret; | |
262 | } | |
263 | ||
a11b8151 JM |
264 | static always_inline int pte32_check (mmu_ctx_t *ctx, |
265 | target_ulong pte0, target_ulong pte1, | |
266 | int h, int rw, int type) | |
caa4039c | 267 | { |
b227a8e9 | 268 | return _pte_check(ctx, 0, pte0, pte1, h, rw, type); |
caa4039c JM |
269 | } |
270 | ||
271 | #if defined(TARGET_PPC64) | |
a11b8151 JM |
272 | static always_inline int pte64_check (mmu_ctx_t *ctx, |
273 | target_ulong pte0, target_ulong pte1, | |
274 | int h, int rw, int type) | |
caa4039c | 275 | { |
b227a8e9 | 276 | return _pte_check(ctx, 1, pte0, pte1, h, rw, type); |
caa4039c JM |
277 | } |
278 | #endif | |
279 | ||
a11b8151 JM |
280 | static always_inline int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p, |
281 | int ret, int rw) | |
76a66253 JM |
282 | { |
283 | int store = 0; | |
284 | ||
285 | /* Update page flags */ | |
286 | if (!(*pte1p & 0x00000100)) { | |
287 | /* Update accessed flag */ | |
288 | *pte1p |= 0x00000100; | |
289 | store = 1; | |
290 | } | |
291 | if (!(*pte1p & 0x00000080)) { | |
292 | if (rw == 1 && ret == 0) { | |
293 | /* Update changed flag */ | |
294 | *pte1p |= 0x00000080; | |
295 | store = 1; | |
296 | } else { | |
297 | /* Force page fault for first write access */ | |
298 | ctx->prot &= ~PAGE_WRITE; | |
299 | } | |
300 | } | |
301 | ||
302 | return store; | |
303 | } | |
304 | ||
305 | /* Software driven TLB helpers */ | |
a11b8151 JM |
306 | static always_inline int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr, |
307 | int way, int is_code) | |
76a66253 JM |
308 | { |
309 | int nr; | |
310 | ||
311 | /* Select TLB num in a way from address */ | |
312 | nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1); | |
313 | /* Select TLB way */ | |
314 | nr += env->tlb_per_way * way; | |
315 | /* 6xx have separate TLBs for instructions and data */ | |
316 | if (is_code && env->id_tlbs == 1) | |
317 | nr += env->nb_tlb; | |
318 | ||
319 | return nr; | |
320 | } | |
321 | ||
a11b8151 | 322 | static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env) |
76a66253 | 323 | { |
1d0a48fb | 324 | ppc6xx_tlb_t *tlb; |
76a66253 JM |
325 | int nr, max; |
326 | ||
d12d51d5 | 327 | //LOG_SWTLB("Invalidate all TLBs\n"); |
76a66253 JM |
328 | /* Invalidate all defined software TLB */ |
329 | max = env->nb_tlb; | |
330 | if (env->id_tlbs == 1) | |
331 | max *= 2; | |
332 | for (nr = 0; nr < max; nr++) { | |
1d0a48fb | 333 | tlb = &env->tlb[nr].tlb6; |
76a66253 JM |
334 | pte_invalidate(&tlb->pte0); |
335 | } | |
76a66253 | 336 | tlb_flush(env, 1); |
76a66253 JM |
337 | } |
338 | ||
b068d6a7 JM |
339 | static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env, |
340 | target_ulong eaddr, | |
341 | int is_code, | |
342 | int match_epn) | |
76a66253 | 343 | { |
4a057712 | 344 | #if !defined(FLUSH_ALL_TLBS) |
1d0a48fb | 345 | ppc6xx_tlb_t *tlb; |
76a66253 JM |
346 | int way, nr; |
347 | ||
76a66253 JM |
348 | /* Invalidate ITLB + DTLB, all ways */ |
349 | for (way = 0; way < env->nb_ways; way++) { | |
350 | nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code); | |
1d0a48fb | 351 | tlb = &env->tlb[nr].tlb6; |
76a66253 | 352 | if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) { |
d12d51d5 | 353 | LOG_SWTLB("TLB invalidate %d/%d " ADDRX "\n", |
76a66253 | 354 | nr, env->nb_tlb, eaddr); |
76a66253 JM |
355 | pte_invalidate(&tlb->pte0); |
356 | tlb_flush_page(env, tlb->EPN); | |
357 | } | |
358 | } | |
359 | #else | |
360 | /* XXX: PowerPC specification say this is valid as well */ | |
361 | ppc6xx_tlb_invalidate_all(env); | |
362 | #endif | |
363 | } | |
364 | ||
a11b8151 JM |
365 | static always_inline void ppc6xx_tlb_invalidate_virt (CPUState *env, |
366 | target_ulong eaddr, | |
367 | int is_code) | |
76a66253 JM |
368 | { |
369 | __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0); | |
370 | } | |
371 | ||
372 | void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code, | |
373 | target_ulong pte0, target_ulong pte1) | |
374 | { | |
1d0a48fb | 375 | ppc6xx_tlb_t *tlb; |
76a66253 JM |
376 | int nr; |
377 | ||
378 | nr = ppc6xx_tlb_getnum(env, EPN, way, is_code); | |
1d0a48fb | 379 | tlb = &env->tlb[nr].tlb6; |
d12d51d5 | 380 | LOG_SWTLB("Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX |
1b9eb036 | 381 | " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1); |
76a66253 JM |
382 | /* Invalidate any pending reference in Qemu for this virtual address */ |
383 | __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1); | |
384 | tlb->pte0 = pte0; | |
385 | tlb->pte1 = pte1; | |
386 | tlb->EPN = EPN; | |
76a66253 JM |
387 | /* Store last way for LRU mechanism */ |
388 | env->last_way = way; | |
389 | } | |
390 | ||
a11b8151 JM |
391 | static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx, |
392 | target_ulong eaddr, int rw, | |
393 | int access_type) | |
76a66253 | 394 | { |
1d0a48fb | 395 | ppc6xx_tlb_t *tlb; |
76a66253 JM |
396 | int nr, best, way; |
397 | int ret; | |
d9bce9d9 | 398 | |
76a66253 JM |
399 | best = -1; |
400 | ret = -1; /* No TLB found */ | |
401 | for (way = 0; way < env->nb_ways; way++) { | |
402 | nr = ppc6xx_tlb_getnum(env, eaddr, way, | |
403 | access_type == ACCESS_CODE ? 1 : 0); | |
1d0a48fb | 404 | tlb = &env->tlb[nr].tlb6; |
76a66253 JM |
405 | /* This test "emulates" the PTE index match for hardware TLBs */ |
406 | if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) { | |
d12d51d5 | 407 | LOG_SWTLB("TLB %d/%d %s [" ADDRX " " ADDRX |
1b9eb036 | 408 | "] <> " ADDRX "\n", |
76a66253 JM |
409 | nr, env->nb_tlb, |
410 | pte_is_valid(tlb->pte0) ? "valid" : "inval", | |
411 | tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr); | |
76a66253 JM |
412 | continue; |
413 | } | |
d12d51d5 | 414 | LOG_SWTLB("TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX |
1b9eb036 | 415 | " %c %c\n", |
76a66253 JM |
416 | nr, env->nb_tlb, |
417 | pte_is_valid(tlb->pte0) ? "valid" : "inval", | |
418 | tlb->EPN, eaddr, tlb->pte1, | |
419 | rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D'); | |
b227a8e9 | 420 | switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) { |
76a66253 JM |
421 | case -3: |
422 | /* TLB inconsistency */ | |
423 | return -1; | |
424 | case -2: | |
425 | /* Access violation */ | |
426 | ret = -2; | |
427 | best = nr; | |
428 | break; | |
429 | case -1: | |
430 | default: | |
431 | /* No match */ | |
432 | break; | |
433 | case 0: | |
434 | /* access granted */ | |
435 | /* XXX: we should go on looping to check all TLBs consistency | |
436 | * but we can speed-up the whole thing as the | |
437 | * result would be undefined if TLBs are not consistent. | |
438 | */ | |
439 | ret = 0; | |
440 | best = nr; | |
441 | goto done; | |
442 | } | |
443 | } | |
444 | if (best != -1) { | |
445 | done: | |
d12d51d5 | 446 | LOG_SWTLB("found TLB at addr " PADDRX " prot=%01x ret=%d\n", |
76a66253 | 447 | ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret); |
76a66253 | 448 | /* Update page flags */ |
1d0a48fb | 449 | pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw); |
76a66253 JM |
450 | } |
451 | ||
452 | return ret; | |
453 | } | |
454 | ||
9a64fbe4 | 455 | /* Perform BAT hit & translation */ |
faadf50e JM |
456 | static always_inline void bat_size_prot (CPUState *env, target_ulong *blp, |
457 | int *validp, int *protp, | |
458 | target_ulong *BATu, target_ulong *BATl) | |
459 | { | |
460 | target_ulong bl; | |
461 | int pp, valid, prot; | |
462 | ||
463 | bl = (*BATu & 0x00001FFC) << 15; | |
464 | valid = 0; | |
465 | prot = 0; | |
466 | if (((msr_pr == 0) && (*BATu & 0x00000002)) || | |
467 | ((msr_pr != 0) && (*BATu & 0x00000001))) { | |
468 | valid = 1; | |
469 | pp = *BATl & 0x00000003; | |
470 | if (pp != 0) { | |
471 | prot = PAGE_READ | PAGE_EXEC; | |
472 | if (pp == 0x2) | |
473 | prot |= PAGE_WRITE; | |
474 | } | |
475 | } | |
476 | *blp = bl; | |
477 | *validp = valid; | |
478 | *protp = prot; | |
479 | } | |
480 | ||
481 | static always_inline void bat_601_size_prot (CPUState *env,target_ulong *blp, | |
482 | int *validp, int *protp, | |
483 | target_ulong *BATu, | |
484 | target_ulong *BATl) | |
485 | { | |
486 | target_ulong bl; | |
487 | int key, pp, valid, prot; | |
488 | ||
489 | bl = (*BATl & 0x0000003F) << 17; | |
d12d51d5 | 490 | LOG_BATS("b %02x ==> bl " ADDRX " msk " ADDRX "\n", |
6b542af7 | 491 | (uint8_t)(*BATl & 0x0000003F), bl, ~bl); |
faadf50e JM |
492 | prot = 0; |
493 | valid = (*BATl >> 6) & 1; | |
494 | if (valid) { | |
495 | pp = *BATu & 0x00000003; | |
496 | if (msr_pr == 0) | |
497 | key = (*BATu >> 3) & 1; | |
498 | else | |
499 | key = (*BATu >> 2) & 1; | |
500 | prot = pp_check(key, pp, 0); | |
501 | } | |
502 | *blp = bl; | |
503 | *validp = valid; | |
504 | *protp = prot; | |
505 | } | |
506 | ||
a11b8151 JM |
507 | static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx, |
508 | target_ulong virtual, int rw, int type) | |
9a64fbe4 | 509 | { |
76a66253 JM |
510 | target_ulong *BATlt, *BATut, *BATu, *BATl; |
511 | target_ulong base, BEPIl, BEPIu, bl; | |
faadf50e | 512 | int i, valid, prot; |
9a64fbe4 FB |
513 | int ret = -1; |
514 | ||
d12d51d5 | 515 | LOG_BATS("%s: %cBAT v " ADDRX "\n", __func__, |
76a66253 | 516 | type == ACCESS_CODE ? 'I' : 'D', virtual); |
9a64fbe4 FB |
517 | switch (type) { |
518 | case ACCESS_CODE: | |
519 | BATlt = env->IBAT[1]; | |
520 | BATut = env->IBAT[0]; | |
521 | break; | |
522 | default: | |
523 | BATlt = env->DBAT[1]; | |
524 | BATut = env->DBAT[0]; | |
525 | break; | |
526 | } | |
9a64fbe4 | 527 | base = virtual & 0xFFFC0000; |
faadf50e | 528 | for (i = 0; i < env->nb_BATs; i++) { |
9a64fbe4 FB |
529 | BATu = &BATut[i]; |
530 | BATl = &BATlt[i]; | |
531 | BEPIu = *BATu & 0xF0000000; | |
532 | BEPIl = *BATu & 0x0FFE0000; | |
faadf50e JM |
533 | if (unlikely(env->mmu_model == POWERPC_MMU_601)) { |
534 | bat_601_size_prot(env, &bl, &valid, &prot, BATu, BATl); | |
535 | } else { | |
536 | bat_size_prot(env, &bl, &valid, &prot, BATu, BATl); | |
537 | } | |
d12d51d5 | 538 | LOG_BATS("%s: %cBAT%d v " ADDRX " BATu " ADDRX |
6b542af7 JM |
539 | " BATl " ADDRX "\n", __func__, |
540 | type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl); | |
9a64fbe4 FB |
541 | if ((virtual & 0xF0000000) == BEPIu && |
542 | ((virtual & 0x0FFE0000) & ~bl) == BEPIl) { | |
543 | /* BAT matches */ | |
faadf50e | 544 | if (valid != 0) { |
9a64fbe4 | 545 | /* Get physical address */ |
76a66253 | 546 | ctx->raddr = (*BATl & 0xF0000000) | |
9a64fbe4 | 547 | ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) | |
a541f297 | 548 | (virtual & 0x0001F000); |
b227a8e9 | 549 | /* Compute access rights */ |
faadf50e | 550 | ctx->prot = prot; |
b227a8e9 | 551 | ret = check_prot(ctx->prot, rw, type); |
d12d51d5 AL |
552 | if (ret == 0) |
553 | LOG_BATS("BAT %d match: r " PADDRX " prot=%c%c\n", | |
554 | i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', | |
555 | ctx->prot & PAGE_WRITE ? 'W' : '-'); | |
9a64fbe4 FB |
556 | break; |
557 | } | |
558 | } | |
559 | } | |
560 | if (ret < 0) { | |
d12d51d5 AL |
561 | #if defined(DEBUG_BATS) |
562 | if (IS_LOGGING) { | |
563 | QEMU_LOG0("no BAT match for " ADDRX ":\n", virtual); | |
4a057712 JM |
564 | for (i = 0; i < 4; i++) { |
565 | BATu = &BATut[i]; | |
566 | BATl = &BATlt[i]; | |
567 | BEPIu = *BATu & 0xF0000000; | |
568 | BEPIl = *BATu & 0x0FFE0000; | |
569 | bl = (*BATu & 0x00001FFC) << 15; | |
d12d51d5 | 570 | QEMU_LOG0("%s: %cBAT%d v " ADDRX " BATu " ADDRX |
6b542af7 | 571 | " BATl " ADDRX " \n\t" ADDRX " " ADDRX " " ADDRX "\n", |
4a057712 JM |
572 | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
573 | *BATu, *BATl, BEPIu, BEPIl, bl); | |
574 | } | |
9a64fbe4 FB |
575 | } |
576 | #endif | |
9a64fbe4 FB |
577 | } |
578 | /* No hit */ | |
579 | return ret; | |
580 | } | |
581 | ||
582 | /* PTE table lookup */ | |
b227a8e9 | 583 | static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, |
5b5aba4f BS |
584 | int rw, int type, |
585 | int target_page_bits) | |
9a64fbe4 | 586 | { |
76a66253 JM |
587 | target_ulong base, pte0, pte1; |
588 | int i, good = -1; | |
caa4039c | 589 | int ret, r; |
9a64fbe4 | 590 | |
76a66253 JM |
591 | ret = -1; /* No entry found */ |
592 | base = ctx->pg_addr[h]; | |
9a64fbe4 | 593 | for (i = 0; i < 8; i++) { |
caa4039c JM |
594 | #if defined(TARGET_PPC64) |
595 | if (is_64b) { | |
596 | pte0 = ldq_phys(base + (i * 16)); | |
5b5aba4f BS |
597 | pte1 = ldq_phys(base + (i * 16) + 8); |
598 | ||
599 | /* We have a TLB that saves 4K pages, so let's | |
600 | * split a huge page to 4k chunks */ | |
601 | if (target_page_bits != TARGET_PAGE_BITS) | |
602 | pte1 |= (ctx->eaddr & (( 1 << target_page_bits ) - 1)) | |
603 | & TARGET_PAGE_MASK; | |
604 | ||
b227a8e9 | 605 | r = pte64_check(ctx, pte0, pte1, h, rw, type); |
d12d51d5 | 606 | LOG_MMU("Load pte from " ADDRX " => " ADDRX " " ADDRX |
6b542af7 | 607 | " %d %d %d " ADDRX "\n", |
12de9a39 JM |
608 | base + (i * 16), pte0, pte1, |
609 | (int)(pte0 & 1), h, (int)((pte0 >> 1) & 1), | |
610 | ctx->ptem); | |
caa4039c JM |
611 | } else |
612 | #endif | |
613 | { | |
614 | pte0 = ldl_phys(base + (i * 8)); | |
615 | pte1 = ldl_phys(base + (i * 8) + 4); | |
b227a8e9 | 616 | r = pte32_check(ctx, pte0, pte1, h, rw, type); |
d12d51d5 | 617 | LOG_MMU("Load pte from " ADDRX " => " ADDRX " " ADDRX |
6b542af7 | 618 | " %d %d %d " ADDRX "\n", |
12de9a39 JM |
619 | base + (i * 8), pte0, pte1, |
620 | (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1), | |
621 | ctx->ptem); | |
12de9a39 | 622 | } |
caa4039c | 623 | switch (r) { |
76a66253 JM |
624 | case -3: |
625 | /* PTE inconsistency */ | |
626 | return -1; | |
627 | case -2: | |
628 | /* Access violation */ | |
629 | ret = -2; | |
630 | good = i; | |
631 | break; | |
632 | case -1: | |
633 | default: | |
634 | /* No PTE match */ | |
635 | break; | |
636 | case 0: | |
637 | /* access granted */ | |
638 | /* XXX: we should go on looping to check all PTEs consistency | |
639 | * but if we can speed-up the whole thing as the | |
640 | * result would be undefined if PTEs are not consistent. | |
641 | */ | |
642 | ret = 0; | |
643 | good = i; | |
644 | goto done; | |
9a64fbe4 FB |
645 | } |
646 | } | |
647 | if (good != -1) { | |
76a66253 | 648 | done: |
d12d51d5 | 649 | LOG_MMU("found PTE at addr " PADDRX " prot=%01x ret=%d\n", |
76a66253 | 650 | ctx->raddr, ctx->prot, ret); |
9a64fbe4 | 651 | /* Update page flags */ |
76a66253 | 652 | pte1 = ctx->raddr; |
caa4039c JM |
653 | if (pte_update_flags(ctx, &pte1, ret, rw) == 1) { |
654 | #if defined(TARGET_PPC64) | |
655 | if (is_64b) { | |
656 | stq_phys_notdirty(base + (good * 16) + 8, pte1); | |
657 | } else | |
658 | #endif | |
659 | { | |
660 | stl_phys_notdirty(base + (good * 8) + 4, pte1); | |
661 | } | |
662 | } | |
9a64fbe4 FB |
663 | } |
664 | ||
665 | return ret; | |
79aceca5 FB |
666 | } |
667 | ||
5b5aba4f BS |
668 | static always_inline int find_pte32 (mmu_ctx_t *ctx, int h, int rw, |
669 | int type, int target_page_bits) | |
caa4039c | 670 | { |
5b5aba4f | 671 | return _find_pte(ctx, 0, h, rw, type, target_page_bits); |
caa4039c JM |
672 | } |
673 | ||
674 | #if defined(TARGET_PPC64) | |
5b5aba4f BS |
675 | static always_inline int find_pte64 (mmu_ctx_t *ctx, int h, int rw, |
676 | int type, int target_page_bits) | |
caa4039c | 677 | { |
5b5aba4f | 678 | return _find_pte(ctx, 1, h, rw, type, target_page_bits); |
caa4039c JM |
679 | } |
680 | #endif | |
681 | ||
b068d6a7 | 682 | static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx, |
5b5aba4f BS |
683 | int h, int rw, int type, |
684 | int target_page_bits) | |
caa4039c JM |
685 | { |
686 | #if defined(TARGET_PPC64) | |
add78955 | 687 | if (env->mmu_model & POWERPC_MMU_64) |
5b5aba4f | 688 | return find_pte64(ctx, h, rw, type, target_page_bits); |
caa4039c JM |
689 | #endif |
690 | ||
5b5aba4f | 691 | return find_pte32(ctx, h, rw, type, target_page_bits); |
caa4039c JM |
692 | } |
693 | ||
caa4039c | 694 | #if defined(TARGET_PPC64) |
8eee0af9 | 695 | static ppc_slb_t *slb_get_entry(CPUPPCState *env, int nr) |
eacc3249 | 696 | { |
8eee0af9 BS |
697 | ppc_slb_t *retval = &env->slb[nr]; |
698 | ||
699 | #if 0 // XXX implement bridge mode? | |
700 | if (env->spr[SPR_ASR] & 1) { | |
701 | target_phys_addr_t sr_base; | |
702 | ||
703 | sr_base = env->spr[SPR_ASR] & 0xfffffffffffff000; | |
704 | sr_base += (12 * nr); | |
705 | ||
706 | retval->tmp64 = ldq_phys(sr_base); | |
707 | retval->tmp = ldl_phys(sr_base + 8); | |
708 | } | |
709 | #endif | |
710 | ||
711 | return retval; | |
eacc3249 JM |
712 | } |
713 | ||
8eee0af9 | 714 | static void slb_set_entry(CPUPPCState *env, int nr, ppc_slb_t *slb) |
eacc3249 | 715 | { |
8eee0af9 BS |
716 | ppc_slb_t *entry = &env->slb[nr]; |
717 | ||
718 | if (slb == entry) | |
719 | return; | |
720 | ||
721 | entry->tmp64 = slb->tmp64; | |
722 | entry->tmp = slb->tmp; | |
723 | } | |
724 | ||
725 | static always_inline int slb_is_valid (ppc_slb_t *slb) | |
726 | { | |
727 | return (int)(slb->tmp64 & 0x0000000008000000ULL); | |
728 | } | |
729 | ||
730 | static always_inline void slb_invalidate (ppc_slb_t *slb) | |
731 | { | |
732 | slb->tmp64 &= ~0x0000000008000000ULL; | |
eacc3249 JM |
733 | } |
734 | ||
a11b8151 JM |
735 | static always_inline int slb_lookup (CPUPPCState *env, target_ulong eaddr, |
736 | target_ulong *vsid, | |
5b5aba4f BS |
737 | target_ulong *page_mask, int *attr, |
738 | int *target_page_bits) | |
caa4039c | 739 | { |
caa4039c | 740 | target_ulong mask; |
caa4039c | 741 | int n, ret; |
caa4039c JM |
742 | |
743 | ret = -5; | |
8eee0af9 | 744 | LOG_SLB("%s: eaddr " ADDRX "\n", __func__, eaddr); |
caa4039c | 745 | mask = 0x0000000000000000ULL; /* Avoid gcc warning */ |
eacc3249 | 746 | for (n = 0; n < env->slb_nr; n++) { |
8eee0af9 BS |
747 | ppc_slb_t *slb = slb_get_entry(env, n); |
748 | ||
749 | LOG_SLB("%s: seg %d %016" PRIx64 " %08" | |
750 | PRIx32 "\n", __func__, n, slb->tmp64, slb->tmp); | |
751 | if (slb_is_valid(slb)) { | |
caa4039c | 752 | /* SLB entry is valid */ |
8eee0af9 | 753 | if (slb->tmp & 0x8) { |
5b5aba4f | 754 | /* 1 TB Segment */ |
caa4039c | 755 | mask = 0xFFFF000000000000ULL; |
5b5aba4f BS |
756 | if (target_page_bits) |
757 | *target_page_bits = 24; // XXX 16M pages? | |
758 | } else { | |
759 | /* 256MB Segment */ | |
760 | mask = 0xFFFFFFFFF0000000ULL; | |
761 | if (target_page_bits) | |
762 | *target_page_bits = TARGET_PAGE_BITS; | |
caa4039c | 763 | } |
8eee0af9 | 764 | if ((eaddr & mask) == (slb->tmp64 & mask)) { |
caa4039c | 765 | /* SLB match */ |
8eee0af9 | 766 | *vsid = ((slb->tmp64 << 24) | (slb->tmp >> 8)) & 0x0003FFFFFFFFFFFFULL; |
caa4039c | 767 | *page_mask = ~mask; |
8eee0af9 | 768 | *attr = slb->tmp & 0xFF; |
eacc3249 | 769 | ret = n; |
caa4039c JM |
770 | break; |
771 | } | |
772 | } | |
caa4039c JM |
773 | } |
774 | ||
775 | return ret; | |
79aceca5 | 776 | } |
12de9a39 | 777 | |
eacc3249 JM |
778 | void ppc_slb_invalidate_all (CPUPPCState *env) |
779 | { | |
eacc3249 JM |
780 | int n, do_invalidate; |
781 | ||
782 | do_invalidate = 0; | |
2c1ee068 JM |
783 | /* XXX: Warning: slbia never invalidates the first segment */ |
784 | for (n = 1; n < env->slb_nr; n++) { | |
8eee0af9 BS |
785 | ppc_slb_t *slb = slb_get_entry(env, n); |
786 | ||
787 | if (slb_is_valid(slb)) { | |
788 | slb_invalidate(slb); | |
789 | slb_set_entry(env, n, slb); | |
eacc3249 JM |
790 | /* XXX: given the fact that segment size is 256 MB or 1TB, |
791 | * and we still don't have a tlb_flush_mask(env, n, mask) | |
792 | * in Qemu, we just invalidate all TLBs | |
793 | */ | |
794 | do_invalidate = 1; | |
795 | } | |
eacc3249 JM |
796 | } |
797 | if (do_invalidate) | |
798 | tlb_flush(env, 1); | |
799 | } | |
800 | ||
801 | void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0) | |
802 | { | |
eacc3249 | 803 | target_ulong vsid, page_mask; |
eacc3249 JM |
804 | int attr; |
805 | int n; | |
806 | ||
5b5aba4f | 807 | n = slb_lookup(env, T0, &vsid, &page_mask, &attr, NULL); |
eacc3249 | 808 | if (n >= 0) { |
8eee0af9 BS |
809 | ppc_slb_t *slb = slb_get_entry(env, n); |
810 | ||
811 | if (slb_is_valid(slb)) { | |
812 | slb_invalidate(slb); | |
813 | slb_set_entry(env, n, slb); | |
eacc3249 JM |
814 | /* XXX: given the fact that segment size is 256 MB or 1TB, |
815 | * and we still don't have a tlb_flush_mask(env, n, mask) | |
816 | * in Qemu, we just invalidate all TLBs | |
817 | */ | |
818 | tlb_flush(env, 1); | |
819 | } | |
820 | } | |
821 | } | |
822 | ||
12de9a39 JM |
823 | target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr) |
824 | { | |
12de9a39 | 825 | target_ulong rt; |
8eee0af9 BS |
826 | ppc_slb_t *slb = slb_get_entry(env, slb_nr); |
827 | ||
828 | if (slb_is_valid(slb)) { | |
12de9a39 JM |
829 | /* SLB entry is valid */ |
830 | /* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */ | |
8eee0af9 BS |
831 | rt = slb->tmp >> 8; /* 65:88 => 40:63 */ |
832 | rt |= (slb->tmp64 & 0x7) << 24; /* 62:64 => 37:39 */ | |
12de9a39 | 833 | /* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */ |
8eee0af9 | 834 | rt |= ((slb->tmp >> 4) & 0xF) << 27; |
12de9a39 JM |
835 | } else { |
836 | rt = 0; | |
837 | } | |
8eee0af9 BS |
838 | LOG_SLB("%s: %016" PRIx64 " %08" PRIx32 " => %d " |
839 | ADDRX "\n", __func__, slb->tmp64, slb->tmp, slb_nr, rt); | |
12de9a39 JM |
840 | |
841 | return rt; | |
842 | } | |
843 | ||
f6b868fc | 844 | void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs) |
12de9a39 | 845 | { |
8eee0af9 | 846 | ppc_slb_t *slb; |
12de9a39 | 847 | |
f6b868fc BS |
848 | uint64_t vsid; |
849 | uint64_t esid; | |
850 | int flags, valid, slb_nr; | |
851 | ||
852 | vsid = rs >> 12; | |
853 | flags = ((rs >> 8) & 0xf); | |
854 | ||
855 | esid = rb >> 28; | |
856 | valid = (rb & (1 << 27)); | |
857 | slb_nr = rb & 0xfff; | |
858 | ||
8eee0af9 BS |
859 | slb = slb_get_entry(env, slb_nr); |
860 | slb->tmp64 = (esid << 28) | valid | (vsid >> 24); | |
861 | slb->tmp = (vsid << 8) | (flags << 3); | |
f6b868fc | 862 | |
8eee0af9 | 863 | LOG_SLB("%s: %d " ADDRX " - " ADDRX " => %016" PRIx64 |
6b542af7 | 864 | " %08" PRIx32 "\n", __func__, |
8eee0af9 | 865 | slb_nr, rb, rs, tmp64, tmp); |
f6b868fc | 866 | |
8eee0af9 | 867 | slb_set_entry(env, slb_nr, slb); |
12de9a39 | 868 | } |
caa4039c | 869 | #endif /* defined(TARGET_PPC64) */ |
79aceca5 | 870 | |
9a64fbe4 | 871 | /* Perform segment based translation */ |
b068d6a7 JM |
872 | static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1, |
873 | int sdr_sh, | |
874 | target_phys_addr_t hash, | |
875 | target_phys_addr_t mask) | |
12de9a39 | 876 | { |
6f2d8978 | 877 | return (sdr1 & ((target_phys_addr_t)(-1ULL) << sdr_sh)) | (hash & mask); |
12de9a39 JM |
878 | } |
879 | ||
a11b8151 JM |
880 | static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx, |
881 | target_ulong eaddr, int rw, int type) | |
79aceca5 | 882 | { |
12de9a39 | 883 | target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask; |
caa4039c JM |
884 | target_ulong sr, vsid, vsid_mask, pgidx, page_mask; |
885 | #if defined(TARGET_PPC64) | |
886 | int attr; | |
9a64fbe4 | 887 | #endif |
5b5aba4f | 888 | int ds, vsid_sh, sdr_sh, pr, target_page_bits; |
caa4039c JM |
889 | int ret, ret2; |
890 | ||
0411a972 | 891 | pr = msr_pr; |
caa4039c | 892 | #if defined(TARGET_PPC64) |
add78955 | 893 | if (env->mmu_model & POWERPC_MMU_64) { |
d12d51d5 | 894 | LOG_MMU("Check SLBs\n"); |
5b5aba4f BS |
895 | ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr, |
896 | &target_page_bits); | |
caa4039c JM |
897 | if (ret < 0) |
898 | return ret; | |
0411a972 JM |
899 | ctx->key = ((attr & 0x40) && (pr != 0)) || |
900 | ((attr & 0x80) && (pr == 0)) ? 1 : 0; | |
caa4039c | 901 | ds = 0; |
5b5aba4f BS |
902 | ctx->nx = attr & 0x10 ? 1 : 0; |
903 | ctx->eaddr = eaddr; | |
caa4039c JM |
904 | vsid_mask = 0x00003FFFFFFFFF80ULL; |
905 | vsid_sh = 7; | |
906 | sdr_sh = 18; | |
907 | sdr_mask = 0x3FF80; | |
908 | } else | |
909 | #endif /* defined(TARGET_PPC64) */ | |
910 | { | |
911 | sr = env->sr[eaddr >> 28]; | |
912 | page_mask = 0x0FFFFFFF; | |
0411a972 JM |
913 | ctx->key = (((sr & 0x20000000) && (pr != 0)) || |
914 | ((sr & 0x40000000) && (pr == 0))) ? 1 : 0; | |
caa4039c | 915 | ds = sr & 0x80000000 ? 1 : 0; |
b227a8e9 | 916 | ctx->nx = sr & 0x10000000 ? 1 : 0; |
caa4039c JM |
917 | vsid = sr & 0x00FFFFFF; |
918 | vsid_mask = 0x01FFFFC0; | |
919 | vsid_sh = 6; | |
920 | sdr_sh = 16; | |
921 | sdr_mask = 0xFFC0; | |
5b5aba4f | 922 | target_page_bits = TARGET_PAGE_BITS; |
d12d51d5 | 923 | LOG_MMU("Check segment v=" ADDRX " %d " ADDRX |
6b542af7 | 924 | " nip=" ADDRX " lr=" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n", |
caa4039c | 925 | eaddr, (int)(eaddr >> 28), sr, env->nip, |
0411a972 JM |
926 | env->lr, (int)msr_ir, (int)msr_dr, pr != 0 ? 1 : 0, |
927 | rw, type); | |
caa4039c | 928 | } |
d12d51d5 | 929 | LOG_MMU("pte segment: key=%d ds %d nx %d vsid " ADDRX "\n", |
b227a8e9 | 930 | ctx->key, ds, ctx->nx, vsid); |
caa4039c JM |
931 | ret = -1; |
932 | if (!ds) { | |
9a64fbe4 | 933 | /* Check if instruction fetch is allowed, if needed */ |
b227a8e9 | 934 | if (type != ACCESS_CODE || ctx->nx == 0) { |
9a64fbe4 | 935 | /* Page address translation */ |
76a66253 JM |
936 | /* Primary table address */ |
937 | sdr = env->sdr1; | |
5b5aba4f | 938 | pgidx = (eaddr & page_mask) >> target_page_bits; |
12de9a39 | 939 | #if defined(TARGET_PPC64) |
add78955 | 940 | if (env->mmu_model & POWERPC_MMU_64) { |
12de9a39 JM |
941 | htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F)); |
942 | /* XXX: this is false for 1 TB segments */ | |
943 | hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; | |
944 | } else | |
945 | #endif | |
946 | { | |
947 | htab_mask = sdr & 0x000001FF; | |
948 | hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; | |
949 | } | |
950 | mask = (htab_mask << sdr_sh) | sdr_mask; | |
d12d51d5 | 951 | LOG_MMU("sdr " PADDRX " sh %d hash " PADDRX |
6b542af7 JM |
952 | " mask " PADDRX " " ADDRX "\n", |
953 | sdr, sdr_sh, hash, mask, page_mask); | |
caa4039c | 954 | ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask); |
76a66253 | 955 | /* Secondary table address */ |
caa4039c | 956 | hash = (~hash) & vsid_mask; |
d12d51d5 | 957 | LOG_MMU("sdr " PADDRX " sh %d hash " PADDRX |
6b542af7 JM |
958 | " mask " PADDRX "\n", |
959 | sdr, sdr_sh, hash, mask); | |
caa4039c JM |
960 | ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask); |
961 | #if defined(TARGET_PPC64) | |
add78955 | 962 | if (env->mmu_model & POWERPC_MMU_64) { |
caa4039c | 963 | /* Only 5 bits of the page index are used in the AVPN */ |
5b5aba4f BS |
964 | if (target_page_bits > 23) { |
965 | ctx->ptem = (vsid << 12) | | |
966 | ((pgidx << (target_page_bits - 16)) & 0xF80); | |
967 | } else { | |
968 | ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80); | |
969 | } | |
caa4039c JM |
970 | } else |
971 | #endif | |
972 | { | |
973 | ctx->ptem = (vsid << 7) | (pgidx >> 10); | |
974 | } | |
76a66253 | 975 | /* Initialize real address with an invalid value */ |
6f2d8978 | 976 | ctx->raddr = (target_phys_addr_t)-1ULL; |
7dbe11ac JM |
977 | if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx || |
978 | env->mmu_model == POWERPC_MMU_SOFT_74xx)) { | |
76a66253 JM |
979 | /* Software TLB search */ |
980 | ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type); | |
76a66253 | 981 | } else { |
d12d51d5 | 982 | LOG_MMU("0 sdr1=" PADDRX " vsid=" ADDRX " " |
6b542af7 JM |
983 | "api=" ADDRX " hash=" PADDRX |
984 | " pg_addr=" PADDRX "\n", | |
985 | sdr, vsid, pgidx, hash, ctx->pg_addr[0]); | |
76a66253 | 986 | /* Primary table lookup */ |
5b5aba4f | 987 | ret = find_pte(env, ctx, 0, rw, type, target_page_bits); |
76a66253 JM |
988 | if (ret < 0) { |
989 | /* Secondary table lookup */ | |
d12d51d5 AL |
990 | if (eaddr != 0xEFFFFFFF) |
991 | LOG_MMU("1 sdr1=" PADDRX " vsid=" ADDRX " " | |
6b542af7 JM |
992 | "api=" ADDRX " hash=" PADDRX |
993 | " pg_addr=" PADDRX "\n", | |
994 | sdr, vsid, pgidx, hash, ctx->pg_addr[1]); | |
5b5aba4f BS |
995 | ret2 = find_pte(env, ctx, 1, rw, type, |
996 | target_page_bits); | |
76a66253 JM |
997 | if (ret2 != -1) |
998 | ret = ret2; | |
999 | } | |
9a64fbe4 | 1000 | } |
0411a972 | 1001 | #if defined (DUMP_PAGE_TABLES) |
93fcfe39 | 1002 | if (qemu_log_enabled()) { |
b33c17e1 JM |
1003 | target_phys_addr_t curaddr; |
1004 | uint32_t a0, a1, a2, a3; | |
93fcfe39 AL |
1005 | qemu_log("Page table: " PADDRX " len " PADDRX "\n", |
1006 | sdr, mask + 0x80); | |
b33c17e1 JM |
1007 | for (curaddr = sdr; curaddr < (sdr + mask + 0x80); |
1008 | curaddr += 16) { | |
1009 | a0 = ldl_phys(curaddr); | |
1010 | a1 = ldl_phys(curaddr + 4); | |
1011 | a2 = ldl_phys(curaddr + 8); | |
1012 | a3 = ldl_phys(curaddr + 12); | |
1013 | if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) { | |
93fcfe39 AL |
1014 | qemu_log(PADDRX ": %08x %08x %08x %08x\n", |
1015 | curaddr, a0, a1, a2, a3); | |
12de9a39 | 1016 | } |
b33c17e1 JM |
1017 | } |
1018 | } | |
12de9a39 | 1019 | #endif |
9a64fbe4 | 1020 | } else { |
d12d51d5 | 1021 | LOG_MMU("No access allowed\n"); |
76a66253 | 1022 | ret = -3; |
9a64fbe4 FB |
1023 | } |
1024 | } else { | |
d12d51d5 | 1025 | LOG_MMU("direct store...\n"); |
9a64fbe4 FB |
1026 | /* Direct-store segment : absolutely *BUGGY* for now */ |
1027 | switch (type) { | |
1028 | case ACCESS_INT: | |
1029 | /* Integer load/store : only access allowed */ | |
1030 | break; | |
1031 | case ACCESS_CODE: | |
1032 | /* No code fetch is allowed in direct-store areas */ | |
1033 | return -4; | |
1034 | case ACCESS_FLOAT: | |
1035 | /* Floating point load/store */ | |
1036 | return -4; | |
1037 | case ACCESS_RES: | |
1038 | /* lwarx, ldarx or srwcx. */ | |
1039 | return -4; | |
1040 | case ACCESS_CACHE: | |
1041 | /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */ | |
1042 | /* Should make the instruction do no-op. | |
1043 | * As it already do no-op, it's quite easy :-) | |
1044 | */ | |
76a66253 | 1045 | ctx->raddr = eaddr; |
9a64fbe4 FB |
1046 | return 0; |
1047 | case ACCESS_EXT: | |
1048 | /* eciwx or ecowx */ | |
1049 | return -4; | |
1050 | default: | |
93fcfe39 | 1051 | qemu_log("ERROR: instruction should not need " |
9a64fbe4 | 1052 | "address translation\n"); |
9a64fbe4 FB |
1053 | return -4; |
1054 | } | |
76a66253 JM |
1055 | if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) { |
1056 | ctx->raddr = eaddr; | |
9a64fbe4 FB |
1057 | ret = 2; |
1058 | } else { | |
1059 | ret = -2; | |
1060 | } | |
79aceca5 | 1061 | } |
9a64fbe4 FB |
1062 | |
1063 | return ret; | |
79aceca5 FB |
1064 | } |
1065 | ||
c294fc58 | 1066 | /* Generic TLB check function for embedded PowerPC implementations */ |
a11b8151 JM |
1067 | static always_inline int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb, |
1068 | target_phys_addr_t *raddrp, | |
1069 | target_ulong address, | |
1070 | uint32_t pid, int ext, int i) | |
c294fc58 JM |
1071 | { |
1072 | target_ulong mask; | |
1073 | ||
1074 | /* Check valid flag */ | |
1075 | if (!(tlb->prot & PAGE_VALID)) { | |
93fcfe39 | 1076 | qemu_log("%s: TLB %d not valid\n", __func__, i); |
c294fc58 JM |
1077 | return -1; |
1078 | } | |
1079 | mask = ~(tlb->size - 1); | |
d12d51d5 | 1080 | LOG_SWTLB("%s: TLB %d address " ADDRX " PID %u <=> " ADDRX |
6b542af7 JM |
1081 | " " ADDRX " %u\n", |
1082 | __func__, i, address, pid, tlb->EPN, mask, (uint32_t)tlb->PID); | |
c294fc58 | 1083 | /* Check PID */ |
36081602 | 1084 | if (tlb->PID != 0 && tlb->PID != pid) |
c294fc58 JM |
1085 | return -1; |
1086 | /* Check effective address */ | |
1087 | if ((address & mask) != tlb->EPN) | |
1088 | return -1; | |
1089 | *raddrp = (tlb->RPN & mask) | (address & ~mask); | |
9706285b | 1090 | #if (TARGET_PHYS_ADDR_BITS >= 36) |
36081602 JM |
1091 | if (ext) { |
1092 | /* Extend the physical address to 36 bits */ | |
1093 | *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32; | |
1094 | } | |
9706285b | 1095 | #endif |
c294fc58 JM |
1096 | |
1097 | return 0; | |
1098 | } | |
1099 | ||
1100 | /* Generic TLB search function for PowerPC embedded implementations */ | |
36081602 | 1101 | int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid) |
c294fc58 JM |
1102 | { |
1103 | ppcemb_tlb_t *tlb; | |
1104 | target_phys_addr_t raddr; | |
1105 | int i, ret; | |
1106 | ||
1107 | /* Default return value is no match */ | |
1108 | ret = -1; | |
a750fc0b | 1109 | for (i = 0; i < env->nb_tlb; i++) { |
c294fc58 | 1110 | tlb = &env->tlb[i].tlbe; |
36081602 | 1111 | if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) { |
c294fc58 JM |
1112 | ret = i; |
1113 | break; | |
1114 | } | |
1115 | } | |
1116 | ||
1117 | return ret; | |
1118 | } | |
1119 | ||
daf4f96e | 1120 | /* Helpers specific to PowerPC 40x implementations */ |
a11b8151 | 1121 | static always_inline void ppc4xx_tlb_invalidate_all (CPUState *env) |
a750fc0b JM |
1122 | { |
1123 | ppcemb_tlb_t *tlb; | |
a750fc0b JM |
1124 | int i; |
1125 | ||
1126 | for (i = 0; i < env->nb_tlb; i++) { | |
1127 | tlb = &env->tlb[i].tlbe; | |
daf4f96e | 1128 | tlb->prot &= ~PAGE_VALID; |
a750fc0b | 1129 | } |
daf4f96e | 1130 | tlb_flush(env, 1); |
a750fc0b JM |
1131 | } |
1132 | ||
a11b8151 JM |
1133 | static always_inline void ppc4xx_tlb_invalidate_virt (CPUState *env, |
1134 | target_ulong eaddr, | |
1135 | uint32_t pid) | |
0a032cbe | 1136 | { |
daf4f96e | 1137 | #if !defined(FLUSH_ALL_TLBS) |
0a032cbe | 1138 | ppcemb_tlb_t *tlb; |
daf4f96e JM |
1139 | target_phys_addr_t raddr; |
1140 | target_ulong page, end; | |
0a032cbe JM |
1141 | int i; |
1142 | ||
1143 | for (i = 0; i < env->nb_tlb; i++) { | |
1144 | tlb = &env->tlb[i].tlbe; | |
daf4f96e | 1145 | if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) { |
0a032cbe JM |
1146 | end = tlb->EPN + tlb->size; |
1147 | for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) | |
1148 | tlb_flush_page(env, page); | |
0a032cbe | 1149 | tlb->prot &= ~PAGE_VALID; |
daf4f96e | 1150 | break; |
0a032cbe JM |
1151 | } |
1152 | } | |
daf4f96e JM |
1153 | #else |
1154 | ppc4xx_tlb_invalidate_all(env); | |
1155 | #endif | |
0a032cbe JM |
1156 | } |
1157 | ||
93220573 | 1158 | static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx, |
e96efcfc | 1159 | target_ulong address, int rw, int access_type) |
a8dea12f JM |
1160 | { |
1161 | ppcemb_tlb_t *tlb; | |
1162 | target_phys_addr_t raddr; | |
0411a972 | 1163 | int i, ret, zsel, zpr, pr; |
3b46e624 | 1164 | |
c55e9aef | 1165 | ret = -1; |
6f2d8978 | 1166 | raddr = (target_phys_addr_t)-1ULL; |
0411a972 | 1167 | pr = msr_pr; |
a8dea12f JM |
1168 | for (i = 0; i < env->nb_tlb; i++) { |
1169 | tlb = &env->tlb[i].tlbe; | |
36081602 JM |
1170 | if (ppcemb_tlb_check(env, tlb, &raddr, address, |
1171 | env->spr[SPR_40x_PID], 0, i) < 0) | |
a8dea12f | 1172 | continue; |
a8dea12f JM |
1173 | zsel = (tlb->attr >> 4) & 0xF; |
1174 | zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3; | |
d12d51d5 | 1175 | LOG_SWTLB("%s: TLB %d zsel %d zpr %d rw %d attr %08x\n", |
a8dea12f | 1176 | __func__, i, zsel, zpr, rw, tlb->attr); |
b227a8e9 JM |
1177 | /* Check execute enable bit */ |
1178 | switch (zpr) { | |
1179 | case 0x2: | |
0411a972 | 1180 | if (pr != 0) |
b227a8e9 JM |
1181 | goto check_perms; |
1182 | /* No break here */ | |
1183 | case 0x3: | |
1184 | /* All accesses granted */ | |
1185 | ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
1186 | ret = 0; | |
1187 | break; | |
1188 | case 0x0: | |
0411a972 | 1189 | if (pr != 0) { |
b227a8e9 JM |
1190 | ctx->prot = 0; |
1191 | ret = -2; | |
a8dea12f JM |
1192 | break; |
1193 | } | |
b227a8e9 JM |
1194 | /* No break here */ |
1195 | case 0x1: | |
1196 | check_perms: | |
1197 | /* Check from TLB entry */ | |
1198 | /* XXX: there is a problem here or in the TLB fill code... */ | |
1199 | ctx->prot = tlb->prot; | |
1200 | ctx->prot |= PAGE_EXEC; | |
1201 | ret = check_prot(ctx->prot, rw, access_type); | |
1202 | break; | |
a8dea12f JM |
1203 | } |
1204 | if (ret >= 0) { | |
1205 | ctx->raddr = raddr; | |
d12d51d5 | 1206 | LOG_SWTLB("%s: access granted " ADDRX " => " PADDRX |
c55e9aef JM |
1207 | " %d %d\n", __func__, address, ctx->raddr, ctx->prot, |
1208 | ret); | |
c55e9aef | 1209 | return 0; |
a8dea12f JM |
1210 | } |
1211 | } | |
d12d51d5 | 1212 | LOG_SWTLB("%s: access refused " ADDRX " => " PADDRX |
c55e9aef JM |
1213 | " %d %d\n", __func__, address, raddr, ctx->prot, |
1214 | ret); | |
3b46e624 | 1215 | |
a8dea12f JM |
1216 | return ret; |
1217 | } | |
1218 | ||
c294fc58 JM |
1219 | void store_40x_sler (CPUPPCState *env, uint32_t val) |
1220 | { | |
1221 | /* XXX: TO BE FIXED */ | |
1222 | if (val != 0x00000000) { | |
1223 | cpu_abort(env, "Little-endian regions are not supported by now\n"); | |
1224 | } | |
1225 | env->spr[SPR_405_SLER] = val; | |
1226 | } | |
1227 | ||
93220573 AJ |
1228 | static int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx, |
1229 | target_ulong address, int rw, | |
1230 | int access_type) | |
5eb7995e JM |
1231 | { |
1232 | ppcemb_tlb_t *tlb; | |
1233 | target_phys_addr_t raddr; | |
1234 | int i, prot, ret; | |
1235 | ||
1236 | ret = -1; | |
6f2d8978 | 1237 | raddr = (target_phys_addr_t)-1ULL; |
5eb7995e JM |
1238 | for (i = 0; i < env->nb_tlb; i++) { |
1239 | tlb = &env->tlb[i].tlbe; | |
1240 | if (ppcemb_tlb_check(env, tlb, &raddr, address, | |
1241 | env->spr[SPR_BOOKE_PID], 1, i) < 0) | |
1242 | continue; | |
0411a972 | 1243 | if (msr_pr != 0) |
5eb7995e JM |
1244 | prot = tlb->prot & 0xF; |
1245 | else | |
1246 | prot = (tlb->prot >> 4) & 0xF; | |
1247 | /* Check the address space */ | |
1248 | if (access_type == ACCESS_CODE) { | |
d26bfc9a | 1249 | if (msr_ir != (tlb->attr & 1)) |
5eb7995e JM |
1250 | continue; |
1251 | ctx->prot = prot; | |
1252 | if (prot & PAGE_EXEC) { | |
1253 | ret = 0; | |
1254 | break; | |
1255 | } | |
1256 | ret = -3; | |
1257 | } else { | |
d26bfc9a | 1258 | if (msr_dr != (tlb->attr & 1)) |
5eb7995e JM |
1259 | continue; |
1260 | ctx->prot = prot; | |
1261 | if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) { | |
1262 | ret = 0; | |
1263 | break; | |
1264 | } | |
1265 | ret = -2; | |
1266 | } | |
1267 | } | |
1268 | if (ret >= 0) | |
1269 | ctx->raddr = raddr; | |
1270 | ||
1271 | return ret; | |
1272 | } | |
1273 | ||
a11b8151 JM |
1274 | static always_inline int check_physical (CPUState *env, mmu_ctx_t *ctx, |
1275 | target_ulong eaddr, int rw) | |
76a66253 JM |
1276 | { |
1277 | int in_plb, ret; | |
3b46e624 | 1278 | |
76a66253 | 1279 | ctx->raddr = eaddr; |
b227a8e9 | 1280 | ctx->prot = PAGE_READ | PAGE_EXEC; |
76a66253 | 1281 | ret = 0; |
a750fc0b JM |
1282 | switch (env->mmu_model) { |
1283 | case POWERPC_MMU_32B: | |
faadf50e | 1284 | case POWERPC_MMU_601: |
a750fc0b | 1285 | case POWERPC_MMU_SOFT_6xx: |
7dbe11ac | 1286 | case POWERPC_MMU_SOFT_74xx: |
a750fc0b | 1287 | case POWERPC_MMU_SOFT_4xx: |
b4095fed | 1288 | case POWERPC_MMU_REAL: |
7dbe11ac | 1289 | case POWERPC_MMU_BOOKE: |
caa4039c JM |
1290 | ctx->prot |= PAGE_WRITE; |
1291 | break; | |
1292 | #if defined(TARGET_PPC64) | |
add78955 | 1293 | case POWERPC_MMU_620: |
a750fc0b | 1294 | case POWERPC_MMU_64B: |
caa4039c | 1295 | /* Real address are 60 bits long */ |
a750fc0b | 1296 | ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL; |
caa4039c JM |
1297 | ctx->prot |= PAGE_WRITE; |
1298 | break; | |
9706285b | 1299 | #endif |
a750fc0b | 1300 | case POWERPC_MMU_SOFT_4xx_Z: |
caa4039c JM |
1301 | if (unlikely(msr_pe != 0)) { |
1302 | /* 403 family add some particular protections, | |
1303 | * using PBL/PBU registers for accesses with no translation. | |
1304 | */ | |
1305 | in_plb = | |
1306 | /* Check PLB validity */ | |
1307 | (env->pb[0] < env->pb[1] && | |
1308 | /* and address in plb area */ | |
1309 | eaddr >= env->pb[0] && eaddr < env->pb[1]) || | |
1310 | (env->pb[2] < env->pb[3] && | |
1311 | eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0; | |
1312 | if (in_plb ^ msr_px) { | |
1313 | /* Access in protected area */ | |
1314 | if (rw == 1) { | |
1315 | /* Access is not allowed */ | |
1316 | ret = -2; | |
1317 | } | |
1318 | } else { | |
1319 | /* Read-write access is allowed */ | |
1320 | ctx->prot |= PAGE_WRITE; | |
76a66253 | 1321 | } |
76a66253 | 1322 | } |
e1833e1f | 1323 | break; |
b4095fed JM |
1324 | case POWERPC_MMU_MPC8xx: |
1325 | /* XXX: TODO */ | |
1326 | cpu_abort(env, "MPC8xx MMU model is not implemented\n"); | |
1327 | break; | |
a750fc0b | 1328 | case POWERPC_MMU_BOOKE_FSL: |
caa4039c JM |
1329 | /* XXX: TODO */ |
1330 | cpu_abort(env, "BookE FSL MMU model not implemented\n"); | |
1331 | break; | |
1332 | default: | |
1333 | cpu_abort(env, "Unknown or invalid MMU model\n"); | |
1334 | return -1; | |
76a66253 JM |
1335 | } |
1336 | ||
1337 | return ret; | |
1338 | } | |
1339 | ||
1340 | int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr, | |
faadf50e | 1341 | int rw, int access_type) |
9a64fbe4 FB |
1342 | { |
1343 | int ret; | |
0411a972 | 1344 | |
514fb8c1 | 1345 | #if 0 |
93fcfe39 | 1346 | qemu_log("%s\n", __func__); |
d9bce9d9 | 1347 | #endif |
4b3686fa FB |
1348 | if ((access_type == ACCESS_CODE && msr_ir == 0) || |
1349 | (access_type != ACCESS_CODE && msr_dr == 0)) { | |
9a64fbe4 | 1350 | /* No address translation */ |
76a66253 | 1351 | ret = check_physical(env, ctx, eaddr, rw); |
9a64fbe4 | 1352 | } else { |
c55e9aef | 1353 | ret = -1; |
a750fc0b JM |
1354 | switch (env->mmu_model) { |
1355 | case POWERPC_MMU_32B: | |
faadf50e | 1356 | case POWERPC_MMU_601: |
a750fc0b | 1357 | case POWERPC_MMU_SOFT_6xx: |
7dbe11ac | 1358 | case POWERPC_MMU_SOFT_74xx: |
94855937 BS |
1359 | /* Try to find a BAT */ |
1360 | if (env->nb_BATs != 0) | |
1361 | ret = get_bat(env, ctx, eaddr, rw, access_type); | |
c55e9aef | 1362 | #if defined(TARGET_PPC64) |
add78955 | 1363 | case POWERPC_MMU_620: |
a750fc0b | 1364 | case POWERPC_MMU_64B: |
c55e9aef | 1365 | #endif |
a8dea12f | 1366 | if (ret < 0) { |
c55e9aef | 1367 | /* We didn't match any BAT entry or don't have BATs */ |
a8dea12f JM |
1368 | ret = get_segment(env, ctx, eaddr, rw, access_type); |
1369 | } | |
1370 | break; | |
a750fc0b JM |
1371 | case POWERPC_MMU_SOFT_4xx: |
1372 | case POWERPC_MMU_SOFT_4xx_Z: | |
36081602 | 1373 | ret = mmu40x_get_physical_address(env, ctx, eaddr, |
a8dea12f JM |
1374 | rw, access_type); |
1375 | break; | |
a750fc0b | 1376 | case POWERPC_MMU_BOOKE: |
5eb7995e JM |
1377 | ret = mmubooke_get_physical_address(env, ctx, eaddr, |
1378 | rw, access_type); | |
1379 | break; | |
b4095fed JM |
1380 | case POWERPC_MMU_MPC8xx: |
1381 | /* XXX: TODO */ | |
1382 | cpu_abort(env, "MPC8xx MMU model is not implemented\n"); | |
1383 | break; | |
a750fc0b | 1384 | case POWERPC_MMU_BOOKE_FSL: |
c55e9aef JM |
1385 | /* XXX: TODO */ |
1386 | cpu_abort(env, "BookE FSL MMU model not implemented\n"); | |
1387 | return -1; | |
b4095fed JM |
1388 | case POWERPC_MMU_REAL: |
1389 | cpu_abort(env, "PowerPC in real mode do not do any translation\n"); | |
2662a059 | 1390 | return -1; |
c55e9aef JM |
1391 | default: |
1392 | cpu_abort(env, "Unknown or invalid MMU model\n"); | |
a8dea12f | 1393 | return -1; |
9a64fbe4 FB |
1394 | } |
1395 | } | |
514fb8c1 | 1396 | #if 0 |
93fcfe39 | 1397 | qemu_log("%s address " ADDRX " => %d " PADDRX "\n", |
c55e9aef | 1398 | __func__, eaddr, ret, ctx->raddr); |
76a66253 | 1399 | #endif |
d9bce9d9 | 1400 | |
9a64fbe4 FB |
1401 | return ret; |
1402 | } | |
1403 | ||
9b3c35e0 | 1404 | target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
a6b025d3 | 1405 | { |
76a66253 | 1406 | mmu_ctx_t ctx; |
a6b025d3 | 1407 | |
faadf50e | 1408 | if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0)) |
a6b025d3 | 1409 | return -1; |
76a66253 JM |
1410 | |
1411 | return ctx.raddr & TARGET_PAGE_MASK; | |
a6b025d3 | 1412 | } |
9a64fbe4 | 1413 | |
9a64fbe4 | 1414 | /* Perform address translation */ |
e96efcfc | 1415 | int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
6ebbf390 | 1416 | int mmu_idx, int is_softmmu) |
9a64fbe4 | 1417 | { |
76a66253 | 1418 | mmu_ctx_t ctx; |
a541f297 | 1419 | int access_type; |
9a64fbe4 | 1420 | int ret = 0; |
d9bce9d9 | 1421 | |
b769d8fe FB |
1422 | if (rw == 2) { |
1423 | /* code access */ | |
1424 | rw = 0; | |
1425 | access_type = ACCESS_CODE; | |
1426 | } else { | |
1427 | /* data access */ | |
b4cec7b4 | 1428 | access_type = env->access_type; |
b769d8fe | 1429 | } |
faadf50e | 1430 | ret = get_physical_address(env, &ctx, address, rw, access_type); |
9a64fbe4 | 1431 | if (ret == 0) { |
b227a8e9 JM |
1432 | ret = tlb_set_page_exec(env, address & TARGET_PAGE_MASK, |
1433 | ctx.raddr & TARGET_PAGE_MASK, ctx.prot, | |
1434 | mmu_idx, is_softmmu); | |
9a64fbe4 | 1435 | } else if (ret < 0) { |
d12d51d5 | 1436 | LOG_MMU_STATE(env); |
9a64fbe4 | 1437 | if (access_type == ACCESS_CODE) { |
9a64fbe4 FB |
1438 | switch (ret) { |
1439 | case -1: | |
76a66253 | 1440 | /* No matches in page tables or TLB */ |
a750fc0b JM |
1441 | switch (env->mmu_model) { |
1442 | case POWERPC_MMU_SOFT_6xx: | |
8f793433 JM |
1443 | env->exception_index = POWERPC_EXCP_IFTLB; |
1444 | env->error_code = 1 << 18; | |
76a66253 JM |
1445 | env->spr[SPR_IMISS] = address; |
1446 | env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem; | |
76a66253 | 1447 | goto tlb_miss; |
7dbe11ac | 1448 | case POWERPC_MMU_SOFT_74xx: |
8f793433 | 1449 | env->exception_index = POWERPC_EXCP_IFTLB; |
7dbe11ac | 1450 | goto tlb_miss_74xx; |
a750fc0b JM |
1451 | case POWERPC_MMU_SOFT_4xx: |
1452 | case POWERPC_MMU_SOFT_4xx_Z: | |
8f793433 JM |
1453 | env->exception_index = POWERPC_EXCP_ITLB; |
1454 | env->error_code = 0; | |
a8dea12f JM |
1455 | env->spr[SPR_40x_DEAR] = address; |
1456 | env->spr[SPR_40x_ESR] = 0x00000000; | |
c55e9aef | 1457 | break; |
a750fc0b | 1458 | case POWERPC_MMU_32B: |
faadf50e | 1459 | case POWERPC_MMU_601: |
c55e9aef | 1460 | #if defined(TARGET_PPC64) |
add78955 | 1461 | case POWERPC_MMU_620: |
a750fc0b | 1462 | case POWERPC_MMU_64B: |
c55e9aef | 1463 | #endif |
8f793433 JM |
1464 | env->exception_index = POWERPC_EXCP_ISI; |
1465 | env->error_code = 0x40000000; | |
1466 | break; | |
a750fc0b | 1467 | case POWERPC_MMU_BOOKE: |
c55e9aef | 1468 | /* XXX: TODO */ |
b4095fed | 1469 | cpu_abort(env, "BookE MMU model is not implemented\n"); |
c55e9aef | 1470 | return -1; |
a750fc0b | 1471 | case POWERPC_MMU_BOOKE_FSL: |
c55e9aef | 1472 | /* XXX: TODO */ |
b4095fed | 1473 | cpu_abort(env, "BookE FSL MMU model is not implemented\n"); |
c55e9aef | 1474 | return -1; |
b4095fed JM |
1475 | case POWERPC_MMU_MPC8xx: |
1476 | /* XXX: TODO */ | |
1477 | cpu_abort(env, "MPC8xx MMU model is not implemented\n"); | |
1478 | break; | |
1479 | case POWERPC_MMU_REAL: | |
1480 | cpu_abort(env, "PowerPC in real mode should never raise " | |
1481 | "any MMU exceptions\n"); | |
2662a059 | 1482 | return -1; |
c55e9aef JM |
1483 | default: |
1484 | cpu_abort(env, "Unknown or invalid MMU model\n"); | |
1485 | return -1; | |
76a66253 | 1486 | } |
9a64fbe4 FB |
1487 | break; |
1488 | case -2: | |
1489 | /* Access rights violation */ | |
8f793433 JM |
1490 | env->exception_index = POWERPC_EXCP_ISI; |
1491 | env->error_code = 0x08000000; | |
9a64fbe4 FB |
1492 | break; |
1493 | case -3: | |
76a66253 | 1494 | /* No execute protection violation */ |
8f793433 JM |
1495 | env->exception_index = POWERPC_EXCP_ISI; |
1496 | env->error_code = 0x10000000; | |
9a64fbe4 FB |
1497 | break; |
1498 | case -4: | |
1499 | /* Direct store exception */ | |
1500 | /* No code fetch is allowed in direct-store areas */ | |
8f793433 JM |
1501 | env->exception_index = POWERPC_EXCP_ISI; |
1502 | env->error_code = 0x10000000; | |
2be0071f | 1503 | break; |
e1833e1f | 1504 | #if defined(TARGET_PPC64) |
2be0071f FB |
1505 | case -5: |
1506 | /* No match in segment table */ | |
add78955 JM |
1507 | if (env->mmu_model == POWERPC_MMU_620) { |
1508 | env->exception_index = POWERPC_EXCP_ISI; | |
1509 | /* XXX: this might be incorrect */ | |
1510 | env->error_code = 0x40000000; | |
1511 | } else { | |
1512 | env->exception_index = POWERPC_EXCP_ISEG; | |
1513 | env->error_code = 0; | |
1514 | } | |
9a64fbe4 | 1515 | break; |
e1833e1f | 1516 | #endif |
9a64fbe4 FB |
1517 | } |
1518 | } else { | |
9a64fbe4 FB |
1519 | switch (ret) { |
1520 | case -1: | |
76a66253 | 1521 | /* No matches in page tables or TLB */ |
a750fc0b JM |
1522 | switch (env->mmu_model) { |
1523 | case POWERPC_MMU_SOFT_6xx: | |
76a66253 | 1524 | if (rw == 1) { |
8f793433 JM |
1525 | env->exception_index = POWERPC_EXCP_DSTLB; |
1526 | env->error_code = 1 << 16; | |
76a66253 | 1527 | } else { |
8f793433 JM |
1528 | env->exception_index = POWERPC_EXCP_DLTLB; |
1529 | env->error_code = 0; | |
76a66253 JM |
1530 | } |
1531 | env->spr[SPR_DMISS] = address; | |
1532 | env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem; | |
1533 | tlb_miss: | |
8f793433 | 1534 | env->error_code |= ctx.key << 19; |
76a66253 JM |
1535 | env->spr[SPR_HASH1] = ctx.pg_addr[0]; |
1536 | env->spr[SPR_HASH2] = ctx.pg_addr[1]; | |
8f793433 | 1537 | break; |
7dbe11ac JM |
1538 | case POWERPC_MMU_SOFT_74xx: |
1539 | if (rw == 1) { | |
8f793433 | 1540 | env->exception_index = POWERPC_EXCP_DSTLB; |
7dbe11ac | 1541 | } else { |
8f793433 | 1542 | env->exception_index = POWERPC_EXCP_DLTLB; |
7dbe11ac JM |
1543 | } |
1544 | tlb_miss_74xx: | |
1545 | /* Implement LRU algorithm */ | |
8f793433 | 1546 | env->error_code = ctx.key << 19; |
7dbe11ac JM |
1547 | env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) | |
1548 | ((env->last_way + 1) & (env->nb_ways - 1)); | |
1549 | env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem; | |
7dbe11ac | 1550 | break; |
a750fc0b JM |
1551 | case POWERPC_MMU_SOFT_4xx: |
1552 | case POWERPC_MMU_SOFT_4xx_Z: | |
8f793433 JM |
1553 | env->exception_index = POWERPC_EXCP_DTLB; |
1554 | env->error_code = 0; | |
a8dea12f JM |
1555 | env->spr[SPR_40x_DEAR] = address; |
1556 | if (rw) | |
1557 | env->spr[SPR_40x_ESR] = 0x00800000; | |
1558 | else | |
1559 | env->spr[SPR_40x_ESR] = 0x00000000; | |
c55e9aef | 1560 | break; |
a750fc0b | 1561 | case POWERPC_MMU_32B: |
faadf50e | 1562 | case POWERPC_MMU_601: |
c55e9aef | 1563 | #if defined(TARGET_PPC64) |
add78955 | 1564 | case POWERPC_MMU_620: |
a750fc0b | 1565 | case POWERPC_MMU_64B: |
c55e9aef | 1566 | #endif |
8f793433 JM |
1567 | env->exception_index = POWERPC_EXCP_DSI; |
1568 | env->error_code = 0; | |
1569 | env->spr[SPR_DAR] = address; | |
1570 | if (rw == 1) | |
1571 | env->spr[SPR_DSISR] = 0x42000000; | |
1572 | else | |
1573 | env->spr[SPR_DSISR] = 0x40000000; | |
1574 | break; | |
b4095fed JM |
1575 | case POWERPC_MMU_MPC8xx: |
1576 | /* XXX: TODO */ | |
1577 | cpu_abort(env, "MPC8xx MMU model is not implemented\n"); | |
1578 | break; | |
a750fc0b | 1579 | case POWERPC_MMU_BOOKE: |
c55e9aef | 1580 | /* XXX: TODO */ |
b4095fed | 1581 | cpu_abort(env, "BookE MMU model is not implemented\n"); |
c55e9aef | 1582 | return -1; |
a750fc0b | 1583 | case POWERPC_MMU_BOOKE_FSL: |
c55e9aef | 1584 | /* XXX: TODO */ |
b4095fed | 1585 | cpu_abort(env, "BookE FSL MMU model is not implemented\n"); |
c55e9aef | 1586 | return -1; |
b4095fed JM |
1587 | case POWERPC_MMU_REAL: |
1588 | cpu_abort(env, "PowerPC in real mode should never raise " | |
1589 | "any MMU exceptions\n"); | |
2662a059 | 1590 | return -1; |
c55e9aef JM |
1591 | default: |
1592 | cpu_abort(env, "Unknown or invalid MMU model\n"); | |
1593 | return -1; | |
76a66253 | 1594 | } |
9a64fbe4 FB |
1595 | break; |
1596 | case -2: | |
1597 | /* Access rights violation */ | |
8f793433 JM |
1598 | env->exception_index = POWERPC_EXCP_DSI; |
1599 | env->error_code = 0; | |
1600 | env->spr[SPR_DAR] = address; | |
1601 | if (rw == 1) | |
1602 | env->spr[SPR_DSISR] = 0x0A000000; | |
1603 | else | |
1604 | env->spr[SPR_DSISR] = 0x08000000; | |
9a64fbe4 FB |
1605 | break; |
1606 | case -4: | |
1607 | /* Direct store exception */ | |
1608 | switch (access_type) { | |
1609 | case ACCESS_FLOAT: | |
1610 | /* Floating point load/store */ | |
8f793433 JM |
1611 | env->exception_index = POWERPC_EXCP_ALIGN; |
1612 | env->error_code = POWERPC_EXCP_ALIGN_FP; | |
1613 | env->spr[SPR_DAR] = address; | |
9a64fbe4 FB |
1614 | break; |
1615 | case ACCESS_RES: | |
8f793433 JM |
1616 | /* lwarx, ldarx or stwcx. */ |
1617 | env->exception_index = POWERPC_EXCP_DSI; | |
1618 | env->error_code = 0; | |
1619 | env->spr[SPR_DAR] = address; | |
1620 | if (rw == 1) | |
1621 | env->spr[SPR_DSISR] = 0x06000000; | |
1622 | else | |
1623 | env->spr[SPR_DSISR] = 0x04000000; | |
9a64fbe4 FB |
1624 | break; |
1625 | case ACCESS_EXT: | |
1626 | /* eciwx or ecowx */ | |
8f793433 JM |
1627 | env->exception_index = POWERPC_EXCP_DSI; |
1628 | env->error_code = 0; | |
1629 | env->spr[SPR_DAR] = address; | |
1630 | if (rw == 1) | |
1631 | env->spr[SPR_DSISR] = 0x06100000; | |
1632 | else | |
1633 | env->spr[SPR_DSISR] = 0x04100000; | |
9a64fbe4 FB |
1634 | break; |
1635 | default: | |
76a66253 | 1636 | printf("DSI: invalid exception (%d)\n", ret); |
8f793433 JM |
1637 | env->exception_index = POWERPC_EXCP_PROGRAM; |
1638 | env->error_code = | |
1639 | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL; | |
1640 | env->spr[SPR_DAR] = address; | |
9a64fbe4 FB |
1641 | break; |
1642 | } | |
fdabc366 | 1643 | break; |
e1833e1f | 1644 | #if defined(TARGET_PPC64) |
2be0071f FB |
1645 | case -5: |
1646 | /* No match in segment table */ | |
add78955 JM |
1647 | if (env->mmu_model == POWERPC_MMU_620) { |
1648 | env->exception_index = POWERPC_EXCP_DSI; | |
1649 | env->error_code = 0; | |
1650 | env->spr[SPR_DAR] = address; | |
1651 | /* XXX: this might be incorrect */ | |
1652 | if (rw == 1) | |
1653 | env->spr[SPR_DSISR] = 0x42000000; | |
1654 | else | |
1655 | env->spr[SPR_DSISR] = 0x40000000; | |
1656 | } else { | |
1657 | env->exception_index = POWERPC_EXCP_DSEG; | |
1658 | env->error_code = 0; | |
1659 | env->spr[SPR_DAR] = address; | |
1660 | } | |
2be0071f | 1661 | break; |
e1833e1f | 1662 | #endif |
9a64fbe4 | 1663 | } |
9a64fbe4 FB |
1664 | } |
1665 | #if 0 | |
8f793433 JM |
1666 | printf("%s: set exception to %d %02x\n", __func__, |
1667 | env->exception, env->error_code); | |
9a64fbe4 | 1668 | #endif |
9a64fbe4 FB |
1669 | ret = 1; |
1670 | } | |
76a66253 | 1671 | |
9a64fbe4 FB |
1672 | return ret; |
1673 | } | |
1674 | ||
3fc6c082 FB |
1675 | /*****************************************************************************/ |
1676 | /* BATs management */ | |
1677 | #if !defined(FLUSH_ALL_TLBS) | |
b068d6a7 JM |
1678 | static always_inline void do_invalidate_BAT (CPUPPCState *env, |
1679 | target_ulong BATu, | |
1680 | target_ulong mask) | |
3fc6c082 FB |
1681 | { |
1682 | target_ulong base, end, page; | |
76a66253 | 1683 | |
3fc6c082 FB |
1684 | base = BATu & ~0x0001FFFF; |
1685 | end = base + mask + 0x00020000; | |
d12d51d5 | 1686 | LOG_BATS("Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n", |
76a66253 | 1687 | base, end, mask); |
3fc6c082 FB |
1688 | for (page = base; page != end; page += TARGET_PAGE_SIZE) |
1689 | tlb_flush_page(env, page); | |
d12d51d5 | 1690 | LOG_BATS("Flush done\n"); |
3fc6c082 FB |
1691 | } |
1692 | #endif | |
1693 | ||
b068d6a7 JM |
1694 | static always_inline void dump_store_bat (CPUPPCState *env, char ID, |
1695 | int ul, int nr, target_ulong value) | |
3fc6c082 | 1696 | { |
d12d51d5 | 1697 | LOG_BATS("Set %cBAT%d%c to " ADDRX " (" ADDRX ")\n", |
1b9eb036 | 1698 | ID, nr, ul == 0 ? 'u' : 'l', value, env->nip); |
3fc6c082 FB |
1699 | } |
1700 | ||
45d827d2 | 1701 | void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value) |
3fc6c082 FB |
1702 | { |
1703 | target_ulong mask; | |
1704 | ||
1705 | dump_store_bat(env, 'I', 0, nr, value); | |
1706 | if (env->IBAT[0][nr] != value) { | |
1707 | mask = (value << 15) & 0x0FFE0000UL; | |
1708 | #if !defined(FLUSH_ALL_TLBS) | |
1709 | do_invalidate_BAT(env, env->IBAT[0][nr], mask); | |
1710 | #endif | |
1711 | /* When storing valid upper BAT, mask BEPI and BRPN | |
1712 | * and invalidate all TLBs covered by this BAT | |
1713 | */ | |
1714 | mask = (value << 15) & 0x0FFE0000UL; | |
1715 | env->IBAT[0][nr] = (value & 0x00001FFFUL) | | |
1716 | (value & ~0x0001FFFFUL & ~mask); | |
1717 | env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) | | |
1718 | (env->IBAT[1][nr] & ~0x0001FFFF & ~mask); | |
1719 | #if !defined(FLUSH_ALL_TLBS) | |
1720 | do_invalidate_BAT(env, env->IBAT[0][nr], mask); | |
76a66253 | 1721 | #else |
3fc6c082 FB |
1722 | tlb_flush(env, 1); |
1723 | #endif | |
1724 | } | |
1725 | } | |
1726 | ||
45d827d2 | 1727 | void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value) |
3fc6c082 FB |
1728 | { |
1729 | dump_store_bat(env, 'I', 1, nr, value); | |
1730 | env->IBAT[1][nr] = value; | |
1731 | } | |
1732 | ||
45d827d2 | 1733 | void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value) |
3fc6c082 FB |
1734 | { |
1735 | target_ulong mask; | |
1736 | ||
1737 | dump_store_bat(env, 'D', 0, nr, value); | |
1738 | if (env->DBAT[0][nr] != value) { | |
1739 | /* When storing valid upper BAT, mask BEPI and BRPN | |
1740 | * and invalidate all TLBs covered by this BAT | |
1741 | */ | |
1742 | mask = (value << 15) & 0x0FFE0000UL; | |
1743 | #if !defined(FLUSH_ALL_TLBS) | |
1744 | do_invalidate_BAT(env, env->DBAT[0][nr], mask); | |
1745 | #endif | |
1746 | mask = (value << 15) & 0x0FFE0000UL; | |
1747 | env->DBAT[0][nr] = (value & 0x00001FFFUL) | | |
1748 | (value & ~0x0001FFFFUL & ~mask); | |
1749 | env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) | | |
1750 | (env->DBAT[1][nr] & ~0x0001FFFF & ~mask); | |
1751 | #if !defined(FLUSH_ALL_TLBS) | |
1752 | do_invalidate_BAT(env, env->DBAT[0][nr], mask); | |
1753 | #else | |
1754 | tlb_flush(env, 1); | |
1755 | #endif | |
1756 | } | |
1757 | } | |
1758 | ||
45d827d2 | 1759 | void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value) |
3fc6c082 FB |
1760 | { |
1761 | dump_store_bat(env, 'D', 1, nr, value); | |
1762 | env->DBAT[1][nr] = value; | |
1763 | } | |
1764 | ||
45d827d2 | 1765 | void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value) |
056401ea JM |
1766 | { |
1767 | target_ulong mask; | |
1768 | int do_inval; | |
1769 | ||
1770 | dump_store_bat(env, 'I', 0, nr, value); | |
1771 | if (env->IBAT[0][nr] != value) { | |
1772 | do_inval = 0; | |
1773 | mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL; | |
1774 | if (env->IBAT[1][nr] & 0x40) { | |
1775 | /* Invalidate BAT only if it is valid */ | |
1776 | #if !defined(FLUSH_ALL_TLBS) | |
1777 | do_invalidate_BAT(env, env->IBAT[0][nr], mask); | |
1778 | #else | |
1779 | do_inval = 1; | |
1780 | #endif | |
1781 | } | |
1782 | /* When storing valid upper BAT, mask BEPI and BRPN | |
1783 | * and invalidate all TLBs covered by this BAT | |
1784 | */ | |
1785 | env->IBAT[0][nr] = (value & 0x00001FFFUL) | | |
1786 | (value & ~0x0001FFFFUL & ~mask); | |
1787 | env->DBAT[0][nr] = env->IBAT[0][nr]; | |
1788 | if (env->IBAT[1][nr] & 0x40) { | |
1789 | #if !defined(FLUSH_ALL_TLBS) | |
1790 | do_invalidate_BAT(env, env->IBAT[0][nr], mask); | |
1791 | #else | |
1792 | do_inval = 1; | |
1793 | #endif | |
1794 | } | |
1795 | #if defined(FLUSH_ALL_TLBS) | |
1796 | if (do_inval) | |
1797 | tlb_flush(env, 1); | |
1798 | #endif | |
1799 | } | |
1800 | } | |
1801 | ||
45d827d2 | 1802 | void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value) |
056401ea JM |
1803 | { |
1804 | target_ulong mask; | |
1805 | int do_inval; | |
1806 | ||
1807 | dump_store_bat(env, 'I', 1, nr, value); | |
1808 | if (env->IBAT[1][nr] != value) { | |
1809 | do_inval = 0; | |
1810 | if (env->IBAT[1][nr] & 0x40) { | |
1811 | #if !defined(FLUSH_ALL_TLBS) | |
1812 | mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL; | |
1813 | do_invalidate_BAT(env, env->IBAT[0][nr], mask); | |
1814 | #else | |
1815 | do_inval = 1; | |
1816 | #endif | |
1817 | } | |
1818 | if (value & 0x40) { | |
1819 | #if !defined(FLUSH_ALL_TLBS) | |
1820 | mask = (value << 17) & 0x0FFE0000UL; | |
1821 | do_invalidate_BAT(env, env->IBAT[0][nr], mask); | |
1822 | #else | |
1823 | do_inval = 1; | |
1824 | #endif | |
1825 | } | |
1826 | env->IBAT[1][nr] = value; | |
1827 | env->DBAT[1][nr] = value; | |
1828 | #if defined(FLUSH_ALL_TLBS) | |
1829 | if (do_inval) | |
1830 | tlb_flush(env, 1); | |
1831 | #endif | |
1832 | } | |
1833 | } | |
1834 | ||
0a032cbe JM |
1835 | /*****************************************************************************/ |
1836 | /* TLB management */ | |
1837 | void ppc_tlb_invalidate_all (CPUPPCState *env) | |
1838 | { | |
daf4f96e JM |
1839 | switch (env->mmu_model) { |
1840 | case POWERPC_MMU_SOFT_6xx: | |
7dbe11ac | 1841 | case POWERPC_MMU_SOFT_74xx: |
0a032cbe | 1842 | ppc6xx_tlb_invalidate_all(env); |
daf4f96e JM |
1843 | break; |
1844 | case POWERPC_MMU_SOFT_4xx: | |
1845 | case POWERPC_MMU_SOFT_4xx_Z: | |
0a032cbe | 1846 | ppc4xx_tlb_invalidate_all(env); |
daf4f96e | 1847 | break; |
b4095fed | 1848 | case POWERPC_MMU_REAL: |
7dbe11ac JM |
1849 | cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n"); |
1850 | break; | |
b4095fed JM |
1851 | case POWERPC_MMU_MPC8xx: |
1852 | /* XXX: TODO */ | |
1853 | cpu_abort(env, "MPC8xx MMU model is not implemented\n"); | |
1854 | break; | |
7dbe11ac JM |
1855 | case POWERPC_MMU_BOOKE: |
1856 | /* XXX: TODO */ | |
b4095fed | 1857 | cpu_abort(env, "BookE MMU model is not implemented\n"); |
7dbe11ac JM |
1858 | break; |
1859 | case POWERPC_MMU_BOOKE_FSL: | |
1860 | /* XXX: TODO */ | |
da07cf59 AL |
1861 | if (!kvm_enabled()) |
1862 | cpu_abort(env, "BookE MMU model is not implemented\n"); | |
7dbe11ac | 1863 | break; |
7dbe11ac | 1864 | case POWERPC_MMU_32B: |
faadf50e | 1865 | case POWERPC_MMU_601: |
00af685f | 1866 | #if defined(TARGET_PPC64) |
add78955 | 1867 | case POWERPC_MMU_620: |
7dbe11ac | 1868 | case POWERPC_MMU_64B: |
00af685f | 1869 | #endif /* defined(TARGET_PPC64) */ |
0a032cbe | 1870 | tlb_flush(env, 1); |
daf4f96e | 1871 | break; |
00af685f JM |
1872 | default: |
1873 | /* XXX: TODO */ | |
12de9a39 | 1874 | cpu_abort(env, "Unknown MMU model\n"); |
00af685f | 1875 | break; |
0a032cbe JM |
1876 | } |
1877 | } | |
1878 | ||
daf4f96e JM |
1879 | void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr) |
1880 | { | |
1881 | #if !defined(FLUSH_ALL_TLBS) | |
1882 | addr &= TARGET_PAGE_MASK; | |
1883 | switch (env->mmu_model) { | |
1884 | case POWERPC_MMU_SOFT_6xx: | |
7dbe11ac | 1885 | case POWERPC_MMU_SOFT_74xx: |
daf4f96e JM |
1886 | ppc6xx_tlb_invalidate_virt(env, addr, 0); |
1887 | if (env->id_tlbs == 1) | |
1888 | ppc6xx_tlb_invalidate_virt(env, addr, 1); | |
1889 | break; | |
1890 | case POWERPC_MMU_SOFT_4xx: | |
1891 | case POWERPC_MMU_SOFT_4xx_Z: | |
1892 | ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]); | |
1893 | break; | |
b4095fed | 1894 | case POWERPC_MMU_REAL: |
7dbe11ac JM |
1895 | cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n"); |
1896 | break; | |
b4095fed JM |
1897 | case POWERPC_MMU_MPC8xx: |
1898 | /* XXX: TODO */ | |
1899 | cpu_abort(env, "MPC8xx MMU model is not implemented\n"); | |
1900 | break; | |
7dbe11ac JM |
1901 | case POWERPC_MMU_BOOKE: |
1902 | /* XXX: TODO */ | |
b4095fed | 1903 | cpu_abort(env, "BookE MMU model is not implemented\n"); |
7dbe11ac JM |
1904 | break; |
1905 | case POWERPC_MMU_BOOKE_FSL: | |
1906 | /* XXX: TODO */ | |
b4095fed | 1907 | cpu_abort(env, "BookE FSL MMU model is not implemented\n"); |
7dbe11ac JM |
1908 | break; |
1909 | case POWERPC_MMU_32B: | |
faadf50e | 1910 | case POWERPC_MMU_601: |
daf4f96e | 1911 | /* tlbie invalidate TLBs for all segments */ |
6f2d8978 | 1912 | addr &= ~((target_ulong)-1ULL << 28); |
daf4f96e JM |
1913 | /* XXX: this case should be optimized, |
1914 | * giving a mask to tlb_flush_page | |
1915 | */ | |
1916 | tlb_flush_page(env, addr | (0x0 << 28)); | |
1917 | tlb_flush_page(env, addr | (0x1 << 28)); | |
1918 | tlb_flush_page(env, addr | (0x2 << 28)); | |
1919 | tlb_flush_page(env, addr | (0x3 << 28)); | |
1920 | tlb_flush_page(env, addr | (0x4 << 28)); | |
1921 | tlb_flush_page(env, addr | (0x5 << 28)); | |
1922 | tlb_flush_page(env, addr | (0x6 << 28)); | |
1923 | tlb_flush_page(env, addr | (0x7 << 28)); | |
1924 | tlb_flush_page(env, addr | (0x8 << 28)); | |
1925 | tlb_flush_page(env, addr | (0x9 << 28)); | |
1926 | tlb_flush_page(env, addr | (0xA << 28)); | |
1927 | tlb_flush_page(env, addr | (0xB << 28)); | |
1928 | tlb_flush_page(env, addr | (0xC << 28)); | |
1929 | tlb_flush_page(env, addr | (0xD << 28)); | |
1930 | tlb_flush_page(env, addr | (0xE << 28)); | |
1931 | tlb_flush_page(env, addr | (0xF << 28)); | |
7dbe11ac | 1932 | break; |
00af685f | 1933 | #if defined(TARGET_PPC64) |
add78955 | 1934 | case POWERPC_MMU_620: |
7dbe11ac | 1935 | case POWERPC_MMU_64B: |
7dbe11ac JM |
1936 | /* tlbie invalidate TLBs for all segments */ |
1937 | /* XXX: given the fact that there are too many segments to invalidate, | |
00af685f | 1938 | * and we still don't have a tlb_flush_mask(env, n, mask) in Qemu, |
7dbe11ac JM |
1939 | * we just invalidate all TLBs |
1940 | */ | |
1941 | tlb_flush(env, 1); | |
1942 | break; | |
00af685f JM |
1943 | #endif /* defined(TARGET_PPC64) */ |
1944 | default: | |
1945 | /* XXX: TODO */ | |
12de9a39 | 1946 | cpu_abort(env, "Unknown MMU model\n"); |
00af685f | 1947 | break; |
daf4f96e JM |
1948 | } |
1949 | #else | |
1950 | ppc_tlb_invalidate_all(env); | |
1951 | #endif | |
1952 | } | |
1953 | ||
3fc6c082 FB |
1954 | /*****************************************************************************/ |
1955 | /* Special registers manipulation */ | |
d9bce9d9 | 1956 | #if defined(TARGET_PPC64) |
d9bce9d9 JM |
1957 | void ppc_store_asr (CPUPPCState *env, target_ulong value) |
1958 | { | |
1959 | if (env->asr != value) { | |
1960 | env->asr = value; | |
1961 | tlb_flush(env, 1); | |
1962 | } | |
1963 | } | |
1964 | #endif | |
1965 | ||
45d827d2 | 1966 | void ppc_store_sdr1 (CPUPPCState *env, target_ulong value) |
3fc6c082 | 1967 | { |
d12d51d5 | 1968 | LOG_MMU("%s: " ADDRX "\n", __func__, value); |
3fc6c082 | 1969 | if (env->sdr1 != value) { |
12de9a39 JM |
1970 | /* XXX: for PowerPC 64, should check that the HTABSIZE value |
1971 | * is <= 28 | |
1972 | */ | |
3fc6c082 | 1973 | env->sdr1 = value; |
76a66253 | 1974 | tlb_flush(env, 1); |
3fc6c082 FB |
1975 | } |
1976 | } | |
1977 | ||
f6b868fc BS |
1978 | #if defined(TARGET_PPC64) |
1979 | target_ulong ppc_load_sr (CPUPPCState *env, int slb_nr) | |
1980 | { | |
1981 | // XXX | |
1982 | return 0; | |
1983 | } | |
1984 | #endif | |
1985 | ||
45d827d2 | 1986 | void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value) |
3fc6c082 | 1987 | { |
d12d51d5 | 1988 | LOG_MMU("%s: reg=%d " ADDRX " " ADDRX "\n", |
1b9eb036 | 1989 | __func__, srnum, value, env->sr[srnum]); |
f6b868fc BS |
1990 | #if defined(TARGET_PPC64) |
1991 | if (env->mmu_model & POWERPC_MMU_64) { | |
1992 | uint64_t rb = 0, rs = 0; | |
1993 | ||
1994 | /* ESID = srnum */ | |
1995 | rb |= ((uint32_t)srnum & 0xf) << 28; | |
1996 | /* Set the valid bit */ | |
1997 | rb |= 1 << 27; | |
1998 | /* Index = ESID */ | |
1999 | rb |= (uint32_t)srnum; | |
2000 | ||
2001 | /* VSID = VSID */ | |
2002 | rs |= (value & 0xfffffff) << 12; | |
2003 | /* flags = flags */ | |
2004 | rs |= ((value >> 27) & 0xf) << 9; | |
2005 | ||
2006 | ppc_store_slb(env, rb, rs); | |
2007 | } else | |
2008 | #endif | |
3fc6c082 FB |
2009 | if (env->sr[srnum] != value) { |
2010 | env->sr[srnum] = value; | |
bf1752ef AJ |
2011 | /* Invalidating 256MB of virtual memory in 4kB pages is way longer than |
2012 | flusing the whole TLB. */ | |
3fc6c082 FB |
2013 | #if !defined(FLUSH_ALL_TLBS) && 0 |
2014 | { | |
2015 | target_ulong page, end; | |
2016 | /* Invalidate 256 MB of virtual memory */ | |
2017 | page = (16 << 20) * srnum; | |
2018 | end = page + (16 << 20); | |
2019 | for (; page != end; page += TARGET_PAGE_SIZE) | |
2020 | tlb_flush_page(env, page); | |
2021 | } | |
2022 | #else | |
76a66253 | 2023 | tlb_flush(env, 1); |
3fc6c082 FB |
2024 | #endif |
2025 | } | |
2026 | } | |
76a66253 | 2027 | #endif /* !defined (CONFIG_USER_ONLY) */ |
3fc6c082 | 2028 | |
76a66253 | 2029 | /* GDBstub can read and write MSR... */ |
0411a972 | 2030 | void ppc_store_msr (CPUPPCState *env, target_ulong value) |
3fc6c082 | 2031 | { |
a4f30719 | 2032 | hreg_store_msr(env, value, 0); |
3fc6c082 FB |
2033 | } |
2034 | ||
2035 | /*****************************************************************************/ | |
2036 | /* Exception processing */ | |
18fba28c | 2037 | #if defined (CONFIG_USER_ONLY) |
9a64fbe4 | 2038 | void do_interrupt (CPUState *env) |
79aceca5 | 2039 | { |
e1833e1f JM |
2040 | env->exception_index = POWERPC_EXCP_NONE; |
2041 | env->error_code = 0; | |
18fba28c | 2042 | } |
47103572 | 2043 | |
e9df014c | 2044 | void ppc_hw_interrupt (CPUState *env) |
47103572 | 2045 | { |
e1833e1f JM |
2046 | env->exception_index = POWERPC_EXCP_NONE; |
2047 | env->error_code = 0; | |
47103572 | 2048 | } |
76a66253 | 2049 | #else /* defined (CONFIG_USER_ONLY) */ |
a11b8151 | 2050 | static always_inline void dump_syscall (CPUState *env) |
d094807b | 2051 | { |
93fcfe39 | 2052 | qemu_log_mask(CPU_LOG_INT, "syscall r0=" REGX " r3=" REGX " r4=" REGX |
6b542af7 JM |
2053 | " r5=" REGX " r6=" REGX " nip=" ADDRX "\n", |
2054 | ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3), ppc_dump_gpr(env, 4), | |
2055 | ppc_dump_gpr(env, 5), ppc_dump_gpr(env, 6), env->nip); | |
d094807b FB |
2056 | } |
2057 | ||
e1833e1f JM |
2058 | /* Note that this function should be greatly optimized |
2059 | * when called with a constant excp, from ppc_hw_interrupt | |
2060 | */ | |
2061 | static always_inline void powerpc_excp (CPUState *env, | |
2062 | int excp_model, int excp) | |
18fba28c | 2063 | { |
0411a972 | 2064 | target_ulong msr, new_msr, vector; |
e1833e1f | 2065 | int srr0, srr1, asrr0, asrr1; |
a4f30719 | 2066 | int lpes0, lpes1, lev; |
79aceca5 | 2067 | |
b172c56a JM |
2068 | if (0) { |
2069 | /* XXX: find a suitable condition to enable the hypervisor mode */ | |
2070 | lpes0 = (env->spr[SPR_LPCR] >> 1) & 1; | |
2071 | lpes1 = (env->spr[SPR_LPCR] >> 2) & 1; | |
2072 | } else { | |
2073 | /* Those values ensure we won't enter the hypervisor mode */ | |
2074 | lpes0 = 0; | |
2075 | lpes1 = 1; | |
2076 | } | |
2077 | ||
93fcfe39 AL |
2078 | qemu_log_mask(CPU_LOG_INT, "Raise exception at " ADDRX " => %08x (%02x)\n", |
2079 | env->nip, excp, env->error_code); | |
0411a972 JM |
2080 | msr = env->msr; |
2081 | new_msr = msr; | |
e1833e1f JM |
2082 | srr0 = SPR_SRR0; |
2083 | srr1 = SPR_SRR1; | |
2084 | asrr0 = -1; | |
2085 | asrr1 = -1; | |
2086 | msr &= ~((target_ulong)0x783F0000); | |
9a64fbe4 | 2087 | switch (excp) { |
e1833e1f JM |
2088 | case POWERPC_EXCP_NONE: |
2089 | /* Should never happen */ | |
2090 | return; | |
2091 | case POWERPC_EXCP_CRITICAL: /* Critical input */ | |
0411a972 | 2092 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
e1833e1f | 2093 | switch (excp_model) { |
a750fc0b | 2094 | case POWERPC_EXCP_40x: |
e1833e1f JM |
2095 | srr0 = SPR_40x_SRR2; |
2096 | srr1 = SPR_40x_SRR3; | |
c62db105 | 2097 | break; |
a750fc0b | 2098 | case POWERPC_EXCP_BOOKE: |
e1833e1f JM |
2099 | srr0 = SPR_BOOKE_CSRR0; |
2100 | srr1 = SPR_BOOKE_CSRR1; | |
c62db105 | 2101 | break; |
e1833e1f | 2102 | case POWERPC_EXCP_G2: |
c62db105 | 2103 | break; |
e1833e1f JM |
2104 | default: |
2105 | goto excp_invalid; | |
2be0071f | 2106 | } |
9a64fbe4 | 2107 | goto store_next; |
e1833e1f JM |
2108 | case POWERPC_EXCP_MCHECK: /* Machine check exception */ |
2109 | if (msr_me == 0) { | |
e63ecc6f JM |
2110 | /* Machine check exception is not enabled. |
2111 | * Enter checkstop state. | |
2112 | */ | |
93fcfe39 AL |
2113 | if (qemu_log_enabled()) { |
2114 | qemu_log("Machine check while not allowed. " | |
e63ecc6f JM |
2115 | "Entering checkstop state\n"); |
2116 | } else { | |
2117 | fprintf(stderr, "Machine check while not allowed. " | |
2118 | "Entering checkstop state\n"); | |
2119 | } | |
2120 | env->halted = 1; | |
2121 | env->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
e1833e1f | 2122 | } |
0411a972 JM |
2123 | new_msr &= ~((target_ulong)1 << MSR_RI); |
2124 | new_msr &= ~((target_ulong)1 << MSR_ME); | |
b172c56a JM |
2125 | if (0) { |
2126 | /* XXX: find a suitable condition to enable the hypervisor mode */ | |
a4f30719 | 2127 | new_msr |= (target_ulong)MSR_HVB; |
b172c56a | 2128 | } |
e1833e1f JM |
2129 | /* XXX: should also have something loaded in DAR / DSISR */ |
2130 | switch (excp_model) { | |
a750fc0b | 2131 | case POWERPC_EXCP_40x: |
e1833e1f JM |
2132 | srr0 = SPR_40x_SRR2; |
2133 | srr1 = SPR_40x_SRR3; | |
c62db105 | 2134 | break; |
a750fc0b | 2135 | case POWERPC_EXCP_BOOKE: |
e1833e1f JM |
2136 | srr0 = SPR_BOOKE_MCSRR0; |
2137 | srr1 = SPR_BOOKE_MCSRR1; | |
2138 | asrr0 = SPR_BOOKE_CSRR0; | |
2139 | asrr1 = SPR_BOOKE_CSRR1; | |
c62db105 JM |
2140 | break; |
2141 | default: | |
2142 | break; | |
2be0071f | 2143 | } |
e1833e1f JM |
2144 | goto store_next; |
2145 | case POWERPC_EXCP_DSI: /* Data storage exception */ | |
d12d51d5 | 2146 | LOG_EXCP("DSI exception: DSISR=" ADDRX" DAR=" ADDRX "\n", |
6b542af7 | 2147 | env->spr[SPR_DSISR], env->spr[SPR_DAR]); |
0411a972 | 2148 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2149 | if (lpes1 == 0) |
a4f30719 | 2150 | new_msr |= (target_ulong)MSR_HVB; |
a541f297 | 2151 | goto store_next; |
e1833e1f | 2152 | case POWERPC_EXCP_ISI: /* Instruction storage exception */ |
d12d51d5 | 2153 | LOG_EXCP("ISI exception: msr=" ADDRX ", nip=" ADDRX "\n", |
6b542af7 | 2154 | msr, env->nip); |
0411a972 | 2155 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2156 | if (lpes1 == 0) |
a4f30719 | 2157 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f | 2158 | msr |= env->error_code; |
9a64fbe4 | 2159 | goto store_next; |
e1833e1f | 2160 | case POWERPC_EXCP_EXTERNAL: /* External input */ |
0411a972 | 2161 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2162 | if (lpes0 == 1) |
a4f30719 | 2163 | new_msr |= (target_ulong)MSR_HVB; |
9a64fbe4 | 2164 | goto store_next; |
e1833e1f | 2165 | case POWERPC_EXCP_ALIGN: /* Alignment exception */ |
0411a972 | 2166 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2167 | if (lpes1 == 0) |
a4f30719 | 2168 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f JM |
2169 | /* XXX: this is false */ |
2170 | /* Get rS/rD and rA from faulting opcode */ | |
2171 | env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16; | |
9a64fbe4 | 2172 | goto store_current; |
e1833e1f | 2173 | case POWERPC_EXCP_PROGRAM: /* Program exception */ |
9a64fbe4 | 2174 | switch (env->error_code & ~0xF) { |
e1833e1f JM |
2175 | case POWERPC_EXCP_FP: |
2176 | if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { | |
d12d51d5 | 2177 | LOG_EXCP("Ignore floating point exception\n"); |
7c58044c JM |
2178 | env->exception_index = POWERPC_EXCP_NONE; |
2179 | env->error_code = 0; | |
9a64fbe4 | 2180 | return; |
76a66253 | 2181 | } |
0411a972 | 2182 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2183 | if (lpes1 == 0) |
a4f30719 | 2184 | new_msr |= (target_ulong)MSR_HVB; |
9a64fbe4 | 2185 | msr |= 0x00100000; |
5b52b991 JM |
2186 | if (msr_fe0 == msr_fe1) |
2187 | goto store_next; | |
2188 | msr |= 0x00010000; | |
76a66253 | 2189 | break; |
e1833e1f | 2190 | case POWERPC_EXCP_INVAL: |
d12d51d5 | 2191 | LOG_EXCP("Invalid instruction at " ADDRX "\n", |
a496775f | 2192 | env->nip); |
0411a972 | 2193 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2194 | if (lpes1 == 0) |
a4f30719 | 2195 | new_msr |= (target_ulong)MSR_HVB; |
9a64fbe4 | 2196 | msr |= 0x00080000; |
76a66253 | 2197 | break; |
e1833e1f | 2198 | case POWERPC_EXCP_PRIV: |
0411a972 | 2199 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2200 | if (lpes1 == 0) |
a4f30719 | 2201 | new_msr |= (target_ulong)MSR_HVB; |
9a64fbe4 | 2202 | msr |= 0x00040000; |
76a66253 | 2203 | break; |
e1833e1f | 2204 | case POWERPC_EXCP_TRAP: |
0411a972 | 2205 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2206 | if (lpes1 == 0) |
a4f30719 | 2207 | new_msr |= (target_ulong)MSR_HVB; |
9a64fbe4 FB |
2208 | msr |= 0x00020000; |
2209 | break; | |
2210 | default: | |
2211 | /* Should never occur */ | |
e1833e1f JM |
2212 | cpu_abort(env, "Invalid program exception %d. Aborting\n", |
2213 | env->error_code); | |
76a66253 JM |
2214 | break; |
2215 | } | |
5b52b991 | 2216 | goto store_current; |
e1833e1f | 2217 | case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ |
0411a972 | 2218 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2219 | if (lpes1 == 0) |
a4f30719 | 2220 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f JM |
2221 | goto store_current; |
2222 | case POWERPC_EXCP_SYSCALL: /* System call exception */ | |
d094807b FB |
2223 | /* NOTE: this is a temporary hack to support graphics OSI |
2224 | calls from the MOL driver */ | |
e1833e1f | 2225 | /* XXX: To be removed */ |
d094807b FB |
2226 | if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b && |
2227 | env->osi_call) { | |
7c58044c JM |
2228 | if (env->osi_call(env) != 0) { |
2229 | env->exception_index = POWERPC_EXCP_NONE; | |
2230 | env->error_code = 0; | |
d094807b | 2231 | return; |
7c58044c | 2232 | } |
d094807b | 2233 | } |
93fcfe39 | 2234 | dump_syscall(env); |
0411a972 | 2235 | new_msr &= ~((target_ulong)1 << MSR_RI); |
f9fdea6b | 2236 | lev = env->error_code; |
e1833e1f | 2237 | if (lev == 1 || (lpes0 == 0 && lpes1 == 0)) |
a4f30719 | 2238 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f JM |
2239 | goto store_next; |
2240 | case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ | |
0411a972 | 2241 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f JM |
2242 | goto store_current; |
2243 | case POWERPC_EXCP_DECR: /* Decrementer exception */ | |
0411a972 | 2244 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2245 | if (lpes1 == 0) |
a4f30719 | 2246 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f JM |
2247 | goto store_next; |
2248 | case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ | |
2249 | /* FIT on 4xx */ | |
d12d51d5 | 2250 | LOG_EXCP("FIT exception\n"); |
0411a972 | 2251 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
9a64fbe4 | 2252 | goto store_next; |
e1833e1f | 2253 | case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ |
d12d51d5 | 2254 | LOG_EXCP("WDT exception\n"); |
e1833e1f JM |
2255 | switch (excp_model) { |
2256 | case POWERPC_EXCP_BOOKE: | |
2257 | srr0 = SPR_BOOKE_CSRR0; | |
2258 | srr1 = SPR_BOOKE_CSRR1; | |
2259 | break; | |
2260 | default: | |
2261 | break; | |
2262 | } | |
0411a972 | 2263 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2be0071f | 2264 | goto store_next; |
e1833e1f | 2265 | case POWERPC_EXCP_DTLB: /* Data TLB error */ |
0411a972 | 2266 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
e1833e1f JM |
2267 | goto store_next; |
2268 | case POWERPC_EXCP_ITLB: /* Instruction TLB error */ | |
0411a972 | 2269 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
e1833e1f JM |
2270 | goto store_next; |
2271 | case POWERPC_EXCP_DEBUG: /* Debug interrupt */ | |
2272 | switch (excp_model) { | |
2273 | case POWERPC_EXCP_BOOKE: | |
2274 | srr0 = SPR_BOOKE_DSRR0; | |
2275 | srr1 = SPR_BOOKE_DSRR1; | |
2276 | asrr0 = SPR_BOOKE_CSRR0; | |
2277 | asrr1 = SPR_BOOKE_CSRR1; | |
2278 | break; | |
2279 | default: | |
2280 | break; | |
2281 | } | |
2be0071f | 2282 | /* XXX: TODO */ |
e1833e1f | 2283 | cpu_abort(env, "Debug exception is not implemented yet !\n"); |
2be0071f | 2284 | goto store_next; |
e1833e1f | 2285 | case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */ |
0411a972 | 2286 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
e1833e1f JM |
2287 | goto store_current; |
2288 | case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ | |
2be0071f | 2289 | /* XXX: TODO */ |
e1833e1f | 2290 | cpu_abort(env, "Embedded floating point data exception " |
2be0071f FB |
2291 | "is not implemented yet !\n"); |
2292 | goto store_next; | |
e1833e1f | 2293 | case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ |
2be0071f | 2294 | /* XXX: TODO */ |
e1833e1f JM |
2295 | cpu_abort(env, "Embedded floating point round exception " |
2296 | "is not implemented yet !\n"); | |
9a64fbe4 | 2297 | goto store_next; |
e1833e1f | 2298 | case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */ |
0411a972 | 2299 | new_msr &= ~((target_ulong)1 << MSR_RI); |
2be0071f FB |
2300 | /* XXX: TODO */ |
2301 | cpu_abort(env, | |
e1833e1f | 2302 | "Performance counter exception is not implemented yet !\n"); |
9a64fbe4 | 2303 | goto store_next; |
e1833e1f | 2304 | case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ |
76a66253 | 2305 | /* XXX: TODO */ |
e1833e1f JM |
2306 | cpu_abort(env, |
2307 | "Embedded doorbell interrupt is not implemented yet !\n"); | |
2be0071f | 2308 | goto store_next; |
e1833e1f JM |
2309 | case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ |
2310 | switch (excp_model) { | |
2311 | case POWERPC_EXCP_BOOKE: | |
2312 | srr0 = SPR_BOOKE_CSRR0; | |
2313 | srr1 = SPR_BOOKE_CSRR1; | |
a750fc0b | 2314 | break; |
2be0071f | 2315 | default: |
2be0071f FB |
2316 | break; |
2317 | } | |
e1833e1f JM |
2318 | /* XXX: TODO */ |
2319 | cpu_abort(env, "Embedded doorbell critical interrupt " | |
2320 | "is not implemented yet !\n"); | |
2321 | goto store_next; | |
e1833e1f | 2322 | case POWERPC_EXCP_RESET: /* System reset exception */ |
0411a972 | 2323 | new_msr &= ~((target_ulong)1 << MSR_RI); |
a4f30719 JM |
2324 | if (0) { |
2325 | /* XXX: find a suitable condition to enable the hypervisor mode */ | |
2326 | new_msr |= (target_ulong)MSR_HVB; | |
2327 | } | |
e1833e1f | 2328 | goto store_next; |
e1833e1f | 2329 | case POWERPC_EXCP_DSEG: /* Data segment exception */ |
0411a972 | 2330 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2331 | if (lpes1 == 0) |
a4f30719 | 2332 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f JM |
2333 | goto store_next; |
2334 | case POWERPC_EXCP_ISEG: /* Instruction segment exception */ | |
0411a972 | 2335 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2336 | if (lpes1 == 0) |
a4f30719 | 2337 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f | 2338 | goto store_next; |
e1833e1f JM |
2339 | case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ |
2340 | srr0 = SPR_HSRR0; | |
f9fdea6b | 2341 | srr1 = SPR_HSRR1; |
a4f30719 | 2342 | new_msr |= (target_ulong)MSR_HVB; |
b172c56a | 2343 | goto store_next; |
e1833e1f | 2344 | case POWERPC_EXCP_TRACE: /* Trace exception */ |
0411a972 | 2345 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2346 | if (lpes1 == 0) |
a4f30719 | 2347 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f | 2348 | goto store_next; |
e1833e1f JM |
2349 | case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ |
2350 | srr0 = SPR_HSRR0; | |
f9fdea6b | 2351 | srr1 = SPR_HSRR1; |
a4f30719 | 2352 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f JM |
2353 | goto store_next; |
2354 | case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */ | |
2355 | srr0 = SPR_HSRR0; | |
f9fdea6b | 2356 | srr1 = SPR_HSRR1; |
a4f30719 | 2357 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f JM |
2358 | goto store_next; |
2359 | case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ | |
2360 | srr0 = SPR_HSRR0; | |
f9fdea6b | 2361 | srr1 = SPR_HSRR1; |
a4f30719 | 2362 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f JM |
2363 | goto store_next; |
2364 | case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */ | |
2365 | srr0 = SPR_HSRR0; | |
f9fdea6b | 2366 | srr1 = SPR_HSRR1; |
a4f30719 | 2367 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f | 2368 | goto store_next; |
e1833e1f | 2369 | case POWERPC_EXCP_VPU: /* Vector unavailable exception */ |
0411a972 | 2370 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2371 | if (lpes1 == 0) |
a4f30719 | 2372 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f JM |
2373 | goto store_current; |
2374 | case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ | |
d12d51d5 | 2375 | LOG_EXCP("PIT exception\n"); |
0411a972 | 2376 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
e1833e1f JM |
2377 | goto store_next; |
2378 | case POWERPC_EXCP_IO: /* IO error exception */ | |
2379 | /* XXX: TODO */ | |
2380 | cpu_abort(env, "601 IO error exception is not implemented yet !\n"); | |
2381 | goto store_next; | |
2382 | case POWERPC_EXCP_RUNM: /* Run mode exception */ | |
2383 | /* XXX: TODO */ | |
2384 | cpu_abort(env, "601 run mode exception is not implemented yet !\n"); | |
2385 | goto store_next; | |
2386 | case POWERPC_EXCP_EMUL: /* Emulation trap exception */ | |
2387 | /* XXX: TODO */ | |
2388 | cpu_abort(env, "602 emulation trap exception " | |
2389 | "is not implemented yet !\n"); | |
2390 | goto store_next; | |
2391 | case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ | |
0411a972 | 2392 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
a4f30719 JM |
2393 | if (lpes1 == 0) /* XXX: check this */ |
2394 | new_msr |= (target_ulong)MSR_HVB; | |
e1833e1f | 2395 | switch (excp_model) { |
a750fc0b JM |
2396 | case POWERPC_EXCP_602: |
2397 | case POWERPC_EXCP_603: | |
2398 | case POWERPC_EXCP_603E: | |
2399 | case POWERPC_EXCP_G2: | |
e1833e1f | 2400 | goto tlb_miss_tgpr; |
a750fc0b | 2401 | case POWERPC_EXCP_7x5: |
76a66253 | 2402 | goto tlb_miss; |
7dbe11ac JM |
2403 | case POWERPC_EXCP_74xx: |
2404 | goto tlb_miss_74xx; | |
2be0071f | 2405 | default: |
e1833e1f | 2406 | cpu_abort(env, "Invalid instruction TLB miss exception\n"); |
2be0071f FB |
2407 | break; |
2408 | } | |
e1833e1f JM |
2409 | break; |
2410 | case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ | |
0411a972 | 2411 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
a4f30719 JM |
2412 | if (lpes1 == 0) /* XXX: check this */ |
2413 | new_msr |= (target_ulong)MSR_HVB; | |
e1833e1f | 2414 | switch (excp_model) { |
a750fc0b JM |
2415 | case POWERPC_EXCP_602: |
2416 | case POWERPC_EXCP_603: | |
2417 | case POWERPC_EXCP_603E: | |
2418 | case POWERPC_EXCP_G2: | |
e1833e1f | 2419 | goto tlb_miss_tgpr; |
a750fc0b | 2420 | case POWERPC_EXCP_7x5: |
76a66253 | 2421 | goto tlb_miss; |
7dbe11ac JM |
2422 | case POWERPC_EXCP_74xx: |
2423 | goto tlb_miss_74xx; | |
2be0071f | 2424 | default: |
e1833e1f | 2425 | cpu_abort(env, "Invalid data load TLB miss exception\n"); |
2be0071f FB |
2426 | break; |
2427 | } | |
e1833e1f JM |
2428 | break; |
2429 | case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ | |
0411a972 | 2430 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
a4f30719 JM |
2431 | if (lpes1 == 0) /* XXX: check this */ |
2432 | new_msr |= (target_ulong)MSR_HVB; | |
e1833e1f | 2433 | switch (excp_model) { |
a750fc0b JM |
2434 | case POWERPC_EXCP_602: |
2435 | case POWERPC_EXCP_603: | |
2436 | case POWERPC_EXCP_603E: | |
2437 | case POWERPC_EXCP_G2: | |
e1833e1f | 2438 | tlb_miss_tgpr: |
76a66253 | 2439 | /* Swap temporary saved registers with GPRs */ |
0411a972 JM |
2440 | if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { |
2441 | new_msr |= (target_ulong)1 << MSR_TGPR; | |
2442 | hreg_swap_gpr_tgpr(env); | |
2443 | } | |
e1833e1f JM |
2444 | goto tlb_miss; |
2445 | case POWERPC_EXCP_7x5: | |
2446 | tlb_miss: | |
2be0071f | 2447 | #if defined (DEBUG_SOFTWARE_TLB) |
93fcfe39 | 2448 | if (qemu_log_enabled()) { |
76a66253 JM |
2449 | const unsigned char *es; |
2450 | target_ulong *miss, *cmp; | |
2451 | int en; | |
1e6784f9 | 2452 | if (excp == POWERPC_EXCP_IFTLB) { |
76a66253 JM |
2453 | es = "I"; |
2454 | en = 'I'; | |
2455 | miss = &env->spr[SPR_IMISS]; | |
2456 | cmp = &env->spr[SPR_ICMP]; | |
2457 | } else { | |
1e6784f9 | 2458 | if (excp == POWERPC_EXCP_DLTLB) |
76a66253 JM |
2459 | es = "DL"; |
2460 | else | |
2461 | es = "DS"; | |
2462 | en = 'D'; | |
2463 | miss = &env->spr[SPR_DMISS]; | |
2464 | cmp = &env->spr[SPR_DCMP]; | |
2465 | } | |
93fcfe39 | 2466 | qemu_log("6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX |
4a057712 | 2467 | " H1 " ADDRX " H2 " ADDRX " %08x\n", |
1b9eb036 | 2468 | es, en, *miss, en, *cmp, |
76a66253 | 2469 | env->spr[SPR_HASH1], env->spr[SPR_HASH2], |
2be0071f FB |
2470 | env->error_code); |
2471 | } | |
9a64fbe4 | 2472 | #endif |
2be0071f FB |
2473 | msr |= env->crf[0] << 28; |
2474 | msr |= env->error_code; /* key, D/I, S/L bits */ | |
2475 | /* Set way using a LRU mechanism */ | |
76a66253 | 2476 | msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; |
c62db105 | 2477 | break; |
7dbe11ac JM |
2478 | case POWERPC_EXCP_74xx: |
2479 | tlb_miss_74xx: | |
2480 | #if defined (DEBUG_SOFTWARE_TLB) | |
93fcfe39 | 2481 | if (qemu_log_enabled()) { |
7dbe11ac JM |
2482 | const unsigned char *es; |
2483 | target_ulong *miss, *cmp; | |
2484 | int en; | |
2485 | if (excp == POWERPC_EXCP_IFTLB) { | |
2486 | es = "I"; | |
2487 | en = 'I'; | |
0411a972 JM |
2488 | miss = &env->spr[SPR_TLBMISS]; |
2489 | cmp = &env->spr[SPR_PTEHI]; | |
7dbe11ac JM |
2490 | } else { |
2491 | if (excp == POWERPC_EXCP_DLTLB) | |
2492 | es = "DL"; | |
2493 | else | |
2494 | es = "DS"; | |
2495 | en = 'D'; | |
2496 | miss = &env->spr[SPR_TLBMISS]; | |
2497 | cmp = &env->spr[SPR_PTEHI]; | |
2498 | } | |
93fcfe39 | 2499 | qemu_log("74xx %sTLB miss: %cM " ADDRX " %cC " ADDRX |
7dbe11ac JM |
2500 | " %08x\n", |
2501 | es, en, *miss, en, *cmp, env->error_code); | |
2502 | } | |
2503 | #endif | |
2504 | msr |= env->error_code; /* key bit */ | |
2505 | break; | |
2be0071f | 2506 | default: |
e1833e1f | 2507 | cpu_abort(env, "Invalid data store TLB miss exception\n"); |
2be0071f FB |
2508 | break; |
2509 | } | |
e1833e1f JM |
2510 | goto store_next; |
2511 | case POWERPC_EXCP_FPA: /* Floating-point assist exception */ | |
2512 | /* XXX: TODO */ | |
2513 | cpu_abort(env, "Floating point assist exception " | |
2514 | "is not implemented yet !\n"); | |
2515 | goto store_next; | |
b4095fed JM |
2516 | case POWERPC_EXCP_DABR: /* Data address breakpoint */ |
2517 | /* XXX: TODO */ | |
2518 | cpu_abort(env, "DABR exception is not implemented yet !\n"); | |
2519 | goto store_next; | |
e1833e1f JM |
2520 | case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ |
2521 | /* XXX: TODO */ | |
2522 | cpu_abort(env, "IABR exception is not implemented yet !\n"); | |
2523 | goto store_next; | |
2524 | case POWERPC_EXCP_SMI: /* System management interrupt */ | |
2525 | /* XXX: TODO */ | |
2526 | cpu_abort(env, "SMI exception is not implemented yet !\n"); | |
2527 | goto store_next; | |
2528 | case POWERPC_EXCP_THERM: /* Thermal interrupt */ | |
2529 | /* XXX: TODO */ | |
2530 | cpu_abort(env, "Thermal management exception " | |
2531 | "is not implemented yet !\n"); | |
2532 | goto store_next; | |
2533 | case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ | |
0411a972 | 2534 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2535 | if (lpes1 == 0) |
a4f30719 | 2536 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f JM |
2537 | /* XXX: TODO */ |
2538 | cpu_abort(env, | |
2539 | "Performance counter exception is not implemented yet !\n"); | |
2540 | goto store_next; | |
2541 | case POWERPC_EXCP_VPUA: /* Vector assist exception */ | |
2542 | /* XXX: TODO */ | |
2543 | cpu_abort(env, "VPU assist exception is not implemented yet !\n"); | |
2544 | goto store_next; | |
2545 | case POWERPC_EXCP_SOFTP: /* Soft patch exception */ | |
2546 | /* XXX: TODO */ | |
2547 | cpu_abort(env, | |
2548 | "970 soft-patch exception is not implemented yet !\n"); | |
2549 | goto store_next; | |
2550 | case POWERPC_EXCP_MAINT: /* Maintenance exception */ | |
2551 | /* XXX: TODO */ | |
2552 | cpu_abort(env, | |
2553 | "970 maintenance exception is not implemented yet !\n"); | |
2554 | goto store_next; | |
b4095fed JM |
2555 | case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */ |
2556 | /* XXX: TODO */ | |
2557 | cpu_abort(env, "Maskable external exception " | |
2558 | "is not implemented yet !\n"); | |
2559 | goto store_next; | |
2560 | case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */ | |
2561 | /* XXX: TODO */ | |
2562 | cpu_abort(env, "Non maskable external exception " | |
2563 | "is not implemented yet !\n"); | |
2564 | goto store_next; | |
2be0071f | 2565 | default: |
e1833e1f JM |
2566 | excp_invalid: |
2567 | cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp); | |
2568 | break; | |
9a64fbe4 | 2569 | store_current: |
2be0071f | 2570 | /* save current instruction location */ |
e1833e1f | 2571 | env->spr[srr0] = env->nip - 4; |
9a64fbe4 FB |
2572 | break; |
2573 | store_next: | |
2be0071f | 2574 | /* save next instruction location */ |
e1833e1f | 2575 | env->spr[srr0] = env->nip; |
9a64fbe4 FB |
2576 | break; |
2577 | } | |
e1833e1f JM |
2578 | /* Save MSR */ |
2579 | env->spr[srr1] = msr; | |
2580 | /* If any alternate SRR register are defined, duplicate saved values */ | |
2581 | if (asrr0 != -1) | |
2582 | env->spr[asrr0] = env->spr[srr0]; | |
2583 | if (asrr1 != -1) | |
2584 | env->spr[asrr1] = env->spr[srr1]; | |
2be0071f | 2585 | /* If we disactivated any translation, flush TLBs */ |
0411a972 | 2586 | if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR))) |
2be0071f | 2587 | tlb_flush(env, 1); |
9a64fbe4 | 2588 | /* reload MSR with correct bits */ |
0411a972 JM |
2589 | new_msr &= ~((target_ulong)1 << MSR_EE); |
2590 | new_msr &= ~((target_ulong)1 << MSR_PR); | |
2591 | new_msr &= ~((target_ulong)1 << MSR_FP); | |
2592 | new_msr &= ~((target_ulong)1 << MSR_FE0); | |
2593 | new_msr &= ~((target_ulong)1 << MSR_SE); | |
2594 | new_msr &= ~((target_ulong)1 << MSR_BE); | |
2595 | new_msr &= ~((target_ulong)1 << MSR_FE1); | |
2596 | new_msr &= ~((target_ulong)1 << MSR_IR); | |
2597 | new_msr &= ~((target_ulong)1 << MSR_DR); | |
e1833e1f | 2598 | #if 0 /* Fix this: not on all targets */ |
0411a972 | 2599 | new_msr &= ~((target_ulong)1 << MSR_PMM); |
e1833e1f | 2600 | #endif |
0411a972 JM |
2601 | new_msr &= ~((target_ulong)1 << MSR_LE); |
2602 | if (msr_ile) | |
2603 | new_msr |= (target_ulong)1 << MSR_LE; | |
2604 | else | |
2605 | new_msr &= ~((target_ulong)1 << MSR_LE); | |
e1833e1f JM |
2606 | /* Jump to handler */ |
2607 | vector = env->excp_vectors[excp]; | |
6f2d8978 | 2608 | if (vector == (target_ulong)-1ULL) { |
e1833e1f JM |
2609 | cpu_abort(env, "Raised an exception without defined vector %d\n", |
2610 | excp); | |
2611 | } | |
2612 | vector |= env->excp_prefix; | |
c62db105 | 2613 | #if defined(TARGET_PPC64) |
e1833e1f | 2614 | if (excp_model == POWERPC_EXCP_BOOKE) { |
0411a972 JM |
2615 | if (!msr_icm) { |
2616 | new_msr &= ~((target_ulong)1 << MSR_CM); | |
e1833e1f | 2617 | vector = (uint32_t)vector; |
0411a972 JM |
2618 | } else { |
2619 | new_msr |= (target_ulong)1 << MSR_CM; | |
2620 | } | |
c62db105 | 2621 | } else { |
6ce0ca12 | 2622 | if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) { |
0411a972 | 2623 | new_msr &= ~((target_ulong)1 << MSR_SF); |
e1833e1f | 2624 | vector = (uint32_t)vector; |
0411a972 JM |
2625 | } else { |
2626 | new_msr |= (target_ulong)1 << MSR_SF; | |
2627 | } | |
c62db105 | 2628 | } |
e1833e1f | 2629 | #endif |
0411a972 JM |
2630 | /* XXX: we don't use hreg_store_msr here as already have treated |
2631 | * any special case that could occur. Just store MSR and update hflags | |
2632 | */ | |
a4f30719 | 2633 | env->msr = new_msr & env->msr_mask; |
0411a972 | 2634 | hreg_compute_hflags(env); |
e1833e1f JM |
2635 | env->nip = vector; |
2636 | /* Reset exception state */ | |
2637 | env->exception_index = POWERPC_EXCP_NONE; | |
2638 | env->error_code = 0; | |
fb0eaffc | 2639 | } |
47103572 | 2640 | |
e1833e1f | 2641 | void do_interrupt (CPUState *env) |
47103572 | 2642 | { |
e1833e1f JM |
2643 | powerpc_excp(env, env->excp_model, env->exception_index); |
2644 | } | |
47103572 | 2645 | |
e1833e1f JM |
2646 | void ppc_hw_interrupt (CPUPPCState *env) |
2647 | { | |
f9fdea6b | 2648 | int hdice; |
f9fdea6b | 2649 | |
0411a972 | 2650 | #if 0 |
93fcfe39 | 2651 | qemu_log_mask(CPU_LOG_INT, "%s: %p pending %08x req %08x me %d ee %d\n", |
a496775f | 2652 | __func__, env, env->pending_interrupts, |
0411a972 | 2653 | env->interrupt_request, (int)msr_me, (int)msr_ee); |
47103572 | 2654 | #endif |
e1833e1f | 2655 | /* External reset */ |
47103572 | 2656 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) { |
47103572 | 2657 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET); |
e1833e1f JM |
2658 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET); |
2659 | return; | |
2660 | } | |
2661 | /* Machine check exception */ | |
2662 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) { | |
2663 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK); | |
2664 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK); | |
2665 | return; | |
47103572 | 2666 | } |
e1833e1f JM |
2667 | #if 0 /* TODO */ |
2668 | /* External debug exception */ | |
2669 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) { | |
2670 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG); | |
2671 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG); | |
2672 | return; | |
2673 | } | |
2674 | #endif | |
b172c56a JM |
2675 | if (0) { |
2676 | /* XXX: find a suitable condition to enable the hypervisor mode */ | |
2677 | hdice = env->spr[SPR_LPCR] & 1; | |
2678 | } else { | |
2679 | hdice = 0; | |
2680 | } | |
f9fdea6b | 2681 | if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) && hdice != 0) { |
47103572 JM |
2682 | /* Hypervisor decrementer exception */ |
2683 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) { | |
47103572 | 2684 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR); |
e1833e1f JM |
2685 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR); |
2686 | return; | |
2687 | } | |
2688 | } | |
e1833e1f JM |
2689 | if (msr_ce != 0) { |
2690 | /* External critical interrupt */ | |
2691 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) { | |
2692 | /* Taking a critical external interrupt does not clear the external | |
2693 | * critical interrupt status | |
2694 | */ | |
2695 | #if 0 | |
2696 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT); | |
47103572 | 2697 | #endif |
e1833e1f JM |
2698 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL); |
2699 | return; | |
2700 | } | |
2701 | } | |
2702 | if (msr_ee != 0) { | |
2703 | /* Watchdog timer on embedded PowerPC */ | |
2704 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) { | |
2705 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT); | |
2706 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT); | |
2707 | return; | |
2708 | } | |
e1833e1f JM |
2709 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) { |
2710 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL); | |
2711 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI); | |
2712 | return; | |
2713 | } | |
e1833e1f JM |
2714 | /* Fixed interval timer on embedded PowerPC */ |
2715 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) { | |
2716 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT); | |
2717 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT); | |
2718 | return; | |
2719 | } | |
2720 | /* Programmable interval timer on embedded PowerPC */ | |
2721 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) { | |
2722 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT); | |
2723 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT); | |
2724 | return; | |
2725 | } | |
47103572 JM |
2726 | /* Decrementer exception */ |
2727 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) { | |
47103572 | 2728 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR); |
e1833e1f JM |
2729 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR); |
2730 | return; | |
2731 | } | |
47103572 | 2732 | /* External interrupt */ |
e1833e1f | 2733 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { |
e9df014c JM |
2734 | /* Taking an external interrupt does not clear the external |
2735 | * interrupt status | |
2736 | */ | |
2737 | #if 0 | |
47103572 | 2738 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT); |
e9df014c | 2739 | #endif |
e1833e1f JM |
2740 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL); |
2741 | return; | |
2742 | } | |
e1833e1f JM |
2743 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { |
2744 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL); | |
2745 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI); | |
2746 | return; | |
47103572 | 2747 | } |
e1833e1f JM |
2748 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) { |
2749 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM); | |
2750 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM); | |
2751 | return; | |
2752 | } | |
2753 | /* Thermal interrupt */ | |
2754 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) { | |
2755 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM); | |
2756 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM); | |
2757 | return; | |
2758 | } | |
47103572 | 2759 | } |
47103572 | 2760 | } |
18fba28c | 2761 | #endif /* !CONFIG_USER_ONLY */ |
a496775f | 2762 | |
4a057712 JM |
2763 | void cpu_dump_rfi (target_ulong RA, target_ulong msr) |
2764 | { | |
93fcfe39 AL |
2765 | qemu_log("Return from exception at " ADDRX " with flags " ADDRX "\n", |
2766 | RA, msr); | |
a496775f JM |
2767 | } |
2768 | ||
0a032cbe JM |
2769 | void cpu_ppc_reset (void *opaque) |
2770 | { | |
eca1bdf4 | 2771 | CPUPPCState *env = opaque; |
0411a972 | 2772 | target_ulong msr; |
0a032cbe | 2773 | |
eca1bdf4 AL |
2774 | if (qemu_loglevel_mask(CPU_LOG_RESET)) { |
2775 | qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); | |
2776 | log_cpu_state(env, 0); | |
2777 | } | |
2778 | ||
0411a972 | 2779 | msr = (target_ulong)0; |
a4f30719 JM |
2780 | if (0) { |
2781 | /* XXX: find a suitable condition to enable the hypervisor mode */ | |
2782 | msr |= (target_ulong)MSR_HVB; | |
2783 | } | |
0411a972 JM |
2784 | msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ |
2785 | msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ | |
2786 | msr |= (target_ulong)1 << MSR_EP; | |
0a032cbe JM |
2787 | #if defined (DO_SINGLE_STEP) && 0 |
2788 | /* Single step trace mode */ | |
0411a972 JM |
2789 | msr |= (target_ulong)1 << MSR_SE; |
2790 | msr |= (target_ulong)1 << MSR_BE; | |
0a032cbe JM |
2791 | #endif |
2792 | #if defined(CONFIG_USER_ONLY) | |
0411a972 | 2793 | msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ |
4c2ab988 AJ |
2794 | msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ |
2795 | msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ | |
0411a972 | 2796 | msr |= (target_ulong)1 << MSR_PR; |
fe33cc71 | 2797 | #else |
fc1c67bc | 2798 | env->excp_prefix = env->hreset_excp_prefix; |
1c27f8fb | 2799 | env->nip = env->hreset_vector | env->excp_prefix; |
b4095fed | 2800 | if (env->mmu_model != POWERPC_MMU_REAL) |
141c8ae2 | 2801 | ppc_tlb_invalidate_all(env); |
0a032cbe | 2802 | #endif |
07c485ce | 2803 | env->msr = msr & env->msr_mask; |
6ce0ca12 BS |
2804 | #if defined(TARGET_PPC64) |
2805 | if (env->mmu_model & POWERPC_MMU_64) | |
2806 | env->msr |= (1ULL << MSR_SF); | |
2807 | #endif | |
0411a972 | 2808 | hreg_compute_hflags(env); |
6f2d8978 | 2809 | env->reserve = (target_ulong)-1ULL; |
5eb7995e JM |
2810 | /* Be sure no exception or interrupt is pending */ |
2811 | env->pending_interrupts = 0; | |
e1833e1f JM |
2812 | env->exception_index = POWERPC_EXCP_NONE; |
2813 | env->error_code = 0; | |
5eb7995e JM |
2814 | /* Flush all TLBs */ |
2815 | tlb_flush(env, 1); | |
0a032cbe JM |
2816 | } |
2817 | ||
aaed909a | 2818 | CPUPPCState *cpu_ppc_init (const char *cpu_model) |
0a032cbe JM |
2819 | { |
2820 | CPUPPCState *env; | |
aaed909a FB |
2821 | const ppc_def_t *def; |
2822 | ||
2823 | def = cpu_ppc_find_by_name(cpu_model); | |
2824 | if (!def) | |
2825 | return NULL; | |
0a032cbe JM |
2826 | |
2827 | env = qemu_mallocz(sizeof(CPUPPCState)); | |
0a032cbe | 2828 | cpu_exec_init(env); |
2e70f6ef | 2829 | ppc_translate_init(); |
01ba9816 | 2830 | env->cpu_model_str = cpu_model; |
aaed909a FB |
2831 | cpu_ppc_register_internal(env, def); |
2832 | cpu_ppc_reset(env); | |
d76d1650 | 2833 | |
0bf46a40 | 2834 | qemu_init_vcpu(env); |
d76d1650 | 2835 | |
0a032cbe JM |
2836 | return env; |
2837 | } | |
2838 | ||
2839 | void cpu_ppc_close (CPUPPCState *env) | |
2840 | { | |
2841 | /* Should also remove all opcode tables... */ | |
aaed909a | 2842 | qemu_free(env); |
0a032cbe | 2843 | } |