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Commit | Line | Data |
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d76d1650 AJ |
1 | /* |
2 | * PowerPC implementation of KVM hooks | |
3 | * | |
4 | * Copyright IBM Corp. 2007 | |
90dc8812 | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
d76d1650 AJ |
6 | * |
7 | * Authors: | |
8 | * Jerone Young <jyoung5@us.ibm.com> | |
9 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> | |
10 | * Hollis Blanchard <hollisb@us.ibm.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
13 | * See the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
16 | ||
eadaada1 | 17 | #include <dirent.h> |
d76d1650 AJ |
18 | #include <sys/types.h> |
19 | #include <sys/ioctl.h> | |
20 | #include <sys/mman.h> | |
21 | ||
22 | #include <linux/kvm.h> | |
23 | ||
24 | #include "qemu-common.h" | |
25 | #include "qemu-timer.h" | |
26 | #include "sysemu.h" | |
27 | #include "kvm.h" | |
28 | #include "kvm_ppc.h" | |
29 | #include "cpu.h" | |
30 | #include "device_tree.h" | |
e97c3636 | 31 | #include "hw/spapr.h" |
d76d1650 | 32 | |
f61b4bed AG |
33 | #include "hw/sysbus.h" |
34 | #include "hw/spapr.h" | |
35 | #include "hw/spapr_vio.h" | |
36 | ||
d76d1650 AJ |
37 | //#define DEBUG_KVM |
38 | ||
39 | #ifdef DEBUG_KVM | |
40 | #define dprintf(fmt, ...) \ | |
41 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) | |
42 | #else | |
43 | #define dprintf(fmt, ...) \ | |
44 | do { } while (0) | |
45 | #endif | |
46 | ||
eadaada1 AG |
47 | #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/" |
48 | ||
94a8d39a JK |
49 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { |
50 | KVM_CAP_LAST_INFO | |
51 | }; | |
52 | ||
fc87e185 AG |
53 | static int cap_interrupt_unset = false; |
54 | static int cap_interrupt_level = false; | |
90dc8812 | 55 | static int cap_segstate; |
90dc8812 | 56 | static int cap_booke_sregs; |
e97c3636 | 57 | static int cap_ppc_smt; |
fc87e185 | 58 | |
c821c2bd AG |
59 | /* XXX We have a race condition where we actually have a level triggered |
60 | * interrupt, but the infrastructure can't expose that yet, so the guest | |
61 | * takes but ignores it, goes to sleep and never gets notified that there's | |
62 | * still an interrupt pending. | |
c6a94ba5 | 63 | * |
c821c2bd AG |
64 | * As a quick workaround, let's just wake up again 20 ms after we injected |
65 | * an interrupt. That way we can assure that we're always reinjecting | |
66 | * interrupts in case the guest swallowed them. | |
c6a94ba5 AG |
67 | */ |
68 | static QEMUTimer *idle_timer; | |
69 | ||
c821c2bd | 70 | static void kvm_kick_env(void *env) |
c6a94ba5 | 71 | { |
c821c2bd | 72 | qemu_cpu_kick(env); |
c6a94ba5 AG |
73 | } |
74 | ||
cad1e282 | 75 | int kvm_arch_init(KVMState *s) |
d76d1650 | 76 | { |
fc87e185 | 77 | cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ); |
fc87e185 | 78 | cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL); |
90dc8812 | 79 | cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE); |
90dc8812 | 80 | cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS); |
e97c3636 | 81 | cap_ppc_smt = kvm_check_extension(s, KVM_CAP_PPC_SMT); |
fc87e185 AG |
82 | |
83 | if (!cap_interrupt_level) { | |
84 | fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the " | |
85 | "VM to stall at times!\n"); | |
86 | } | |
87 | ||
d76d1650 AJ |
88 | return 0; |
89 | } | |
90 | ||
5666ca4a | 91 | static int kvm_arch_sync_sregs(CPUState *cenv) |
d76d1650 | 92 | { |
861bbc80 | 93 | struct kvm_sregs sregs; |
5666ca4a SW |
94 | int ret; |
95 | ||
96 | if (cenv->excp_model == POWERPC_EXCP_BOOKE) { | |
64e07be5 AG |
97 | /* What we're really trying to say is "if we're on BookE, we use |
98 | the native PVR for now". This is the only sane way to check | |
99 | it though, so we potentially confuse users that they can run | |
100 | BookE guests on BookS. Let's hope nobody dares enough :) */ | |
5666ca4a SW |
101 | return 0; |
102 | } else { | |
90dc8812 | 103 | if (!cap_segstate) { |
64e07be5 AG |
104 | fprintf(stderr, "kvm error: missing PVR setting capability\n"); |
105 | return -ENOSYS; | |
5666ca4a | 106 | } |
5666ca4a SW |
107 | } |
108 | ||
109 | ret = kvm_vcpu_ioctl(cenv, KVM_GET_SREGS, &sregs); | |
110 | if (ret) { | |
111 | return ret; | |
112 | } | |
861bbc80 AG |
113 | |
114 | sregs.pvr = cenv->spr[SPR_PVR]; | |
5666ca4a SW |
115 | return kvm_vcpu_ioctl(cenv, KVM_SET_SREGS, &sregs); |
116 | } | |
117 | ||
93dd5e85 SW |
118 | /* Set up a shared TLB array with KVM */ |
119 | static int kvm_booke206_tlb_init(CPUState *env) | |
120 | { | |
121 | struct kvm_book3e_206_tlb_params params = {}; | |
122 | struct kvm_config_tlb cfg = {}; | |
123 | struct kvm_enable_cap encap = {}; | |
124 | unsigned int entries = 0; | |
125 | int ret, i; | |
126 | ||
127 | if (!kvm_enabled() || | |
128 | !kvm_check_extension(env->kvm_state, KVM_CAP_SW_TLB)) { | |
129 | return 0; | |
130 | } | |
131 | ||
132 | assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN); | |
133 | ||
134 | for (i = 0; i < BOOKE206_MAX_TLBN; i++) { | |
135 | params.tlb_sizes[i] = booke206_tlb_size(env, i); | |
136 | params.tlb_ways[i] = booke206_tlb_ways(env, i); | |
137 | entries += params.tlb_sizes[i]; | |
138 | } | |
139 | ||
140 | assert(entries == env->nb_tlb); | |
141 | assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t)); | |
142 | ||
143 | env->tlb_dirty = true; | |
144 | ||
145 | cfg.array = (uintptr_t)env->tlb.tlbm; | |
146 | cfg.array_len = sizeof(ppcmas_tlb_t) * entries; | |
147 | cfg.params = (uintptr_t)¶ms; | |
148 | cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV; | |
149 | ||
150 | encap.cap = KVM_CAP_SW_TLB; | |
151 | encap.args[0] = (uintptr_t)&cfg; | |
152 | ||
153 | ret = kvm_vcpu_ioctl(env, KVM_ENABLE_CAP, &encap); | |
154 | if (ret < 0) { | |
155 | fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n", | |
156 | __func__, strerror(-ret)); | |
157 | return ret; | |
158 | } | |
159 | ||
160 | env->kvm_sw_tlb = true; | |
161 | return 0; | |
162 | } | |
163 | ||
5666ca4a SW |
164 | int kvm_arch_init_vcpu(CPUState *cenv) |
165 | { | |
166 | int ret; | |
167 | ||
168 | ret = kvm_arch_sync_sregs(cenv); | |
169 | if (ret) { | |
170 | return ret; | |
171 | } | |
861bbc80 | 172 | |
74475455 | 173 | idle_timer = qemu_new_timer_ns(vm_clock, kvm_kick_env, cenv); |
c821c2bd | 174 | |
93dd5e85 SW |
175 | /* Some targets support access to KVM's guest TLB. */ |
176 | switch (cenv->mmu_model) { | |
177 | case POWERPC_MMU_BOOKE206: | |
178 | ret = kvm_booke206_tlb_init(cenv); | |
179 | break; | |
180 | default: | |
181 | break; | |
182 | } | |
183 | ||
861bbc80 | 184 | return ret; |
d76d1650 AJ |
185 | } |
186 | ||
caa5af0f JK |
187 | void kvm_arch_reset_vcpu(CPUState *env) |
188 | { | |
189 | } | |
190 | ||
93dd5e85 SW |
191 | static void kvm_sw_tlb_put(CPUState *env) |
192 | { | |
193 | struct kvm_dirty_tlb dirty_tlb; | |
194 | unsigned char *bitmap; | |
195 | int ret; | |
196 | ||
197 | if (!env->kvm_sw_tlb) { | |
198 | return; | |
199 | } | |
200 | ||
201 | bitmap = g_malloc((env->nb_tlb + 7) / 8); | |
202 | memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8); | |
203 | ||
204 | dirty_tlb.bitmap = (uintptr_t)bitmap; | |
205 | dirty_tlb.num_dirty = env->nb_tlb; | |
206 | ||
207 | ret = kvm_vcpu_ioctl(env, KVM_DIRTY_TLB, &dirty_tlb); | |
208 | if (ret) { | |
209 | fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n", | |
210 | __func__, strerror(-ret)); | |
211 | } | |
212 | ||
213 | g_free(bitmap); | |
214 | } | |
215 | ||
ea375f9a | 216 | int kvm_arch_put_registers(CPUState *env, int level) |
d76d1650 AJ |
217 | { |
218 | struct kvm_regs regs; | |
219 | int ret; | |
220 | int i; | |
221 | ||
222 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); | |
223 | if (ret < 0) | |
224 | return ret; | |
225 | ||
226 | regs.ctr = env->ctr; | |
227 | regs.lr = env->lr; | |
228 | regs.xer = env->xer; | |
229 | regs.msr = env->msr; | |
230 | regs.pc = env->nip; | |
231 | ||
232 | regs.srr0 = env->spr[SPR_SRR0]; | |
233 | regs.srr1 = env->spr[SPR_SRR1]; | |
234 | ||
235 | regs.sprg0 = env->spr[SPR_SPRG0]; | |
236 | regs.sprg1 = env->spr[SPR_SPRG1]; | |
237 | regs.sprg2 = env->spr[SPR_SPRG2]; | |
238 | regs.sprg3 = env->spr[SPR_SPRG3]; | |
239 | regs.sprg4 = env->spr[SPR_SPRG4]; | |
240 | regs.sprg5 = env->spr[SPR_SPRG5]; | |
241 | regs.sprg6 = env->spr[SPR_SPRG6]; | |
242 | regs.sprg7 = env->spr[SPR_SPRG7]; | |
243 | ||
90dc8812 SW |
244 | regs.pid = env->spr[SPR_BOOKE_PID]; |
245 | ||
d76d1650 AJ |
246 | for (i = 0;i < 32; i++) |
247 | regs.gpr[i] = env->gpr[i]; | |
248 | ||
249 | ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); | |
250 | if (ret < 0) | |
251 | return ret; | |
252 | ||
93dd5e85 SW |
253 | if (env->tlb_dirty) { |
254 | kvm_sw_tlb_put(env); | |
255 | env->tlb_dirty = false; | |
256 | } | |
257 | ||
d76d1650 AJ |
258 | return ret; |
259 | } | |
260 | ||
261 | int kvm_arch_get_registers(CPUState *env) | |
262 | { | |
263 | struct kvm_regs regs; | |
ba5e5090 | 264 | struct kvm_sregs sregs; |
90dc8812 | 265 | uint32_t cr; |
138b38b6 | 266 | int i, ret; |
d76d1650 AJ |
267 | |
268 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); | |
269 | if (ret < 0) | |
270 | return ret; | |
271 | ||
90dc8812 SW |
272 | cr = regs.cr; |
273 | for (i = 7; i >= 0; i--) { | |
274 | env->crf[i] = cr & 15; | |
275 | cr >>= 4; | |
276 | } | |
ba5e5090 | 277 | |
d76d1650 AJ |
278 | env->ctr = regs.ctr; |
279 | env->lr = regs.lr; | |
280 | env->xer = regs.xer; | |
281 | env->msr = regs.msr; | |
282 | env->nip = regs.pc; | |
283 | ||
284 | env->spr[SPR_SRR0] = regs.srr0; | |
285 | env->spr[SPR_SRR1] = regs.srr1; | |
286 | ||
287 | env->spr[SPR_SPRG0] = regs.sprg0; | |
288 | env->spr[SPR_SPRG1] = regs.sprg1; | |
289 | env->spr[SPR_SPRG2] = regs.sprg2; | |
290 | env->spr[SPR_SPRG3] = regs.sprg3; | |
291 | env->spr[SPR_SPRG4] = regs.sprg4; | |
292 | env->spr[SPR_SPRG5] = regs.sprg5; | |
293 | env->spr[SPR_SPRG6] = regs.sprg6; | |
294 | env->spr[SPR_SPRG7] = regs.sprg7; | |
295 | ||
90dc8812 SW |
296 | env->spr[SPR_BOOKE_PID] = regs.pid; |
297 | ||
d76d1650 AJ |
298 | for (i = 0;i < 32; i++) |
299 | env->gpr[i] = regs.gpr[i]; | |
300 | ||
90dc8812 SW |
301 | if (cap_booke_sregs) { |
302 | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); | |
303 | if (ret < 0) { | |
304 | return ret; | |
305 | } | |
306 | ||
307 | if (sregs.u.e.features & KVM_SREGS_E_BASE) { | |
308 | env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0; | |
309 | env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1; | |
310 | env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr; | |
311 | env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear; | |
312 | env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr; | |
313 | env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr; | |
314 | env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr; | |
315 | env->spr[SPR_DECR] = sregs.u.e.dec; | |
316 | env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff; | |
317 | env->spr[SPR_TBU] = sregs.u.e.tb >> 32; | |
318 | env->spr[SPR_VRSAVE] = sregs.u.e.vrsave; | |
319 | } | |
320 | ||
321 | if (sregs.u.e.features & KVM_SREGS_E_ARCH206) { | |
322 | env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir; | |
323 | env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0; | |
324 | env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1; | |
325 | env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar; | |
326 | env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr; | |
327 | } | |
328 | ||
329 | if (sregs.u.e.features & KVM_SREGS_E_64) { | |
330 | env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr; | |
331 | } | |
332 | ||
333 | if (sregs.u.e.features & KVM_SREGS_E_SPRG8) { | |
334 | env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8; | |
335 | } | |
336 | ||
337 | if (sregs.u.e.features & KVM_SREGS_E_IVOR) { | |
338 | env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0]; | |
339 | env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1]; | |
340 | env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2]; | |
341 | env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3]; | |
342 | env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4]; | |
343 | env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5]; | |
344 | env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6]; | |
345 | env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7]; | |
346 | env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8]; | |
347 | env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9]; | |
348 | env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10]; | |
349 | env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11]; | |
350 | env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12]; | |
351 | env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13]; | |
352 | env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14]; | |
353 | env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15]; | |
354 | ||
355 | if (sregs.u.e.features & KVM_SREGS_E_SPE) { | |
356 | env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0]; | |
357 | env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1]; | |
358 | env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2]; | |
359 | } | |
360 | ||
361 | if (sregs.u.e.features & KVM_SREGS_E_PM) { | |
362 | env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3]; | |
363 | } | |
364 | ||
365 | if (sregs.u.e.features & KVM_SREGS_E_PC) { | |
366 | env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4]; | |
367 | env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5]; | |
368 | } | |
369 | } | |
370 | ||
371 | if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) { | |
372 | env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0; | |
373 | env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1; | |
374 | env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2; | |
375 | env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff; | |
376 | env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4; | |
377 | env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6; | |
378 | env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32; | |
379 | env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg; | |
380 | env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0]; | |
381 | env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1]; | |
382 | } | |
383 | ||
384 | if (sregs.u.e.features & KVM_SREGS_EXP) { | |
385 | env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr; | |
386 | } | |
387 | ||
388 | if (sregs.u.e.features & KVM_SREGS_E_PD) { | |
389 | env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc; | |
390 | env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc; | |
391 | } | |
392 | ||
393 | if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) { | |
394 | env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr; | |
395 | env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar; | |
396 | env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0; | |
397 | ||
398 | if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) { | |
399 | env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1; | |
400 | env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2; | |
401 | } | |
402 | } | |
fafc0b6a | 403 | } |
90dc8812 | 404 | |
90dc8812 SW |
405 | if (cap_segstate) { |
406 | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); | |
407 | if (ret < 0) { | |
408 | return ret; | |
409 | } | |
410 | ||
bb593904 | 411 | ppc_store_sdr1(env, sregs.u.s.sdr1); |
ba5e5090 AG |
412 | |
413 | /* Sync SLB */ | |
82c09f2f | 414 | #ifdef TARGET_PPC64 |
ba5e5090 AG |
415 | for (i = 0; i < 64; i++) { |
416 | ppc_store_slb(env, sregs.u.s.ppc64.slb[i].slbe, | |
417 | sregs.u.s.ppc64.slb[i].slbv); | |
418 | } | |
82c09f2f | 419 | #endif |
ba5e5090 AG |
420 | |
421 | /* Sync SRs */ | |
422 | for (i = 0; i < 16; i++) { | |
423 | env->sr[i] = sregs.u.s.ppc32.sr[i]; | |
424 | } | |
425 | ||
426 | /* Sync BATs */ | |
427 | for (i = 0; i < 8; i++) { | |
428 | env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff; | |
429 | env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32; | |
430 | env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff; | |
431 | env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32; | |
432 | } | |
fafc0b6a | 433 | } |
ba5e5090 | 434 | |
d76d1650 AJ |
435 | return 0; |
436 | } | |
437 | ||
fc87e185 AG |
438 | int kvmppc_set_interrupt(CPUState *env, int irq, int level) |
439 | { | |
440 | unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET; | |
441 | ||
442 | if (irq != PPC_INTERRUPT_EXT) { | |
443 | return 0; | |
444 | } | |
445 | ||
446 | if (!kvm_enabled() || !cap_interrupt_unset || !cap_interrupt_level) { | |
447 | return 0; | |
448 | } | |
449 | ||
450 | kvm_vcpu_ioctl(env, KVM_INTERRUPT, &virq); | |
451 | ||
452 | return 0; | |
453 | } | |
454 | ||
16415335 AG |
455 | #if defined(TARGET_PPCEMB) |
456 | #define PPC_INPUT_INT PPC40x_INPUT_INT | |
457 | #elif defined(TARGET_PPC64) | |
458 | #define PPC_INPUT_INT PPC970_INPUT_INT | |
459 | #else | |
460 | #define PPC_INPUT_INT PPC6xx_INPUT_INT | |
461 | #endif | |
462 | ||
bdcbd3e2 | 463 | void kvm_arch_pre_run(CPUState *env, struct kvm_run *run) |
d76d1650 AJ |
464 | { |
465 | int r; | |
466 | unsigned irq; | |
467 | ||
468 | /* PowerPC Qemu tracks the various core input pins (interrupt, critical | |
469 | * interrupt, reset, etc) in PPC-specific env->irq_input_state. */ | |
fc87e185 AG |
470 | if (!cap_interrupt_level && |
471 | run->ready_for_interrupt_injection && | |
d76d1650 | 472 | (env->interrupt_request & CPU_INTERRUPT_HARD) && |
16415335 | 473 | (env->irq_input_state & (1<<PPC_INPUT_INT))) |
d76d1650 AJ |
474 | { |
475 | /* For now KVM disregards the 'irq' argument. However, in the | |
476 | * future KVM could cache it in-kernel to avoid a heavyweight exit | |
477 | * when reading the UIC. | |
478 | */ | |
fc87e185 | 479 | irq = KVM_INTERRUPT_SET; |
d76d1650 AJ |
480 | |
481 | dprintf("injected interrupt %d\n", irq); | |
482 | r = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &irq); | |
483 | if (r < 0) | |
484 | printf("cpu %d fail inject %x\n", env->cpu_index, irq); | |
c821c2bd AG |
485 | |
486 | /* Always wake up soon in case the interrupt was level based */ | |
74475455 | 487 | qemu_mod_timer(idle_timer, qemu_get_clock_ns(vm_clock) + |
c821c2bd | 488 | (get_ticks_per_sec() / 50)); |
d76d1650 AJ |
489 | } |
490 | ||
491 | /* We don't know if there are more interrupts pending after this. However, | |
492 | * the guest will return to userspace in the course of handling this one | |
493 | * anyways, so we will get a chance to deliver the rest. */ | |
d76d1650 AJ |
494 | } |
495 | ||
7a39fe58 | 496 | void kvm_arch_post_run(CPUState *env, struct kvm_run *run) |
d76d1650 | 497 | { |
d76d1650 AJ |
498 | } |
499 | ||
99036865 | 500 | int kvm_arch_process_async_events(CPUState *env) |
0af691d7 | 501 | { |
bdcbd3e2 | 502 | return 0; |
0af691d7 MT |
503 | } |
504 | ||
d76d1650 AJ |
505 | static int kvmppc_handle_halt(CPUState *env) |
506 | { | |
507 | if (!(env->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) { | |
508 | env->halted = 1; | |
509 | env->exception_index = EXCP_HLT; | |
510 | } | |
511 | ||
bb4ea393 | 512 | return 0; |
d76d1650 AJ |
513 | } |
514 | ||
515 | /* map dcr access to existing qemu dcr emulation */ | |
516 | static int kvmppc_handle_dcr_read(CPUState *env, uint32_t dcrn, uint32_t *data) | |
517 | { | |
518 | if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) | |
519 | fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn); | |
520 | ||
bb4ea393 | 521 | return 0; |
d76d1650 AJ |
522 | } |
523 | ||
524 | static int kvmppc_handle_dcr_write(CPUState *env, uint32_t dcrn, uint32_t data) | |
525 | { | |
526 | if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) | |
527 | fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn); | |
528 | ||
bb4ea393 | 529 | return 0; |
d76d1650 AJ |
530 | } |
531 | ||
532 | int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) | |
533 | { | |
bb4ea393 | 534 | int ret; |
d76d1650 AJ |
535 | |
536 | switch (run->exit_reason) { | |
537 | case KVM_EXIT_DCR: | |
538 | if (run->dcr.is_write) { | |
539 | dprintf("handle dcr write\n"); | |
540 | ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data); | |
541 | } else { | |
542 | dprintf("handle dcr read\n"); | |
543 | ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data); | |
544 | } | |
545 | break; | |
546 | case KVM_EXIT_HLT: | |
547 | dprintf("handle halt\n"); | |
548 | ret = kvmppc_handle_halt(env); | |
549 | break; | |
f61b4bed AG |
550 | #ifdef CONFIG_PSERIES |
551 | case KVM_EXIT_PAPR_HCALL: | |
552 | dprintf("handle PAPR hypercall\n"); | |
553 | run->papr_hcall.ret = spapr_hypercall(env, run->papr_hcall.nr, | |
554 | run->papr_hcall.args); | |
555 | ret = 1; | |
556 | break; | |
557 | #endif | |
73aaec4a JK |
558 | default: |
559 | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); | |
560 | ret = -1; | |
561 | break; | |
d76d1650 AJ |
562 | } |
563 | ||
564 | return ret; | |
565 | } | |
566 | ||
dc333cd6 AG |
567 | static int read_cpuinfo(const char *field, char *value, int len) |
568 | { | |
569 | FILE *f; | |
570 | int ret = -1; | |
571 | int field_len = strlen(field); | |
572 | char line[512]; | |
573 | ||
574 | f = fopen("/proc/cpuinfo", "r"); | |
575 | if (!f) { | |
576 | return -1; | |
577 | } | |
578 | ||
579 | do { | |
580 | if(!fgets(line, sizeof(line), f)) { | |
581 | break; | |
582 | } | |
583 | if (!strncmp(line, field, field_len)) { | |
584 | strncpy(value, line, len); | |
585 | ret = 0; | |
586 | break; | |
587 | } | |
588 | } while(*line); | |
589 | ||
590 | fclose(f); | |
591 | ||
592 | return ret; | |
593 | } | |
594 | ||
595 | uint32_t kvmppc_get_tbfreq(void) | |
596 | { | |
597 | char line[512]; | |
598 | char *ns; | |
599 | uint32_t retval = get_ticks_per_sec(); | |
600 | ||
601 | if (read_cpuinfo("timebase", line, sizeof(line))) { | |
602 | return retval; | |
603 | } | |
604 | ||
605 | if (!(ns = strchr(line, ':'))) { | |
606 | return retval; | |
607 | } | |
608 | ||
609 | ns++; | |
610 | ||
611 | retval = atoi(ns); | |
612 | return retval; | |
613 | } | |
4513d923 | 614 | |
eadaada1 AG |
615 | /* Try to find a device tree node for a CPU with clock-frequency property */ |
616 | static int kvmppc_find_cpu_dt(char *buf, int buf_len) | |
617 | { | |
618 | struct dirent *dirp; | |
619 | DIR *dp; | |
620 | ||
621 | if ((dp = opendir(PROC_DEVTREE_CPU)) == NULL) { | |
622 | printf("Can't open directory " PROC_DEVTREE_CPU "\n"); | |
623 | return -1; | |
624 | } | |
625 | ||
626 | buf[0] = '\0'; | |
627 | while ((dirp = readdir(dp)) != NULL) { | |
628 | FILE *f; | |
629 | snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU, | |
630 | dirp->d_name); | |
631 | f = fopen(buf, "r"); | |
632 | if (f) { | |
633 | snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name); | |
634 | fclose(f); | |
635 | break; | |
636 | } | |
637 | buf[0] = '\0'; | |
638 | } | |
639 | closedir(dp); | |
640 | if (buf[0] == '\0') { | |
641 | printf("Unknown host!\n"); | |
642 | return -1; | |
643 | } | |
644 | ||
645 | return 0; | |
646 | } | |
647 | ||
648 | uint64_t kvmppc_get_clockfreq(void) | |
649 | { | |
650 | char buf[512]; | |
651 | uint32_t tb[2]; | |
652 | FILE *f; | |
653 | int len; | |
654 | ||
655 | if (kvmppc_find_cpu_dt(buf, sizeof(buf))) { | |
656 | return 0; | |
657 | } | |
658 | ||
659 | strncat(buf, "/clock-frequency", sizeof(buf) - strlen(buf)); | |
660 | ||
661 | f = fopen(buf, "rb"); | |
662 | if (!f) { | |
663 | return -1; | |
664 | } | |
665 | ||
666 | len = fread(tb, sizeof(tb[0]), 2, f); | |
667 | fclose(f); | |
668 | switch (len) { | |
669 | case 1: | |
670 | /* freq is only a single cell */ | |
671 | return tb[0]; | |
672 | case 2: | |
673 | return *(uint64_t*)tb; | |
674 | } | |
675 | ||
676 | return 0; | |
677 | } | |
678 | ||
45024f09 AG |
679 | int kvmppc_get_hypercall(CPUState *env, uint8_t *buf, int buf_len) |
680 | { | |
681 | uint32_t *hc = (uint32_t*)buf; | |
682 | ||
45024f09 AG |
683 | struct kvm_ppc_pvinfo pvinfo; |
684 | ||
685 | if (kvm_check_extension(env->kvm_state, KVM_CAP_PPC_GET_PVINFO) && | |
686 | !kvm_vm_ioctl(env->kvm_state, KVM_PPC_GET_PVINFO, &pvinfo)) { | |
687 | memcpy(buf, pvinfo.hcall, buf_len); | |
688 | ||
689 | return 0; | |
690 | } | |
45024f09 AG |
691 | |
692 | /* | |
693 | * Fallback to always fail hypercalls: | |
694 | * | |
695 | * li r3, -1 | |
696 | * nop | |
697 | * nop | |
698 | * nop | |
699 | */ | |
700 | ||
701 | hc[0] = 0x3860ffff; | |
702 | hc[1] = 0x60000000; | |
703 | hc[2] = 0x60000000; | |
704 | hc[3] = 0x60000000; | |
705 | ||
706 | return 0; | |
707 | } | |
708 | ||
f61b4bed AG |
709 | void kvmppc_set_papr(CPUState *env) |
710 | { | |
94135e81 AG |
711 | struct kvm_enable_cap cap = {}; |
712 | struct kvm_one_reg reg = {}; | |
713 | struct kvm_sregs sregs = {}; | |
f61b4bed AG |
714 | int ret; |
715 | ||
f61b4bed AG |
716 | cap.cap = KVM_CAP_PPC_PAPR; |
717 | ret = kvm_vcpu_ioctl(env, KVM_ENABLE_CAP, &cap); | |
718 | ||
719 | if (ret) { | |
720 | goto fail; | |
721 | } | |
722 | ||
723 | /* | |
724 | * XXX We set HIOR here. It really should be a qdev property of | |
725 | * the CPU node, but we don't have CPUs converted to qdev yet. | |
726 | * | |
727 | * Once we have qdev CPUs, move HIOR to a qdev property and | |
728 | * remove this chunk. | |
729 | */ | |
94135e81 AG |
730 | reg.id = KVM_ONE_REG_PPC_HIOR; |
731 | reg.u.reg64 = env->spr[SPR_HIOR]; | |
732 | ret = kvm_vcpu_ioctl(env, KVM_SET_ONE_REG, ®); | |
733 | if (ret) { | |
734 | goto fail; | |
735 | } | |
736 | ||
737 | /* Set SDR1 so kernel space finds the HTAB */ | |
738 | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); | |
739 | if (ret) { | |
740 | goto fail; | |
741 | } | |
742 | ||
743 | sregs.u.s.sdr1 = env->spr[SPR_SDR1]; | |
744 | ||
745 | ret = kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs); | |
746 | if (ret) { | |
747 | goto fail; | |
748 | } | |
f61b4bed AG |
749 | |
750 | return; | |
751 | ||
752 | fail: | |
753 | cpu_abort(env, "This KVM version does not support PAPR\n"); | |
754 | } | |
755 | ||
e97c3636 DG |
756 | int kvmppc_smt_threads(void) |
757 | { | |
758 | return cap_ppc_smt ? cap_ppc_smt : 1; | |
759 | } | |
760 | ||
4513d923 GN |
761 | bool kvm_arch_stop_on_emulation_error(CPUState *env) |
762 | { | |
763 | return true; | |
764 | } | |
a1b87fe0 JK |
765 | |
766 | int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr) | |
767 | { | |
768 | return 1; | |
769 | } | |
770 | ||
771 | int kvm_arch_on_sigbus(int code, void *addr) | |
772 | { | |
773 | return 1; | |
774 | } |