[qemu.git] / target-ppc / kvm.c

/*
 * PowerPC implementation of KVM hooks
 *
 * Copyright IBM Corp. 2007
 * Copyright (C) 2011 Freescale Semiconductor, Inc.
 *
 * Authors:
 *  Jerone Young <jyoung5@us.ibm.com>
 *  Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
 *  Hollis Blanchard <hollisb@us.ibm.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 *
 */

#include <sys/types.h>
#include <sys/ioctl.h>
#include <sys/mman.h>

#include <linux/kvm.h>

#include "qemu-common.h"
#include "qemu-timer.h"
#include "sysemu.h"
#include "kvm.h"
#include "kvm_ppc.h"
#include "cpu.h"
#include "device_tree.h"

//#define DEBUG_KVM

#ifdef DEBUG_KVM
#define dprintf(fmt, ...) \
    do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
#else
#define dprintf(fmt, ...) \
    do { } while (0)
#endif

const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
    KVM_CAP_LAST_INFO
};

static int cap_interrupt_unset = false;
static int cap_interrupt_level = false;
static int cap_segstate;
static int cap_booke_sregs;

/* XXX We have a race condition where we actually have a level triggered
 *     interrupt, but the infrastructure can't expose that yet, so the guest
 *     takes but ignores it, goes to sleep and never gets notified that there's
 *     still an interrupt pending.
 *
 *     As a quick workaround, let's just wake up again 20 ms after we injected
 *     an interrupt. That way we can assure that we're always reinjecting
 *     interrupts in case the guest swallowed them.
 */
static QEMUTimer *idle_timer;

static void kvm_kick_env(void *env)
{
    qemu_cpu_kick(env);
}

int kvm_arch_init(KVMState *s)
{
#ifdef KVM_CAP_PPC_UNSET_IRQ
    cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);
#endif
#ifdef KVM_CAP_PPC_IRQ_LEVEL
    cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL);
#endif
#ifdef KVM_CAP_PPC_SEGSTATE
    cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE);
#endif
#ifdef KVM_CAP_PPC_BOOKE_SREGS
    cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS);
#endif

    if (!cap_interrupt_level) {
        fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the "
                        "VM to stall at times!\n");
    }

    return 0;
}

static int kvm_arch_sync_sregs(CPUState *cenv)
{
    struct kvm_sregs sregs;
    int ret;

    if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
        /* What we're really trying to say is "if we're on BookE, we use
           the native PVR for now". This is the only sane way to check
           it though, so we potentially confuse users that they can run
           BookE guests on BookS. Let's hope nobody dares enough :) */
        return 0;
    } else {
        if (!cap_segstate) {
            fprintf(stderr, "kvm error: missing PVR setting capability\n");
            return -ENOSYS;
        }
    }

#if !defined(CONFIG_KVM_PPC_PVR)
    if (1) {
        fprintf(stderr, "kvm error: missing PVR setting capability\n");
        return -ENOSYS;
    }
#endif

    ret = kvm_vcpu_ioctl(cenv, KVM_GET_SREGS, &sregs);
    if (ret) {
        return ret;
    }

#ifdef CONFIG_KVM_PPC_PVR
    sregs.pvr = cenv->spr[SPR_PVR];
#endif
    return kvm_vcpu_ioctl(cenv, KVM_SET_SREGS, &sregs);
}

int kvm_arch_init_vcpu(CPUState *cenv)
{
    int ret;

    ret = kvm_arch_sync_sregs(cenv);
    if (ret) {
        return ret;
    }

    idle_timer = qemu_new_timer_ns(vm_clock, kvm_kick_env, cenv);

    return ret;
}

void kvm_arch_reset_vcpu(CPUState *env)
{
}

int kvm_arch_put_registers(CPUState *env, int level)
{
    struct kvm_regs regs;
    int ret;
    int i;

    ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
    if (ret < 0)
        return ret;

    regs.ctr = env->ctr;
    regs.lr  = env->lr;
    regs.xer = env->xer;
    regs.msr = env->msr;
    regs.pc = env->nip;

    regs.srr0 = env->spr[SPR_SRR0];
    regs.srr1 = env->spr[SPR_SRR1];

    regs.sprg0 = env->spr[SPR_SPRG0];
    regs.sprg1 = env->spr[SPR_SPRG1];
    regs.sprg2 = env->spr[SPR_SPRG2];
    regs.sprg3 = env->spr[SPR_SPRG3];
    regs.sprg4 = env->spr[SPR_SPRG4];
    regs.sprg5 = env->spr[SPR_SPRG5];
    regs.sprg6 = env->spr[SPR_SPRG6];
    regs.sprg7 = env->spr[SPR_SPRG7];

    regs.pid = env->spr[SPR_BOOKE_PID];

    for (i = 0;i < 32; i++)
        regs.gpr[i] = env->gpr[i];

    ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
    if (ret < 0)
        return ret;

    return ret;
}

int kvm_arch_get_registers(CPUState *env)
{
    struct kvm_regs regs;
    struct kvm_sregs sregs;
    uint32_t cr;
    int i, ret;

    ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
    if (ret < 0)
        return ret;

    cr = regs.cr;
    for (i = 7; i >= 0; i--) {
        env->crf[i] = cr & 15;
        cr >>= 4;
    }

    env->ctr = regs.ctr;
    env->lr = regs.lr;
    env->xer = regs.xer;
    env->msr = regs.msr;
    env->nip = regs.pc;

    env->spr[SPR_SRR0] = regs.srr0;
    env->spr[SPR_SRR1] = regs.srr1;

    env->spr[SPR_SPRG0] = regs.sprg0;
    env->spr[SPR_SPRG1] = regs.sprg1;
    env->spr[SPR_SPRG2] = regs.sprg2;
    env->spr[SPR_SPRG3] = regs.sprg3;
    env->spr[SPR_SPRG4] = regs.sprg4;
    env->spr[SPR_SPRG5] = regs.sprg5;
    env->spr[SPR_SPRG6] = regs.sprg6;
    env->spr[SPR_SPRG7] = regs.sprg7;

    env->spr[SPR_BOOKE_PID] = regs.pid;

    for (i = 0;i < 32; i++)
        env->gpr[i] = regs.gpr[i];

    if (cap_booke_sregs) {
        ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
        if (ret < 0) {
            return ret;
        }

#ifdef KVM_CAP_PPC_BOOKE_SREGS
        if (sregs.u.e.features & KVM_SREGS_E_BASE) {
            env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;
            env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;
            env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr;
            env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear;
            env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr;
            env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr;
            env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr;
            env->spr[SPR_DECR] = sregs.u.e.dec;
            env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;
            env->spr[SPR_TBU] = sregs.u.e.tb >> 32;
            env->spr[SPR_VRSAVE] = sregs.u.e.vrsave;
        }

        if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {
            env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir;
            env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0;
            env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1;
            env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar;
            env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr;
        }

        if (sregs.u.e.features & KVM_SREGS_E_64) {
            env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr;
        }

        if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {
            env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8;
        }

        if (sregs.u.e.features & KVM_SREGS_E_IVOR) {
            env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];
            env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];
            env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];
            env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];
            env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];
            env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];
            env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];
            env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];
            env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];
            env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];
            env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];
            env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];
            env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];
            env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];
            env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];
            env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];

            if (sregs.u.e.features & KVM_SREGS_E_SPE) {
                env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];
                env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];
                env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];
            }

            if (sregs.u.e.features & KVM_SREGS_E_PM) {
                env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];
            }

            if (sregs.u.e.features & KVM_SREGS_E_PC) {
                env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];
                env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];
            }
        }

        if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {
            env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0;
            env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1;
            env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2;
            env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;
            env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4;
            env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6;
            env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;
            env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg;
            env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];
            env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];
        }

        if (sregs.u.e.features & KVM_SREGS_EXP) {
            env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr;
        }

        if (sregs.u.e.features & KVM_SREGS_E_PD) {
            env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc;
            env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc;
        }

        if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {
            env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr;
            env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar;
            env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0;

            if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {
                env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1;
                env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;
            }
        }
#endif
    }

    if (cap_segstate) {
        ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
        if (ret < 0) {
            return ret;
        }

#ifdef KVM_CAP_PPC_SEGSTATE
        ppc_store_sdr1(env, sregs.u.s.sdr1);

        /* Sync SLB */
#ifdef TARGET_PPC64
        for (i = 0; i < 64; i++) {
            ppc_store_slb(env, sregs.u.s.ppc64.slb[i].slbe,
                               sregs.u.s.ppc64.slb[i].slbv);
        }
#endif

        /* Sync SRs */
        for (i = 0; i < 16; i++) {
            env->sr[i] = sregs.u.s.ppc32.sr[i];
        }

        /* Sync BATs */
        for (i = 0; i < 8; i++) {
            env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;
            env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;
            env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;
            env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;
        }
#endif
    }

    return 0;
}

int kvmppc_set_interrupt(CPUState *env, int irq, int level)
{
    unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;

    if (irq != PPC_INTERRUPT_EXT) {
        return 0;
    }

    if (!kvm_enabled() || !cap_interrupt_unset || !cap_interrupt_level) {
        return 0;
    }

    kvm_vcpu_ioctl(env, KVM_INTERRUPT, &virq);

    return 0;
}

#if defined(TARGET_PPCEMB)
#define PPC_INPUT_INT PPC40x_INPUT_INT
#elif defined(TARGET_PPC64)
#define PPC_INPUT_INT PPC970_INPUT_INT
#else
#define PPC_INPUT_INT PPC6xx_INPUT_INT
#endif

void kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
{
    int r;
    unsigned irq;

    /* PowerPC Qemu tracks the various core input pins (interrupt, critical
     * interrupt, reset, etc) in PPC-specific env->irq_input_state. */
    if (!cap_interrupt_level &&
        run->ready_for_interrupt_injection &&
        (env->interrupt_request & CPU_INTERRUPT_HARD) &&
        (env->irq_input_state & (1<<PPC_INPUT_INT)))
    {
        /* For now KVM disregards the 'irq' argument. However, in the
         * future KVM could cache it in-kernel to avoid a heavyweight exit
         * when reading the UIC.
         */
        irq = KVM_INTERRUPT_SET;

        dprintf("injected interrupt %d\n", irq);
        r = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &irq);
        if (r < 0)
            printf("cpu %d fail inject %x\n", env->cpu_index, irq);

        /* Always wake up soon in case the interrupt was level based */
        qemu_mod_timer(idle_timer, qemu_get_clock_ns(vm_clock) +
                       (get_ticks_per_sec() / 50));
    }

    /* We don't know if there are more interrupts pending after this. However,
     * the guest will return to userspace in the course of handling this one
     * anyways, so we will get a chance to deliver the rest. */
}

void kvm_arch_post_run(CPUState *env, struct kvm_run *run)
{
}

int kvm_arch_process_async_events(CPUState *env)
{
    return 0;
}

static int kvmppc_handle_halt(CPUState *env)
{
    if (!(env->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
        env->halted = 1;
        env->exception_index = EXCP_HLT;
    }

    return 0;
}

/* map dcr access to existing qemu dcr emulation */
static int kvmppc_handle_dcr_read(CPUState *env, uint32_t dcrn, uint32_t *data)
{
    if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0)
        fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);

    return 0;
}

static int kvmppc_handle_dcr_write(CPUState *env, uint32_t dcrn, uint32_t data)
{
    if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0)
        fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);

    return 0;
}

int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
{
    int ret;

    switch (run->exit_reason) {
    case KVM_EXIT_DCR:
        if (run->dcr.is_write) {
            dprintf("handle dcr write\n");
            ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data);
        } else {
            dprintf("handle dcr read\n");
            ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data);
        }
        break;
    case KVM_EXIT_HLT:
        dprintf("handle halt\n");
        ret = kvmppc_handle_halt(env);
        break;
    default:
        fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
        ret = -1;
        break;
    }

    return ret;
}

static int read_cpuinfo(const char *field, char *value, int len)
{
    FILE *f;
    int ret = -1;
    int field_len = strlen(field);
    char line[512];

    f = fopen("/proc/cpuinfo", "r");
    if (!f) {
        return -1;
    }

    do {
        if(!fgets(line, sizeof(line), f)) {
            break;
        }
        if (!strncmp(line, field, field_len)) {
            strncpy(value, line, len);
            ret = 0;
            break;
        }
    } while(*line);

    fclose(f);

    return ret;
}

uint32_t kvmppc_get_tbfreq(void)
{
    char line[512];
    char *ns;
    uint32_t retval = get_ticks_per_sec();

    if (read_cpuinfo("timebase", line, sizeof(line))) {
        return retval;
    }

    if (!(ns = strchr(line, ':'))) {
        return retval;
    }

    ns++;

    retval = atoi(ns);
    return retval;
}

int kvmppc_get_hypercall(CPUState *env, uint8_t *buf, int buf_len)
{
    uint32_t *hc = (uint32_t*)buf;

#ifdef KVM_CAP_PPC_GET_PVINFO
    struct kvm_ppc_pvinfo pvinfo;

    if (kvm_check_extension(env->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
        !kvm_vm_ioctl(env->kvm_state, KVM_PPC_GET_PVINFO, &pvinfo)) {
        memcpy(buf, pvinfo.hcall, buf_len);

        return 0;
    }
#endif

    /*
     * Fallback to always fail hypercalls:
     *
     *     li r3, -1
     *     nop
     *     nop
     *     nop
     */

    hc[0] = 0x3860ffff;
    hc[1] = 0x60000000;
    hc[2] = 0x60000000;
    hc[3] = 0x60000000;

    return 0;
}

bool kvm_arch_stop_on_emulation_error(CPUState *env)
{
    return true;
}

int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr)
{
    return 1;
}

int kvm_arch_on_sigbus(int code, void *addr)
{
    return 1;
}
Commit	Line	Data
d76d1650 AJ	1	/*
	2	* PowerPC implementation of KVM hooks
	3	*
	4	* Copyright IBM Corp. 2007
90dc8812	5	* Copyright (C) 2011 Freescale Semiconductor, Inc.
d76d1650 AJ	6	*
	7	* Authors:
	8	* Jerone Young <jyoung5@us.ibm.com>
	9	* Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
	10	* Hollis Blanchard <hollisb@us.ibm.com>
	11	*
	12	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	13	* See the COPYING file in the top-level directory.
	14	*
	15	*/
	16
	17	#include <sys/types.h>
	18	#include <sys/ioctl.h>
	19	#include <sys/mman.h>
	20
	21	#include <linux/kvm.h>
	22
	23	#include "qemu-common.h"
	24	#include "qemu-timer.h"
	25	#include "sysemu.h"
	26	#include "kvm.h"
	27	#include "kvm_ppc.h"
	28	#include "cpu.h"
	29	#include "device_tree.h"
	30
	31	//#define DEBUG_KVM
	32
	33	#ifdef DEBUG_KVM
	34	#define dprintf(fmt, ...) \
	35	do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
	36	#else
	37	#define dprintf(fmt, ...) \
	38	do { } while (0)
	39	#endif
	40
94a8d39a JK	41	const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
	42	KVM_CAP_LAST_INFO
	43	};
	44
fc87e185 AG	45	static int cap_interrupt_unset = false;
fc87e185 AG	46	static int cap_interrupt_level = false;
90dc8812	47	static int cap_segstate;
90dc8812	48	static int cap_booke_sregs;
fc87e185	49
c821c2bd AG	50	/* XXX We have a race condition where we actually have a level triggered
	51	* interrupt, but the infrastructure can't expose that yet, so the guest
	52	* takes but ignores it, goes to sleep and never gets notified that there's
	53	* still an interrupt pending.
c6a94ba5	54	*
c821c2bd AG	55	* As a quick workaround, let's just wake up again 20 ms after we injected
	56	* an interrupt. That way we can assure that we're always reinjecting
	57	* interrupts in case the guest swallowed them.
c6a94ba5 AG	58	*/
	59	static QEMUTimer *idle_timer;
	60
c821c2bd	61	static void kvm_kick_env(void *env)
c6a94ba5	62	{
c821c2bd	63	qemu_cpu_kick(env);
c6a94ba5 AG	64	}
c6a94ba5 AG	65
cad1e282	66	int kvm_arch_init(KVMState *s)
d76d1650	67	{
fc87e185 AG	68	#ifdef KVM_CAP_PPC_UNSET_IRQ
	69	cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);
	70	#endif
	71	#ifdef KVM_CAP_PPC_IRQ_LEVEL
	72	cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL);
	73	#endif
90dc8812 SW	74	#ifdef KVM_CAP_PPC_SEGSTATE
	75	cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE);
	76	#endif
	77	#ifdef KVM_CAP_PPC_BOOKE_SREGS
	78	cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS);
	79	#endif
fc87e185 AG	80
	81	if (!cap_interrupt_level) {
	82	fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the "
	83	"VM to stall at times!\n");
	84	}
	85
d76d1650 AJ	86	return 0;
	87	}
	88
5666ca4a	89	static int kvm_arch_sync_sregs(CPUState *cenv)
d76d1650	90	{
861bbc80	91	struct kvm_sregs sregs;
5666ca4a SW	92	int ret;
	93
	94	if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
64e07be5 AG	95	/* What we're really trying to say is "if we're on BookE, we use
	96	the native PVR for now". This is the only sane way to check
	97	it though, so we potentially confuse users that they can run
	98	BookE guests on BookS. Let's hope nobody dares enough :) */
5666ca4a SW	99	return 0;
5666ca4a SW	100	} else {
90dc8812	101	if (!cap_segstate) {
64e07be5 AG	102	fprintf(stderr, "kvm error: missing PVR setting capability\n");
64e07be5 AG	103	return -ENOSYS;
5666ca4a	104	}
5666ca4a SW	105	}
5666ca4a SW	106
64e07be5 AG	107	#if !defined(CONFIG_KVM_PPC_PVR)
	108	if (1) {
	109	fprintf(stderr, "kvm error: missing PVR setting capability\n");
	110	return -ENOSYS;
	111	}
	112	#endif
	113
5666ca4a SW	114	ret = kvm_vcpu_ioctl(cenv, KVM_GET_SREGS, &sregs);
	115	if (ret) {
	116	return ret;
	117	}
861bbc80	118
64e07be5	119	#ifdef CONFIG_KVM_PPC_PVR
861bbc80	120	sregs.pvr = cenv->spr[SPR_PVR];
64e07be5	121	#endif
5666ca4a SW	122	return kvm_vcpu_ioctl(cenv, KVM_SET_SREGS, &sregs);
	123	}
	124
	125	int kvm_arch_init_vcpu(CPUState *cenv)
	126	{
	127	int ret;
	128
	129	ret = kvm_arch_sync_sregs(cenv);
	130	if (ret) {
	131	return ret;
	132	}
861bbc80	133
74475455	134	idle_timer = qemu_new_timer_ns(vm_clock, kvm_kick_env, cenv);
c821c2bd	135
861bbc80	136	return ret;
d76d1650 AJ	137	}
d76d1650 AJ	138
caa5af0f JK	139	void kvm_arch_reset_vcpu(CPUState *env)
	140	{
	141	}
	142
ea375f9a	143	int kvm_arch_put_registers(CPUState *env, int level)
d76d1650 AJ	144	{
	145	struct kvm_regs regs;
	146	int ret;
	147	int i;
	148
	149	ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
	150	if (ret < 0)
	151	return ret;
	152
	153	regs.ctr = env->ctr;
	154	regs.lr = env->lr;
	155	regs.xer = env->xer;
	156	regs.msr = env->msr;
	157	regs.pc = env->nip;
	158
	159	regs.srr0 = env->spr[SPR_SRR0];
	160	regs.srr1 = env->spr[SPR_SRR1];
	161
	162	regs.sprg0 = env->spr[SPR_SPRG0];
	163	regs.sprg1 = env->spr[SPR_SPRG1];
	164	regs.sprg2 = env->spr[SPR_SPRG2];
	165	regs.sprg3 = env->spr[SPR_SPRG3];
	166	regs.sprg4 = env->spr[SPR_SPRG4];
	167	regs.sprg5 = env->spr[SPR_SPRG5];
	168	regs.sprg6 = env->spr[SPR_SPRG6];
	169	regs.sprg7 = env->spr[SPR_SPRG7];
	170
90dc8812 SW	171	regs.pid = env->spr[SPR_BOOKE_PID];
90dc8812 SW	172
d76d1650 AJ	173	for (i = 0;i < 32; i++)
	174	regs.gpr[i] = env->gpr[i];
	175
	176	ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
	177	if (ret < 0)
	178	return ret;
	179
	180	return ret;
	181	}
	182
	183	int kvm_arch_get_registers(CPUState *env)
	184	{
	185	struct kvm_regs regs;
ba5e5090	186	struct kvm_sregs sregs;
90dc8812	187	uint32_t cr;
138b38b6	188	int i, ret;
d76d1650 AJ	189
	190	ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
	191	if (ret < 0)
	192	return ret;
	193
90dc8812 SW	194	cr = regs.cr;
	195	for (i = 7; i >= 0; i--) {
	196	env->crf[i] = cr & 15;
	197	cr >>= 4;
	198	}
ba5e5090	199
d76d1650 AJ	200	env->ctr = regs.ctr;
	201	env->lr = regs.lr;
	202	env->xer = regs.xer;
	203	env->msr = regs.msr;
	204	env->nip = regs.pc;
	205
	206	env->spr[SPR_SRR0] = regs.srr0;
	207	env->spr[SPR_SRR1] = regs.srr1;
	208
	209	env->spr[SPR_SPRG0] = regs.sprg0;
	210	env->spr[SPR_SPRG1] = regs.sprg1;
	211	env->spr[SPR_SPRG2] = regs.sprg2;
	212	env->spr[SPR_SPRG3] = regs.sprg3;
	213	env->spr[SPR_SPRG4] = regs.sprg4;
	214	env->spr[SPR_SPRG5] = regs.sprg5;
	215	env->spr[SPR_SPRG6] = regs.sprg6;
	216	env->spr[SPR_SPRG7] = regs.sprg7;
	217
90dc8812 SW	218	env->spr[SPR_BOOKE_PID] = regs.pid;
90dc8812 SW	219
d76d1650 AJ	220	for (i = 0;i < 32; i++)
	221	env->gpr[i] = regs.gpr[i];
	222
90dc8812 SW	223	if (cap_booke_sregs) {
	224	ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
	225	if (ret < 0) {
	226	return ret;
	227	}
	228
fafc0b6a	229	#ifdef KVM_CAP_PPC_BOOKE_SREGS
90dc8812 SW	230	if (sregs.u.e.features & KVM_SREGS_E_BASE) {
	231	env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;
	232	env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;
	233	env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr;
	234	env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear;
	235	env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr;
	236	env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr;
	237	env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr;
	238	env->spr[SPR_DECR] = sregs.u.e.dec;
	239	env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;
	240	env->spr[SPR_TBU] = sregs.u.e.tb >> 32;
	241	env->spr[SPR_VRSAVE] = sregs.u.e.vrsave;
	242	}
	243
	244	if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {
	245	env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir;
	246	env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0;
	247	env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1;
	248	env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar;
	249	env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr;
	250	}
	251
	252	if (sregs.u.e.features & KVM_SREGS_E_64) {
	253	env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr;
	254	}
	255
	256	if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {
	257	env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8;
	258	}
	259
	260	if (sregs.u.e.features & KVM_SREGS_E_IVOR) {
	261	env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];
	262	env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];
	263	env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];
	264	env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];
	265	env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];
	266	env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];
	267	env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];
	268	env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];
	269	env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];
	270	env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];
	271	env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];
	272	env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];
	273	env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];
	274	env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];
	275	env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];
	276	env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];
	277
	278	if (sregs.u.e.features & KVM_SREGS_E_SPE) {
	279	env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];
	280	env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];
	281	env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];
	282	}
	283
	284	if (sregs.u.e.features & KVM_SREGS_E_PM) {
	285	env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];
	286	}
	287
	288	if (sregs.u.e.features & KVM_SREGS_E_PC) {
	289	env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];
	290	env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];
	291	}
	292	}
	293
294	if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {
295	env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0;
296	env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1;
297	env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2;
298	env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;
299	env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4;
300	env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6;
301	env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;
302	env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg;
303	env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];
304	env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];
305	}
306
307	if (sregs.u.e.features & KVM_SREGS_EXP) {
308	env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr;
309	}
310
311	if (sregs.u.e.features & KVM_SREGS_E_PD) {
312	env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc;
313	env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc;
314	}
315
316	if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {
317	env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr;
318	env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar;
319	env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0;
320
321	if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {
322	env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1;
323	env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;
324	}
325	}
90dc8812	326	#endif
fafc0b6a	327	}
90dc8812	328
90dc8812 SW	329	if (cap_segstate) {
	330	ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
	331	if (ret < 0) {
	332	return ret;
	333	}
	334
fafc0b6a	335	#ifdef KVM_CAP_PPC_SEGSTATE
bb593904	336	ppc_store_sdr1(env, sregs.u.s.sdr1);
ba5e5090 AG	337
ba5e5090 AG	338	/* Sync SLB */
82c09f2f	339	#ifdef TARGET_PPC64
ba5e5090 AG	340	for (i = 0; i < 64; i++) {
	341	ppc_store_slb(env, sregs.u.s.ppc64.slb[i].slbe,
	342	sregs.u.s.ppc64.slb[i].slbv);
	343	}
82c09f2f	344	#endif
ba5e5090 AG	345
	346	/* Sync SRs */
	347	for (i = 0; i < 16; i++) {
	348	env->sr[i] = sregs.u.s.ppc32.sr[i];
	349	}
	350
	351	/* Sync BATs */
	352	for (i = 0; i < 8; i++) {
	353	env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;
	354	env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;
	355	env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;
	356	env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;
	357	}
ba5e5090	358	#endif
fafc0b6a	359	}
ba5e5090	360
d76d1650 AJ	361	return 0;
	362	}
	363
fc87e185 AG	364	int kvmppc_set_interrupt(CPUState *env, int irq, int level)
	365	{
	366	unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
	367
	368	if (irq != PPC_INTERRUPT_EXT) {
	369	return 0;
	370	}
	371
	372	if (!kvm_enabled() \|\| !cap_interrupt_unset \|\| !cap_interrupt_level) {
	373	return 0;
	374	}
	375
	376	kvm_vcpu_ioctl(env, KVM_INTERRUPT, &virq);
	377
	378	return 0;
	379	}
	380
16415335 AG	381	#if defined(TARGET_PPCEMB)
	382	#define PPC_INPUT_INT PPC40x_INPUT_INT
	383	#elif defined(TARGET_PPC64)
	384	#define PPC_INPUT_INT PPC970_INPUT_INT
	385	#else
	386	#define PPC_INPUT_INT PPC6xx_INPUT_INT
	387	#endif
	388
bdcbd3e2	389	void kvm_arch_pre_run(CPUState env, struct kvm_run run)
d76d1650 AJ	390	{
	391	int r;
	392	unsigned irq;
	393
	394	/* PowerPC Qemu tracks the various core input pins (interrupt, critical
	395	* interrupt, reset, etc) in PPC-specific env->irq_input_state. */
fc87e185 AG	396	if (!cap_interrupt_level &&
fc87e185 AG	397	run->ready_for_interrupt_injection &&
d76d1650	398	(env->interrupt_request & CPU_INTERRUPT_HARD) &&
16415335	399	(env->irq_input_state & (1<<PPC_INPUT_INT)))
d76d1650 AJ	400	{
	401	/* For now KVM disregards the 'irq' argument. However, in the
	402	* future KVM could cache it in-kernel to avoid a heavyweight exit
	403	* when reading the UIC.
	404	*/
fc87e185	405	irq = KVM_INTERRUPT_SET;
d76d1650 AJ	406
	407	dprintf("injected interrupt %d\n", irq);
	408	r = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &irq);
	409	if (r < 0)
	410	printf("cpu %d fail inject %x\n", env->cpu_index, irq);
c821c2bd AG	411
c821c2bd AG	412	/* Always wake up soon in case the interrupt was level based */
74475455	413	qemu_mod_timer(idle_timer, qemu_get_clock_ns(vm_clock) +
c821c2bd	414	(get_ticks_per_sec() / 50));
d76d1650 AJ	415	}
	416
	417	/* We don't know if there are more interrupts pending after this. However,
	418	* the guest will return to userspace in the course of handling this one
	419	* anyways, so we will get a chance to deliver the rest. */
d76d1650 AJ	420	}
d76d1650 AJ	421
7a39fe58	422	void kvm_arch_post_run(CPUState env, struct kvm_run run)
d76d1650	423	{
d76d1650 AJ	424	}
d76d1650 AJ	425
99036865	426	int kvm_arch_process_async_events(CPUState *env)
0af691d7	427	{
bdcbd3e2	428	return 0;
0af691d7 MT	429	}
0af691d7 MT	430
d76d1650 AJ	431	static int kvmppc_handle_halt(CPUState *env)
	432	{
	433	if (!(env->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
	434	env->halted = 1;
	435	env->exception_index = EXCP_HLT;
	436	}
	437
bb4ea393	438	return 0;
d76d1650 AJ	439	}
	440
	441	/* map dcr access to existing qemu dcr emulation */
	442	static int kvmppc_handle_dcr_read(CPUState env, uint32_t dcrn, uint32_t data)
	443	{
	444	if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0)
	445	fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
	446
bb4ea393	447	return 0;
d76d1650 AJ	448	}
	449
	450	static int kvmppc_handle_dcr_write(CPUState *env, uint32_t dcrn, uint32_t data)
	451	{
	452	if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0)
	453	fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
	454
bb4ea393	455	return 0;
d76d1650 AJ	456	}
	457
	458	int kvm_arch_handle_exit(CPUState env, struct kvm_run run)
	459	{
bb4ea393	460	int ret;
d76d1650 AJ	461
	462	switch (run->exit_reason) {
	463	case KVM_EXIT_DCR:
	464	if (run->dcr.is_write) {
	465	dprintf("handle dcr write\n");
	466	ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data);
	467	} else {
	468	dprintf("handle dcr read\n");
	469	ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data);
	470	}
	471	break;
	472	case KVM_EXIT_HLT:
	473	dprintf("handle halt\n");
	474	ret = kvmppc_handle_halt(env);
	475	break;
73aaec4a JK	476	default:
	477	fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
	478	ret = -1;
	479	break;
d76d1650 AJ	480	}
	481
	482	return ret;
	483	}
	484
dc333cd6 AG	485	static int read_cpuinfo(const char field, char value, int len)
	486	{
	487	FILE *f;
	488	int ret = -1;
	489	int field_len = strlen(field);
	490	char line[512];
	491
	492	f = fopen("/proc/cpuinfo", "r");
	493	if (!f) {
	494	return -1;
	495	}
	496
	497	do {
	498	if(!fgets(line, sizeof(line), f)) {
	499	break;
	500	}
	501	if (!strncmp(line, field, field_len)) {
	502	strncpy(value, line, len);
	503	ret = 0;
	504	break;
	505	}
	506	} while(*line);
	507
	508	fclose(f);
	509
	510	return ret;
	511	}
	512
	513	uint32_t kvmppc_get_tbfreq(void)
	514	{
	515	char line[512];
	516	char *ns;
	517	uint32_t retval = get_ticks_per_sec();
	518
	519	if (read_cpuinfo("timebase", line, sizeof(line))) {
	520	return retval;
	521	}
	522
	523	if (!(ns = strchr(line, ':'))) {
	524	return retval;
	525	}
	526
	527	ns++;
	528
	529	retval = atoi(ns);
	530	return retval;
	531	}
4513d923	532
45024f09 AG	533	int kvmppc_get_hypercall(CPUState env, uint8_t buf, int buf_len)
	534	{
	535	uint32_t hc = (uint32_t)buf;
	536
	537	#ifdef KVM_CAP_PPC_GET_PVINFO
	538	struct kvm_ppc_pvinfo pvinfo;
	539
	540	if (kvm_check_extension(env->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
	541	!kvm_vm_ioctl(env->kvm_state, KVM_PPC_GET_PVINFO, &pvinfo)) {
	542	memcpy(buf, pvinfo.hcall, buf_len);
	543
	544	return 0;
	545	}
	546	#endif
	547
	548	/*
	549	* Fallback to always fail hypercalls:
	550	*
	551	* li r3, -1
	552	* nop
	553	* nop
	554	* nop
	555	*/
	556
	557	hc[0] = 0x3860ffff;
	558	hc[1] = 0x60000000;
	559	hc[2] = 0x60000000;
	560	hc[3] = 0x60000000;
	561
	562	return 0;
	563	}
	564
4513d923 GN	565	bool kvm_arch_stop_on_emulation_error(CPUState *env)
	566	{
	567	return true;
	568	}
a1b87fe0 JK	569
	570	int kvm_arch_on_sigbus_vcpu(CPUState env, int code, void addr)
	571	{
	572	return 1;
	573	}
	574
	575	int kvm_arch_on_sigbus(int code, void *addr)
	576	{
	577	return 1;
	578	}