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Commit | Line | Data |
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d76d1650 AJ |
1 | /* |
2 | * PowerPC implementation of KVM hooks | |
3 | * | |
4 | * Copyright IBM Corp. 2007 | |
90dc8812 | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
d76d1650 AJ |
6 | * |
7 | * Authors: | |
8 | * Jerone Young <jyoung5@us.ibm.com> | |
9 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> | |
10 | * Hollis Blanchard <hollisb@us.ibm.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
13 | * See the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
16 | ||
eadaada1 | 17 | #include <dirent.h> |
d76d1650 AJ |
18 | #include <sys/types.h> |
19 | #include <sys/ioctl.h> | |
20 | #include <sys/mman.h> | |
21 | ||
22 | #include <linux/kvm.h> | |
23 | ||
24 | #include "qemu-common.h" | |
25 | #include "qemu-timer.h" | |
26 | #include "sysemu.h" | |
27 | #include "kvm.h" | |
28 | #include "kvm_ppc.h" | |
29 | #include "cpu.h" | |
30 | #include "device_tree.h" | |
31 | ||
32 | //#define DEBUG_KVM | |
33 | ||
34 | #ifdef DEBUG_KVM | |
35 | #define dprintf(fmt, ...) \ | |
36 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) | |
37 | #else | |
38 | #define dprintf(fmt, ...) \ | |
39 | do { } while (0) | |
40 | #endif | |
41 | ||
eadaada1 AG |
42 | #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/" |
43 | ||
94a8d39a JK |
44 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { |
45 | KVM_CAP_LAST_INFO | |
46 | }; | |
47 | ||
fc87e185 AG |
48 | static int cap_interrupt_unset = false; |
49 | static int cap_interrupt_level = false; | |
90dc8812 | 50 | static int cap_segstate; |
90dc8812 | 51 | static int cap_booke_sregs; |
fc87e185 | 52 | |
c821c2bd AG |
53 | /* XXX We have a race condition where we actually have a level triggered |
54 | * interrupt, but the infrastructure can't expose that yet, so the guest | |
55 | * takes but ignores it, goes to sleep and never gets notified that there's | |
56 | * still an interrupt pending. | |
c6a94ba5 | 57 | * |
c821c2bd AG |
58 | * As a quick workaround, let's just wake up again 20 ms after we injected |
59 | * an interrupt. That way we can assure that we're always reinjecting | |
60 | * interrupts in case the guest swallowed them. | |
c6a94ba5 AG |
61 | */ |
62 | static QEMUTimer *idle_timer; | |
63 | ||
c821c2bd | 64 | static void kvm_kick_env(void *env) |
c6a94ba5 | 65 | { |
c821c2bd | 66 | qemu_cpu_kick(env); |
c6a94ba5 AG |
67 | } |
68 | ||
cad1e282 | 69 | int kvm_arch_init(KVMState *s) |
d76d1650 | 70 | { |
fc87e185 | 71 | cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ); |
fc87e185 | 72 | cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL); |
90dc8812 | 73 | cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE); |
90dc8812 | 74 | cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS); |
fc87e185 AG |
75 | |
76 | if (!cap_interrupt_level) { | |
77 | fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the " | |
78 | "VM to stall at times!\n"); | |
79 | } | |
80 | ||
d76d1650 AJ |
81 | return 0; |
82 | } | |
83 | ||
5666ca4a | 84 | static int kvm_arch_sync_sregs(CPUState *cenv) |
d76d1650 | 85 | { |
861bbc80 | 86 | struct kvm_sregs sregs; |
5666ca4a SW |
87 | int ret; |
88 | ||
89 | if (cenv->excp_model == POWERPC_EXCP_BOOKE) { | |
64e07be5 AG |
90 | /* What we're really trying to say is "if we're on BookE, we use |
91 | the native PVR for now". This is the only sane way to check | |
92 | it though, so we potentially confuse users that they can run | |
93 | BookE guests on BookS. Let's hope nobody dares enough :) */ | |
5666ca4a SW |
94 | return 0; |
95 | } else { | |
90dc8812 | 96 | if (!cap_segstate) { |
64e07be5 AG |
97 | fprintf(stderr, "kvm error: missing PVR setting capability\n"); |
98 | return -ENOSYS; | |
5666ca4a | 99 | } |
5666ca4a SW |
100 | } |
101 | ||
102 | ret = kvm_vcpu_ioctl(cenv, KVM_GET_SREGS, &sregs); | |
103 | if (ret) { | |
104 | return ret; | |
105 | } | |
861bbc80 AG |
106 | |
107 | sregs.pvr = cenv->spr[SPR_PVR]; | |
5666ca4a SW |
108 | return kvm_vcpu_ioctl(cenv, KVM_SET_SREGS, &sregs); |
109 | } | |
110 | ||
111 | int kvm_arch_init_vcpu(CPUState *cenv) | |
112 | { | |
113 | int ret; | |
114 | ||
115 | ret = kvm_arch_sync_sregs(cenv); | |
116 | if (ret) { | |
117 | return ret; | |
118 | } | |
861bbc80 | 119 | |
74475455 | 120 | idle_timer = qemu_new_timer_ns(vm_clock, kvm_kick_env, cenv); |
c821c2bd | 121 | |
861bbc80 | 122 | return ret; |
d76d1650 AJ |
123 | } |
124 | ||
caa5af0f JK |
125 | void kvm_arch_reset_vcpu(CPUState *env) |
126 | { | |
127 | } | |
128 | ||
ea375f9a | 129 | int kvm_arch_put_registers(CPUState *env, int level) |
d76d1650 AJ |
130 | { |
131 | struct kvm_regs regs; | |
132 | int ret; | |
133 | int i; | |
134 | ||
135 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); | |
136 | if (ret < 0) | |
137 | return ret; | |
138 | ||
139 | regs.ctr = env->ctr; | |
140 | regs.lr = env->lr; | |
141 | regs.xer = env->xer; | |
142 | regs.msr = env->msr; | |
143 | regs.pc = env->nip; | |
144 | ||
145 | regs.srr0 = env->spr[SPR_SRR0]; | |
146 | regs.srr1 = env->spr[SPR_SRR1]; | |
147 | ||
148 | regs.sprg0 = env->spr[SPR_SPRG0]; | |
149 | regs.sprg1 = env->spr[SPR_SPRG1]; | |
150 | regs.sprg2 = env->spr[SPR_SPRG2]; | |
151 | regs.sprg3 = env->spr[SPR_SPRG3]; | |
152 | regs.sprg4 = env->spr[SPR_SPRG4]; | |
153 | regs.sprg5 = env->spr[SPR_SPRG5]; | |
154 | regs.sprg6 = env->spr[SPR_SPRG6]; | |
155 | regs.sprg7 = env->spr[SPR_SPRG7]; | |
156 | ||
90dc8812 SW |
157 | regs.pid = env->spr[SPR_BOOKE_PID]; |
158 | ||
d76d1650 AJ |
159 | for (i = 0;i < 32; i++) |
160 | regs.gpr[i] = env->gpr[i]; | |
161 | ||
162 | ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); | |
163 | if (ret < 0) | |
164 | return ret; | |
165 | ||
166 | return ret; | |
167 | } | |
168 | ||
169 | int kvm_arch_get_registers(CPUState *env) | |
170 | { | |
171 | struct kvm_regs regs; | |
ba5e5090 | 172 | struct kvm_sregs sregs; |
90dc8812 | 173 | uint32_t cr; |
138b38b6 | 174 | int i, ret; |
d76d1650 AJ |
175 | |
176 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); | |
177 | if (ret < 0) | |
178 | return ret; | |
179 | ||
90dc8812 SW |
180 | cr = regs.cr; |
181 | for (i = 7; i >= 0; i--) { | |
182 | env->crf[i] = cr & 15; | |
183 | cr >>= 4; | |
184 | } | |
ba5e5090 | 185 | |
d76d1650 AJ |
186 | env->ctr = regs.ctr; |
187 | env->lr = regs.lr; | |
188 | env->xer = regs.xer; | |
189 | env->msr = regs.msr; | |
190 | env->nip = regs.pc; | |
191 | ||
192 | env->spr[SPR_SRR0] = regs.srr0; | |
193 | env->spr[SPR_SRR1] = regs.srr1; | |
194 | ||
195 | env->spr[SPR_SPRG0] = regs.sprg0; | |
196 | env->spr[SPR_SPRG1] = regs.sprg1; | |
197 | env->spr[SPR_SPRG2] = regs.sprg2; | |
198 | env->spr[SPR_SPRG3] = regs.sprg3; | |
199 | env->spr[SPR_SPRG4] = regs.sprg4; | |
200 | env->spr[SPR_SPRG5] = regs.sprg5; | |
201 | env->spr[SPR_SPRG6] = regs.sprg6; | |
202 | env->spr[SPR_SPRG7] = regs.sprg7; | |
203 | ||
90dc8812 SW |
204 | env->spr[SPR_BOOKE_PID] = regs.pid; |
205 | ||
d76d1650 AJ |
206 | for (i = 0;i < 32; i++) |
207 | env->gpr[i] = regs.gpr[i]; | |
208 | ||
90dc8812 SW |
209 | if (cap_booke_sregs) { |
210 | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); | |
211 | if (ret < 0) { | |
212 | return ret; | |
213 | } | |
214 | ||
215 | if (sregs.u.e.features & KVM_SREGS_E_BASE) { | |
216 | env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0; | |
217 | env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1; | |
218 | env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr; | |
219 | env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear; | |
220 | env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr; | |
221 | env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr; | |
222 | env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr; | |
223 | env->spr[SPR_DECR] = sregs.u.e.dec; | |
224 | env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff; | |
225 | env->spr[SPR_TBU] = sregs.u.e.tb >> 32; | |
226 | env->spr[SPR_VRSAVE] = sregs.u.e.vrsave; | |
227 | } | |
228 | ||
229 | if (sregs.u.e.features & KVM_SREGS_E_ARCH206) { | |
230 | env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir; | |
231 | env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0; | |
232 | env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1; | |
233 | env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar; | |
234 | env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr; | |
235 | } | |
236 | ||
237 | if (sregs.u.e.features & KVM_SREGS_E_64) { | |
238 | env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr; | |
239 | } | |
240 | ||
241 | if (sregs.u.e.features & KVM_SREGS_E_SPRG8) { | |
242 | env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8; | |
243 | } | |
244 | ||
245 | if (sregs.u.e.features & KVM_SREGS_E_IVOR) { | |
246 | env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0]; | |
247 | env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1]; | |
248 | env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2]; | |
249 | env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3]; | |
250 | env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4]; | |
251 | env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5]; | |
252 | env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6]; | |
253 | env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7]; | |
254 | env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8]; | |
255 | env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9]; | |
256 | env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10]; | |
257 | env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11]; | |
258 | env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12]; | |
259 | env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13]; | |
260 | env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14]; | |
261 | env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15]; | |
262 | ||
263 | if (sregs.u.e.features & KVM_SREGS_E_SPE) { | |
264 | env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0]; | |
265 | env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1]; | |
266 | env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2]; | |
267 | } | |
268 | ||
269 | if (sregs.u.e.features & KVM_SREGS_E_PM) { | |
270 | env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3]; | |
271 | } | |
272 | ||
273 | if (sregs.u.e.features & KVM_SREGS_E_PC) { | |
274 | env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4]; | |
275 | env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5]; | |
276 | } | |
277 | } | |
278 | ||
279 | if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) { | |
280 | env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0; | |
281 | env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1; | |
282 | env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2; | |
283 | env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff; | |
284 | env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4; | |
285 | env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6; | |
286 | env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32; | |
287 | env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg; | |
288 | env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0]; | |
289 | env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1]; | |
290 | } | |
291 | ||
292 | if (sregs.u.e.features & KVM_SREGS_EXP) { | |
293 | env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr; | |
294 | } | |
295 | ||
296 | if (sregs.u.e.features & KVM_SREGS_E_PD) { | |
297 | env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc; | |
298 | env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc; | |
299 | } | |
300 | ||
301 | if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) { | |
302 | env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr; | |
303 | env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar; | |
304 | env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0; | |
305 | ||
306 | if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) { | |
307 | env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1; | |
308 | env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2; | |
309 | } | |
310 | } | |
fafc0b6a | 311 | } |
90dc8812 | 312 | |
90dc8812 SW |
313 | if (cap_segstate) { |
314 | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); | |
315 | if (ret < 0) { | |
316 | return ret; | |
317 | } | |
318 | ||
bb593904 | 319 | ppc_store_sdr1(env, sregs.u.s.sdr1); |
ba5e5090 AG |
320 | |
321 | /* Sync SLB */ | |
82c09f2f | 322 | #ifdef TARGET_PPC64 |
ba5e5090 AG |
323 | for (i = 0; i < 64; i++) { |
324 | ppc_store_slb(env, sregs.u.s.ppc64.slb[i].slbe, | |
325 | sregs.u.s.ppc64.slb[i].slbv); | |
326 | } | |
82c09f2f | 327 | #endif |
ba5e5090 AG |
328 | |
329 | /* Sync SRs */ | |
330 | for (i = 0; i < 16; i++) { | |
331 | env->sr[i] = sregs.u.s.ppc32.sr[i]; | |
332 | } | |
333 | ||
334 | /* Sync BATs */ | |
335 | for (i = 0; i < 8; i++) { | |
336 | env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff; | |
337 | env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32; | |
338 | env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff; | |
339 | env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32; | |
340 | } | |
fafc0b6a | 341 | } |
ba5e5090 | 342 | |
d76d1650 AJ |
343 | return 0; |
344 | } | |
345 | ||
fc87e185 AG |
346 | int kvmppc_set_interrupt(CPUState *env, int irq, int level) |
347 | { | |
348 | unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET; | |
349 | ||
350 | if (irq != PPC_INTERRUPT_EXT) { | |
351 | return 0; | |
352 | } | |
353 | ||
354 | if (!kvm_enabled() || !cap_interrupt_unset || !cap_interrupt_level) { | |
355 | return 0; | |
356 | } | |
357 | ||
358 | kvm_vcpu_ioctl(env, KVM_INTERRUPT, &virq); | |
359 | ||
360 | return 0; | |
361 | } | |
362 | ||
16415335 AG |
363 | #if defined(TARGET_PPCEMB) |
364 | #define PPC_INPUT_INT PPC40x_INPUT_INT | |
365 | #elif defined(TARGET_PPC64) | |
366 | #define PPC_INPUT_INT PPC970_INPUT_INT | |
367 | #else | |
368 | #define PPC_INPUT_INT PPC6xx_INPUT_INT | |
369 | #endif | |
370 | ||
bdcbd3e2 | 371 | void kvm_arch_pre_run(CPUState *env, struct kvm_run *run) |
d76d1650 AJ |
372 | { |
373 | int r; | |
374 | unsigned irq; | |
375 | ||
376 | /* PowerPC Qemu tracks the various core input pins (interrupt, critical | |
377 | * interrupt, reset, etc) in PPC-specific env->irq_input_state. */ | |
fc87e185 AG |
378 | if (!cap_interrupt_level && |
379 | run->ready_for_interrupt_injection && | |
d76d1650 | 380 | (env->interrupt_request & CPU_INTERRUPT_HARD) && |
16415335 | 381 | (env->irq_input_state & (1<<PPC_INPUT_INT))) |
d76d1650 AJ |
382 | { |
383 | /* For now KVM disregards the 'irq' argument. However, in the | |
384 | * future KVM could cache it in-kernel to avoid a heavyweight exit | |
385 | * when reading the UIC. | |
386 | */ | |
fc87e185 | 387 | irq = KVM_INTERRUPT_SET; |
d76d1650 AJ |
388 | |
389 | dprintf("injected interrupt %d\n", irq); | |
390 | r = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &irq); | |
391 | if (r < 0) | |
392 | printf("cpu %d fail inject %x\n", env->cpu_index, irq); | |
c821c2bd AG |
393 | |
394 | /* Always wake up soon in case the interrupt was level based */ | |
74475455 | 395 | qemu_mod_timer(idle_timer, qemu_get_clock_ns(vm_clock) + |
c821c2bd | 396 | (get_ticks_per_sec() / 50)); |
d76d1650 AJ |
397 | } |
398 | ||
399 | /* We don't know if there are more interrupts pending after this. However, | |
400 | * the guest will return to userspace in the course of handling this one | |
401 | * anyways, so we will get a chance to deliver the rest. */ | |
d76d1650 AJ |
402 | } |
403 | ||
7a39fe58 | 404 | void kvm_arch_post_run(CPUState *env, struct kvm_run *run) |
d76d1650 | 405 | { |
d76d1650 AJ |
406 | } |
407 | ||
99036865 | 408 | int kvm_arch_process_async_events(CPUState *env) |
0af691d7 | 409 | { |
bdcbd3e2 | 410 | return 0; |
0af691d7 MT |
411 | } |
412 | ||
d76d1650 AJ |
413 | static int kvmppc_handle_halt(CPUState *env) |
414 | { | |
415 | if (!(env->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) { | |
416 | env->halted = 1; | |
417 | env->exception_index = EXCP_HLT; | |
418 | } | |
419 | ||
bb4ea393 | 420 | return 0; |
d76d1650 AJ |
421 | } |
422 | ||
423 | /* map dcr access to existing qemu dcr emulation */ | |
424 | static int kvmppc_handle_dcr_read(CPUState *env, uint32_t dcrn, uint32_t *data) | |
425 | { | |
426 | if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) | |
427 | fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn); | |
428 | ||
bb4ea393 | 429 | return 0; |
d76d1650 AJ |
430 | } |
431 | ||
432 | static int kvmppc_handle_dcr_write(CPUState *env, uint32_t dcrn, uint32_t data) | |
433 | { | |
434 | if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) | |
435 | fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn); | |
436 | ||
bb4ea393 | 437 | return 0; |
d76d1650 AJ |
438 | } |
439 | ||
440 | int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) | |
441 | { | |
bb4ea393 | 442 | int ret; |
d76d1650 AJ |
443 | |
444 | switch (run->exit_reason) { | |
445 | case KVM_EXIT_DCR: | |
446 | if (run->dcr.is_write) { | |
447 | dprintf("handle dcr write\n"); | |
448 | ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data); | |
449 | } else { | |
450 | dprintf("handle dcr read\n"); | |
451 | ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data); | |
452 | } | |
453 | break; | |
454 | case KVM_EXIT_HLT: | |
455 | dprintf("handle halt\n"); | |
456 | ret = kvmppc_handle_halt(env); | |
457 | break; | |
73aaec4a JK |
458 | default: |
459 | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); | |
460 | ret = -1; | |
461 | break; | |
d76d1650 AJ |
462 | } |
463 | ||
464 | return ret; | |
465 | } | |
466 | ||
dc333cd6 AG |
467 | static int read_cpuinfo(const char *field, char *value, int len) |
468 | { | |
469 | FILE *f; | |
470 | int ret = -1; | |
471 | int field_len = strlen(field); | |
472 | char line[512]; | |
473 | ||
474 | f = fopen("/proc/cpuinfo", "r"); | |
475 | if (!f) { | |
476 | return -1; | |
477 | } | |
478 | ||
479 | do { | |
480 | if(!fgets(line, sizeof(line), f)) { | |
481 | break; | |
482 | } | |
483 | if (!strncmp(line, field, field_len)) { | |
484 | strncpy(value, line, len); | |
485 | ret = 0; | |
486 | break; | |
487 | } | |
488 | } while(*line); | |
489 | ||
490 | fclose(f); | |
491 | ||
492 | return ret; | |
493 | } | |
494 | ||
495 | uint32_t kvmppc_get_tbfreq(void) | |
496 | { | |
497 | char line[512]; | |
498 | char *ns; | |
499 | uint32_t retval = get_ticks_per_sec(); | |
500 | ||
501 | if (read_cpuinfo("timebase", line, sizeof(line))) { | |
502 | return retval; | |
503 | } | |
504 | ||
505 | if (!(ns = strchr(line, ':'))) { | |
506 | return retval; | |
507 | } | |
508 | ||
509 | ns++; | |
510 | ||
511 | retval = atoi(ns); | |
512 | return retval; | |
513 | } | |
4513d923 | 514 | |
eadaada1 AG |
515 | /* Try to find a device tree node for a CPU with clock-frequency property */ |
516 | static int kvmppc_find_cpu_dt(char *buf, int buf_len) | |
517 | { | |
518 | struct dirent *dirp; | |
519 | DIR *dp; | |
520 | ||
521 | if ((dp = opendir(PROC_DEVTREE_CPU)) == NULL) { | |
522 | printf("Can't open directory " PROC_DEVTREE_CPU "\n"); | |
523 | return -1; | |
524 | } | |
525 | ||
526 | buf[0] = '\0'; | |
527 | while ((dirp = readdir(dp)) != NULL) { | |
528 | FILE *f; | |
529 | snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU, | |
530 | dirp->d_name); | |
531 | f = fopen(buf, "r"); | |
532 | if (f) { | |
533 | snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name); | |
534 | fclose(f); | |
535 | break; | |
536 | } | |
537 | buf[0] = '\0'; | |
538 | } | |
539 | closedir(dp); | |
540 | if (buf[0] == '\0') { | |
541 | printf("Unknown host!\n"); | |
542 | return -1; | |
543 | } | |
544 | ||
545 | return 0; | |
546 | } | |
547 | ||
548 | uint64_t kvmppc_get_clockfreq(void) | |
549 | { | |
550 | char buf[512]; | |
551 | uint32_t tb[2]; | |
552 | FILE *f; | |
553 | int len; | |
554 | ||
555 | if (kvmppc_find_cpu_dt(buf, sizeof(buf))) { | |
556 | return 0; | |
557 | } | |
558 | ||
559 | strncat(buf, "/clock-frequency", sizeof(buf) - strlen(buf)); | |
560 | ||
561 | f = fopen(buf, "rb"); | |
562 | if (!f) { | |
563 | return -1; | |
564 | } | |
565 | ||
566 | len = fread(tb, sizeof(tb[0]), 2, f); | |
567 | fclose(f); | |
568 | switch (len) { | |
569 | case 1: | |
570 | /* freq is only a single cell */ | |
571 | return tb[0]; | |
572 | case 2: | |
573 | return *(uint64_t*)tb; | |
574 | } | |
575 | ||
576 | return 0; | |
577 | } | |
578 | ||
45024f09 AG |
579 | int kvmppc_get_hypercall(CPUState *env, uint8_t *buf, int buf_len) |
580 | { | |
581 | uint32_t *hc = (uint32_t*)buf; | |
582 | ||
45024f09 AG |
583 | struct kvm_ppc_pvinfo pvinfo; |
584 | ||
585 | if (kvm_check_extension(env->kvm_state, KVM_CAP_PPC_GET_PVINFO) && | |
586 | !kvm_vm_ioctl(env->kvm_state, KVM_PPC_GET_PVINFO, &pvinfo)) { | |
587 | memcpy(buf, pvinfo.hcall, buf_len); | |
588 | ||
589 | return 0; | |
590 | } | |
45024f09 AG |
591 | |
592 | /* | |
593 | * Fallback to always fail hypercalls: | |
594 | * | |
595 | * li r3, -1 | |
596 | * nop | |
597 | * nop | |
598 | * nop | |
599 | */ | |
600 | ||
601 | hc[0] = 0x3860ffff; | |
602 | hc[1] = 0x60000000; | |
603 | hc[2] = 0x60000000; | |
604 | hc[3] = 0x60000000; | |
605 | ||
606 | return 0; | |
607 | } | |
608 | ||
4513d923 GN |
609 | bool kvm_arch_stop_on_emulation_error(CPUState *env) |
610 | { | |
611 | return true; | |
612 | } | |
a1b87fe0 JK |
613 | |
614 | int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr) | |
615 | { | |
616 | return 1; | |
617 | } | |
618 | ||
619 | int kvm_arch_on_sigbus(int code, void *addr) | |
620 | { | |
621 | return 1; | |
622 | } |