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Commit | Line | Data |
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d76d1650 AJ |
1 | /* |
2 | * PowerPC implementation of KVM hooks | |
3 | * | |
4 | * Copyright IBM Corp. 2007 | |
90dc8812 | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
d76d1650 AJ |
6 | * |
7 | * Authors: | |
8 | * Jerone Young <jyoung5@us.ibm.com> | |
9 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> | |
10 | * Hollis Blanchard <hollisb@us.ibm.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
13 | * See the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
16 | ||
eadaada1 | 17 | #include <dirent.h> |
d76d1650 AJ |
18 | #include <sys/types.h> |
19 | #include <sys/ioctl.h> | |
20 | #include <sys/mman.h> | |
4656e1f0 | 21 | #include <sys/vfs.h> |
d76d1650 AJ |
22 | |
23 | #include <linux/kvm.h> | |
24 | ||
25 | #include "qemu-common.h" | |
1de7afc9 | 26 | #include "qemu/timer.h" |
9c17d615 PB |
27 | #include "sysemu/sysemu.h" |
28 | #include "sysemu/kvm.h" | |
d76d1650 AJ |
29 | #include "kvm_ppc.h" |
30 | #include "cpu.h" | |
9c17d615 PB |
31 | #include "sysemu/cpus.h" |
32 | #include "sysemu/device_tree.h" | |
d5aea6f3 | 33 | #include "mmu-hash64.h" |
d76d1650 | 34 | |
f61b4bed | 35 | #include "hw/sysbus.h" |
0d09e41a PB |
36 | #include "hw/ppc/spapr.h" |
37 | #include "hw/ppc/spapr_vio.h" | |
31f2cb8f | 38 | #include "sysemu/watchdog.h" |
f61b4bed | 39 | |
d76d1650 AJ |
40 | //#define DEBUG_KVM |
41 | ||
42 | #ifdef DEBUG_KVM | |
43 | #define dprintf(fmt, ...) \ | |
44 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) | |
45 | #else | |
46 | #define dprintf(fmt, ...) \ | |
47 | do { } while (0) | |
48 | #endif | |
49 | ||
eadaada1 AG |
50 | #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/" |
51 | ||
94a8d39a JK |
52 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { |
53 | KVM_CAP_LAST_INFO | |
54 | }; | |
55 | ||
fc87e185 AG |
56 | static int cap_interrupt_unset = false; |
57 | static int cap_interrupt_level = false; | |
90dc8812 | 58 | static int cap_segstate; |
90dc8812 | 59 | static int cap_booke_sregs; |
e97c3636 | 60 | static int cap_ppc_smt; |
354ac20a | 61 | static int cap_ppc_rma; |
0f5cb298 | 62 | static int cap_spapr_tce; |
f1af19d7 | 63 | static int cap_hior; |
d67d40ea | 64 | static int cap_one_reg; |
3b961124 | 65 | static int cap_epr; |
31f2cb8f | 66 | static int cap_ppc_watchdog; |
9b00ea49 | 67 | static int cap_papr; |
e68cb8b4 | 68 | static int cap_htab_fd; |
fc87e185 | 69 | |
c821c2bd AG |
70 | /* XXX We have a race condition where we actually have a level triggered |
71 | * interrupt, but the infrastructure can't expose that yet, so the guest | |
72 | * takes but ignores it, goes to sleep and never gets notified that there's | |
73 | * still an interrupt pending. | |
c6a94ba5 | 74 | * |
c821c2bd AG |
75 | * As a quick workaround, let's just wake up again 20 ms after we injected |
76 | * an interrupt. That way we can assure that we're always reinjecting | |
77 | * interrupts in case the guest swallowed them. | |
c6a94ba5 AG |
78 | */ |
79 | static QEMUTimer *idle_timer; | |
80 | ||
d5a68146 | 81 | static void kvm_kick_cpu(void *opaque) |
c6a94ba5 | 82 | { |
d5a68146 | 83 | PowerPCCPU *cpu = opaque; |
d5a68146 | 84 | |
c08d7424 | 85 | qemu_cpu_kick(CPU(cpu)); |
c6a94ba5 AG |
86 | } |
87 | ||
5ba4576b AF |
88 | static int kvm_ppc_register_host_cpu_type(void); |
89 | ||
cad1e282 | 90 | int kvm_arch_init(KVMState *s) |
d76d1650 | 91 | { |
fc87e185 | 92 | cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ); |
fc87e185 | 93 | cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL); |
90dc8812 | 94 | cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE); |
90dc8812 | 95 | cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS); |
e97c3636 | 96 | cap_ppc_smt = kvm_check_extension(s, KVM_CAP_PPC_SMT); |
354ac20a | 97 | cap_ppc_rma = kvm_check_extension(s, KVM_CAP_PPC_RMA); |
0f5cb298 | 98 | cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE); |
d67d40ea | 99 | cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG); |
f1af19d7 | 100 | cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR); |
3b961124 | 101 | cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR); |
31f2cb8f | 102 | cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG); |
9b00ea49 DG |
103 | /* Note: we don't set cap_papr here, because this capability is |
104 | * only activated after this by kvmppc_set_papr() */ | |
e68cb8b4 | 105 | cap_htab_fd = kvm_check_extension(s, KVM_CAP_PPC_HTAB_FD); |
fc87e185 AG |
106 | |
107 | if (!cap_interrupt_level) { | |
108 | fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the " | |
109 | "VM to stall at times!\n"); | |
110 | } | |
111 | ||
5ba4576b AF |
112 | kvm_ppc_register_host_cpu_type(); |
113 | ||
d76d1650 AJ |
114 | return 0; |
115 | } | |
116 | ||
1bc22652 | 117 | static int kvm_arch_sync_sregs(PowerPCCPU *cpu) |
d76d1650 | 118 | { |
1bc22652 AF |
119 | CPUPPCState *cenv = &cpu->env; |
120 | CPUState *cs = CPU(cpu); | |
861bbc80 | 121 | struct kvm_sregs sregs; |
5666ca4a SW |
122 | int ret; |
123 | ||
124 | if (cenv->excp_model == POWERPC_EXCP_BOOKE) { | |
64e07be5 AG |
125 | /* What we're really trying to say is "if we're on BookE, we use |
126 | the native PVR for now". This is the only sane way to check | |
127 | it though, so we potentially confuse users that they can run | |
128 | BookE guests on BookS. Let's hope nobody dares enough :) */ | |
5666ca4a SW |
129 | return 0; |
130 | } else { | |
90dc8812 | 131 | if (!cap_segstate) { |
64e07be5 AG |
132 | fprintf(stderr, "kvm error: missing PVR setting capability\n"); |
133 | return -ENOSYS; | |
5666ca4a | 134 | } |
5666ca4a SW |
135 | } |
136 | ||
1bc22652 | 137 | ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs); |
5666ca4a SW |
138 | if (ret) { |
139 | return ret; | |
140 | } | |
861bbc80 AG |
141 | |
142 | sregs.pvr = cenv->spr[SPR_PVR]; | |
1bc22652 | 143 | return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs); |
5666ca4a SW |
144 | } |
145 | ||
93dd5e85 | 146 | /* Set up a shared TLB array with KVM */ |
1bc22652 | 147 | static int kvm_booke206_tlb_init(PowerPCCPU *cpu) |
93dd5e85 | 148 | { |
1bc22652 AF |
149 | CPUPPCState *env = &cpu->env; |
150 | CPUState *cs = CPU(cpu); | |
93dd5e85 SW |
151 | struct kvm_book3e_206_tlb_params params = {}; |
152 | struct kvm_config_tlb cfg = {}; | |
153 | struct kvm_enable_cap encap = {}; | |
154 | unsigned int entries = 0; | |
155 | int ret, i; | |
156 | ||
157 | if (!kvm_enabled() || | |
a60f24b5 | 158 | !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) { |
93dd5e85 SW |
159 | return 0; |
160 | } | |
161 | ||
162 | assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN); | |
163 | ||
164 | for (i = 0; i < BOOKE206_MAX_TLBN; i++) { | |
165 | params.tlb_sizes[i] = booke206_tlb_size(env, i); | |
166 | params.tlb_ways[i] = booke206_tlb_ways(env, i); | |
167 | entries += params.tlb_sizes[i]; | |
168 | } | |
169 | ||
170 | assert(entries == env->nb_tlb); | |
171 | assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t)); | |
172 | ||
173 | env->tlb_dirty = true; | |
174 | ||
175 | cfg.array = (uintptr_t)env->tlb.tlbm; | |
176 | cfg.array_len = sizeof(ppcmas_tlb_t) * entries; | |
177 | cfg.params = (uintptr_t)¶ms; | |
178 | cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV; | |
179 | ||
180 | encap.cap = KVM_CAP_SW_TLB; | |
181 | encap.args[0] = (uintptr_t)&cfg; | |
182 | ||
1bc22652 | 183 | ret = kvm_vcpu_ioctl(cs, KVM_ENABLE_CAP, &encap); |
93dd5e85 SW |
184 | if (ret < 0) { |
185 | fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n", | |
186 | __func__, strerror(-ret)); | |
187 | return ret; | |
188 | } | |
189 | ||
190 | env->kvm_sw_tlb = true; | |
191 | return 0; | |
192 | } | |
193 | ||
4656e1f0 BH |
194 | |
195 | #if defined(TARGET_PPC64) | |
a60f24b5 | 196 | static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu, |
4656e1f0 BH |
197 | struct kvm_ppc_smmu_info *info) |
198 | { | |
a60f24b5 AF |
199 | CPUPPCState *env = &cpu->env; |
200 | CPUState *cs = CPU(cpu); | |
201 | ||
4656e1f0 BH |
202 | memset(info, 0, sizeof(*info)); |
203 | ||
204 | /* We don't have the new KVM_PPC_GET_SMMU_INFO ioctl, so | |
205 | * need to "guess" what the supported page sizes are. | |
206 | * | |
207 | * For that to work we make a few assumptions: | |
208 | * | |
209 | * - If KVM_CAP_PPC_GET_PVINFO is supported we are running "PR" | |
210 | * KVM which only supports 4K and 16M pages, but supports them | |
211 | * regardless of the backing store characteritics. We also don't | |
212 | * support 1T segments. | |
213 | * | |
214 | * This is safe as if HV KVM ever supports that capability or PR | |
215 | * KVM grows supports for more page/segment sizes, those versions | |
216 | * will have implemented KVM_CAP_PPC_GET_SMMU_INFO and thus we | |
217 | * will not hit this fallback | |
218 | * | |
219 | * - Else we are running HV KVM. This means we only support page | |
220 | * sizes that fit in the backing store. Additionally we only | |
221 | * advertize 64K pages if the processor is ARCH 2.06 and we assume | |
222 | * P7 encodings for the SLB and hash table. Here too, we assume | |
223 | * support for any newer processor will mean a kernel that | |
224 | * implements KVM_CAP_PPC_GET_SMMU_INFO and thus doesn't hit | |
225 | * this fallback. | |
226 | */ | |
a60f24b5 | 227 | if (kvm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO)) { |
4656e1f0 BH |
228 | /* No flags */ |
229 | info->flags = 0; | |
230 | info->slb_size = 64; | |
231 | ||
232 | /* Standard 4k base page size segment */ | |
233 | info->sps[0].page_shift = 12; | |
234 | info->sps[0].slb_enc = 0; | |
235 | info->sps[0].enc[0].page_shift = 12; | |
236 | info->sps[0].enc[0].pte_enc = 0; | |
237 | ||
238 | /* Standard 16M large page size segment */ | |
239 | info->sps[1].page_shift = 24; | |
240 | info->sps[1].slb_enc = SLB_VSID_L; | |
241 | info->sps[1].enc[0].page_shift = 24; | |
242 | info->sps[1].enc[0].pte_enc = 0; | |
243 | } else { | |
244 | int i = 0; | |
245 | ||
246 | /* HV KVM has backing store size restrictions */ | |
247 | info->flags = KVM_PPC_PAGE_SIZES_REAL; | |
248 | ||
249 | if (env->mmu_model & POWERPC_MMU_1TSEG) { | |
250 | info->flags |= KVM_PPC_1T_SEGMENTS; | |
251 | } | |
252 | ||
253 | if (env->mmu_model == POWERPC_MMU_2_06) { | |
254 | info->slb_size = 32; | |
255 | } else { | |
256 | info->slb_size = 64; | |
257 | } | |
258 | ||
259 | /* Standard 4k base page size segment */ | |
260 | info->sps[i].page_shift = 12; | |
261 | info->sps[i].slb_enc = 0; | |
262 | info->sps[i].enc[0].page_shift = 12; | |
263 | info->sps[i].enc[0].pte_enc = 0; | |
264 | i++; | |
265 | ||
266 | /* 64K on MMU 2.06 */ | |
267 | if (env->mmu_model == POWERPC_MMU_2_06) { | |
268 | info->sps[i].page_shift = 16; | |
269 | info->sps[i].slb_enc = 0x110; | |
270 | info->sps[i].enc[0].page_shift = 16; | |
271 | info->sps[i].enc[0].pte_enc = 1; | |
272 | i++; | |
273 | } | |
274 | ||
275 | /* Standard 16M large page size segment */ | |
276 | info->sps[i].page_shift = 24; | |
277 | info->sps[i].slb_enc = SLB_VSID_L; | |
278 | info->sps[i].enc[0].page_shift = 24; | |
279 | info->sps[i].enc[0].pte_enc = 0; | |
280 | } | |
281 | } | |
282 | ||
a60f24b5 | 283 | static void kvm_get_smmu_info(PowerPCCPU *cpu, struct kvm_ppc_smmu_info *info) |
4656e1f0 | 284 | { |
a60f24b5 | 285 | CPUState *cs = CPU(cpu); |
4656e1f0 BH |
286 | int ret; |
287 | ||
a60f24b5 AF |
288 | if (kvm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) { |
289 | ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_SMMU_INFO, info); | |
4656e1f0 BH |
290 | if (ret == 0) { |
291 | return; | |
292 | } | |
293 | } | |
294 | ||
a60f24b5 | 295 | kvm_get_fallback_smmu_info(cpu, info); |
4656e1f0 BH |
296 | } |
297 | ||
298 | static long getrampagesize(void) | |
299 | { | |
300 | struct statfs fs; | |
301 | int ret; | |
302 | ||
303 | if (!mem_path) { | |
304 | /* guest RAM is backed by normal anonymous pages */ | |
305 | return getpagesize(); | |
306 | } | |
307 | ||
308 | do { | |
309 | ret = statfs(mem_path, &fs); | |
310 | } while (ret != 0 && errno == EINTR); | |
311 | ||
312 | if (ret != 0) { | |
313 | fprintf(stderr, "Couldn't statfs() memory path: %s\n", | |
314 | strerror(errno)); | |
315 | exit(1); | |
316 | } | |
317 | ||
318 | #define HUGETLBFS_MAGIC 0x958458f6 | |
319 | ||
320 | if (fs.f_type != HUGETLBFS_MAGIC) { | |
321 | /* Explicit mempath, but it's ordinary pages */ | |
322 | return getpagesize(); | |
323 | } | |
324 | ||
325 | /* It's hugepage, return the huge page size */ | |
326 | return fs.f_bsize; | |
327 | } | |
328 | ||
329 | static bool kvm_valid_page_size(uint32_t flags, long rampgsize, uint32_t shift) | |
330 | { | |
331 | if (!(flags & KVM_PPC_PAGE_SIZES_REAL)) { | |
332 | return true; | |
333 | } | |
334 | ||
335 | return (1ul << shift) <= rampgsize; | |
336 | } | |
337 | ||
a60f24b5 | 338 | static void kvm_fixup_page_sizes(PowerPCCPU *cpu) |
4656e1f0 BH |
339 | { |
340 | static struct kvm_ppc_smmu_info smmu_info; | |
341 | static bool has_smmu_info; | |
a60f24b5 | 342 | CPUPPCState *env = &cpu->env; |
4656e1f0 BH |
343 | long rampagesize; |
344 | int iq, ik, jq, jk; | |
345 | ||
346 | /* We only handle page sizes for 64-bit server guests for now */ | |
347 | if (!(env->mmu_model & POWERPC_MMU_64)) { | |
348 | return; | |
349 | } | |
350 | ||
351 | /* Collect MMU info from kernel if not already */ | |
352 | if (!has_smmu_info) { | |
a60f24b5 | 353 | kvm_get_smmu_info(cpu, &smmu_info); |
4656e1f0 BH |
354 | has_smmu_info = true; |
355 | } | |
356 | ||
357 | rampagesize = getrampagesize(); | |
358 | ||
359 | /* Convert to QEMU form */ | |
360 | memset(&env->sps, 0, sizeof(env->sps)); | |
361 | ||
362 | for (ik = iq = 0; ik < KVM_PPC_PAGE_SIZES_MAX_SZ; ik++) { | |
363 | struct ppc_one_seg_page_size *qsps = &env->sps.sps[iq]; | |
364 | struct kvm_ppc_one_seg_page_size *ksps = &smmu_info.sps[ik]; | |
365 | ||
366 | if (!kvm_valid_page_size(smmu_info.flags, rampagesize, | |
367 | ksps->page_shift)) { | |
368 | continue; | |
369 | } | |
370 | qsps->page_shift = ksps->page_shift; | |
371 | qsps->slb_enc = ksps->slb_enc; | |
372 | for (jk = jq = 0; jk < KVM_PPC_PAGE_SIZES_MAX_SZ; jk++) { | |
373 | if (!kvm_valid_page_size(smmu_info.flags, rampagesize, | |
374 | ksps->enc[jk].page_shift)) { | |
375 | continue; | |
376 | } | |
377 | qsps->enc[jq].page_shift = ksps->enc[jk].page_shift; | |
378 | qsps->enc[jq].pte_enc = ksps->enc[jk].pte_enc; | |
379 | if (++jq >= PPC_PAGE_SIZES_MAX_SZ) { | |
380 | break; | |
381 | } | |
382 | } | |
383 | if (++iq >= PPC_PAGE_SIZES_MAX_SZ) { | |
384 | break; | |
385 | } | |
386 | } | |
387 | env->slb_nr = smmu_info.slb_size; | |
388 | if (smmu_info.flags & KVM_PPC_1T_SEGMENTS) { | |
389 | env->mmu_model |= POWERPC_MMU_1TSEG; | |
390 | } else { | |
391 | env->mmu_model &= ~POWERPC_MMU_1TSEG; | |
392 | } | |
393 | } | |
394 | #else /* defined (TARGET_PPC64) */ | |
395 | ||
a60f24b5 | 396 | static inline void kvm_fixup_page_sizes(PowerPCCPU *cpu) |
4656e1f0 BH |
397 | { |
398 | } | |
399 | ||
400 | #endif /* !defined (TARGET_PPC64) */ | |
401 | ||
b164e48e EH |
402 | unsigned long kvm_arch_vcpu_id(CPUState *cpu) |
403 | { | |
404 | return cpu->cpu_index; | |
405 | } | |
406 | ||
20d695a9 | 407 | int kvm_arch_init_vcpu(CPUState *cs) |
5666ca4a | 408 | { |
20d695a9 AF |
409 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
410 | CPUPPCState *cenv = &cpu->env; | |
5666ca4a SW |
411 | int ret; |
412 | ||
4656e1f0 | 413 | /* Gather server mmu info from KVM and update the CPU state */ |
a60f24b5 | 414 | kvm_fixup_page_sizes(cpu); |
4656e1f0 BH |
415 | |
416 | /* Synchronize sregs with kvm */ | |
1bc22652 | 417 | ret = kvm_arch_sync_sregs(cpu); |
5666ca4a SW |
418 | if (ret) { |
419 | return ret; | |
420 | } | |
861bbc80 | 421 | |
d5a68146 | 422 | idle_timer = qemu_new_timer_ns(vm_clock, kvm_kick_cpu, cpu); |
c821c2bd | 423 | |
93dd5e85 SW |
424 | /* Some targets support access to KVM's guest TLB. */ |
425 | switch (cenv->mmu_model) { | |
426 | case POWERPC_MMU_BOOKE206: | |
1bc22652 | 427 | ret = kvm_booke206_tlb_init(cpu); |
93dd5e85 SW |
428 | break; |
429 | default: | |
430 | break; | |
431 | } | |
432 | ||
861bbc80 | 433 | return ret; |
d76d1650 AJ |
434 | } |
435 | ||
20d695a9 | 436 | void kvm_arch_reset_vcpu(CPUState *cpu) |
caa5af0f JK |
437 | { |
438 | } | |
439 | ||
1bc22652 | 440 | static void kvm_sw_tlb_put(PowerPCCPU *cpu) |
93dd5e85 | 441 | { |
1bc22652 AF |
442 | CPUPPCState *env = &cpu->env; |
443 | CPUState *cs = CPU(cpu); | |
93dd5e85 SW |
444 | struct kvm_dirty_tlb dirty_tlb; |
445 | unsigned char *bitmap; | |
446 | int ret; | |
447 | ||
448 | if (!env->kvm_sw_tlb) { | |
449 | return; | |
450 | } | |
451 | ||
452 | bitmap = g_malloc((env->nb_tlb + 7) / 8); | |
453 | memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8); | |
454 | ||
455 | dirty_tlb.bitmap = (uintptr_t)bitmap; | |
456 | dirty_tlb.num_dirty = env->nb_tlb; | |
457 | ||
1bc22652 | 458 | ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb); |
93dd5e85 SW |
459 | if (ret) { |
460 | fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n", | |
461 | __func__, strerror(-ret)); | |
462 | } | |
463 | ||
464 | g_free(bitmap); | |
465 | } | |
466 | ||
d67d40ea DG |
467 | static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr) |
468 | { | |
469 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
470 | CPUPPCState *env = &cpu->env; | |
471 | union { | |
472 | uint32_t u32; | |
473 | uint64_t u64; | |
474 | } val; | |
475 | struct kvm_one_reg reg = { | |
476 | .id = id, | |
477 | .addr = (uintptr_t) &val, | |
478 | }; | |
479 | int ret; | |
480 | ||
481 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); | |
482 | if (ret != 0) { | |
483 | fprintf(stderr, "Warning: Unable to retrieve SPR %d from KVM: %s\n", | |
484 | spr, strerror(errno)); | |
485 | } else { | |
486 | switch (id & KVM_REG_SIZE_MASK) { | |
487 | case KVM_REG_SIZE_U32: | |
488 | env->spr[spr] = val.u32; | |
489 | break; | |
490 | ||
491 | case KVM_REG_SIZE_U64: | |
492 | env->spr[spr] = val.u64; | |
493 | break; | |
494 | ||
495 | default: | |
496 | /* Don't handle this size yet */ | |
497 | abort(); | |
498 | } | |
499 | } | |
500 | } | |
501 | ||
502 | static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr) | |
503 | { | |
504 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
505 | CPUPPCState *env = &cpu->env; | |
506 | union { | |
507 | uint32_t u32; | |
508 | uint64_t u64; | |
509 | } val; | |
510 | struct kvm_one_reg reg = { | |
511 | .id = id, | |
512 | .addr = (uintptr_t) &val, | |
513 | }; | |
514 | int ret; | |
515 | ||
516 | switch (id & KVM_REG_SIZE_MASK) { | |
517 | case KVM_REG_SIZE_U32: | |
518 | val.u32 = env->spr[spr]; | |
519 | break; | |
520 | ||
521 | case KVM_REG_SIZE_U64: | |
522 | val.u64 = env->spr[spr]; | |
523 | break; | |
524 | ||
525 | default: | |
526 | /* Don't handle this size yet */ | |
527 | abort(); | |
528 | } | |
529 | ||
530 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
531 | if (ret != 0) { | |
532 | fprintf(stderr, "Warning: Unable to set SPR %d to KVM: %s\n", | |
533 | spr, strerror(errno)); | |
534 | } | |
535 | } | |
536 | ||
70b79849 DG |
537 | static int kvm_put_fp(CPUState *cs) |
538 | { | |
539 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
540 | CPUPPCState *env = &cpu->env; | |
541 | struct kvm_one_reg reg; | |
542 | int i; | |
543 | int ret; | |
544 | ||
545 | if (env->insns_flags & PPC_FLOAT) { | |
546 | uint64_t fpscr = env->fpscr; | |
547 | bool vsx = !!(env->insns_flags2 & PPC2_VSX); | |
548 | ||
549 | reg.id = KVM_REG_PPC_FPSCR; | |
550 | reg.addr = (uintptr_t)&fpscr; | |
551 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
552 | if (ret < 0) { | |
553 | dprintf("Unable to set FPSCR to KVM: %s\n", strerror(errno)); | |
554 | return ret; | |
555 | } | |
556 | ||
557 | for (i = 0; i < 32; i++) { | |
558 | uint64_t vsr[2]; | |
559 | ||
560 | vsr[0] = float64_val(env->fpr[i]); | |
561 | vsr[1] = env->vsr[i]; | |
562 | reg.addr = (uintptr_t) &vsr; | |
563 | reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); | |
564 | ||
565 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
566 | if (ret < 0) { | |
567 | dprintf("Unable to set %s%d to KVM: %s\n", vsx ? "VSR" : "FPR", | |
568 | i, strerror(errno)); | |
569 | return ret; | |
570 | } | |
571 | } | |
572 | } | |
573 | ||
574 | if (env->insns_flags & PPC_ALTIVEC) { | |
575 | reg.id = KVM_REG_PPC_VSCR; | |
576 | reg.addr = (uintptr_t)&env->vscr; | |
577 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
578 | if (ret < 0) { | |
579 | dprintf("Unable to set VSCR to KVM: %s\n", strerror(errno)); | |
580 | return ret; | |
581 | } | |
582 | ||
583 | for (i = 0; i < 32; i++) { | |
584 | reg.id = KVM_REG_PPC_VR(i); | |
585 | reg.addr = (uintptr_t)&env->avr[i]; | |
586 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
587 | if (ret < 0) { | |
588 | dprintf("Unable to set VR%d to KVM: %s\n", i, strerror(errno)); | |
589 | return ret; | |
590 | } | |
591 | } | |
592 | } | |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
597 | static int kvm_get_fp(CPUState *cs) | |
598 | { | |
599 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
600 | CPUPPCState *env = &cpu->env; | |
601 | struct kvm_one_reg reg; | |
602 | int i; | |
603 | int ret; | |
604 | ||
605 | if (env->insns_flags & PPC_FLOAT) { | |
606 | uint64_t fpscr; | |
607 | bool vsx = !!(env->insns_flags2 & PPC2_VSX); | |
608 | ||
609 | reg.id = KVM_REG_PPC_FPSCR; | |
610 | reg.addr = (uintptr_t)&fpscr; | |
611 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); | |
612 | if (ret < 0) { | |
613 | dprintf("Unable to get FPSCR from KVM: %s\n", strerror(errno)); | |
614 | return ret; | |
615 | } else { | |
616 | env->fpscr = fpscr; | |
617 | } | |
618 | ||
619 | for (i = 0; i < 32; i++) { | |
620 | uint64_t vsr[2]; | |
621 | ||
622 | reg.addr = (uintptr_t) &vsr; | |
623 | reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); | |
624 | ||
625 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); | |
626 | if (ret < 0) { | |
627 | dprintf("Unable to get %s%d from KVM: %s\n", | |
628 | vsx ? "VSR" : "FPR", i, strerror(errno)); | |
629 | return ret; | |
630 | } else { | |
631 | env->fpr[i] = vsr[0]; | |
632 | if (vsx) { | |
633 | env->vsr[i] = vsr[1]; | |
634 | } | |
635 | } | |
636 | } | |
637 | } | |
638 | ||
639 | if (env->insns_flags & PPC_ALTIVEC) { | |
640 | reg.id = KVM_REG_PPC_VSCR; | |
641 | reg.addr = (uintptr_t)&env->vscr; | |
642 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); | |
643 | if (ret < 0) { | |
644 | dprintf("Unable to get VSCR from KVM: %s\n", strerror(errno)); | |
645 | return ret; | |
646 | } | |
647 | ||
648 | for (i = 0; i < 32; i++) { | |
649 | reg.id = KVM_REG_PPC_VR(i); | |
650 | reg.addr = (uintptr_t)&env->avr[i]; | |
651 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); | |
652 | if (ret < 0) { | |
653 | dprintf("Unable to get VR%d from KVM: %s\n", | |
654 | i, strerror(errno)); | |
655 | return ret; | |
656 | } | |
657 | } | |
658 | } | |
659 | ||
660 | return 0; | |
661 | } | |
662 | ||
9b00ea49 DG |
663 | #if defined(TARGET_PPC64) |
664 | static int kvm_get_vpa(CPUState *cs) | |
665 | { | |
666 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
667 | CPUPPCState *env = &cpu->env; | |
668 | struct kvm_one_reg reg; | |
669 | int ret; | |
670 | ||
671 | reg.id = KVM_REG_PPC_VPA_ADDR; | |
672 | reg.addr = (uintptr_t)&env->vpa_addr; | |
673 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); | |
674 | if (ret < 0) { | |
675 | dprintf("Unable to get VPA address from KVM: %s\n", strerror(errno)); | |
676 | return ret; | |
677 | } | |
678 | ||
679 | assert((uintptr_t)&env->slb_shadow_size | |
680 | == ((uintptr_t)&env->slb_shadow_addr + 8)); | |
681 | reg.id = KVM_REG_PPC_VPA_SLB; | |
682 | reg.addr = (uintptr_t)&env->slb_shadow_addr; | |
683 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); | |
684 | if (ret < 0) { | |
685 | dprintf("Unable to get SLB shadow state from KVM: %s\n", | |
686 | strerror(errno)); | |
687 | return ret; | |
688 | } | |
689 | ||
690 | assert((uintptr_t)&env->dtl_size == ((uintptr_t)&env->dtl_addr + 8)); | |
691 | reg.id = KVM_REG_PPC_VPA_DTL; | |
692 | reg.addr = (uintptr_t)&env->dtl_addr; | |
693 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); | |
694 | if (ret < 0) { | |
695 | dprintf("Unable to get dispatch trace log state from KVM: %s\n", | |
696 | strerror(errno)); | |
697 | return ret; | |
698 | } | |
699 | ||
700 | return 0; | |
701 | } | |
702 | ||
703 | static int kvm_put_vpa(CPUState *cs) | |
704 | { | |
705 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
706 | CPUPPCState *env = &cpu->env; | |
707 | struct kvm_one_reg reg; | |
708 | int ret; | |
709 | ||
710 | /* SLB shadow or DTL can't be registered unless a master VPA is | |
711 | * registered. That means when restoring state, if a VPA *is* | |
712 | * registered, we need to set that up first. If not, we need to | |
713 | * deregister the others before deregistering the master VPA */ | |
714 | assert(env->vpa_addr || !(env->slb_shadow_addr || env->dtl_addr)); | |
715 | ||
716 | if (env->vpa_addr) { | |
717 | reg.id = KVM_REG_PPC_VPA_ADDR; | |
718 | reg.addr = (uintptr_t)&env->vpa_addr; | |
719 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
720 | if (ret < 0) { | |
721 | dprintf("Unable to set VPA address to KVM: %s\n", strerror(errno)); | |
722 | return ret; | |
723 | } | |
724 | } | |
725 | ||
726 | assert((uintptr_t)&env->slb_shadow_size | |
727 | == ((uintptr_t)&env->slb_shadow_addr + 8)); | |
728 | reg.id = KVM_REG_PPC_VPA_SLB; | |
729 | reg.addr = (uintptr_t)&env->slb_shadow_addr; | |
730 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
731 | if (ret < 0) { | |
732 | dprintf("Unable to set SLB shadow state to KVM: %s\n", strerror(errno)); | |
733 | return ret; | |
734 | } | |
735 | ||
736 | assert((uintptr_t)&env->dtl_size == ((uintptr_t)&env->dtl_addr + 8)); | |
737 | reg.id = KVM_REG_PPC_VPA_DTL; | |
738 | reg.addr = (uintptr_t)&env->dtl_addr; | |
739 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
740 | if (ret < 0) { | |
741 | dprintf("Unable to set dispatch trace log state to KVM: %s\n", | |
742 | strerror(errno)); | |
743 | return ret; | |
744 | } | |
745 | ||
746 | if (!env->vpa_addr) { | |
747 | reg.id = KVM_REG_PPC_VPA_ADDR; | |
748 | reg.addr = (uintptr_t)&env->vpa_addr; | |
749 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
750 | if (ret < 0) { | |
751 | dprintf("Unable to set VPA address to KVM: %s\n", strerror(errno)); | |
752 | return ret; | |
753 | } | |
754 | } | |
755 | ||
756 | return 0; | |
757 | } | |
758 | #endif /* TARGET_PPC64 */ | |
759 | ||
20d695a9 | 760 | int kvm_arch_put_registers(CPUState *cs, int level) |
d76d1650 | 761 | { |
20d695a9 AF |
762 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
763 | CPUPPCState *env = &cpu->env; | |
d76d1650 AJ |
764 | struct kvm_regs regs; |
765 | int ret; | |
766 | int i; | |
767 | ||
1bc22652 AF |
768 | ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); |
769 | if (ret < 0) { | |
d76d1650 | 770 | return ret; |
1bc22652 | 771 | } |
d76d1650 AJ |
772 | |
773 | regs.ctr = env->ctr; | |
774 | regs.lr = env->lr; | |
da91a00f | 775 | regs.xer = cpu_read_xer(env); |
d76d1650 AJ |
776 | regs.msr = env->msr; |
777 | regs.pc = env->nip; | |
778 | ||
779 | regs.srr0 = env->spr[SPR_SRR0]; | |
780 | regs.srr1 = env->spr[SPR_SRR1]; | |
781 | ||
782 | regs.sprg0 = env->spr[SPR_SPRG0]; | |
783 | regs.sprg1 = env->spr[SPR_SPRG1]; | |
784 | regs.sprg2 = env->spr[SPR_SPRG2]; | |
785 | regs.sprg3 = env->spr[SPR_SPRG3]; | |
786 | regs.sprg4 = env->spr[SPR_SPRG4]; | |
787 | regs.sprg5 = env->spr[SPR_SPRG5]; | |
788 | regs.sprg6 = env->spr[SPR_SPRG6]; | |
789 | regs.sprg7 = env->spr[SPR_SPRG7]; | |
790 | ||
90dc8812 SW |
791 | regs.pid = env->spr[SPR_BOOKE_PID]; |
792 | ||
d76d1650 AJ |
793 | for (i = 0;i < 32; i++) |
794 | regs.gpr[i] = env->gpr[i]; | |
795 | ||
4bddaf55 AK |
796 | regs.cr = 0; |
797 | for (i = 0; i < 8; i++) { | |
798 | regs.cr |= (env->crf[i] & 15) << (4 * (7 - i)); | |
799 | } | |
800 | ||
1bc22652 | 801 | ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s); |
d76d1650 AJ |
802 | if (ret < 0) |
803 | return ret; | |
804 | ||
70b79849 DG |
805 | kvm_put_fp(cs); |
806 | ||
93dd5e85 | 807 | if (env->tlb_dirty) { |
1bc22652 | 808 | kvm_sw_tlb_put(cpu); |
93dd5e85 SW |
809 | env->tlb_dirty = false; |
810 | } | |
811 | ||
f1af19d7 DG |
812 | if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) { |
813 | struct kvm_sregs sregs; | |
814 | ||
815 | sregs.pvr = env->spr[SPR_PVR]; | |
816 | ||
817 | sregs.u.s.sdr1 = env->spr[SPR_SDR1]; | |
818 | ||
819 | /* Sync SLB */ | |
820 | #ifdef TARGET_PPC64 | |
821 | for (i = 0; i < 64; i++) { | |
822 | sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid; | |
823 | sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid; | |
824 | } | |
825 | #endif | |
826 | ||
827 | /* Sync SRs */ | |
828 | for (i = 0; i < 16; i++) { | |
829 | sregs.u.s.ppc32.sr[i] = env->sr[i]; | |
830 | } | |
831 | ||
832 | /* Sync BATs */ | |
833 | for (i = 0; i < 8; i++) { | |
ef8beb0e AG |
834 | /* Beware. We have to swap upper and lower bits here */ |
835 | sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32) | |
836 | | env->DBAT[1][i]; | |
837 | sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32) | |
838 | | env->IBAT[1][i]; | |
f1af19d7 DG |
839 | } |
840 | ||
1bc22652 | 841 | ret = kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs); |
f1af19d7 DG |
842 | if (ret) { |
843 | return ret; | |
844 | } | |
845 | } | |
846 | ||
847 | if (cap_hior && (level >= KVM_PUT_RESET_STATE)) { | |
d67d40ea DG |
848 | kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); |
849 | } | |
f1af19d7 | 850 | |
d67d40ea DG |
851 | if (cap_one_reg) { |
852 | int i; | |
853 | ||
854 | /* We deliberately ignore errors here, for kernels which have | |
855 | * the ONE_REG calls, but don't support the specific | |
856 | * registers, there's a reasonable chance things will still | |
857 | * work, at least until we try to migrate. */ | |
858 | for (i = 0; i < 1024; i++) { | |
859 | uint64_t id = env->spr_cb[i].one_reg_id; | |
860 | ||
861 | if (id != 0) { | |
862 | kvm_put_one_spr(cs, id, i); | |
863 | } | |
f1af19d7 | 864 | } |
9b00ea49 DG |
865 | |
866 | #ifdef TARGET_PPC64 | |
867 | if (cap_papr) { | |
868 | if (kvm_put_vpa(cs) < 0) { | |
869 | dprintf("Warning: Unable to set VPA information to KVM\n"); | |
870 | } | |
871 | } | |
872 | #endif /* TARGET_PPC64 */ | |
f1af19d7 DG |
873 | } |
874 | ||
d76d1650 AJ |
875 | return ret; |
876 | } | |
877 | ||
20d695a9 | 878 | int kvm_arch_get_registers(CPUState *cs) |
d76d1650 | 879 | { |
20d695a9 AF |
880 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
881 | CPUPPCState *env = &cpu->env; | |
d76d1650 | 882 | struct kvm_regs regs; |
ba5e5090 | 883 | struct kvm_sregs sregs; |
90dc8812 | 884 | uint32_t cr; |
138b38b6 | 885 | int i, ret; |
d76d1650 | 886 | |
1bc22652 | 887 | ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); |
d76d1650 AJ |
888 | if (ret < 0) |
889 | return ret; | |
890 | ||
90dc8812 SW |
891 | cr = regs.cr; |
892 | for (i = 7; i >= 0; i--) { | |
893 | env->crf[i] = cr & 15; | |
894 | cr >>= 4; | |
895 | } | |
ba5e5090 | 896 | |
d76d1650 AJ |
897 | env->ctr = regs.ctr; |
898 | env->lr = regs.lr; | |
da91a00f | 899 | cpu_write_xer(env, regs.xer); |
d76d1650 AJ |
900 | env->msr = regs.msr; |
901 | env->nip = regs.pc; | |
902 | ||
903 | env->spr[SPR_SRR0] = regs.srr0; | |
904 | env->spr[SPR_SRR1] = regs.srr1; | |
905 | ||
906 | env->spr[SPR_SPRG0] = regs.sprg0; | |
907 | env->spr[SPR_SPRG1] = regs.sprg1; | |
908 | env->spr[SPR_SPRG2] = regs.sprg2; | |
909 | env->spr[SPR_SPRG3] = regs.sprg3; | |
910 | env->spr[SPR_SPRG4] = regs.sprg4; | |
911 | env->spr[SPR_SPRG5] = regs.sprg5; | |
912 | env->spr[SPR_SPRG6] = regs.sprg6; | |
913 | env->spr[SPR_SPRG7] = regs.sprg7; | |
914 | ||
90dc8812 SW |
915 | env->spr[SPR_BOOKE_PID] = regs.pid; |
916 | ||
d76d1650 AJ |
917 | for (i = 0;i < 32; i++) |
918 | env->gpr[i] = regs.gpr[i]; | |
919 | ||
70b79849 DG |
920 | kvm_get_fp(cs); |
921 | ||
90dc8812 | 922 | if (cap_booke_sregs) { |
1bc22652 | 923 | ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs); |
90dc8812 SW |
924 | if (ret < 0) { |
925 | return ret; | |
926 | } | |
927 | ||
928 | if (sregs.u.e.features & KVM_SREGS_E_BASE) { | |
929 | env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0; | |
930 | env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1; | |
931 | env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr; | |
932 | env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear; | |
933 | env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr; | |
934 | env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr; | |
935 | env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr; | |
936 | env->spr[SPR_DECR] = sregs.u.e.dec; | |
937 | env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff; | |
938 | env->spr[SPR_TBU] = sregs.u.e.tb >> 32; | |
939 | env->spr[SPR_VRSAVE] = sregs.u.e.vrsave; | |
940 | } | |
941 | ||
942 | if (sregs.u.e.features & KVM_SREGS_E_ARCH206) { | |
943 | env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir; | |
944 | env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0; | |
945 | env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1; | |
946 | env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar; | |
947 | env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr; | |
948 | } | |
949 | ||
950 | if (sregs.u.e.features & KVM_SREGS_E_64) { | |
951 | env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr; | |
952 | } | |
953 | ||
954 | if (sregs.u.e.features & KVM_SREGS_E_SPRG8) { | |
955 | env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8; | |
956 | } | |
957 | ||
958 | if (sregs.u.e.features & KVM_SREGS_E_IVOR) { | |
959 | env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0]; | |
960 | env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1]; | |
961 | env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2]; | |
962 | env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3]; | |
963 | env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4]; | |
964 | env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5]; | |
965 | env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6]; | |
966 | env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7]; | |
967 | env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8]; | |
968 | env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9]; | |
969 | env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10]; | |
970 | env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11]; | |
971 | env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12]; | |
972 | env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13]; | |
973 | env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14]; | |
974 | env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15]; | |
975 | ||
976 | if (sregs.u.e.features & KVM_SREGS_E_SPE) { | |
977 | env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0]; | |
978 | env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1]; | |
979 | env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2]; | |
980 | } | |
981 | ||
982 | if (sregs.u.e.features & KVM_SREGS_E_PM) { | |
983 | env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3]; | |
984 | } | |
985 | ||
986 | if (sregs.u.e.features & KVM_SREGS_E_PC) { | |
987 | env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4]; | |
988 | env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5]; | |
989 | } | |
990 | } | |
991 | ||
992 | if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) { | |
993 | env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0; | |
994 | env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1; | |
995 | env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2; | |
996 | env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff; | |
997 | env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4; | |
998 | env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6; | |
999 | env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32; | |
1000 | env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg; | |
1001 | env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0]; | |
1002 | env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1]; | |
1003 | } | |
1004 | ||
1005 | if (sregs.u.e.features & KVM_SREGS_EXP) { | |
1006 | env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr; | |
1007 | } | |
1008 | ||
1009 | if (sregs.u.e.features & KVM_SREGS_E_PD) { | |
1010 | env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc; | |
1011 | env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc; | |
1012 | } | |
1013 | ||
1014 | if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) { | |
1015 | env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr; | |
1016 | env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar; | |
1017 | env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0; | |
1018 | ||
1019 | if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) { | |
1020 | env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1; | |
1021 | env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2; | |
1022 | } | |
1023 | } | |
fafc0b6a | 1024 | } |
90dc8812 | 1025 | |
90dc8812 | 1026 | if (cap_segstate) { |
1bc22652 | 1027 | ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs); |
90dc8812 SW |
1028 | if (ret < 0) { |
1029 | return ret; | |
1030 | } | |
1031 | ||
bb593904 | 1032 | ppc_store_sdr1(env, sregs.u.s.sdr1); |
ba5e5090 AG |
1033 | |
1034 | /* Sync SLB */ | |
82c09f2f | 1035 | #ifdef TARGET_PPC64 |
ba5e5090 AG |
1036 | for (i = 0; i < 64; i++) { |
1037 | ppc_store_slb(env, sregs.u.s.ppc64.slb[i].slbe, | |
1038 | sregs.u.s.ppc64.slb[i].slbv); | |
1039 | } | |
82c09f2f | 1040 | #endif |
ba5e5090 AG |
1041 | |
1042 | /* Sync SRs */ | |
1043 | for (i = 0; i < 16; i++) { | |
1044 | env->sr[i] = sregs.u.s.ppc32.sr[i]; | |
1045 | } | |
1046 | ||
1047 | /* Sync BATs */ | |
1048 | for (i = 0; i < 8; i++) { | |
1049 | env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff; | |
1050 | env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32; | |
1051 | env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff; | |
1052 | env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32; | |
1053 | } | |
fafc0b6a | 1054 | } |
ba5e5090 | 1055 | |
d67d40ea DG |
1056 | if (cap_hior) { |
1057 | kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); | |
1058 | } | |
1059 | ||
1060 | if (cap_one_reg) { | |
1061 | int i; | |
1062 | ||
1063 | /* We deliberately ignore errors here, for kernels which have | |
1064 | * the ONE_REG calls, but don't support the specific | |
1065 | * registers, there's a reasonable chance things will still | |
1066 | * work, at least until we try to migrate. */ | |
1067 | for (i = 0; i < 1024; i++) { | |
1068 | uint64_t id = env->spr_cb[i].one_reg_id; | |
1069 | ||
1070 | if (id != 0) { | |
1071 | kvm_get_one_spr(cs, id, i); | |
1072 | } | |
1073 | } | |
9b00ea49 DG |
1074 | |
1075 | #ifdef TARGET_PPC64 | |
1076 | if (cap_papr) { | |
1077 | if (kvm_get_vpa(cs) < 0) { | |
1078 | dprintf("Warning: Unable to get VPA information from KVM\n"); | |
1079 | } | |
1080 | } | |
1081 | #endif | |
d67d40ea DG |
1082 | } |
1083 | ||
d76d1650 AJ |
1084 | return 0; |
1085 | } | |
1086 | ||
1bc22652 | 1087 | int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level) |
fc87e185 AG |
1088 | { |
1089 | unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET; | |
1090 | ||
1091 | if (irq != PPC_INTERRUPT_EXT) { | |
1092 | return 0; | |
1093 | } | |
1094 | ||
1095 | if (!kvm_enabled() || !cap_interrupt_unset || !cap_interrupt_level) { | |
1096 | return 0; | |
1097 | } | |
1098 | ||
1bc22652 | 1099 | kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); |
fc87e185 AG |
1100 | |
1101 | return 0; | |
1102 | } | |
1103 | ||
16415335 AG |
1104 | #if defined(TARGET_PPCEMB) |
1105 | #define PPC_INPUT_INT PPC40x_INPUT_INT | |
1106 | #elif defined(TARGET_PPC64) | |
1107 | #define PPC_INPUT_INT PPC970_INPUT_INT | |
1108 | #else | |
1109 | #define PPC_INPUT_INT PPC6xx_INPUT_INT | |
1110 | #endif | |
1111 | ||
20d695a9 | 1112 | void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) |
d76d1650 | 1113 | { |
20d695a9 AF |
1114 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
1115 | CPUPPCState *env = &cpu->env; | |
d76d1650 AJ |
1116 | int r; |
1117 | unsigned irq; | |
1118 | ||
5cbdb3a3 | 1119 | /* PowerPC QEMU tracks the various core input pins (interrupt, critical |
d76d1650 | 1120 | * interrupt, reset, etc) in PPC-specific env->irq_input_state. */ |
fc87e185 AG |
1121 | if (!cap_interrupt_level && |
1122 | run->ready_for_interrupt_injection && | |
259186a7 | 1123 | (cs->interrupt_request & CPU_INTERRUPT_HARD) && |
16415335 | 1124 | (env->irq_input_state & (1<<PPC_INPUT_INT))) |
d76d1650 AJ |
1125 | { |
1126 | /* For now KVM disregards the 'irq' argument. However, in the | |
1127 | * future KVM could cache it in-kernel to avoid a heavyweight exit | |
1128 | * when reading the UIC. | |
1129 | */ | |
fc87e185 | 1130 | irq = KVM_INTERRUPT_SET; |
d76d1650 AJ |
1131 | |
1132 | dprintf("injected interrupt %d\n", irq); | |
1bc22652 | 1133 | r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &irq); |
55e5c285 AF |
1134 | if (r < 0) { |
1135 | printf("cpu %d fail inject %x\n", cs->cpu_index, irq); | |
1136 | } | |
c821c2bd AG |
1137 | |
1138 | /* Always wake up soon in case the interrupt was level based */ | |
74475455 | 1139 | qemu_mod_timer(idle_timer, qemu_get_clock_ns(vm_clock) + |
c821c2bd | 1140 | (get_ticks_per_sec() / 50)); |
d76d1650 AJ |
1141 | } |
1142 | ||
1143 | /* We don't know if there are more interrupts pending after this. However, | |
1144 | * the guest will return to userspace in the course of handling this one | |
1145 | * anyways, so we will get a chance to deliver the rest. */ | |
d76d1650 AJ |
1146 | } |
1147 | ||
20d695a9 | 1148 | void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run) |
d76d1650 | 1149 | { |
d76d1650 AJ |
1150 | } |
1151 | ||
20d695a9 | 1152 | int kvm_arch_process_async_events(CPUState *cs) |
0af691d7 | 1153 | { |
259186a7 | 1154 | return cs->halted; |
0af691d7 MT |
1155 | } |
1156 | ||
259186a7 | 1157 | static int kvmppc_handle_halt(PowerPCCPU *cpu) |
d76d1650 | 1158 | { |
259186a7 AF |
1159 | CPUState *cs = CPU(cpu); |
1160 | CPUPPCState *env = &cpu->env; | |
1161 | ||
1162 | if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) { | |
1163 | cs->halted = 1; | |
d76d1650 AJ |
1164 | env->exception_index = EXCP_HLT; |
1165 | } | |
1166 | ||
bb4ea393 | 1167 | return 0; |
d76d1650 AJ |
1168 | } |
1169 | ||
1170 | /* map dcr access to existing qemu dcr emulation */ | |
1328c2bf | 1171 | static int kvmppc_handle_dcr_read(CPUPPCState *env, uint32_t dcrn, uint32_t *data) |
d76d1650 AJ |
1172 | { |
1173 | if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) | |
1174 | fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn); | |
1175 | ||
bb4ea393 | 1176 | return 0; |
d76d1650 AJ |
1177 | } |
1178 | ||
1328c2bf | 1179 | static int kvmppc_handle_dcr_write(CPUPPCState *env, uint32_t dcrn, uint32_t data) |
d76d1650 AJ |
1180 | { |
1181 | if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) | |
1182 | fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn); | |
1183 | ||
bb4ea393 | 1184 | return 0; |
d76d1650 AJ |
1185 | } |
1186 | ||
20d695a9 | 1187 | int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) |
d76d1650 | 1188 | { |
20d695a9 AF |
1189 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
1190 | CPUPPCState *env = &cpu->env; | |
bb4ea393 | 1191 | int ret; |
d76d1650 AJ |
1192 | |
1193 | switch (run->exit_reason) { | |
1194 | case KVM_EXIT_DCR: | |
1195 | if (run->dcr.is_write) { | |
1196 | dprintf("handle dcr write\n"); | |
1197 | ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data); | |
1198 | } else { | |
1199 | dprintf("handle dcr read\n"); | |
1200 | ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data); | |
1201 | } | |
1202 | break; | |
1203 | case KVM_EXIT_HLT: | |
1204 | dprintf("handle halt\n"); | |
259186a7 | 1205 | ret = kvmppc_handle_halt(cpu); |
d76d1650 | 1206 | break; |
c6304a4a | 1207 | #if defined(TARGET_PPC64) |
f61b4bed AG |
1208 | case KVM_EXIT_PAPR_HCALL: |
1209 | dprintf("handle PAPR hypercall\n"); | |
20d695a9 | 1210 | run->papr_hcall.ret = spapr_hypercall(cpu, |
aa100fa4 | 1211 | run->papr_hcall.nr, |
f61b4bed | 1212 | run->papr_hcall.args); |
78e8fde2 | 1213 | ret = 0; |
f61b4bed AG |
1214 | break; |
1215 | #endif | |
5b95b8b9 AG |
1216 | case KVM_EXIT_EPR: |
1217 | dprintf("handle epr\n"); | |
1218 | run->epr.epr = ldl_phys(env->mpic_iack); | |
1219 | ret = 0; | |
1220 | break; | |
31f2cb8f BB |
1221 | case KVM_EXIT_WATCHDOG: |
1222 | dprintf("handle watchdog expiry\n"); | |
1223 | watchdog_perform_action(); | |
1224 | ret = 0; | |
1225 | break; | |
1226 | ||
73aaec4a JK |
1227 | default: |
1228 | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); | |
1229 | ret = -1; | |
1230 | break; | |
d76d1650 AJ |
1231 | } |
1232 | ||
1233 | return ret; | |
1234 | } | |
1235 | ||
31f2cb8f BB |
1236 | int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) |
1237 | { | |
1238 | CPUState *cs = CPU(cpu); | |
1239 | uint32_t bits = tsr_bits; | |
1240 | struct kvm_one_reg reg = { | |
1241 | .id = KVM_REG_PPC_OR_TSR, | |
1242 | .addr = (uintptr_t) &bits, | |
1243 | }; | |
1244 | ||
1245 | return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
1246 | } | |
1247 | ||
1248 | int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) | |
1249 | { | |
1250 | ||
1251 | CPUState *cs = CPU(cpu); | |
1252 | uint32_t bits = tsr_bits; | |
1253 | struct kvm_one_reg reg = { | |
1254 | .id = KVM_REG_PPC_CLEAR_TSR, | |
1255 | .addr = (uintptr_t) &bits, | |
1256 | }; | |
1257 | ||
1258 | return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
1259 | } | |
1260 | ||
1261 | int kvmppc_set_tcr(PowerPCCPU *cpu) | |
1262 | { | |
1263 | CPUState *cs = CPU(cpu); | |
1264 | CPUPPCState *env = &cpu->env; | |
1265 | uint32_t tcr = env->spr[SPR_BOOKE_TCR]; | |
1266 | ||
1267 | struct kvm_one_reg reg = { | |
1268 | .id = KVM_REG_PPC_TCR, | |
1269 | .addr = (uintptr_t) &tcr, | |
1270 | }; | |
1271 | ||
1272 | return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
1273 | } | |
1274 | ||
1275 | int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu) | |
1276 | { | |
1277 | CPUState *cs = CPU(cpu); | |
1278 | struct kvm_enable_cap encap = {}; | |
1279 | int ret; | |
1280 | ||
1281 | if (!kvm_enabled()) { | |
1282 | return -1; | |
1283 | } | |
1284 | ||
1285 | if (!cap_ppc_watchdog) { | |
1286 | printf("warning: KVM does not support watchdog"); | |
1287 | return -1; | |
1288 | } | |
1289 | ||
1290 | encap.cap = KVM_CAP_PPC_BOOKE_WATCHDOG; | |
1291 | ret = kvm_vcpu_ioctl(cs, KVM_ENABLE_CAP, &encap); | |
1292 | if (ret < 0) { | |
1293 | fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n", | |
1294 | __func__, strerror(-ret)); | |
1295 | return ret; | |
1296 | } | |
1297 | ||
1298 | return ret; | |
1299 | } | |
1300 | ||
dc333cd6 AG |
1301 | static int read_cpuinfo(const char *field, char *value, int len) |
1302 | { | |
1303 | FILE *f; | |
1304 | int ret = -1; | |
1305 | int field_len = strlen(field); | |
1306 | char line[512]; | |
1307 | ||
1308 | f = fopen("/proc/cpuinfo", "r"); | |
1309 | if (!f) { | |
1310 | return -1; | |
1311 | } | |
1312 | ||
1313 | do { | |
1314 | if(!fgets(line, sizeof(line), f)) { | |
1315 | break; | |
1316 | } | |
1317 | if (!strncmp(line, field, field_len)) { | |
ae215068 | 1318 | pstrcpy(value, len, line); |
dc333cd6 AG |
1319 | ret = 0; |
1320 | break; | |
1321 | } | |
1322 | } while(*line); | |
1323 | ||
1324 | fclose(f); | |
1325 | ||
1326 | return ret; | |
1327 | } | |
1328 | ||
1329 | uint32_t kvmppc_get_tbfreq(void) | |
1330 | { | |
1331 | char line[512]; | |
1332 | char *ns; | |
1333 | uint32_t retval = get_ticks_per_sec(); | |
1334 | ||
1335 | if (read_cpuinfo("timebase", line, sizeof(line))) { | |
1336 | return retval; | |
1337 | } | |
1338 | ||
1339 | if (!(ns = strchr(line, ':'))) { | |
1340 | return retval; | |
1341 | } | |
1342 | ||
1343 | ns++; | |
1344 | ||
1345 | retval = atoi(ns); | |
1346 | return retval; | |
1347 | } | |
4513d923 | 1348 | |
eadaada1 AG |
1349 | /* Try to find a device tree node for a CPU with clock-frequency property */ |
1350 | static int kvmppc_find_cpu_dt(char *buf, int buf_len) | |
1351 | { | |
1352 | struct dirent *dirp; | |
1353 | DIR *dp; | |
1354 | ||
1355 | if ((dp = opendir(PROC_DEVTREE_CPU)) == NULL) { | |
1356 | printf("Can't open directory " PROC_DEVTREE_CPU "\n"); | |
1357 | return -1; | |
1358 | } | |
1359 | ||
1360 | buf[0] = '\0'; | |
1361 | while ((dirp = readdir(dp)) != NULL) { | |
1362 | FILE *f; | |
1363 | snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU, | |
1364 | dirp->d_name); | |
1365 | f = fopen(buf, "r"); | |
1366 | if (f) { | |
1367 | snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name); | |
1368 | fclose(f); | |
1369 | break; | |
1370 | } | |
1371 | buf[0] = '\0'; | |
1372 | } | |
1373 | closedir(dp); | |
1374 | if (buf[0] == '\0') { | |
1375 | printf("Unknown host!\n"); | |
1376 | return -1; | |
1377 | } | |
1378 | ||
1379 | return 0; | |
1380 | } | |
1381 | ||
9bc884b7 DG |
1382 | /* Read a CPU node property from the host device tree that's a single |
1383 | * integer (32-bit or 64-bit). Returns 0 if anything goes wrong | |
1384 | * (can't find or open the property, or doesn't understand the | |
1385 | * format) */ | |
1386 | static uint64_t kvmppc_read_int_cpu_dt(const char *propname) | |
eadaada1 | 1387 | { |
9bc884b7 DG |
1388 | char buf[PATH_MAX]; |
1389 | union { | |
1390 | uint32_t v32; | |
1391 | uint64_t v64; | |
1392 | } u; | |
eadaada1 AG |
1393 | FILE *f; |
1394 | int len; | |
1395 | ||
1396 | if (kvmppc_find_cpu_dt(buf, sizeof(buf))) { | |
9bc884b7 | 1397 | return -1; |
eadaada1 AG |
1398 | } |
1399 | ||
9bc884b7 DG |
1400 | strncat(buf, "/", sizeof(buf) - strlen(buf)); |
1401 | strncat(buf, propname, sizeof(buf) - strlen(buf)); | |
eadaada1 AG |
1402 | |
1403 | f = fopen(buf, "rb"); | |
1404 | if (!f) { | |
1405 | return -1; | |
1406 | } | |
1407 | ||
9bc884b7 | 1408 | len = fread(&u, 1, sizeof(u), f); |
eadaada1 AG |
1409 | fclose(f); |
1410 | switch (len) { | |
9bc884b7 DG |
1411 | case 4: |
1412 | /* property is a 32-bit quantity */ | |
1413 | return be32_to_cpu(u.v32); | |
1414 | case 8: | |
1415 | return be64_to_cpu(u.v64); | |
eadaada1 AG |
1416 | } |
1417 | ||
1418 | return 0; | |
1419 | } | |
1420 | ||
9bc884b7 DG |
1421 | uint64_t kvmppc_get_clockfreq(void) |
1422 | { | |
1423 | return kvmppc_read_int_cpu_dt("clock-frequency"); | |
1424 | } | |
1425 | ||
6659394f DG |
1426 | uint32_t kvmppc_get_vmx(void) |
1427 | { | |
1428 | return kvmppc_read_int_cpu_dt("ibm,vmx"); | |
1429 | } | |
1430 | ||
1431 | uint32_t kvmppc_get_dfp(void) | |
1432 | { | |
1433 | return kvmppc_read_int_cpu_dt("ibm,dfp"); | |
1434 | } | |
1435 | ||
1a61a9ae SY |
1436 | static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo) |
1437 | { | |
1438 | PowerPCCPU *cpu = ppc_env_get_cpu(env); | |
1439 | CPUState *cs = CPU(cpu); | |
1440 | ||
1441 | if (kvm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) && | |
1442 | !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) { | |
1443 | return 0; | |
1444 | } | |
1445 | ||
1446 | return 1; | |
1447 | } | |
1448 | ||
1449 | int kvmppc_get_hasidle(CPUPPCState *env) | |
1450 | { | |
1451 | struct kvm_ppc_pvinfo pvinfo; | |
1452 | ||
1453 | if (!kvmppc_get_pvinfo(env, &pvinfo) && | |
1454 | (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) { | |
1455 | return 1; | |
1456 | } | |
1457 | ||
1458 | return 0; | |
1459 | } | |
1460 | ||
1328c2bf | 1461 | int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len) |
45024f09 AG |
1462 | { |
1463 | uint32_t *hc = (uint32_t*)buf; | |
45024f09 AG |
1464 | struct kvm_ppc_pvinfo pvinfo; |
1465 | ||
1a61a9ae | 1466 | if (!kvmppc_get_pvinfo(env, &pvinfo)) { |
45024f09 | 1467 | memcpy(buf, pvinfo.hcall, buf_len); |
45024f09 AG |
1468 | return 0; |
1469 | } | |
45024f09 AG |
1470 | |
1471 | /* | |
1472 | * Fallback to always fail hypercalls: | |
1473 | * | |
1474 | * li r3, -1 | |
1475 | * nop | |
1476 | * nop | |
1477 | * nop | |
1478 | */ | |
1479 | ||
1480 | hc[0] = 0x3860ffff; | |
1481 | hc[1] = 0x60000000; | |
1482 | hc[2] = 0x60000000; | |
1483 | hc[3] = 0x60000000; | |
1484 | ||
1485 | return 0; | |
1486 | } | |
1487 | ||
1bc22652 | 1488 | void kvmppc_set_papr(PowerPCCPU *cpu) |
f61b4bed | 1489 | { |
1bc22652 AF |
1490 | CPUPPCState *env = &cpu->env; |
1491 | CPUState *cs = CPU(cpu); | |
94135e81 | 1492 | struct kvm_enable_cap cap = {}; |
f61b4bed AG |
1493 | int ret; |
1494 | ||
f61b4bed | 1495 | cap.cap = KVM_CAP_PPC_PAPR; |
1bc22652 | 1496 | ret = kvm_vcpu_ioctl(cs, KVM_ENABLE_CAP, &cap); |
f61b4bed AG |
1497 | |
1498 | if (ret) { | |
f1af19d7 | 1499 | cpu_abort(env, "This KVM version does not support PAPR\n"); |
94135e81 | 1500 | } |
9b00ea49 DG |
1501 | |
1502 | /* Update the capability flag so we sync the right information | |
1503 | * with kvm */ | |
1504 | cap_papr = 1; | |
f61b4bed AG |
1505 | } |
1506 | ||
5b95b8b9 AG |
1507 | void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy) |
1508 | { | |
1509 | CPUPPCState *env = &cpu->env; | |
1510 | CPUState *cs = CPU(cpu); | |
1511 | struct kvm_enable_cap cap = {}; | |
1512 | int ret; | |
1513 | ||
1514 | cap.cap = KVM_CAP_PPC_EPR; | |
1515 | cap.args[0] = mpic_proxy; | |
1516 | ret = kvm_vcpu_ioctl(cs, KVM_ENABLE_CAP, &cap); | |
1517 | ||
1518 | if (ret && mpic_proxy) { | |
1519 | cpu_abort(env, "This KVM version does not support EPR\n"); | |
1520 | } | |
1521 | } | |
1522 | ||
e97c3636 DG |
1523 | int kvmppc_smt_threads(void) |
1524 | { | |
1525 | return cap_ppc_smt ? cap_ppc_smt : 1; | |
1526 | } | |
1527 | ||
7f763a5d | 1528 | #ifdef TARGET_PPC64 |
354ac20a DG |
1529 | off_t kvmppc_alloc_rma(const char *name, MemoryRegion *sysmem) |
1530 | { | |
1531 | void *rma; | |
1532 | off_t size; | |
1533 | int fd; | |
1534 | struct kvm_allocate_rma ret; | |
1535 | MemoryRegion *rma_region; | |
1536 | ||
1537 | /* If cap_ppc_rma == 0, contiguous RMA allocation is not supported | |
1538 | * if cap_ppc_rma == 1, contiguous RMA allocation is supported, but | |
1539 | * not necessary on this hardware | |
1540 | * if cap_ppc_rma == 2, contiguous RMA allocation is needed on this hardware | |
1541 | * | |
1542 | * FIXME: We should allow the user to force contiguous RMA | |
1543 | * allocation in the cap_ppc_rma==1 case. | |
1544 | */ | |
1545 | if (cap_ppc_rma < 2) { | |
1546 | return 0; | |
1547 | } | |
1548 | ||
1549 | fd = kvm_vm_ioctl(kvm_state, KVM_ALLOCATE_RMA, &ret); | |
1550 | if (fd < 0) { | |
1551 | fprintf(stderr, "KVM: Error on KVM_ALLOCATE_RMA: %s\n", | |
1552 | strerror(errno)); | |
1553 | return -1; | |
1554 | } | |
1555 | ||
1556 | size = MIN(ret.rma_size, 256ul << 20); | |
1557 | ||
1558 | rma = mmap(NULL, size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); | |
1559 | if (rma == MAP_FAILED) { | |
1560 | fprintf(stderr, "KVM: Error mapping RMA: %s\n", strerror(errno)); | |
1561 | return -1; | |
1562 | }; | |
1563 | ||
1564 | rma_region = g_new(MemoryRegion, 1); | |
2c9b15ca | 1565 | memory_region_init_ram_ptr(rma_region, NULL, name, size, rma); |
6148b23d | 1566 | vmstate_register_ram_global(rma_region); |
354ac20a DG |
1567 | memory_region_add_subregion(sysmem, 0, rma_region); |
1568 | ||
1569 | return size; | |
1570 | } | |
1571 | ||
7f763a5d DG |
1572 | uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift) |
1573 | { | |
f36951c1 DG |
1574 | struct kvm_ppc_smmu_info info; |
1575 | long rampagesize, best_page_shift; | |
1576 | int i; | |
1577 | ||
7f763a5d DG |
1578 | if (cap_ppc_rma >= 2) { |
1579 | return current_size; | |
1580 | } | |
f36951c1 DG |
1581 | |
1582 | /* Find the largest hardware supported page size that's less than | |
1583 | * or equal to the (logical) backing page size of guest RAM */ | |
182735ef | 1584 | kvm_get_smmu_info(POWERPC_CPU(first_cpu), &info); |
f36951c1 DG |
1585 | rampagesize = getrampagesize(); |
1586 | best_page_shift = 0; | |
1587 | ||
1588 | for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) { | |
1589 | struct kvm_ppc_one_seg_page_size *sps = &info.sps[i]; | |
1590 | ||
1591 | if (!sps->page_shift) { | |
1592 | continue; | |
1593 | } | |
1594 | ||
1595 | if ((sps->page_shift > best_page_shift) | |
1596 | && ((1UL << sps->page_shift) <= rampagesize)) { | |
1597 | best_page_shift = sps->page_shift; | |
1598 | } | |
1599 | } | |
1600 | ||
7f763a5d | 1601 | return MIN(current_size, |
f36951c1 | 1602 | 1ULL << (best_page_shift + hash_shift - 7)); |
7f763a5d DG |
1603 | } |
1604 | #endif | |
1605 | ||
0f5cb298 DG |
1606 | void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t window_size, int *pfd) |
1607 | { | |
1608 | struct kvm_create_spapr_tce args = { | |
1609 | .liobn = liobn, | |
1610 | .window_size = window_size, | |
1611 | }; | |
1612 | long len; | |
1613 | int fd; | |
1614 | void *table; | |
1615 | ||
b5aec396 DG |
1616 | /* Must set fd to -1 so we don't try to munmap when called for |
1617 | * destroying the table, which the upper layers -will- do | |
1618 | */ | |
1619 | *pfd = -1; | |
0f5cb298 DG |
1620 | if (!cap_spapr_tce) { |
1621 | return NULL; | |
1622 | } | |
1623 | ||
1624 | fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args); | |
1625 | if (fd < 0) { | |
b5aec396 DG |
1626 | fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n", |
1627 | liobn); | |
0f5cb298 DG |
1628 | return NULL; |
1629 | } | |
1630 | ||
a83000f5 | 1631 | len = (window_size / SPAPR_TCE_PAGE_SIZE) * sizeof(uint64_t); |
0f5cb298 DG |
1632 | /* FIXME: round this up to page size */ |
1633 | ||
74b41e56 | 1634 | table = mmap(NULL, len, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); |
0f5cb298 | 1635 | if (table == MAP_FAILED) { |
b5aec396 DG |
1636 | fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n", |
1637 | liobn); | |
0f5cb298 DG |
1638 | close(fd); |
1639 | return NULL; | |
1640 | } | |
1641 | ||
1642 | *pfd = fd; | |
1643 | return table; | |
1644 | } | |
1645 | ||
1646 | int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t window_size) | |
1647 | { | |
1648 | long len; | |
1649 | ||
1650 | if (fd < 0) { | |
1651 | return -1; | |
1652 | } | |
1653 | ||
a83000f5 | 1654 | len = (window_size / SPAPR_TCE_PAGE_SIZE)*sizeof(uint64_t); |
0f5cb298 DG |
1655 | if ((munmap(table, len) < 0) || |
1656 | (close(fd) < 0)) { | |
b5aec396 DG |
1657 | fprintf(stderr, "KVM: Unexpected error removing TCE table: %s", |
1658 | strerror(errno)); | |
0f5cb298 DG |
1659 | /* Leak the table */ |
1660 | } | |
1661 | ||
1662 | return 0; | |
1663 | } | |
1664 | ||
7f763a5d DG |
1665 | int kvmppc_reset_htab(int shift_hint) |
1666 | { | |
1667 | uint32_t shift = shift_hint; | |
1668 | ||
ace9a2cb DG |
1669 | if (!kvm_enabled()) { |
1670 | /* Full emulation, tell caller to allocate htab itself */ | |
1671 | return 0; | |
1672 | } | |
1673 | if (kvm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) { | |
7f763a5d DG |
1674 | int ret; |
1675 | ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift); | |
ace9a2cb DG |
1676 | if (ret == -ENOTTY) { |
1677 | /* At least some versions of PR KVM advertise the | |
1678 | * capability, but don't implement the ioctl(). Oops. | |
1679 | * Return 0 so that we allocate the htab in qemu, as is | |
1680 | * correct for PR. */ | |
1681 | return 0; | |
1682 | } else if (ret < 0) { | |
7f763a5d DG |
1683 | return ret; |
1684 | } | |
1685 | return shift; | |
1686 | } | |
1687 | ||
ace9a2cb DG |
1688 | /* We have a kernel that predates the htab reset calls. For PR |
1689 | * KVM, we need to allocate the htab ourselves, for an HV KVM of | |
1690 | * this era, it has allocated a 16MB fixed size hash table | |
1691 | * already. Kernels of this era have the GET_PVINFO capability | |
1692 | * only on PR, so we use this hack to determine the right | |
1693 | * answer */ | |
1694 | if (kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_PVINFO)) { | |
1695 | /* PR - tell caller to allocate htab */ | |
1696 | return 0; | |
1697 | } else { | |
1698 | /* HV - assume 16MB kernel allocated htab */ | |
1699 | return 24; | |
1700 | } | |
7f763a5d DG |
1701 | } |
1702 | ||
a1e98583 DG |
1703 | static inline uint32_t mfpvr(void) |
1704 | { | |
1705 | uint32_t pvr; | |
1706 | ||
1707 | asm ("mfpvr %0" | |
1708 | : "=r"(pvr)); | |
1709 | return pvr; | |
1710 | } | |
1711 | ||
a7342588 DG |
1712 | static void alter_insns(uint64_t *word, uint64_t flags, bool on) |
1713 | { | |
1714 | if (on) { | |
1715 | *word |= flags; | |
1716 | } else { | |
1717 | *word &= ~flags; | |
1718 | } | |
1719 | } | |
1720 | ||
2985b86b | 1721 | static void kvmppc_host_cpu_initfn(Object *obj) |
a1e98583 | 1722 | { |
2985b86b AF |
1723 | assert(kvm_enabled()); |
1724 | } | |
1725 | ||
1726 | static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data) | |
1727 | { | |
1728 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); | |
a7342588 DG |
1729 | uint32_t vmx = kvmppc_get_vmx(); |
1730 | uint32_t dfp = kvmppc_get_dfp(); | |
0cbad81f DG |
1731 | uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size"); |
1732 | uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size"); | |
a1e98583 | 1733 | |
cfe34f44 | 1734 | /* Now fix up the class with information we can query from the host */ |
a7342588 | 1735 | |
70bca53f AG |
1736 | if (vmx != -1) { |
1737 | /* Only override when we know what the host supports */ | |
cfe34f44 AF |
1738 | alter_insns(&pcc->insns_flags, PPC_ALTIVEC, vmx > 0); |
1739 | alter_insns(&pcc->insns_flags2, PPC2_VSX, vmx > 1); | |
70bca53f AG |
1740 | } |
1741 | if (dfp != -1) { | |
1742 | /* Only override when we know what the host supports */ | |
cfe34f44 | 1743 | alter_insns(&pcc->insns_flags2, PPC2_DFP, dfp); |
70bca53f | 1744 | } |
0cbad81f DG |
1745 | |
1746 | if (dcache_size != -1) { | |
1747 | pcc->l1_dcache_size = dcache_size; | |
1748 | } | |
1749 | ||
1750 | if (icache_size != -1) { | |
1751 | pcc->l1_icache_size = icache_size; | |
1752 | } | |
a1e98583 DG |
1753 | } |
1754 | ||
55e5c285 | 1755 | int kvmppc_fixup_cpu(PowerPCCPU *cpu) |
12b1143b | 1756 | { |
55e5c285 | 1757 | CPUState *cs = CPU(cpu); |
12b1143b DG |
1758 | int smt; |
1759 | ||
1760 | /* Adjust cpu index for SMT */ | |
1761 | smt = kvmppc_smt_threads(); | |
55e5c285 AF |
1762 | cs->cpu_index = (cs->cpu_index / smp_threads) * smt |
1763 | + (cs->cpu_index % smp_threads); | |
12b1143b DG |
1764 | |
1765 | return 0; | |
1766 | } | |
1767 | ||
3b961124 SY |
1768 | bool kvmppc_has_cap_epr(void) |
1769 | { | |
1770 | return cap_epr; | |
1771 | } | |
1772 | ||
5ba4576b AF |
1773 | static int kvm_ppc_register_host_cpu_type(void) |
1774 | { | |
1775 | TypeInfo type_info = { | |
1776 | .name = TYPE_HOST_POWERPC_CPU, | |
1777 | .instance_init = kvmppc_host_cpu_initfn, | |
1778 | .class_init = kvmppc_host_cpu_class_init, | |
1779 | }; | |
1780 | uint32_t host_pvr = mfpvr(); | |
1781 | PowerPCCPUClass *pvr_pcc; | |
1782 | ||
1783 | pvr_pcc = ppc_cpu_class_by_pvr(host_pvr); | |
1784 | if (pvr_pcc == NULL) { | |
1785 | return -1; | |
1786 | } | |
1787 | type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc)); | |
1788 | type_register(&type_info); | |
1789 | return 0; | |
1790 | } | |
1791 | ||
12b1143b | 1792 | |
e68cb8b4 AK |
1793 | int kvmppc_get_htab_fd(bool write) |
1794 | { | |
1795 | struct kvm_get_htab_fd s = { | |
1796 | .flags = write ? KVM_GET_HTAB_WRITE : 0, | |
1797 | .start_index = 0, | |
1798 | }; | |
1799 | ||
1800 | if (!cap_htab_fd) { | |
1801 | fprintf(stderr, "KVM version doesn't support saving the hash table\n"); | |
1802 | return -1; | |
1803 | } | |
1804 | ||
1805 | return kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s); | |
1806 | } | |
1807 | ||
1808 | int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns) | |
1809 | { | |
1810 | int64_t starttime = qemu_get_clock_ns(rt_clock); | |
1811 | uint8_t buf[bufsize]; | |
1812 | ssize_t rc; | |
1813 | ||
1814 | do { | |
1815 | rc = read(fd, buf, bufsize); | |
1816 | if (rc < 0) { | |
1817 | fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n", | |
1818 | strerror(errno)); | |
1819 | return rc; | |
1820 | } else if (rc) { | |
1821 | /* Kernel already retuns data in BE format for the file */ | |
1822 | qemu_put_buffer(f, buf, rc); | |
1823 | } | |
1824 | } while ((rc != 0) | |
1825 | && ((max_ns < 0) | |
1826 | || ((qemu_get_clock_ns(rt_clock) - starttime) < max_ns))); | |
1827 | ||
1828 | return (rc == 0) ? 1 : 0; | |
1829 | } | |
1830 | ||
1831 | int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index, | |
1832 | uint16_t n_valid, uint16_t n_invalid) | |
1833 | { | |
1834 | struct kvm_get_htab_header *buf; | |
1835 | size_t chunksize = sizeof(*buf) + n_valid*HASH_PTE_SIZE_64; | |
1836 | ssize_t rc; | |
1837 | ||
1838 | buf = alloca(chunksize); | |
1839 | /* This is KVM on ppc, so this is all big-endian */ | |
1840 | buf->index = index; | |
1841 | buf->n_valid = n_valid; | |
1842 | buf->n_invalid = n_invalid; | |
1843 | ||
1844 | qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64*n_valid); | |
1845 | ||
1846 | rc = write(fd, buf, chunksize); | |
1847 | if (rc < 0) { | |
1848 | fprintf(stderr, "Error writing KVM hash table: %s\n", | |
1849 | strerror(errno)); | |
1850 | return rc; | |
1851 | } | |
1852 | if (rc != chunksize) { | |
1853 | /* We should never get a short write on a single chunk */ | |
1854 | fprintf(stderr, "Short write, restoring KVM hash table\n"); | |
1855 | return -1; | |
1856 | } | |
1857 | return 0; | |
1858 | } | |
1859 | ||
20d695a9 | 1860 | bool kvm_arch_stop_on_emulation_error(CPUState *cpu) |
4513d923 GN |
1861 | { |
1862 | return true; | |
1863 | } | |
a1b87fe0 | 1864 | |
20d695a9 | 1865 | int kvm_arch_on_sigbus_vcpu(CPUState *cpu, int code, void *addr) |
a1b87fe0 JK |
1866 | { |
1867 | return 1; | |
1868 | } | |
1869 | ||
1870 | int kvm_arch_on_sigbus(int code, void *addr) | |
1871 | { | |
1872 | return 1; | |
1873 | } | |
82169660 SW |
1874 | |
1875 | void kvm_arch_init_irq_routing(KVMState *s) | |
1876 | { | |
1877 | } |